A device for time tagging measurement

Abstract

An FPGA is disclosed comprising a group of TDCs, a clock generation unit that provides a clock to the group of TDCs in common, a tag counter configured to provide a tag count, which is a value obtained by counting the clock, to the group of TDCs in common, and a processing unit. Any of the TDCs includes an input signal generation part that generates an input pulse having a rising edge occurring at the same time as the rising edge of a start signal input to the TDC, and a delay line part into which the generated input pulse is input. The processing unit calculates a first value by multiplying the value of the tag count observed at the time of occurrence of the first newly generated clock pulse after the rising edge of the start signal input to the TDC occurs by the pulse period of the clock, and calculates the time of occurrence of the first start signal by subtracting the thermometer code output by the delay line part or the converted code obtained by converting the thermometer code from the first value at the time of occurrence of the rising edge of the first newly generated clock pulse.

Description

Technology Field

[0001] The present invention relates to a technology for TDC, and in particular to a TDC technology capable of tagging the time of occurrence of a pulse signal. Background Technology

[0002] Time-to-Digital Converters (TDCs) play a critical role in many scientific and industrial applications requiring precise timing measurements. They are widely used in applications demanding high-precision timing, such as particle physics, medical imaging, radar systems, and Time of Arrival (TOF) measurements in laser rangefinders.

[0003] A TDC can convert the time interval between two events into a digital output. Designed to measure the time difference between two events, a TDC typically uses a counter to count the number of clock cycles between the two events. It then converts the count into a digital output representing the time interval. There are various types of TDCs, such as leading-edge TDCs, trailing-edge TDCs, and interpolation TDCs. A leading-edge TDC measures the time between the leading edge of a start signal and the leading edge of a stop signal, while a trailing-edge TDC measures the time between the trailing edge of a start signal and the trailing edge of a stop signal. An interpolation TDC increases the resolution of the TDC by using interpolation techniques to estimate the time interval between two clock cycles.

[0004] As a prerequisite for determining measurement values, the TDC providing the aforementioned functions requires time tagging one or more independent signals based on a specific time, rather than the interval between two pulses occurring in a single channel, depending on the application using the TDC. To achieve this, it is necessary to provide a technology that inputs only a single signal representing a single event from each channel to the TDC, and tags the occurrence time of the input signal to store it as a number. The problem to be solved

[0005] The present invention aims to provide a TDC that provides a function for time tagging the occurrence time of a single signal representing a single event. means of solving the problem

[0006] TDCs include Application-Specific Integrated Circuits (ASICs), Microcontrollers (MCUs), Programmable System-on-Chip (PSoC), Digital Signal Processors (DSPs), Field Programmable Analog Arrays (FPAAs), Time-to-Amplitude Converters (TACs), Time-to-Frequency Converters (TFCs), and FPGAs (Field Programmable Analog Arrays). It can be implemented using a Programmable Gate Array, etc.

[0007] When implementing TDC using an FPGA, the following issues may arise. First, since the resources provided to the FPGA, including logic cells, lookup tables (LUTs), and routing channels, are limited, the resolution and accuracy of the TDC implemented on the FPGA may be restricted. Second, at high clock frequencies, jitter can introduce errors into TDC measurements. Here, jitter refers to variations in the timing of the clock signal caused by factors such as noise and temperature. Third, TDC may exhibit non-linear behavior due to factors such as voltage drop, temperature changes, and differences in manufacturing processes, which can consequently introduce errors into TDC measurements at high resolutions. Fourth, FPGAs experience delays through signal processing and routing, and these delays can introduce errors into TDC measurements over small time intervals.

[0008] In FPGAs, routing refers to the process of connecting programmable logic elements (e.g., lookup tables, flip-flops, and multiplexers) to a chip to form desired logic circuits. Routing determines how signals propagate through the chip and can significantly impact the overall performance of the design. One of the major factors that can cause latency in FPGA routing is the capacitance of the interconnect wires connecting the logic elements. As the number of logic elements and the distance between them increase, the capacitance of the interconnect wires also increases. This capacitance delays signal propagation through the wires, which can increase overall design latency. Another factor that can cause latency in FPGA routing is routing congestion. Routing congestion occurs when the routing resources of the FPGA are limited and the number of logic elements to be connected is large. Routing congestion can cause latency because it increases the distance between logic elements, thereby increasing the capacitance of the interconnect wires.

[0009] A tapped delay line is a digital signal processing technique used to implement thermometer codes. In a thermometer code, each bit of a binary number is represented by a separate signal line, and the line corresponding to the "on" bit indicates what the binary value represents. To implement a thermometer code using a tapped delay line, a series of delay elements representing each bit is used. The input binary number is converted into a series of pulses, with each pulse representing one bit of the binary number. These pulses are delayed by a different amount depending on the position of each bit before being supplied to the tapped delay line. At the output of the tapped delay line, each output signal line represents a bit of the binary number, and the "on" line indicates the binary value. This technique is commonly used in digital-to-analog converters (DACs) to convert digital signals into analog signals.

[0010] In FPGAs, a carry chain block is a hardware block used to perform fast arithmetic operations, particularly addition and subtraction. In digital circuits, the addition and subtraction of multi-bit numbers require the calculation of carry bits, which can become a bottleneck in high-speed operations. Carry chain blocks efficiently handle these carry bit calculations, enabling faster and more efficient arithmetic operations. A carry chain block typically consists of a series of full adder circuits interconnected in a specific manner to form a carry chain. Each full adder circuit calculates one bit of output and a carry bit passed to the next stage of the chain. By chaining these full adder circuits together, the carry bit propagates through the chain over a single clock cycle, enabling fast addition and subtraction of multi-bit numbers. In addition to providing fast arithmetic operations, carry chain blocks can also be used to implement counters and other sequential circuits that require carry bit calculation.

[0011] A timing report tool is a software tool used to analyze the timing performance of a design implemented on an FPGA. This tool generates a report that provides information on the timing characteristics of the design. This report includes information on the design's timing characteristics, including data path delay, critical path, set time and hold time, clock skew, and maximum operating frequency. The data path delay is the time it takes for a data signal to propagate through the logic elements of the FPGA.

[0012] A multiplexer, abbreviated as "MUX," is an electronic circuit that selects one of several input signals and transmits the selected input to an output line. The input-output structure of a multiplexer generally consists of several input lines, a select line, and one or more output lines. The number of input lines corresponds to the number of input signals that the multiplexer can select, and the select line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a select line that determines which of the four input signals to transmit to the output. The select line can be controlled by a binary code representing the selected input line. Multiplexers are frequently used to reduce the number of wires required to transmit data and control signals in digital systems. They can be used to implement functions such as data selectors, memory address decoders, and bus allocation circuits. An FPGA (1) provided according to one aspect of the present invention comprises: a first delay line part (20) into which an input pulse having a width of the time difference between the occurrence of a start signal and an end signal is input; The system is programmed to include: a code conversion part (30) that converts and outputs the order of elements of the thermometer code output by the first delay line part; and a calculation part (60) that determines the occurrence time difference using the conversion code output by the code conversion part, wherein the conversion code is a sorted order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops (FF) included in the first delay line part.

[0013] At this time, the FPGA (1) is programmed to further include a second delay line part into which the input pulse is input, and the code conversion part is configured to generate the conversion code by aligning and merging the elements of the thermometer code output by the first delay line part and the elements of the thermometer code output by the second delay line part according to a predetermined second criterion, and the predetermined second criterion may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops included in the first delay line part and the second delay line part.

[0014] At this time, the FPGA (1) may be programmed to further include: an input signal generating part (10) that generates an input pulse having a width of the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting part (40) that counts the number of clock pulses generated during the maintenance period of the input pulse; and a first thermometer code (TC1) output by the code conversion part at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion part at the rising edge of the clock pulse immediately after the last clock pulse among the generated clock pulses, and a calculation part that determines the value of the generated time difference using the number of counted clock pulses.

[0015] An FPGA provided according to another aspect of the present invention is programmed to include: a plurality of delay line parts into which an input pulse having a width of the time difference between the occurrence of a start signal and a end signal is input; a code conversion part that merges a plurality of thermometer codes output by the plurality of delay line parts and outputs a single conversion code; and a calculation part that determines the time difference using the conversion code; wherein the conversion code is a sequence of elements of the plurality of thermometer codes arranged according to a predetermined standard, and the predetermined standard may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops in the plurality of delay line parts.

[0016] At this time, the FPGA may be programmed to further include: an input signal generating part that generates the input pulse having a width of the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting part that counts the number of clock pulses generated during the maintenance period of the input pulse; and a first thermometer code (TC1) output by the code conversion part at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion part at the rising edge of the clock pulse generated immediately after the last clock pulse among the generated clock pulses, and an operation part that determines the value of the generated time difference using the number of counted clock pulses.

[0017] According to one aspect of the present invention, a non-volatile recording medium readable by an electronic device may have a binary file recorded thereon that includes configuration data configured to program the FPGA to implement a digital circuit comprising: a first delay line part (20) into which an input pulse having a width of the time difference between the occurrence of a start signal and a end signal is input using an FPGA; a code conversion part (30) that converts and outputs the order of elements of a thermometer code output by the first delay line part; and a calculation part (60) that determines the time difference using the conversion code output by the code conversion part. In this case, the conversion code is a sorted order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops (FF) included in the first delay line part.

[0018] At this time, the digital circuit further includes a second delay line part into which the input pulse is input; and the code conversion part is configured to generate the conversion code by aligning and merging the elements of the thermometer code output by the first delay line part and the elements of the thermometer code output by the second delay line part according to a predetermined second criterion, and the predetermined second criterion may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops included in the first delay line part and the second delay line part.

[0019] At this time, the digital part may further include: an input signal generating part (10) that generates the input pulse having a width of the time difference between the rising edge of the start signal and the rising edge of the end signal; a clock pulse counting part (40) that counts the number of clock pulses generated during the maintenance period of the input pulse; and a first thermometer code (TC1) output by the code conversion part at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion part at the rising edge of the clock pulse generated immediately after the last clock pulse among the generated clock pulses, and a calculation part that determines the value of the generated time difference using the number of counted clock pulses.

[0020] According to another aspect of the present invention, a non-volatile recording medium readable by an electronic device may have a binary file recorded thereon containing configuration data configured to program the FPGA to implement a digital circuit comprising: a plurality of delay line parts into which an input pulse having a width of the time difference between the occurrence of a start signal and a end signal is input; a code conversion part that merges a plurality of thermometer codes output by the plurality of delay line parts and outputs a single conversion code; and a calculation part that determines the time difference using the conversion code. In this case, the conversion code is a sequence of elements of the plurality of thermometer codes arranged according to a predetermined standard, and the predetermined standard may be a data path delay from the output node of the input pulse to the output nodes of each of the plurality of flip-flops in the plurality of delay line parts.

[0021] A TDC system provided according to one aspect of the present invention may include a PCB board (100) including the above-described FPGA (1); and a computing device (200) that obtains the occurrence time difference from the PCB board.

[0022] According to one aspect of the present invention, a non-volatile recording medium readable by an electronic device may be provided, wherein a binary file containing configuration data configured to program the FPGA to implement a digital circuit comprising: a group of TDCs using an FPGA; a clock generation unit that generates a clock and provides it commonly to the group of TDCs; a tag counter configured to generate a second count, which is a value obtained by counting the clock, and provide it commonly to the group of TDCs; and a processing unit. Any TDC among the group of TDCs includes: an input signal generation part that generates an input pulse having a rising edge occurring at the same time as the rising edge of a start signal input to the arbitrary TDC; and a delay line part into which the generated input pulse is input. At this time, the processing unit calculates a first value by multiplying the value of the second count (TC) observed at the time of occurrence of the first newly generated clock pulse of the clock after the rising edge of the start signal input to the arbitrary TDC occurs by the pulse period (CP) of the clock, and calculates the time of occurrence of the first start signal by subtracting the thermometer code output by the delay line part or the converted code of the thermometer code from the first value at the time of the rising edge of the first newly generated clock pulse.

[0023] At this time, the arbitrary TDC is configured to operate in either a first mode or a second mode, and the arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode, and the arbitrary TDC may be configured to receive a termination signal in the first mode. Furthermore, when the termination signal is input to the arbitrary TDC, the input signal generation part may be configured to generate the input pulse such that the width of the input pulse is equal to the time difference between the rising edge of the start signal and the rising edge of the termination signal. Furthermore, when the arbitrary TDC operates in the first mode, the processing unit is configured to calculate the time difference between the start signal and the termination signal using the thermometer code output by the delay line part of the arbitrary TDC at the time of the rising edge of the first newly generated clock pulse, and when the arbitrary TDC operates in the second mode, it may be configured to calculate the time of occurrence of the start signal.

[0024] At this time, the arbitrary TDC may further include a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. And when the arbitrary TDC operates in the first mode, the processing unit may be configured to determine the value of the occurrence time difference using the thermometer code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the thermometer code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part.

[0025] At this time, the arbitrary TDC may further include: a code conversion part that outputs a conversion code generated by converting the order of elements of the thermometer code output by the delay line part; and a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. And when the arbitrary TDC operates in the first mode, the processing unit may be configured to determine the value of the occurrence time difference using the first thermometer code output by the code conversion part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the second thermometer code output by the code conversion part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part.

[0026] At this time, the processing unit may be configured to determine the relationship between a first occurrence time, which is the occurrence time of the start signal input to any TDC among the TDCs of the group, and a second occurrence time, which is the occurrence time of the second start signal input to another TDC among the TDCs of the group. And on the circuit plane of the FPGA, the tag counter may be placed inside an area connecting the areas occupied by the TDCs of the group.

[0027] According to one aspect of the present invention, the system is programmed to include: a group of TDCs (100) having identical configurations; a clock generation unit (140) that generates a clock and provides the generated clock to the TDCs in common; a tag counter (130) that generates a second count, which is a value obtained by counting the clock, and provides the generated second count to the TDCs in common; and a processing unit (160). The first TDC among the group of TDCs comprises an input signal generation part (10) that generates a first input pulse (P1) having a rising edge that occurs at the same time as the rising edge of a first start signal (S1) input to the first TDC. An FPGA may be provided that includes a delay line part (20) into which the first input pulse generated above is input, wherein the processing unit calculates a first value by multiplying the value of the second count (TC) observed at the time of occurrence of the first clock pulse that is newly generated after the rising edge of the first start signal input to the first TDC is generated by the pulse period (CP) of the clock, and calculates the time of occurrence of the first start signal by subtracting the thermometer code output by the delay line part of the first TDC or the converted code converted from the thermometer code from the first value at the time of occurrence of the rising edge of the first clock pulse that is newly generated.

[0028] At this time, the first TDC is configured to operate in either a first mode or a second mode, and the first TDC is configured to generate the first input pulse in both the first mode and the second mode, and the first TDC may be configured to receive a first termination signal in the first mode. When the first termination signal is input to the first TDC, the input signal generation part may be configured to generate the first input pulse such that the width of the first input pulse is equal to the time difference between the rising edge of the first start signal and the rising edge of the first termination signal. Furthermore, when the first TDC operates in the first mode, the processing unit is configured to calculate the time difference between the first start signal and the first termination signal using the thermometer code output by the delay line part of the first TDC at the time of the rising edge of the first newly generated clock pulse, and when the first TDC operates in the second mode, it may be configured to calculate the time of occurrence of the first start signal.

[0029] At this time, the first TDC may further include a clock pulse count part (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse. And when the first TDC operates in the first mode, the processing unit may be configured to determine the value of the occurrence time difference using the thermometer code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, the thermometer code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count part.

[0030] At this time, the first TDC may further include a code conversion part (30) that outputs a conversion code generated by converting the order of elements of the thermometer code output by the delay line part; and a clock pulse count part (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse. And when the first TDC operates in the first mode, the processing unit may be configured to determine the value of the occurrence time difference using the first thermometer code output by the code conversion part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, the second thermometer code output by the code conversion part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count part.

[0031] At this time, the conversion code is a sequence of elements of the thermometer code output by the delay line part according to a predetermined standard, and the predetermined standard may be a data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops (FF) included in the delay line part.

[0032] At this time, the processing unit may be configured to determine the relationship between the first occurrence time, which is the occurrence time of the first start signal input to the first TDC among the TDCs of the group, and the second occurrence time, which is the occurrence time of the second start signal input to the second TDC among the TDCs of the group. And on the circuit plane of the FPGA, the tag counter may be placed inside an area (1000) that connects the areas occupied by the TDCs of the group.

[0033] At this time, the first TDC may further include a clock pulse count part (40) that outputs a first count, which is a result of counting the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse; and a count selection part (60) configured to select and output the first count among the first count and the second count in the first mode, and to select and output the second count among the first count and the second count in the second mode.

[0034] At this time, if the first termination signal is not input to the first TDC operating in the first mode, the processing unit may be configured to extinguish the first input pulse when the calculation of the occurrence time of the first start signal is completed.

[0035] According to another aspect of the present invention, a non-volatile recording medium storing program instructions executable in an electronic device may be provided. The electronic device comprises a group of TDCs having the same configuration, a clock generation unit that provides a clock in common to the group of TDCs, a tag counter configured to generate a second count, which is a value obtained by counting the clock, and provide it in common to the group of TDCs, and a processing unit. Each of the TDCs includes an input signal generation part and a delay line part. When the program instructions are executed in the electronic device, the input signal generation part of any TDC in the group of TDCs generates an input pulse having a rising edge that occurs at the same time as the rising edge of a start signal input to the arbitrary TDC; and the delay line part of the arbitrary TDC outputs a code among a thermometer code of the input pulse and a conversion code obtained by converting the thermometer code at the time of the rising edge of the clock pulse of the clock that occurs for the first time after the rising edge of the start signal occurs. and the processing unit calculates a first value by multiplying the value of the second count observed at the time of occurrence of the first newly generated clock pulse by the pulse period of the clock, and calculates the time of occurrence of the first start signal by subtracting any one of the output codes from the first value; the step is executed.

[0036] At this time, when the above program instructions are executed in the electronic device, the arbitrary TDC is configured to operate in either a first mode or a second mode, and the arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode, and the arbitrary TDC is configured to receive a termination signal in the first mode, and when the termination signal is input to the arbitrary TDC, the input signal generation part is configured to generate the input pulse such that the width of the input pulse is equal to the time difference between the rising edge of the start signal and the rising edge of the termination signal, and the processing unit is configured to calculate the time difference between the start signal and the termination signal using any one of the codes output by the delay line part of the arbitrary TDC at the time of the rising edge of the first newly generated clock pulse when the arbitrary TDC operates in the first mode, and otherwise, when the arbitrary TDC operates in the second mode, it may be configured to calculate the time of occurrence of the start signal.

[0037] At this time, each of the above TDCs may further include a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. And when the above program instructions are executed in the electronic device, if the arbitrary TDC operates in the first mode, the processing unit may be configured to execute a step of determining the value of the occurrence time difference using the one code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the one code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part.

[0038] At this time, each of the above TDCs may further include a code conversion part that outputs a conversion code generated by converting the order of elements of the thermometer code output by the delay line part; and a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. And when the above program instructions are executed in the electronic device, if the arbitrary TDC operates in the first mode, the processing unit may further execute a step of determining the value of the occurrence time difference using the first thermometer code output by the code conversion part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the second thermometer code output by the code conversion part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part.

[0039] At this time, when the above program instructions are executed in the electronic device, the processing unit may further execute a step of determining the relationship between a first occurrence time, which is the occurrence time of the start signal input to any TDC among the group of TDCs, and a second occurrence time, which is the occurrence time of the second start signal input to another TDC among the group of TDCs. On the circuit plane of the FPGA, the tag counter may be placed inside an area connecting the areas occupied by the group of TDCs.

[0040] At this time, the electronic device may be an FPGA.

[0041] According to another aspect of the present invention, a TDC system may be provided comprising: a PCB board (100) including the above-described FPGA; and a computing device (200) for obtaining the occurrence time difference from the PCB board. Effects of the invention

[0042] According to the present invention, a TDC can be provided that provides a function of time tagging the occurrence time of a single signal representing a single event. Brief explanation of the drawing

[0043] Figure 1 shows a configuration diagram of an FPGA according to one embodiment of the present invention. FIG. 2 is a diagram illustrating an input pulse input to a first delay line part according to an embodiment of the present invention. FIG. 3 shows the configuration of a first delay line part according to one embodiment of the present invention. Figure 4 is a diagram illustrating the indices of the buffers in Figure 3. FIG. 5 shows a table for explaining data pass delay according to one embodiment of the present invention. FIGS. 6a and FIGS. 6b show a plurality of delay line parts configured in parallel according to one embodiment of the present invention. Figure 7a shows the configuration of the first delay line part and the second delay line part of Figure 6b. FIG. 7b shows a change in the configuration of the FPGA of FIG. 1 when a second delay line part is added in addition to the first delay line part. FIG. 7c is intended to explain the operation of a code conversion part when two delay line parts are used according to an embodiment of the present invention. Figure 8 shows a graph of delay depending on whether a code conversion part is applied according to one embodiment of the present invention. FIG. 9 is a diagram for explaining the arrangement criteria of flip-flop output values ​​according to whether a code conversion part is applied and the increase value of the number of taps in FIG. 8 according to an embodiment of the present invention. FIG. 10 shows the configuration of an FPGA provided according to a preferred embodiment of the present invention. FIGS. 11a to 11c are intended to explain the configuration and operation method of any one of the multiple TDCs presented in FIG. 10. FIG. 12 is a diagram illustrating an input pulse input to a delay line part according to an embodiment of the present invention. FIG. 13a shows the relative positions of a plurality of TDCs, a tag counter, and an input multiplexer presented in FIG. 10 on the surface of an actual circuit implemented on an FPGA according to one embodiment of the present invention. FIGS. 13b and FIGS. 13c conceptually illustrate the features of the present invention presented in FIG. 13a. FIG. 14 is a flowchart illustrating a signal generation time calculation method for calculating the generation time of a predetermined input signal, provided according to one embodiment of the present invention. FIG. 15 is a flowchart illustrating a method for calculating the time difference between a predetermined start signal and an end signal input, provided according to an embodiment of the present invention. FIG. 16 is a block diagram of a TDC system provided according to one embodiment of the present invention. Specific details for implementing the invention

[0044] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terms used in this specification are intended to aid in understanding the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular forms used below include plural forms unless the phrases clearly indicate otherwise.

[0045] Configuration for measuring the time difference between two events

[0046] Figure 1 shows a configuration diagram of an FPGA according to one embodiment of the present invention.

[0047] FIG. 2 is a diagram illustrating an input pulse input to a first delay line part according to an embodiment of the present invention.

[0048] The following description will be explained with reference to FIGS. 1 and FIGS. 2.

[0049] The FPGA (1) may include an input signal generation part (10), a first delay line part (20), a code conversion part (30), a clock pulse count part (40), a priority encoder part (50), and an operation part (60).

[0050] Specifically, the configurations of the FPGA (1) described above may be configurations of a TDC (Time to Digital converter).

[0051] As shown in FIG. 2, the input signal generating part (10) can generate an input pulse (P1) having a width of the time difference (T) between the rising edge (E1) of a given start signal (S1) and the rising edge (E2) of a given end signal (S2). The input signal generating part (10) may be composed of logic gates necessary for the generation.

[0052] The first delay line part (20) can receive an input pulse (P1) having a width of the time difference (T) between the start signal (S1) and the end signal (S2). The first delay line part (20) can output a thermometer code (O1). At this time, the thermometer code is, for example, an 8-bit value composed of the output values ​​of flip-flops included in the first delay line part (20), and the output value of each flip-flop can be referred to as an element of the thermometer code.

[0053] FIG. 3 shows the configuration of a first delay line part according to one embodiment of the present invention.

[0054] Figure 4 is a diagram illustrating the indices of the buffers in Figure 3.

[0055] The first delay line part (20) may include a delay line (D_L) comprising a plurality of buffers (delay elements, delay elements) (B) and D-flip-flops (FF) tapped to the output terminals of each buffer (B) of the delay line.

[0056] Multiple buffers can be connected in a cascade delay manner. That is, multiple buffers can be arranged according to the order in which the input pulse (P1) flows.

[0057] The waveform (Signal) of the input pulse (P1) of FIG. 3 can be output with a predetermined delay at the output terminal of each buffer (B). That is, the output value of the first buffer (B1) is output with a predetermined delay at the output terminal of the first buffer (B1), and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value of the first buffer (B1) (e.g., '1') can also be input to the first flip-flop (FF1).

[0058] That is, the signal entered into the input terminal of the [k]-th buffer can be output from the output terminal of the [k]-th buffer with a predetermined delay. And the output terminal of the [k]-th buffer can be connected to the input terminal of the [k+1]-th buffer. The output value of the [k]-th buffer (e.g., '1' or '0') can also be input to the [k]-th flip-flop.

[0059] At this time, a data path delay may occur between each buffer (B) and through the flip-flop (FF). For example, a delay of d1 may occur until the input value ('1') of the first buffer (B1) is transferred to the second buffer (B2), and a delay of d11 may occur until the output value ('1') of the first buffer (B1) is transferred to the first flip-flop (FF1). Similarly, a delay may occur whenever data is transferred from the previous buffer to the next buffer, and a delay may occur whenever data is transferred from any buffer to the flip-flop connected to the said buffer.

[0060] FIG. 4 is a diagram illustrating the index of a buffer according to one embodiment of the present invention.

[0061] Each field of the table in Figure 4 represents the buffer name, index, and output value of each buffer.

[0062] Each buffer may be assigned an index that defines the connection order of each buffer. For example, the first buffer (B1) may be assigned index '1', the second buffer (B2) may be assigned index '2', and likewise the eighth buffer (B8) may be assigned index '8'. In this way, when each buffer (B) is arranged according to the order in which the input pulse (P1) flows and the indices are arranged according to that order, for example, 1000 buffers may each be assigned an index from 1 to 1000.

[0063] FIG. 5 shows a table for explaining the data path delay considered in one embodiment of the present invention.

[0064] Referring to FIGS. 1 and FIGS. 5, the code conversion part (30) can convert and output the sequence of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line part (20). At this time, the code output by the code conversion part (30) (e.g., 11010000) (the sequence of indices of the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) can be referred to as the 'conversion code (CO1)'.

[0065] The conversion code (CO1) output by the code conversion part (30) may be one in which the order of the elements of the thermometer code (O1) is arranged according to a predetermined standard. In this case, the predetermined standard may be the data path delay from the output node (N1) of the input pulse (P1) to the output nodes (N2) of each of the plurality of flip-flops (FF) included in the first delay line part (20). This will be explained in detail with reference to FIG. 5.

[0066] Each field of the table may represent a buffer index number, a value of the first delay, a value of the second delay, and a sum value (rank). In this case, the rank may represent the rank among all sum values. In this case, the buffer with the smallest sum value may have the 1st rank, and the buffer with the highest sum value may have the last rank. Alternatively, in another embodiment, the opposite is possible.

[0067] As described above in FIG. 3, the sum value may represent the time taken for data to be transmitted from the node (N1) where the input pulse (P1) is output to any flip-flop (e.g., FF4).

[0068] A first delay, which is the time taken for the input value of an arbitrary buffer to be transmitted to another buffer connected to the arbitrary buffer, and a second delay, which is the time taken for the output value of the arbitrary buffer to be transmitted to the input of a flip-flop connected to the arbitrary buffer, may occur.

[0069] At this time, the value obtained by adding the value of the first delay and the value of the second delay for each buffer can be referred to as the data path delay.

[0070] Referring to FIG. 3 and FIG. 5 together, when the indices of each buffer are listed in order, the rank of the sum of the first delay value and the second delay value may differ from the rank of the index number of each buffer. For example, in the case of the third buffer, the buffer array rank is 3rd, so the index number is '3', but the rank of the sum value may be '5'. Upon closer examination, in order for data to be transmitted to the third flip-flop (FF3), it passes through the first buffer (B1), the second buffer, and the third buffer. At this time, a predetermined delay (d1, d2, d3) occurs each time it passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur until the data output from the third buffer (B3) is output as the output value of the third flip-flop (FF3). That is, the delay until data is transferred from the output node (N1) of the input pulse (P1) to the output node (N2, N23) of the third flip-flop (FF3) may be the sum of d1, d2, d3, and d13.

[0071] In this way, the delay (i.e., sum) until data is transmitted to the output node of each flip-flop (FF3) can be calculated.

[0072] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3 and the buffer index for the fourth flip-flop (FF4) is 4. That is, the fourth flip-flop (FF3) must pass through one more buffer than the third flip-flop (FF4), but nevertheless, the sum of the delays to the output node of the third flip-flop with a buffer index of 3 may be greater.

[0073] The code conversion part (30) can convert the order of the elements of the thermometer code (O1) based on the calculated delay (sum value) (e.g., from the smallest sum value).

[0074] The converted code (CO1) output by the code conversion part (30) can be provided to the priority encoder part (50).

[0075] The first encoder part (50) can digitize a long thermometer code. For example, the first encoder part (50) can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if the buffer (delay element) (B) and the flip-flop (FF) connected to the buffer described above in FIG. 3 each have 5200 numbers, a sequence of 5200 consecutive binary numbers is output, which can be represented as a 13-bit binary number.

[0076] That is, the first encoder part (50) can represent the 5200-bit first thermometer code (TC1) and the second thermometer code (TC2) as 13-bit binary numbers as the time-dependent output value (CO1) of the code conversion part (30).

[0077] Referring to FIG. 2, the first thermometer code (TC1) may be a code output by the code conversion part (30) in relation to the rising edge of the input pulse (P1) at the time of the rising edge (E4) of the first clock pulse (CK2) that occurs after the rising edge (E1) of the input pulse (P1) among the generated clock pulses (CK). The first thermometer code (TC1), expressed in 13 bits, may be provided as an input to the operation part (60).

[0078] And the second thermometer code (TC2) may be a code output by the code conversion part (30) in relation to the falling edge (E2) of the input pulse (P1) at the time of the rising edge (E6) of the first clock pulse (CK4) that occurs after the falling edge (E2) of the input pulse (P1) among the generated clock pulses (CK). The second thermometer code (TC2), expressed in 13 bits, may be provided as an input to the operation part (60).

[0079] At this time, the time interval of the first thermometer code (TC1) and the time interval of the second thermometer code (TC2) may be smaller than the period of the clock pulse (CK).

[0080] Referring again to FIGS. 1 and FIGS. 2, the clock pulse count part (40) can receive an input pulse (P1) from the input signal generation part (10).

[0081] The clock pulse count part (40) can count the number of clock pulses (CK) that occur during the maintenance period (T) of the input pulse (P1). For example, in FIG. 2, since there are two rising edges of the clock pulses that occur during the period when the input pulse (P1) is in the ON state, such as the edges (E4, E5), the counted value may be two. The clock pulses may refer to pulses that constitute a clock generated inside or outside the TDC.

[0082] The output value (Coarse count) of the clock pulse count part (40), that is, the counted value, can be provided to the calculation part (60).

[0083] Referring to FIGS. 1 and 2, the operation part (60) can determine the value of the occurrence time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses.

[0084] That is, the above-mentioned time difference can be calculated as in Equation 1.

[0085] [Formula 1]

[0086] T = CP * CC + TC1 - TC2

[0087] In Equation 1, T is the time difference between the start signal and the end signal, CP is the period of occurrence of clock pulses, CC is the number of clock pulses counted by the clock pulse count part (40), TC1 is the first thermometer code, and TC2 is the second thermometer code.

[0088] For example, in the example of Fig. 2, the above-mentioned time difference may be 2*Period+TC1-TC2.

[0089] FIGS. 6a and FIGS. 6b show a plurality of delay line parts configured in parallel according to one embodiment of the present invention.

[0090] As shown in FIG. 6a, two or more delay line parts (20) may be connected in parallel. At this time, the input pulse (P1) output from the input signal generating part (10) may be input to the first delay line part (21), the second delay line part (22), the third delay line part (23), and the fourth delay line part (24), respectively. Also, the first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line part (21), the second delay line part (22), the third delay line part (23), and the fourth delay line part (24) may be input to the code conversion part (30).

[0091] In another embodiment as shown in FIG. 6b, it can be assumed that two delay line parts (20) are connected in parallel.

[0092] For example, an input pulse (P1) output from an input signal generating part (10) can be provided along a first path (path1) in which the output terminal of the input signal generating part (10) and the input terminal of the first delay line part (21) are connected to each other, and a second path (path2) in which the output terminal of the input signal generating part (10) and the input terminal of the second delay line part (22) are connected to each other.

[0093] At this time, the time it takes for the input pulse (P1) output from the input signal generation part (10) to reach the input terminal of the first delay line part (21) and the input terminal of the second delay line part (22) may be different. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path). In the embodiment of FIG. 6a, since the length of the first path (path1) is shorter than the length of the second path (path2), it can be seen that the input time interval of the input pulse (path1) through the first path (path1) is smaller than the input time interval of the input pulse (path2) through the second path (path2).

[0094] Figure 7a shows the configuration of the first delay line part and the second delay line part of Figure 6b.

[0095] FIG. 7b shows a change in the configuration of the FPGA of FIG. 1 when a second delay line part is added in addition to the first delay line part.

[0096] FIG. 7c is intended to explain the operation of a code conversion part when two delay line parts are used according to an embodiment of the present invention.

[0097] In Fig. 7a, for convenience of explanation, the buffers and flip-flops within each delay line part are each shown as containing 4.

[0098] In FIG. 7c, each field of the table may represent a delay line part number, a buffer index number, a value of the first delay, a value of the second delay, a first sum value (first rank), and a first sum value (overall rank). In this case, the first rank may represent the rank of each sum value for the buffer index of the buffers within each delay line part. The overall rank may represent the rank of each sum value for the buffer index of all buffers in the first delay line part and the second delay line part. In this case, the first rank and overall rank may have the buffer with the smallest sum value as the first rank and the buffer with the highest sum value as the last rank. Alternatively, in another embodiment, the opposite may be possible. The method for calculating the sum value may be as described in FIG. 5.

[0099] The code conversion part (30) may be configured to generate a single conversion code by arranging and merging the elements of a first set (e.g., {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) in which the sum of the elements of the thermometer code output by the first delay line part (21) and buffer index pairs are arranged in order of lowest sum, and the elements of a second set (e.g., {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) in which the sum of the elements of the thermometer code output by the second delay line part (22) and index pairs are arranged in order of lowest sum.

[0100] That is, each element of the first set and each element of the second set can be sorted in order of lowest sum value.

[0101] For example, in the first delay line part (21), the output value based on the buffer index may be {1, 2, 3, 4}, and in the second delay line part (22), the output value based on the buffer index may be {5, 6, 7, 8}. Also, in the embodiment of FIG. 6b and FIG. 7a, the delay (d1) may be smaller than the delay (d5). Thus, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output values ​​of the flip-flops for each buffer index may be sorted according to the sorted order. For example, the sorted values ​​(buffer indices) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0102] As described above, when multiple delay line parts (20) are used, they may have slightly different input delays depending on the arrangement. FIG. 8, which is described below, shows the delay according to the arrangement when multiple delay line parts are used.

[0103] Figure 8 shows a graph of delay depending on whether a code conversion part is applied according to one embodiment of the present invention.

[0104] FIG. 9 is a diagram for explaining the arrangement criteria of flip-flop output values ​​according to whether a code conversion part is applied and the increase value of the number of taps in FIG. 8 according to an embodiment of the present invention.

[0105] FIG. 8 (a) shows a delay graph according to the number of tabs when the code conversion part (30) is not applied, and FIG. 8 (b) shows a delay graph according to the number of tabs when the code conversion part (30) is applied.

[0106] The fields of the table in Fig. 9 include the arrangement criteria of flip-flop output values ​​before and after alignment, and the arrangement order of the total delay sum value.

[0107] The following explanation will be provided with reference to FIGS. 8 and FIGS. 9.

[0108] The horizontal axis of the graph (g1, g2) represents the number of taps. Referring to FIG. 7c, one tap may represent a pair of a buffer (delay element) (e.g., B1) and a flip-flop (FF1) connected thereto. For example, if the total number of pairs of buffers and flip-flops connected thereto is 1000, the total number of taps may be 1000.

[0109] The vertical axis of the graph (g1, g2) represents the delay time (ns). The above delay time may represent the sum of the delays required to transmit data to the output node of the flip-flop tapped in each buffer described in FIG. 5.

[0110] Referring to FIGS. 7a through 9 together, an increase in the number of taps in graph (g1) may mean, for example, an increase in the buffer index. For example, if the number of taps on the horizontal axis of graph (g1) is 4, it may mean buffer index 4. In this case, the delay value on the vertical axis of graph (g1) may be D4 (=d1+d2+d3+d4+d14) as shown in FIG. 7c. For example, if the number of taps is 5, it may mean buffer index 5. In this case, the delay value on the vertical axis of graph (g1) may be D5 (=d5+d15) as shown in FIG. 7c. In this case, referring to FIG. 9, D4 > D5. Here, it can be seen that the delay observed in each tap flip-flop does not increase as the tap index (e.g., index 4 -> index 5) increases, but rather there are cases where it decreases locally even if the tap index increases.

[0111] On the other hand, an increase in the number of taps in graph (g2) does not mean an increase in the buffer index, but rather an increase in the position according to the sorting order when the output values ​​of each flip-flop are sorted by the code conversion part (30). For example, if the number of taps on the horizontal axis of graph (g2) is 4, the position order of the sorted buffer index is 1, 2, 5, 3, which may mean buffer index 3. In this case, the delay value on the vertical axis of graph (g2) may be D3 (=d1+d2+d3+d13). For example, if the number of taps is 5, the position order of the sorted buffer index is 1, 2, 5, 3, 6, which may mean buffer index 6. In this case, the delay value may be D6 (=d5+d6+d16). At this time, referring to FIG. 9, D3 <D6 일 수 있다.

[0112] That is, as shown in FIG. 8 (a), when the code conversion part (30) of the present invention is not applied, it can be seen that the graph (g1) for delay according to the increase in the number of taps does not exhibit a monotonically increasing property. On the other hand, as shown in FIG. 8 (b), when the code conversion part (30) of the present invention is applied, it can be seen that the graph (g2) for delay according to the increase in the number of taps exhibits an increasing phenomenon without a decrease.

[0113] For example, unlike ASICs, which are application-specific semiconductors, FPGAs, which can be directly designed through programming, can change the functions of the chip according to the programming. Therefore, unlike ASICs, the functions of each component included in an FPGA can vary (or depending on the arrangement of the components), so the delay may not always increase as the number of taps increases, but may decrease, thus preventing an increase without decrease.

[0114] However, as explained, it can be confirmed through the graph (g2) that the code conversion part (30) can correct the monotonically increasing nature of the first delay line part (20).

[0115] As described above, when multiple delay line parts (20) are used, the alignment of the delay can be provided through the code conversion part. As a result, errors caused by jitter can be corrected and a TDC with high time resolution can be provided. For example, if four delay line parts are configured in parallel to have a total of 9600 taps, a TDC with a resolution of 0.8 ps per tap can be provided.

[0116] Configuration for tagging the occurrence time of a single event

[0117] FIG. 10 shows the configuration of an FPGA provided according to a preferred embodiment of the present invention.

[0118] The configuration of the FPGA (1) shown in FIG. 10 can be implemented by a binary file containing configuration data that is configured to program the FPGA (1) to implement a digital circuit having the configuration of FIG. 10.

[0119] The FPGA (1) shown in FIG. 10 may include one or more TDCs. A TDC may be represented by reference numeral 100, and different TDCs may be represented as TDCx (e.g., TDC1 (101), TDC2 (102), TDC3 (103), TDC4 (104), ...).

[0120] The above one or more TDCs may all have the same internal configuration, that is, they may all operate in the same way.

[0121] The FPGA (1) may include an input multiplexer (150) that provides a start signal and a stop signal to each TDC (100). The input multiplexer (150) may receive event pulses representing events that the FPGA (1) intends to detect, and may output the event pulses as the start signal or stop signal for each TDC (100) according to a predetermined rule.

[0122] The FPGA (1) may include a tag counter (130).

[0123] The FPGA (1) may include a clock generation unit (140). Part or all of the TDC (100) included in the FPGA (1) and the tag counter (130) may receive the clock generated by the clock generation unit (140). Therefore, the clock generated by the TDC (100) may be referred to as a common clock.

[0124] The tag counter (130) can provide a second count, which is the result of counting the number of occurrences of the input clock, to some or all of the TDC (100) included in the FPGA (1). The second count may also be called a 'tag count' or a 'global count'.

[0125] Each TDC (100) may be configured to operate in one of two modes. The mode selection signal, which is a signal determining the operating mode of each TDC (100), is indicated by the symbol 'Mode Sel' in FIG. 10. The operating mode of each TDC (100) may be determined by an external device of the TDC (100). The two modes are described in more detail later in this specification.

[0126] As described above, each TDC (100) can receive a start signal and an end signal provided by an input multiplexer (150), a clock provided by a clock generator (140), and a second count provided by a tag counter (130).

[0127] Each TDC (100) can output three output signals, which are denoted as TC1, TC2, and CNT, respectively, in FIG. 10. The meanings of these three symbols will be explained in more detail later in this specification.

[0128] The FPGA (1) may include one or more DMA units. The DMA units may be represented by reference numeral 110, and different DMAs may be represented as DMAx (e.g., DMA1 (111), DMA2 (112), DMA3 (113), DMA4 (114), ...). DMAx corresponds to TDCx.

[0129] The three output signals output by each TDC (100) are provided to the corresponding DMA (110).

[0130] The input signal generation part (10) may further include a processing unit (160). The processing unit (160) receives signals output by the TDC (100) from the DMA (110) and can process them according to a predetermined algorithm.

[0131] FIG. 11 is intended to explain the configuration and operation method of any one of the multiple TDCs presented in FIG. 10.

[0132] The TDC (100) may include an input signal generation part (10), a delay line part (20), a data sampling part (70), and a priority encoder part (50).

[0133] The data sampling unit (70) may include a code conversion part (30), a clock pulse count part (40), and a count selection unit (60).

[0134] The count selection unit (60) may receive a first count output by the clock pulse count part (40) and a second count output by the tag counter (130) of FIG. 10. The count selection unit (60) may be configured to select and output either the first count or the second count according to the mode selection signal (Model Sel) input to the TDC (100).

[0135] The configuration and function of the input signal generation part (10), delay line part (20), code conversion part (30), clock pulse count part (40), and priority encoder part (50) are identical to those of the components having the same reference number as shown in FIG. 1 and FIG. 7b, so they are replaced by the above description.

[0136] FIG. 11b shows the case where the TDC of FIG. 11a operates in the first mode, and FIG. 11c shows the case where the TDC of FIG. 11a operates in the second mode.

[0137] The following is an explanation with reference to FIG. 11b.

[0138] Hereinafter, the case where the above mode selection signal (Model Sel) is a value representing the first mode is described. In this case, the input multiplexer (150) of FIG. 10 may provide the start signal and the end signal to the TDC (100). And in this case, the count selection unit (60) may be configured to select and output the first count output by the tag counter (130). In this case, the code conversion part (30) may output a first thermometer code (TC1) corresponding to the start signal and a second thermometer code (TC2) corresponding to the end signal. As a result, the TDC (100) may output the first thermometer code (TC1), the second thermometer code (TC2), and the first count (CNT).

[0139] The following is an explanation with reference to FIG. 11c.

[0140] Hereinafter, the case where the above mode selection signal (Model Sel) is a value representing the second mode is described. At this time, the input multiplexer (150) of FIG. 10 may provide the start signal to the TDC (100). At this time, the count selection unit (60) may be configured to select and output the second count output by the tag counter (130). At this time, although it is not strictly prohibited for the input multiplexer (150) of FIG. 10 to provide the end signal to the TDC (100), in a preferred embodiment, the input multiplexer (150) may not provide the end signal to the TDC (100). If the input multiplexer (150) does not provide the end signal to the TDC (100), the code conversion part (30) may not output the second thermometer code (TC2). However, even in this case, since the input multiplexer (150) provides a start signal to the TDC (100), the code conversion part (30) outputs the first thermometer code (TC1). As a result, the TDC (100) can output the first thermometer code (TC1) and the second count (CNT).

[0141] As illustrated in FIG. 10, each DMA (110) can provide signals output from the corresponding TDC (100) to the processing unit (160).

[0142] When a TDC (100) connected to any DMA (110) operates in the first mode, the any DMA (110) can transmit the first thermometer code (TC1), the second thermometer code (TC2), and the first count (CNT) output by the TDC (100) to the processing unit (160).

[0143] In contrast, when a TDC (100) connected to any DMA (110) operates in the second mode, the any DMA (110) can transmit the first thermometer code (TC1) and the second count (CNT) output by the TDC (100) to the processing unit (160).

[0144] The processing unit (160) can use information provided from any DMA (110) to determine the time difference between two consecutive events associated with said any DMA (110), or to determine the time of occurrence of a single event associated with said any DMA (110).

[0145] The processing unit (160) may be configured to know whether the TDC (100) connected to any DMA (110) operated in the first mode or in the second mode.

[0146] In one embodiment, the entity determining the value of the mode selection signal (Model Sel) input to the TDC (100) may be another functional unit not shown in FIG. 10, and in this case, the value of the mode selection signal (Model Sel) input to the TDC (100) may be provided to the processing unit (160).

[0147] In another embodiment, the entity determining the value of the mode selection signal (Model Sel) may be the processing unit (160).

[0148] When the TDC (100) connected to the arbitrary DMA (110) operates in the first mode, the processing unit (160) can determine the time difference between two consecutive events associated with the arbitrary DMA (110). That is, the processing unit (160) can execute the function of the computation part (60) of FIG. 1. The time of occurrence of the two events can be determined by the start signal and the end signal input to the TDC (100), respectively.

[0149] When the TDC (100) connected to the arbitrary DMA (110) operates in the second mode, the processing unit (160) can determine the time of occurrence of a series of single events associated with the arbitrary DMA (110). Here, the time of occurrence of the single event can be determined by a start signal input to the TDC (100). At this time, the processing unit (160) can know that the TDC (100) is operating in the second mode, and therefore can ignore information regarding a termination signal that may or may not be input to the TDC (100) without waiting. That is, the processing unit (160) can execute a predetermined routine regardless of whether a second thermometer code (TC2) that may be output by the TDC (100) operating in the second mode occurs.

[0150] When the TDC (100) that provided the data to be processed by the processing unit (160) operates in the first mode, the processing method of the processing unit (160) is presented in the above-described Equation 1 and FIG. 2. Now, when the TDC (100) that provided the data to be processed by the processing unit (160) operates in the second mode, the processing method of the processing unit (160) is explained using Equation 2 and FIG. 12.

[0151] [Equation 2]

[0152] T0 = ​​CP * TC - TC1

[0153] In Equation 2, T0 is the time of occurrence of the start signal, CP is the period of occurrence of clock pulses, TC is the number of occurrences of clock pulses counted by the tag counter (130) of FIG. 10, and TC1 is the first thermometer code.

[0154] FIG. 12 is a diagram illustrating an input pulse input to a delay line part according to an embodiment of the present invention.

[0155] As shown in FIG. 12, the input signal generating part (10) can generate an input pulse (P1) starting from the rising edge of a given starting signal (S1). That is, the rising edge of the input pulse (P1) occurs at the rising edge of the starting signal (S1).

[0156] Since the operating principle of the input signal generating part (10) presented in FIG. 11a is the same as that of the input signal generating part (10) presented in FIG. 1, if a termination signal is provided to the input signal generating part (10), a falling edge of the input pulse (P1) may occur and the input pulse (P1) may be extinguished. However, FIG. 12 presents an example in which the termination signal is not provided to the input signal generating part (10), so the falling edge of the input pulse (P1) does not occur.

[0157] If the above termination signal does not occur, the input pulse (P1) may continue semi-permanently. To eliminate the input pulse (P1), the processing unit (160) may reset the TDC (100) operating in the second mode after processing all the data provided by the TDC (100) operating in the second mode according to a predetermined algorithm. In this way, the input pulse (P1) output by the input signal generation part (10) may be eliminated. The input pulse (P1) may also be eliminated according to a design method different from the configuration described above. For example, the processing unit (160) may provide a dummy pulse, which is not a measurement target, to the TDC (100) operating in the second mode as the termination signal at an appropriate time.

[0158] In one embodiment, the TC of Equation 2 may be the occurrence number (e.g., 247) of the first clock pulse input to the tag counter (130) after the rising edge of the input pulse occurs. The TC of Equation 2 may be the same as the second count shown in FIG. 10.

[0159] And TC1 of the above formula 2 may be the first thermometer code (TC1) output by the code conversion part (30) at the rising edge of the first input clock pulse.

[0160] The processing unit (160) can determine the time of occurrence of the start signal input to the TDC (100) operating in the second mode by applying the clock period (CP) of the clock output by the second count (TC), the first thermometer code (TC1), and the clock generation unit (140) to Equation 2.

[0161] The multiple TDCs shown in Fig. 10 can each operate independently. To aid understanding, the following example is provided.

[0162] That is, two signals selected by the input multiplexer (150) can be provided as a start signal and a stop signal for the first TDC (101), respectively, and at this time, the mode selection signal (Model Sel 1) input to the first TDC (101) may have a value representing the first mode, and the processing unit (160) can analyze the data output by the first TDC (101) to calculate the time difference between the two signals.

[0163] At the same time or with a time difference, the input multiplexer (150) may provide the start signal or the end signal for the first TDC (101) and provide the second start signal for the second TDC (102) to the second TDC (102). At this time, the mode selection signal (Model Sel 2) input to the second TDC (102) may have a value representing the second mode, and the processing unit (160) may analyze the data output by the second TDC (102) to determine the time of occurrence of the second start signal.

[0164] FIG. 13a shows the relative positions of a plurality of TDCs, a tag counter, and an input multiplexer presented in FIG. 10 on the surface of an actual circuit implemented on an FPGA according to one embodiment of the present invention.

[0165] The values ​​related to the occurrence time of the start or end signal measured by each TDC may have a large error depending on the length of the track along which the start or end signal travels. Therefore, the location where the start or end signal is provided needs to be optimized.

[0166] Additionally, in the process of determining the occurrence time of the start signal measured by each TDC in the second mode, a clock commonly provided to the plurality of TDCs by the clock generation unit (140) is involved. If the time difference for the clock generated by the clock generation unit (140) to reach the input terminals of different TDCs (100) is large, there is a problem that the value regarding the occurrence time calculated by each of the plurality of TDCs includes a time axis bias. The time difference for the clock to reach the input terminals of different TDCs (100) may be proportional to the distance between the clock generation unit (140) and the input terminals of the different TDCs (100). Therefore, it must be designed so that the difference between the distances between the clock generation unit (140) and the input terminals of the different TDCs (100) is small.

[0167] To this end, as shown in FIG. 13a, one embodiment of the present invention is characterized by a plurality of TDCs being arranged inside a surrounded area.

[0168] Each TDC includes a delay line part (20), and in one embodiment of the present invention, the delay line part (20) has a shape that is extended in one direction on the actual circuit plane of the FPGA. Thus, one TDC has a shape that is extended in one direction.

[0169] FIGS. 13b and FIGS. 13c conceptually illustrate the features of the present invention presented in FIG. 13a.

[0170] Each TDC formed in the FPGA (1) has a shape that is long in one direction, and both ends can be defined along the extension direction of each TDC. For example, in FIG. 13b, both ends of the first TDC (101) are shown as reference numbers 1011 and 1012, both ends of the second TDC (102) are shown as reference numbers 1021 and 1022, both ends of the third TDC (103) are shown as reference numbers 1031 and 1032, and both ends of the fourth TDC (104) are shown as reference numbers 1041 and 1042.

[0171] FIG. 13c shows a case where there are only two TDCs receiving the common clock provided by the clock generation unit (140) of FIG. 10.

[0172] As illustrated in FIG. 13b and FIG. 13c, in a preferred embodiment of the present invention, the tag counter (130) is characterized by being placed inside a region (1000) that can form the ends of a plurality of the TDCs in succession. Configuration data configured to program the above-described FPGA (1) may include data that causes the tag counter (130) to be placed inside the region (1000).

[0173] FIG. 14 is a flowchart illustrating a signal generation time calculation method for calculating the generation time of a predetermined input signal, provided according to one embodiment of the present invention.

[0174] The method presented in FIG. 14 can be executed in a predetermined electronic device. In a preferred embodiment, the electronic device may be an FPGA, but the electronic device is not limited to an FPGA.

[0175] The above electronic device may include a group of TDCs having the same configuration, a clock generation unit that provides a clock in common to the group of TDCs, a tag counter configured to generate a second count, which is a value obtained by counting the clock, and provide it in common to the group of TDCs, and a processing unit. Each of the above TDCs may include an input signal generation part and a delay line part.

[0176] The above method for calculating the signal generation time may include the following steps (S110), (S120), and (S130).

[0177] In step (S110), the input signal generating part of any TDC among the group of TDCs can generate an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the arbitrary TDC.

[0178] In step (S120), the delay line part of the arbitrary TDC can output either the thermometer code of the input pulse or a converted code obtained by converting the thermometer code at the time of the rising edge of the clock pulse of the clock that first occurs after the rising edge of the start signal occurs.

[0179] In step (S130), the processing unit can calculate a first value by multiplying the value of the second count observed at the time of occurrence of the first newly generated clock pulse by the pulse period of the clock, and calculate the time of occurrence of the first start signal by subtracting any one of the output codes from the first value.

[0180] One embodiment of the present invention may further include the step (S140) described below after the step (S130) described above.

[0181] In step (S140), the processing unit may determine the relationship between a first occurrence time, which is the occurrence time of the start signal input to any TDC among the group of TDCs, and a second occurrence time, which is the occurrence time of the second start signal input to another TDC among the group of TDCs. For example, the difference value between the first occurrence time and the second occurrence time may be determined. At this time, in order to determine the second occurrence time, steps (S110), (S120), and (S130) may be executed separately and independently with respect to the second start signal.

[0182] At this time, the above arbitrary TDC may be configured to operate in either the first mode or the second mode.

[0183] At this time, the arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode, and the arbitrary TDC may be configured to receive a termination signal in the first mode.

[0184] At this time, when the termination signal is input to the arbitrary TDC, the input signal generating part may be configured to generate the input pulse such that the width of the input pulse is equal to the time difference between the rising edge of the start signal and the rising edge of the termination signal.

[0185] At this time, the processing unit is configured to calculate the time difference between the start signal and the end signal using any one of the codes output by the delay line part of the arbitrary TDC at the rising edge of the first newly generated clock pulse when the arbitrary TDC operates in the first mode, and, conversely, may be configured to calculate the time of occurrence of the start signal when the arbitrary TDC operates in the second mode.

[0186] FIG. 15 is a flowchart illustrating a method for calculating the time difference between a predetermined start signal and an end signal input, provided according to an embodiment of the present invention.

[0187] The method presented in FIG. 15 can be executed in a predetermined electronic device. In a preferred embodiment, the electronic device may be an FPGA, but the electronic device is not limited to an FPGA.

[0188] The above electronic device may include a group of TDCs having the same configuration, a clock generation unit that provides a clock in common to the group of TDCs, a tag counter configured to generate a second count, which is a value obtained by counting the clock, and provide it in common to the group of TDCs, and a processing unit. Each of the above TDCs may include an input signal generation part and a delay line part.

[0189] The method for calculating the time difference between the start signal and the end signal may include the following steps (S210), (S220), and (S230).

[0190] In step (S210), the input signal generating part of any TDC among the group of TDCs can generate an input pulse having a rising edge occurring at the same time as the rising edge of the start signal input to the arbitrary TDC and a falling edge occurring at the same time as the end signal input to the arbitrary TDC.

[0191] In step (S220), the delay line part of the arbitrary TDC can output a code of either the thermometer code of the input pulse or a converted code of the thermometer code.

[0192] In step (S230), the processing unit can determine the value of the occurrence time difference using any one code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, any one code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part.

[0193] FIG. 16 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0194] The TDC system (1000) may include a PCB board (600) and a computing device (700).

[0195] The PCB board (600) is a device capable of digital signal processing and may include the above-described FPGA (1), data interface (601), signal interface (602), clock generation unit (603), and power supply unit (604).

[0196] The data interface (601) is a device that enables data exchange between the PCB mode (600) and the computing device (700), and may be composed of USB, Ethernet, or UART, but is not limited thereto.

[0197] The signal interface (602) receives signals from the outside to measure the time difference using the FPAG (1) and transmits them to the FPGA (1).

[0198] The clock generation unit (603) can provide a train of clock pulses that the FPGA (1) counts.

[0199] The time difference value of two selected signals calculated by the FPGA (1) can be output from the FPGA (1) and provided to the data interface (601). The data interface (601) can provide the time difference value of the two signals to a computing device (700).

[0200] The power supply unit (104) supplies power used in the PCB board (600).

[0201] The computing device (700) may include a data interface (701), a CPU (702), and a memory (703).

[0202] The computing device (700) may be configured to execute a predetermined algorithm using the time difference value of two selected signals received from the PCB board (600). The time difference value of the two received signals may be processed by a process executed in the CPU (702). A program consisting of instructions for executing the process may be stored in memory (703). The program may be loaded from memory (703) into the CPU (702) and executed. The memory (703) may be a non-volatile memory.

[0203] Using the embodiments of the present invention described above, those skilled in the art will be able to easily make various changes and modifications within the scope of the essential characteristics of the present invention. The content of each claim of the patent claims may be combined with other claims that are not related by reference within the scope of what can be understood from this specification.

Claims

Claim 1 A group of TDCs (100) including a first TDC; a clock generation unit (140) that provides a clock to the first TDC; a tag counter (130) configured to provide a second count, which is a value obtained by counting the clock, to the first TDC; and a processing unit (160); wherein the first TDC is programmed to include an input signal generation part (10) that generates a first input pulse (P1) having a rising edge that occurs at the same time as the rising edge of a first start signal (S1) input to the first TDC; FPGA comprising: a delay line part (20) into which the first input pulse generated above is input; wherein the processing unit calculates a first value by multiplying the value of the second count (TC) observed at the time of occurrence of the first clock pulse that is newly generated after the rising edge of the first start signal input to the first TDC occurs by the pulse period (CP) of the clock, and calculates the time of occurrence of the first start signal by subtracting the thermometer code output by the delay line part of the first TDC or the converted code converted from the thermometer code from the first value at the time of the rising edge of the first clock pulse that is newly generated. Claim 2 In claim 1, the first TDC is configured to operate in either a first mode or a second mode, and the first TDC is configured to generate the first input pulse in both the first mode and the second mode, and the first TDC is configured to receive a first termination signal input to the first TDC in the first mode, and when the first termination signal is input to the first TDC, the input signal generation part is configured to generate the first input pulse such that the width of the first input pulse is equal to the time difference between the rising edge of the first start signal and the rising edge of the first termination signal, and the processing unit is configured to calculate the time difference between the first start signal and the first termination signal using the thermometer code output by the delay line part of the first TDC at the time of the rising edge of the first newly generated clock pulse when the first TDC operates in the first mode, and to calculate the time of occurrence of the first start signal when the first TDC operates in the second mode. FPGA. Claim 3 In paragraph 2, the first TDC further includes a clock pulse count part (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, and when the first TDC operates in the first mode, the processing unit is configured to determine the value of the occurrence time difference using the thermometer code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, the thermometer code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count part. Claim 4 In paragraph 2, the first TDC further comprises: a code conversion part (30) that outputs a conversion code generated by converting the order of elements of the thermometer code output by the delay line part; and a clock pulse count part (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, wherein when the first TDC operates in the first mode, the processing unit is configured to determine the value of the occurrence time difference using the first thermometer code output by the code conversion part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, the second thermometer code output by the code conversion part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count part. Claim 5 In paragraph 4, the conversion code is a sequence of elements of a thermometer code output by the delay line part according to a predetermined standard, and the predetermined standard is a data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops (FF) included in the delay line part, FPGA. Claim 6 In claim 1, the above group of TDCs further includes a second TDC having the same configuration as the first TDC, the clock generation unit is configured to provide the clock in common to the first TDC and the second TDC, the tag counter is configured to provide the second count in common to the first TDC and the second TDC, the processing unit is configured to determine the relationship between a first occurrence time, which is the occurrence time of the first start signal input to the first TDC, and a second occurrence time, which is the occurrence time of the second start signal input to the second TDC, and on the circuit plane of the FPGA, the tag counter is characterized by being placed inside an area (1000) that connects the areas occupied by the above group of TDCs. Claim 7 In paragraph 2, the FPGA further comprises: a clock pulse count part (40) which outputs a first count, which is a result of counting the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse; and a count selection part (60) which is configured to select and output the first count among the first count and the second count in the first mode, and to select and output the second count among the first count and the second count in the second mode. Claim 8 In paragraph 2, when the first termination signal is not input to the first TDC operating in the first mode, the processing unit is configured to extinguish the first input pulse when the calculation of the occurrence time of the first start signal is completed, an FPGA. Claim 9 A non-volatile recording medium storing program instructions executable in an electronic device, wherein the electronic device comprises a group of TDCs including one or more TDCs, a clock generation unit that provides a clock in common to the group of TDCs, a tag counter configured to generate a second count which is a value obtained by counting the clock and provide it in common to the group of TDCs, and a processing unit, wherein each of the TDCs included in the group of TDCs includes an input signal generation part and a delay line part, and when the program instructions are executed in the electronic device, the input signal generation part of any TDC in the group of TDCs generates an input pulse having a rising edge that occurs at the same time as the rising edge of a start signal input to the arbitrary TDC; and the delay line part of the arbitrary TDC outputs a code among a thermometer code of the input pulse and a converted code obtained by converting the thermometer code at the time of the rising edge of the clock pulse of the clock that occurs for the first time after the rising edge of the start signal occurs. A non-volatile recording medium characterized by the step of executing the processing unit, wherein the processing unit calculates a first value by multiplying the value of the second count observed at the time of occurrence of the first newly generated clock pulse of the clock by the pulse period of the clock, and calculates the time of occurrence of the start signal by subtracting any one of the output codes from the first value. Claim 10 A non-volatile recording medium according to claim 9, wherein when the program instructions are executed in the electronic device, the arbitrary TDC is configured to operate in either a first mode or a second mode, the arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode, the arbitrary TDC is configured to receive a termination signal in the first mode, and when the termination signal is input to the arbitrary TDC, the input signal generating part is configured to generate the input pulse such that the width of the input pulse is equal to the time difference between the rising edge of the start signal and the rising edge of the termination signal, and the processing part is configured to calculate the time difference between the start signal and the termination signal using any one code output by the delay line part of the arbitrary TDC at the time of the rising edge of the first newly generated clock pulse when the arbitrary TDC operates in the first mode, and otherwise, when the arbitrary TDC operates in the second mode, to calculate the time of occurrence of the start signal. Claim 11 A non-volatile recording medium according to claim 10, wherein each of the TDCs included in the above group of TDCs further includes a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse, and when the program instructions are executed in the electronic device, when any TDC operates in the first mode, the processing unit is configured to execute a step of determining the value of the occurrence time difference using any one code output by the delay line part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, any one code output by the delay line part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part. Claim 12 A non-volatile recording medium according to claim 10, wherein each of the TDCs included in the above group of TDCs further comprises: a code conversion part that outputs a conversion code generated by converting the order of elements of a thermometer code output by the delay line part; and a clock pulse count part that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse; wherein, when the program instructions are executed in the electronic device, if the arbitrary TDC operates in the first mode, the processing unit further executes the step of determining the value of the occurrence time difference using the first thermometer code output by the code conversion part at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the second thermometer code output by the code conversion part at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count part. Claim 13 In claim 9, the above group of TDCs includes a plurality of TDCs including the arbitrary TDC, and the plurality of TDCs all have the same configuration; when the program instructions are executed in the electronic device, the processing unit further performs the step of determining the relationship between a first occurrence time, which is the occurrence time of the start signal input to the arbitrary TDC among the group of TDCs, and a second occurrence time, which is the occurrence time of the second start signal input to another TDC among the group of TDCs; the electronic device is an FPGA, and on the circuit plane of the FPGA, the tag counter is disposed inside an area connecting the areas occupied by the group of TDCs. Claim 14 A non-volatile recording medium according to claim 9, characterized in that the electronic device is an FPGA. Claim 15 A TDC system comprising: a PCB board (100) including an FPGA of any one of claims 1 to 8; and a computing device (200) for obtaining, from the PCB board, the time difference between a first start signal input to the first TDC included in the FPGA and a first end signal input to the first TDC.

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