Ceramic electronic component, substrate arrangement and method of manufacturing ceramic electronic component

Abstract

A ceramic electronic component comprises a raw body and first and second external electrodes formed on the raw body. The raw body has a dielectric and first and second internal electrodes. The first external electrode comprises a first underlayer formed on the raw body. The first underlayer is connected to the first internal electrode, and the edge of the first underlayer is present on the first surface of the raw body. The first external electrode also comprises a first plating layer formed on the first underlayer. The edge of the first plating layer is present on the first surface of the raw body at a position different from the position of the edge of the first underlayer in a direction perpendicular to the first surface. The second external electrode has a structure similar to that of the first external electrode.

Description

Technology Field

[0001] The present invention relates to a ceramic electronic component, a substrate arrangement, and a method for manufacturing a ceramic electronic component. Background Technology

[0002] A multilayer ceramic capacitor generally comprises a ceramic element body in which a plurality of internal electrodes are arranged, and external electrodes formed on the surfaces of the ceramic element body. The external electrodes are connected to the internal electrodes in the ceramic element body. As the external electrodes are attached to a mounting substrate by means of solder or the like, the multilayer ceramic capacitor is mounted on the mounting substrate.

[0003] JP-A-2000-182879 discloses a terminal electrode having a multilayer structure comprising a first electrode layer and a second electrode layer. The second electrode layer is made of a conductive resin. The distal end of the covered portion of the second electrode layer extends at least 50 μm toward another terminal electrode than the distal end of the covered portion of the first electrode layer.

[0004] JP-A-2016-9836 discloses a structure for preventing cracks in a portion of a ceramic nonworked body corresponding to the free end of an external electrode that wraps around the ceramic nonworked body. To this end, JP-A-2016-9836 includes a resin layer between the side face of the ceramic nonworked body and the surface of the external electrode. The problem to be solved

[0005] In JP-A-2000-182879, a third electrode layer having a two-layer structure (a stack of a Ni plating layer and a solder plating layer) is formed on the second electrode layer. Thus, the leading edge of the first electrode layer and the leading edge of the third electrode layer are located on the same plane. As a result, the stress applied to the first electrode layer and the stress applied to the third electrode layer tend to be concentrated at the same point in the ceramic raw body. This can cause cracks in the ceramic raw body.

[0006] In JP-A-2016-9836, in order to provide a resin layer between the leading portion of the wraparound portion of the external electrode and the surface of the ceramic nonwork, it is necessary to form a gap between the leading portion of the wraparound portion of the external electrode and the surface of the ceramic nonwork.

[0007] JP-A-2017-152623 discloses a structure having an external electrode extending from a first surface to a fifth surface of the body of a capacitor and another external electrode extending from a second surface to a fifth surface of the body of a capacitor. JP-A-Hei-10-289837 discloses a structure in which external electrodes are formed only on one end face of a substrate.

[0008] The object of the present invention is to provide a ceramic electronic component capable of reducing stress applied to a raw body through external electrodes. Another object of the present invention is to provide a method for manufacturing such a ceramic electronic component. Yet another object of the present invention is to provide a circuit board arrangement comprising a ceramic electronic component capable of reducing stress applied to a raw body of the ceramic electronic component through external electrodes.

[0009] Additional or distinct features and advantages of the present invention will be stated in the following description and will become apparent in part from the description, or may be known through the practice of the invention. Objects and other advantages of the present invention will be realized and achieved by the structures specifically indicated in the written description and the claims thereof, as well as by the accompanying drawings. means of solving the problem

[0010] To achieve these and other advantages and according to the purposes of the present invention, as embodied and extensively described, in one embodiment, the present disclosure provides a ceramic electronic component comprising an element body, a first external electrode, and a second external electrode. The element body comprises at least one first internal electrode and at least one second internal electrode, which are dielectrics. The element body has a plurality of surfaces, including at least one first surface and two side surfaces (opposing side surfaces). The first and second external electrodes are formed on the element body. The first external electrode comprises a first base layer formed on the element body such that the first base layer is connected to the first internal electrode(s) and the edge of the first base layer exists on the first surface of the element body. Additionally, the first external electrode comprises a first plating layer formed on the first base layer such that the edge of the first plating layer exists on the first surface of the element body at a position different from the position of the edge of the first base layer in a direction perpendicular to the first surface of the element body. The second external electrode includes a second lower layer formed on a raw body such that the second lower layer is connected to the second internal electrode(s) and the edge of the second lower layer exists on the first surface of the raw body. Additionally, the second external electrode includes a second plating layer formed on the second lower layer such that the edge of the second plating layer exists on the first surface of the raw body at a position different from the position of the edge of the second lower layer in a direction perpendicular to the first surface of the raw body.

[0011] The unworked body may have at least one first step or inclined surface on a first surface between the position of the edge of the first underlayer and the position of the edge of the first plating layer. The unworked body may have at least one second step or inclined surface on a first surface between the position of the edge of the second underlayer and the position of the edge of the second plating layer.

[0012] The first internal electrode(s) may be exposed on one of the opposing side surfaces of the raw body. The second internal electrode(s) may be exposed on the other of the opposing side surfaces of the raw body. The first external electrode may be formed on one of the opposing side surfaces mentioned above and may extend onto adjacent areas on other surfaces of the raw body including the first surface. The second external electrode may be formed on the other of the opposing side surfaces and may extend onto adjacent areas on other surfaces of the raw body including the first surface.

[0013] The first internal electrode(s) may be exposed on one of the opposing side surfaces of the raw body. The second internal electrode(s) may be exposed on the other opposing side surfaces of the raw body. The first external electrode may be formed on one of the opposing side surfaces mentioned above and may extend onto an adjacent area on one of the other surfaces of the raw body including the first surface. The second external electrode may be formed on the other of the opposing side surfaces and may extend onto an adjacent area on one of the other surfaces of the raw body including the first surface mentioned above.

[0014] The first and second internal electrodes may be exposed on only one of the surfaces of the unworked body. The first and second external electrodes may be formed spaced apart from each other on only one of the aforementioned surfaces.

[0015] The thickness of the unworked body can be measured in a direction perpendicular to the first surface of the unworked body. The thickness of the unworked body may be greater in the first zone covered by the first underlayer than in the second zone not covered by the first underlayer, and may be greater in the third zone covered by the second underlayer than in the second zone.

[0016] The difference between the position of the edge of the first plating layer and the position of the edge of the first underlayer in a direction perpendicular to the first surface of the unworked body may be 0.5 μm to 2.0 μm. The difference between the position of the edge of the second plating layer and the position of the edge of the second underlayer in a direction perpendicular to the first surface of the unworked body may be 0.5 μm to 2.0 μm.

[0017] The first plating layer may have a first sublayer of plating formed on a first underlayer and a second sublayer of plating formed on the first sublayer. The second plating layer may have a third sublayer of plating formed on a second underlayer and a fourth sublayer of plating formed on the third sublayer. The position of the edge of the first sublayer and the position of the edge of the second sublayer may differ from the position of the edge of the first underlayer in a direction perpendicular to the first surface of the unworked body. The position of the edge of the third sublayer and the position of the edge of the fourth sublayer may differ from the position of the edge of the second underlayer in a direction perpendicular to the first surface of the unworked body.

[0018] The wrap-around angle of the first sublayer from the edge of the first lower layer to the first surface of the unworked body may be 180 to 270 degrees. The wrap-around angle of the third sublayer from the edge of the second lower layer to the first surface of the unworked body may be 180 to 270 degrees.

[0019] The first plating layer may further include a fifth sublayer of plating formed on the second sublayer. The second plating layer may further include a sixth sublayer of plating formed on the fourth sublayer. The position of the edge of the first sublayer, the position of the edge of the second sublayer, and the position of the edge of the fifth sublayer may differ from the position of the edge of the first lower layer in a direction perpendicular to the first surface of the unworked body. The position of the edge of the third sublayer, the position of the edge of the fourth sublayer, and the position of the edge of the sixth sublayer may differ from the position of the edge of the second lower layer in a direction perpendicular to the first surface of the unworked body.

[0020] Each of the first and second plating layers may be made of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or may be an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

[0021] Each of the first and second external electrodes may be made of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or may be an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Each of the first and second internal electrodes may be made of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or may be an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

[0022] The main component of the dielectric may be barium titanate, strontium titanate, calcium titanate, magnesium titanate, strontium barium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, or titanium dioxide.

[0023] The main component of each of the first and second lower layers may be Ni.

[0024] Each of the first and second lower layers may have a co-material containing a dielectric as a main component.

[0025] The external size of the ceramic electronic component may be any one of the 0201 size to the 5750 size.

[0026] A dielectric layer containing a dielectric is interposed between each of the first and second internal electrode layers, so that the first internal electrodes and the second internal electrodes can be alternately stacked. The first external electrode can be connected to the first internal electrode layers. The second external electrode can be provided separately from the first external electrode and can be connected to the second internal electrode layers.

[0027] The raw body may have a longitudinal direction perpendicular to the opposite side faces and a width direction perpendicular to the longitudinal direction. The raw body may further include an upper cover layer containing a dielectric and a lower cover layer containing a dielectric so that the upper cover layer can be provided on top of the stack of the first and second internal electrode layers. The lower cover layer may be provided below the stack. The first surfaces of the raw body may include the surface of the upper cover layer and the surface of the lower cover layer. The first steps or inclined surfaces may include two first steps or inclined surfaces. The second steps or inclined surfaces may include two second steps or inclined surfaces. One of the two first steps or inclined surfaces may be formed on the surface of the upper cover layer and the other may be formed on the surface of the lower cover layer. One of the two second steps or inclined surfaces may be formed on the surface of the upper cover layer and the other may be formed on the surface of the lower cover layer. The unworked body may further include a pair of margin portions that include a dielectric and sandwich a stack of first and second internal electrode layers in the width direction of the unworked body. A third step or inclined surface may be formed on one of the pair of margin portions so that the edge of the first plating layer may exist on the surface of one of the pair of margin portions at a position different from the position of the edge of the first underlayer in the width direction of the unworked body. A fourth step or inclined surface may be formed on the other of the pair of margin portions so that the edge of the first plating layer may exist on the other of the pair of margin portions at a position different from the position of the edge of the first underlayer in the width direction of the unworked body. A fifth step or inclined surface may be formed on one of the pair of margin portions so that the edge of the second plating layer may exist on the surface of one of the pair of margin portions at a position different from the position of the edge of the second underlayer in the width direction of the unworked body.A sixth step or inclined surface may be formed on the other side of the pair of margin portions so that the edge of the second plating layer may exist on the other side of the pair of margin portions at a position different from the position of the edge of the second underlayer in the width direction of the unworked body. One of the first surfaces may be the top surface of the unworked body, and the other may be the bottom surface of the unworked body.

[0028] In another aspect, the present disclosure provides a device comprising a mounting substrate, at least one solder layer attached to the mounting substrate, and a ceramic electronic component as described above. The ceramic electronic component is mounted on the mounting substrate via the solder layer(s). The device may be referred to as a circuit board arrangement.

[0029] In another aspect, the present disclosure provides a method for manufacturing a ceramic electronic component. The method comprises the step of forming a raw body having six surfaces. The six surfaces include two side surfaces. The raw body comprises a dielectric and at least one internal electrode. The internal electrode(s) are exposed on each of the two side surfaces of the raw body. The method also comprises the step of applying a base material, which will serve as an underlayer for each of the at least one external electrode, to specific portions on the side surfaces and the remaining four surfaces of the raw body. The method also comprises the step of sintering the base material to form an underlayer for the external electrode(s). The method also comprises the step of etching the raw body in areas not covered by the underlayer to form a step or slope on the raw body. The method also comprises the step of forming a plating layer on the underlayer such that the plating layer covers the step or slope and the edge of the plating layer contacts the etched surface of the raw body. Effects of the invention

[0030] According to the present invention, stress(s) applied to a raw body through external electrode(s) can be reduced.

[0031] The foregoing general description and the following detailed description should all be understood as illustrative and descriptive and intended to provide further description of the invention as claimed. Brief explanation of the drawing

[0032] FIG. 1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1, cut along the longitudinal direction of the multilayer ceramic capacitor. FIG. 3a is an enlarged cross-sectional view of a specific area in FIG. 2 to illustrate stress load points when steps exist on the surface of the unworked body of the capacitor. Figure 3b illustrates stress load points similar to Figure 3a when there is no step difference on the surface of the unworked body. FIG. 4a is the same cross-sectional view as FIG. 3a and illustrates the wrap-around angle of the end portion of the plating layer on the underlayer and the step difference of the unworked body. FIG. 4b is the same cross-sectional view as FIG. 3b and illustrates the wrap-around angle of the end portion of the plating layer on the underlayer. Figure 5 is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor as shown in Figure 1. FIG. 6a is a cross-sectional view useful for explaining the method of manufacturing a multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6b is another cross-sectional view useful for explaining the method of manufacturing a multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6c is another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6d is another cross-sectional view useful for explaining the method of manufacturing a multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6e is another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6f shows another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6g shows another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6h is another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor shown in FIG. 1. FIG. 6i is another cross-sectional view useful for explaining the method of manufacturing a multilayer ceramic capacitor illustrated in FIG. 1. FIG. 6j is another cross-sectional view useful for explaining the method of manufacturing the multilayer ceramic capacitor illustrated in FIG. 1. FIG. 7 illustrates a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 8 is a perspective and cross-sectional view of a multilayer ceramic capacitor according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view of a device according to a fourth embodiment of the present invention, comprising a substrate and a multilayer ceramic capacitor mounted on the substrate. FIG. 10 is a perspective view of a ceramic electronic component according to a fifth embodiment of the present invention. Specific details for implementing the invention

[0033] Embodiments of the present invention will be described in detail below with reference to the attached drawings. Furthermore, the following embodiments do not limit the present invention, and not all combinations of features described in the embodiments are essential to the configuration of the present invention. The configurations of the embodiments may be appropriately modified or changed depending on the specifications of the device to which the present invention is applied or various conditions (operating conditions, operating environment, etc.). The scope of the present invention is not limited by the following individual embodiments. The drawings used in the following description may differ in scale and shape from the actual structure to facilitate understanding of the illustrated configurations.

[0034] First embodiment

[0035] FIG. 1 illustrates a multilayer ceramic capacitor (1) according to a first embodiment of the present invention. FIG. 2 illustrates a cross-sectional view of the multilayer ceramic capacitor (1) shown in FIG. 1, cut along the longitudinal direction (DL) of the capacitor (1).

[0036] In FIGS. 1 and 2, the multilayer ceramic capacitor (1) has a raw body (2) and external electrodes (6A, 6B). The raw body (2) has a laminate (2A), a lower cover layer (5A), and an upper cover layer (5B). The laminate (2A) has internal electrode layers (3A, 3B) and dielectric layers (4).

[0037] A lower cover layer (5A) is provided below the laminate (2A), and an upper cover layer (5B) is provided on top of the laminate (2A). Internal electrode layers (3A, 3B) are alternately stacked via dielectric layers (4). FIGS. 1 and 2 illustrate an example in which internal electrode layers (3A, 3B) are stacked for a total of 11 layers. However, the number of stacked internal electrode layers (3A, 3B) is not limited to 11. The shape of the raw body (2) may generally be a rectangular parallelepiped. In the following description, the raw body (2) has six surfaces, namely a front surface (2F), a rear surface (2R), a top surface (2T), a bottom surface (2W), a left surface (2P), and a right surface (2Q). The top surface (2T) and the bottom surface (2W) may be referred to as the first surfaces of the raw body (2). The left surface (2P) and the right surface (2Q) may be referred to as the opposing side surfaces of the unworked body (2). The shape of the laminate (2A) may generally be a rectangular parallelepiped.

[0038] In the following description, the length direction of the raw body (2) is designated as DL, the width direction of the raw body (2) is designated as DW, and the height direction of the raw body (2) is designated as DH. The height direction (DH) is the direction in which the top and bottom surfaces (2T and 2W) of the raw body (2) face each other. When the multilayer ceramic capacitor (1) is mounted on a substrate (circuit board (11) in FIG. 9), the bottom surface (2W) of the raw body (2) may face the mounting surface of the substrate (11). The raw body (2) may be chamfered along the ridges of the raw body (2). As a result of the chamfering, the raw body (2) has curved surfaces (R) at its chamfered corners, as shown in FIG. 2.

[0039] As illustrated in FIGS. 1 and 2, external electrodes (6A, 6B) are formed on the raw body (2) such that the external electrodes (6A, 6B) are separated from each other in the longitudinal direction (DL). The left external electrode (6A) generally covers the left surface (2P) of the raw body (2), and the right external electrode (6B) generally covers the right surface (2Q) of the raw body (2). Specifically, the external electrode (6A) extends from the left end area of ​​the bottom surface (2W) of the raw body (2) on the left surface (2P) to the left end area of ​​the top surface (2T), and the external electrode (6B) extends from the right end area of ​​the bottom surface (2W) of the raw body (2) on the right surface (2Q) to the right end area of ​​the top surface (2T). Each of the external electrodes (6A, 6B) may also extend onto the front surface (2F) and / or rear surface (2R) of the unworked body (2).

[0040] In the longitudinal direction (DL) of the raw body (2), the internal electrode layers (3A, 3B) are alternately arranged at different positions within the laminate (2A). Specifically, compared to the internal electrode layers (3B), the internal electrode layers (3A) are arranged on the left side of the raw body (2), that is, the internal electrode layers (3A) extend in the longitudinal direction (DL) from the left surface (2P) of the raw body toward the right surface (2Q). The internal electrode layers (3B) are arranged on the right side of the raw body (2), that is, the internal electrode layers (3B) extend in the longitudinal direction (DL) from the right surface (2Q) toward the left surface (2P). The left end of each internal electrode layer (3A) is exposed on the left surface (2P) of the raw body (2) and connected to the left external electrode (6A). The right end of each of the internal electrode layers (3B) is exposed on the right surface (2Q) of the unworked body (2) and connected to the right external electrode (6B).

[0041] In the width direction (DW) of the raw body (2), the ends of the internal electrode layers (3A, 3B) are covered by dielectric layers (4). In the width direction (DW), the ends of the internal electrode layers (3A, 3B) can be aligned with each other as shown in FIG. 1. Thus, in the width direction (DW), the raw body (2) has margin portions (10) covering the internal electrode layers (3A and 3B) (i.e., a front margin portion (10) and a rear margin portion (10); in the drawing, only the front margin portion (10) is illustrated).

[0042] In the height direction (DH), the thickness of each of the internal electrode layers (3A, 3B) may be from 0.05 μm to 25 μm. In the height direction (DH), the thickness of each of the dielectric layers (4) may also be from 0.05 μm to 25 μm. For example, the thickness of the internal electrode layer (3A) is 0.3 μm, the thickness of the internal electrode layer (3B) is 0.3 μm, and the thickness of the dielectric layer (4) is 0.3 μm. The material of the internal electrode layers (3A, 3B) may be a metal such as, for example, Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or an alloy containing these metals.

[0043] The main component of the material of the dielectric layer (4) may be, for example, a ceramic material having a perovskite structure. The main component may be included in an amount of 50 at% or more. The ceramic material of the dielectric layer (4) may be, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, strontium barium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, or titanium oxide.

[0044] The main component of the material of each of the lower cover layer (5A) and the upper cover layer (5B) may be, for example, a ceramic material. The main component (i.e., ceramic material) of each of the lower cover layer (5A) and the upper cover layer (5B) may be the same as the main component (i.e., ceramic material) of the dielectric layer (4). The thickness (TA) of the lower cover layer (5A) is preferably in the range of 5 μm to 30 μm, and the thickness (TB) of the upper cover layer (5B) is preferably in the range of 5 μm to 30 μm.

[0045] Each of the external electrodes (6A, 6B) has an underlayer (underlayer) (7) formed on the raw body (2) and a plating layer (9) laminated on the underlayer (7). The right and left underlayers (7) are formed on the right and left sides of the raw body (2), respectively, so that the right and left underlayers (7) are separated from each other in the longitudinal direction (DL). The left underlayer (7) is connected to the internal electrode layers (3A), and the right underlayer (7) is connected to the internal electrode layers (3B). The left underlayer (7) is formed on the left surface (2P) of the raw body (2) and also on adjacent areas of the top surface (2T), bottom surface (2W), front surface (2F), and rear surface (2R). Similarly, the right lower layer (7) is formed on the right surface (2Q) of the raw body (2) and also on adjacent areas of the top surface (2T), bottom surface (2W), front surface (2F) and rear surface (2R) of the raw body (2). That is, each of the lower layers (7) can be continuously extended from the bottom surface (2W) to the top surface (2T) on the side surface (2P) (or 2Q), and can also be extended from the side surface (2P) (2Q) of the raw body (2) to the front surface (2F) and rear surface (2R). The left lower layer (7) may be referred to as the first lower layer, and the right lower layer (7) may be referred to as the second lower layer.

[0046] The main component of the metal used as the conductive material of the underlayer (7) may include, for example, at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or may include an alloy containing at least one of these metals. The underlayer (7) may include a co-material that is mixed with the metal(s) of the underlayer (7). The co-material may exist in the form of a plurality of islands in the underlayer (7). When the co-material exists in the underlayer (7) in the form of islands, the co-material can reduce the difference in the coefficient of thermal expansion between the unworked body (2) and the underlayer (7) and relieve stress on the underlayer (7). The co-material is, for example, a ceramic component which is the main component of the dielectric layer (4). The underlayer (7) may include a glass component. When a glass component is mixed into the underlayer (7), the glass component can densify the underlayer (7). These glass components are, for example, oxides of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0047] The lower layer (7) is preferably composed of a metal sintered body. This enables the lower layer (7) to be made thick while ensuring adhesion between the unworked body (2) and the lower layer (7), and enables the strength of the external electrodes (6A, 6B) while ensuring conductivity with the internal electrode layers (3A, 3B).

[0048] Left and right plating layers (9) are formed on the left and right external electrodes (6A, 6B), respectively, such that the left plating layer (9) covers the left lower layer (7) and the right plating layer (9) covers the right lower layer (7). The left plating layer (9) is conductive to the internal electrode layers (3A) through the left lower layer (7), and the right plating layer (9) is conductive to the internal electrode layers (3B) through the right lower layer (7). When the capacitor (1) is mounted on the substrate (11) (Fig. 9), each of the plating layers (9) is conductive to the terminals (12A, 12B) (Fig. 9) of the substrate (11) via solder (13A, 13B) (Fig. 9).

[0049] The material of the plating layers (9) comprises, for example, at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy comprising at least one selected from these metals. The plating layer (9) may be a plating layer composed of a single metal component or may have a multi-layer structure comprising a plurality of sublayers composed of different metal components. In FIG. 1, the plating layer (9) has a three-layer structure. Specifically, the plating layer (9) comprises a Cu plating layer (9A) formed on the underlayer (7), a Ni plating layer (9B) formed on the Cu plating layer (9A), and a Sn plating layer (9C) formed on the Ni plating layer (9B). The Cu plating layer (9A) can improve the adhesion of the plating layer (9) to the underlayer (7). The Ni plating layer (9B) can improve the heat resistance of the external electrodes (6A, 6B) during soldering. The Sn plating layer (9C) can improve the wettability of the solder on the plating layer (9). Each of the plating layers (9A-9C) may be referred to as a sublayer of the plating layer (9). It should be noted that the three-layer structure of the plating layer (9) is merely an example of a multilayer structure, and the plating layer (9) may have a two-layer structure or a four-layer (or more) structure instead of a three-layer structure.

[0050] As illustrated in FIG. 2, the raw body (2) has a turned "I" shape. Specifically, the top surface (2T) of the raw body (2) has two protrusions (M1) on its left and right sides and a middle section (M2) between the two protrusions (M1). Each edge (EU) of the lower layers (7) is located at the protrusion (M1) of the top surface (2T) of the raw body (2), and each edge (EM) of the plating layers (9) is located at the middle section (M2) of the top surface (2T) of the raw body (2). Thus, the position of the edge (EU) of the lower layer (7) is different from the position of the edge (EM) of the plating layer (9) in the height direction (DH). The term "edge" of the lower layer (7) refers to the end face of the lower layer (7), and the "edge" of the plating layer (9) refers to the end face of the plating layer (9). The same structure is seen on the bottom surface (2W) of the raw body (2). Specifically, the bottom surface (2W) of the raw body (2) has two protrusions (M3) on its left and right sides, and a middle section (M4) between the two protrusions (M3). The lower edge (EU) of each of the lower layers (7) is located on the protrusion (M3) of the bottom surface (2W) of the raw body (2), and the lower edge (EM) of each of the plating layers (9) is located on the middle section (M4) of the bottom surface (2W) of the raw body (2). Accordingly, the position of the lower edge (EU) of the lower layer (7) is different from the position of the lower edge (EM) of the plating layer (9) in the height direction (DH). The front surface (2F) of the raw body (2) may have the same structure and / or the rear surface (2R) of the raw body (2) may have the same structure. When the front surface (2F) of the raw body (2) has two protrusions and an intermediate portion between the two protrusions, the two protrusions protrude in the width direction (DW), and thus the position of the edge (EU) of the lower layer (7) is different from the position of the edge (EM) of the plating layer (9) in the width direction (DW).

[0051] FIG. 3a illustrates an enlarged view of zone R1 in FIG. 2. As shown in FIG. 3a, the edges (EA) of the Cu plating layer (9A), the edges (EB) of the Ni plating layer (9B), and the edges (EC) of the Sn plating layer (9C) have different positions from the edges (EU) of the underlayer (7) in the height direction (DH) (in the normal direction of the top surface (2T) of the raw body (2). The edges (EA, EB, EC) of the sublayers (9A, 9B, 9C) and the edge (EU) of the underlayer (7) are located in the raw body (2). The edges (EA, EB, EC) of the sublayers (9A, 9B, 9C) are closer to the center of the raw body (2) than the edge (EU) of the underlayer (7).

[0052] As described above, the edge (EU) of the base layer (7) and the edge (EM) of the plating layer (9) have different positions in the normal direction of a specific surface of the raw body (2) (top surface (2T) in FIG. 3a). Therefore, the stress load point (P1) of the base layer (7) and the stress load point (P2) of the plating layer (9) do not exist on the same plane of the raw body (2). The stress load point is the point where the stress applied to the raw body (2) from the base layer (7) or the plating layer (9) is maximum, and the stress load point is likely to be the starting point of a crack. Therefore, the configuration of the capacitor (1) of the present embodiment can disperse the stress applied to the raw body (2) through the external electrodes (6A, 6B), and thus can suppress or prevent cracks occurring in the raw body (2).

[0053] As illustrated in FIG. 3a, a step (8) is formed on the upper surface (2T) of the raw body (2) because the position of the edge (EU) of the lower layer (7) is different from the position of the edge (EM) of the plating layer (9) in the normal direction (height direction (DH)) of the upper surface (2T) of the raw body (2). The step (8) is provided between the edge (EU) of the lower layer (7) and the edge (EM) of the plating layer (9). Thus, the upper surface (2T) of the raw body (2) is separated into an upper surface (M1) and a lower surface (M2). The edge (EU) of the lower layer (7) is located on the upper surface (M1), and the edge (EM) of the plating layer (9) is located on the lower surface (M2). The step (8) extends in a direction perpendicular to the top surface (2T) in the illustrated embodiment. However, it should be noted that the vertical step (8) can be replaced by an inclined surface. The height (H) of the step (8) is preferably 0.5 μm to 2.0 μm. If the height (H) of the step (8) is greater than 0.5 μm, the stress applied to the raw body (2) via the external electrodes (6A, 6B) can be distributed in an effective manner. If the height (H) of the step (8) is less than 2.0 μm, the reduction in the thickness of the raw body (2) between the external electrodes (6A, 6B) can be suppressed. This suppresses the reduction in the flexural strength of the multilayer ceramic capacitor (1).

[0054] The step (8) can be formed to extend around the raw body (2) along the edge of the lower layer (7) of each of the external electrodes (6A, 6B). In this configuration, for each of the external electrodes (6A, 6B), the step (8) is formed on the upper surface (2T), rear surface (2R), lower surface (2W), and front surface (2F) of the raw body (2). The step (8) is positioned vertically on each of the upper surface (2T), rear surface (2R), lower surface (2W), and front surface (2F) of the raw body (2). That is, the upper cover layer (5B) has the step (8), the rear margin portion (10) has the step (8), the lower cover layer (5A) has the step (8), and the front margin portion (10) has the step (8). The thickness (height) of the raw body (2) at the location covered by the lower layer (7) (i.e., the thickness between the lower surface (M3) and the upper surface (M1)) is thicker than the thickness of the raw body (2) at the location exposed from the lower layer (7) (i.e., the thickness between the lower surface (M4) and the upper surface (M2). The thickness of the raw body (2) is a value (size) in the height direction (DH) of the raw body (2) and is measured at points on each surface (M1-M3, M2-M4) within 20 μm from the step (8). For example, the thickness of the raw body (2) at the location covered by the lower layer (7) is measured from a specific point on the lower surface (M3) and a specific point on the upper surface (M1), and the distance from each of the points to the step (8) is within 20 μm. The width of the unworked body (2) at the location covered by the lower layer (7) may be wider than the width of the unworked body (2) at the location exposed from the lower layer (7). The width of the unworked body (2) is a value in the width direction (DW) of the unworked body (2) and is measured at points on each surface within 20 μm from the step (8).The thickness of the lower cover layer (5A), the thickness of the upper cover layer (5B), the thickness of the front margin portion (10), and / or the thickness of the rear margin portion (10) can be adjusted so that the internal electrode layers (3A, 3B) are not exposed from the unworked body (2) having a step (8).

[0055] The dimensions (size) of the multilayer ceramic capacitor (1) are not limited to specific values, but, for example, the following design values ​​may be used:

[0056] Length 0.25mm, Width 0.125mm, Height 0.125mm (Size 0201),

[0057] Length 0.4mm, width 0.2mm, height 0.2mm (size 0402),

[0058] Length 0.6mm, width 0.3mm, height 0.3mm (size 0603),

[0059] Length 1.0mm, width 0.5mm, height 0.5mm (Size 1005),

[0060] Length 3.2mm, width 1.6mm, height 1.6mm (size 3216),

[0061] Length 4.5mm, width 3.2mm, height 2.5mm (size 4532) or

[0062] Length 5.7mm, width 5.0mm, height 2.3mm (size 5750).

[0063] Preferably, one of "size 0201" to "size 4532" may be used.

[0064] FIG. 3a is a partial cross-sectional view of a capacitor (1) and illustrates stress load points (P1, P2) when the raw body (2) has a step (8). FIG. 3b is a partial cross-sectional view of a different capacitor (1') comprising a raw body (2'), a base layer (7') formed on the raw body (2'), and a plating layer (9') formed on the base layer (7'). The raw body (2') does not have a step (8). The plating layer (9') has a three-layer structure and includes a Cu plating layer (9A'), a Ni plating layer (9B'), and a Sn plating layer (9C'). FIG. 3b illustrates stress load points (P3, P4) when the raw body (2') does not have a step (8).

[0065] As illustrated in FIG. 3a, when the raw body (2) has a step (8) at the edge of the base layer (7), the edge (EU) of the base layer (7) is located on the upper surface (M1), and the edge (EM) of the plating layer (9) is located on the lower surface (M2). Therefore, the stress load point (P1) from the base layer (7) and the stress load point (P2) from the plating layer (9) are not located on the same plane of the raw body (2). As a result, the concentration of two stresses (i.e., the stress applied to the raw body (2) through the base layer (7) and the stress applied to the raw body (2) through the plating layer (9)) can be avoided. Accordingly, the possibility of cracking in the raw body (2) can be reduced or eliminated.

[0066] Meanwhile, in the configuration illustrated in FIG. 3b, the edge (EU') of the underlayer (7') and the edge (EM') of the plating layer (9') exist on the same surface (M3) of the raw body (2'). Therefore, the stress load point (P3) from the underlayer (7') and the stress load point (P4) from the plating layer (9') exist on the same plane (M3) of the raw body (2'). More specifically, the stress load point (P3) substantially overlaps with the stress load point (P4). As a result, the stress applied to the raw body (2') through the underlayer (7') and the stress applied to the raw body (2') through the plating layer (9') are concentrated, making it easier for cracks to occur in the raw body (2').

[0067] FIG. 4a is the same cross-sectional view as FIG. 3a and illustrates the wrap-around angle (θ1) of the end portion of the plating layer (9) when the unworked body (2) has a step (8). FIG. 4b is the same cross-sectional view as FIG. 3b and illustrates the wrap-around angle (θ2) of the end portion of the plating layer (9') when the unworked body (2') does not have a step.

[0068] In FIG. 4a, the raw body (2) has a step (8) at the edge (EU) of the base layer (7), and the step (8) is covered by a Cu plating layer (9A). The Cu plating layer (9A) goes around the step (8) and reaches the surface (M3) of the raw body (2). The edge (EU) of the base layer (7) may be in the form of an acute angle. The wrap-around angle (θ1) of the Cu plating layer (9A) from the edge (EU) of the base layer (7) to the surface (M3) of the raw body (2) is 180 to 270 degrees.

[0069] Meanwhile, in FIG. 4b, there is no step (8) on the raw body (2') at the edge (EU') of the base layer (7'). The Cu plating layer (9A') extends over the base layer (7') and reaches the surface (M3) of the raw body (2'). The end surface (EU') of the base layer (7') and the end surface (EA') of the Cu plating layer (9A') exist on the same plane. Therefore, the wrap-around angle (θ2) of the Cu plating layer (9A') from the edge (EU') of the base layer (7') to the surface (M3) of the raw body (2') is less than 180 degrees.

[0070] FIG. 5 is a flowchart illustrating an exemplary manufacturing method for a multilayer ceramic capacitor (1), and FIGS. 6a through 6j are a series of cross-sectional views corresponding to the respective manufacturing processes illustrated in FIG. 5. In FIGS. 6c through 6j, for the sake of explanation and understanding, it should be noted that three internal electrode layers (3A) and three internal electrode layers (3B) are alternately stacked with dielectric layers (4) interposed between the internal electrode layers (3A, 3B).

[0071] As shown in step S1 of FIG. 5, an organic binder and an organic solvent as a dispersant and a forming aid are added to the dielectric material powder, and the mixture is ground and mixed to produce a muddy slurry. The dielectric material powder comprises, for example, ceramic powder. The dielectric material powder may include an additive or additives. The additive(s) may be, for example, oxides of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si, or glass. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0072] Next, as shown in step S2 of FIG. 5 and illustrated in FIG. 6a, a green sheet (24) is prepared. Specifically, a slurry containing ceramic powder is applied in the form of a sheet onto a carrier film and dried to produce the green sheet (24). The carrier film is, for example, a PET (polyethylene terephthalate) film. To apply the slurry onto the carrier film, a doctor blade method, a die coater method, or a gravure coater method may be used. Step S2 is repeated to prepare a plurality of green sheets (24).

[0073] Next, as described in step S3 of FIG. 5 and illustrated in FIG. 6b, a conductive paste to be an internal electrode is applied in a predetermined pattern to each of the green sheets (24) prepared in step S1 to form the internal electrode layers (3A, 3B), thereby forming a plurality of internal electrode patterns (23) on the green sheets (24). In step 3, a plurality of internal electrode patterns (23) may be formed on a single green sheet (24) such that the internal electrode patterns (23) are separated from each other along the longitudinal direction of the green sheet (24). The conductive paste for the internal electrode comprises a metal powder used as a material for the internal electrode layers (3A, 3B). For example, if the metal used as a material for the internal electrode layers (3A, 3B) is Ni, the conductive paste for the internal electrode comprises Ni powder. Additionally, the conductive paste for the internal electrode comprises a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for the internal electrode may include a ceramic material that is the main component of the dielectric layers (4) as a co-material. The application of the conductive paste for the internal electrode may be performed by screen printing, inkjet printing, or gravure printing. Accordingly, step S3 may be referred to as a printing step. In this way, a plurality of green sheets (24) having internal electrode patterns (23) are prepared.

[0074] Next, as described in step S4 of FIG. 5 and illustrated in FIG. 6c, a block (25) of green sheets (24) is fabricated by stacking green sheets (24) with internal electrode patterns (23) formed thereon and green sheets (24A, 25A, 25B) without internal electrode patterns (23) formed thereon in a predetermined order. The green sheets (25A, 25B) without internal electrode patterns (23) formed thereon are used as outer layers (i.e., bottom layer and top layer). The thickness of the green sheets (25A, 25B) is greater than the thickness of the green sheets (24) with internal electrode patterns (23) formed thereon. In step S4, the green sheets (24) with internal electrode patterns (23) are divided into two groups, namely, green sheets (24) with internal electrode patterns (23A) and green sheets (24) with internal electrode patterns (23B). Then, green sheets (24) having internal electrode patterns (23A) and green sheets (24) having internal electrode patterns (23B) are alternately stacked in the stacking direction so that internal electrode patterns (23A) on the green sheet (24) and internal electrode patterns (23B) on the next or adjacent green sheet (24) are alternately shifted in the length direction of the green sheet (24). Additionally, three types of parts are defined in the green sheet block (25). Specifically, a part in which only internal electrode patterns (23A) are stacked in the stacking direction, a part in which internal electrode patterns (23A, 23B) are alternately stacked in the stacking direction, and a part in which only internal electrode patterns (23B) are stacked in the stacking direction are defined in the green sheet block (25).

[0075] Next, as described in step S5 of FIG. 5 and illustrated in FIG. 6d, the laminate block (25) obtained in the forming process of step S4 of FIG. 5 is pressed so that the green sheets (24, 24A, 25A, 25B) are pressure-bonded. Pressing the laminate block (25) can be performed, for example, by sandwiching the laminate block (25) between resin films and hydrostatically pressing the laminate block (25).

[0076] Next, as described in step S6 of FIG. 5 and illustrated in FIG. 6e, the pressed laminated block (25) is cut so that the block (25) is separated into a plurality of raw bodies, each having a rectangular shape. Each raw body has six surfaces. The cutting of the laminated block (25) is performed in portions where only internal electrode patterns (23A) exist in the stacking direction and in portions where only internal electrode patterns (23B) exist in the stacking direction, as indicated by a plurality of vertical dashed lines (27). The cutting of the laminated block (25) is performed, for example, by blade dicing or a similar method. One of the resulting raw bodies (2B) is illustrated in FIG. 6f.

[0077] As illustrated in FIG. 6f, in each individual raw body (2B), internal electrode layers (3A, 3B) are alternately stacked via dielectric layers (4), with the upper cover layer (5A) being the upper layer and the lower cover layer (5B) being the lower layer. The internal electrode layers (3A) are exposed on the left side (2P) of each raw body (2B), and the internal electrode layers (3B) are exposed on the right side (2Q) of each raw body (2B). It should be noted that in FIG. 6f, the raw body (2B) is illustrated in an enlarged lengthwise direction (DL).

[0078] Next, as described in step S7 of FIG. 5 and illustrated in FIG. 6g, chamfering is performed on the raw body (2B) to form a raw body (2) having a curved surface (R) at each corner of the raw body (2). For example, barrel polishing may be used to chamfer the raw body (2B).

[0079] Next, as shown in step S8 of FIG. 5, the binder contained in the raw body (2) in step S7 of FIG. 5 is removed. The removal of the binder is performed, for example, by heating the raw body (2) in an N2 atmosphere of about 350°C.

[0080] Next, as shown in step S9 of FIG. 5, a conductive paste for the base layer (7) is applied to the end areas of the two side surfaces (2P, 2Q) of each raw body (2) that has undergone chamfering in step S8 of FIG. 5 and the remaining four surfaces (top surface (2T), bottom surface (2W), front surface (2F), and rear surface (2R)) of the raw body (2) that are in contact with their respective side surfaces (2P, 2Q). Then, the conductive paste is dried. A dipping method may be used to apply the conductive paste for the base layer (7). The conductive paste for the base layer (7) comprises powder or filler of a metal used as the conductive material of the base layer (7). For example, when the metal used as the conductive material of the base layer (7) is Ni, the conductive paste for the base layer comprises powder or filler of Ni. Additionally, the conductive paste for the underlayer includes, as a filler, a ceramic component which is, for example, the main component of the dielectric layers (4). For example, the conductive paste for the underlayer contains, as a filler, particles of oxide ceramic (with a D50 particle size of 0.8 μm to 4 μm) having barium titanate as the main component. Additionally, the conductive paste for the underlayer includes a binder and a solvent.

[0081] Next, as described in step S10 of FIG. 5 and illustrated in FIG. 6h, the unworked bodies (2) coated with the conductive paste for the underlayer in step S9 of FIG. 5 undergo a sintering process so that the internal electrode layers (3A, 3B) are integrated with the dielectric layers (4) in each unworked body (2), and the underlayers (7) are formed and integrated with the unworked body (2). The sintering of the unworked bodies (2) and the conductive paste for the underlayer is performed, for example, in a sintering furnace at a temperature range of 1000°C to 1400°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used as the material for the internal electrode layers (3A, 3B), the sintering process may be performed in the sintering furnace while maintaining the inside of the sintering furnace in a reducing atmosphere to prevent oxidation of the internal electrode layers (3A, 3B). In the process of forming the lower layer (7), an oxidation treatment may be additionally applied to the unworked bodies (2) at a temperature of 600°C to 1000°C in an N2 gas atmosphere.

[0082] Next, as described in step S11 of FIG. 5 and illustrated in FIG. 6i, an etching process is applied to the raw bodies (2) so that the surfaces of each of the raw bodies (2) exposed from the right and left lower layers (7) are etched to form right and left steps (8) on the raw bodies (2) along the edges of the right and left lower layers (7). An etched surface (EM) is formed on the bottom surface (2W), top surface (2T), front surface (2F), and rear surface (2R) of the raw bodies (2). The left and right steps (8) circumferentially surround the raw bodies (2) and are associated with the left and right external electrodes (6A, 6B), respectively.

[0083] The etching process applied to the unworked bodies (2) may be wet etching or dry etching. The etching process may be performed with a hydrofluoric acid-based etching solution or etching gas. By adjusting the etching time, etching temperature, etching rate, how many unworked bodies (2) are etched, and the stirring speed of the etching solution, the etching process can be performed in a desired manner (e.g., the depth of the etched surfaces (EM) can be determined).

[0084] Following step S11 (Fig. 6i), a plating process is performed. Specifically, as shown in step S12 of Fig. 5 and illustrated in Fig. 6j, a plating layer (9) is formed on each of the underlayers (7). In the process of forming the plating layer (9), a Cu plating layer (9A), a Ni plating layer (9B), and a Sn plating layer (9C) are formed sequentially on the underlayers (7). The edges (end surfaces) of the Cu plating layer (9A), the edges of the Ni plating layer (9B), and the edges of the Sn plating layer (9C) come into contact with the etched surface (EM) of the raw body (2). In the plating process, the raw body (2) on which the underlayers (7) are formed is placed in a barrel with a plating solution, and electricity is supplied to the barrel while rotating the barrel to form the plating layers (9).

[0085] In an etching process for forming steps (8) on a raw body (2), a metal oxide film and a pore are removed from the surface of each of the underlayers (7). Thus, steps (8) can be formed on the raw body (2) while suppressing an increase in the number of manufacturing processes, and the adhesion of the Cu plating layer (9A) to the underlayers (7) can also be improved.

[0086] Second embodiment

[0087] A second embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view of a multilayer ceramic capacitor (1X) according to a second embodiment. Similar or identical reference numbers and symbols are used to designate similar or identical parts and elements in the first and second embodiments.

[0088] As illustrated in FIG. 7, a multilayer ceramic capacitor (1X) has a raw body (2X) and external electrodes (6AX, 6BX). The raw body (2X) includes a laminate (2A), a lower cover layer (5AX), and an upper cover layer (5BX). The laminate (2A) has internal electrode layers (3A, 3B) and dielectric layers (4). A lower cover layer (5AX) is provided below the laminate (2A), and an upper cover layer (5BX) is provided on top of the laminate (2A). The configuration of the laminate (2A) is the same as that illustrated in FIG. 2.

[0089] External electrodes (6AX, 6BX) are formed on the raw body (2X) such that the external electrode (6BX) and the external electrode (6AX) are separated in the longitudinal direction (DL). The left external electrode (6AX) extends upward from the left end region of the bottom surface (2W) of the raw body (2X) and rests on the left side (2P) of the raw body (2X). The right external electrode (6AB) extends upward from the right end region of the bottom surface (2W) of the raw body (2X) and rests on the right side (2Q) of the raw body (2X). The external electrodes (6AX, 6BX) do not extend over the top surface (2T) of the raw body (2X). The upper edge (upper end) of each of the external electrodes (6AX, 6BX) is lower than the top surface (2T) of the raw body (2X).

[0090] External electrodes (6AX, 6BX) may also be formed on the front surface (2F) and rear surface (2R) of the raw body (2X). Alternatively, external electrodes (6AX, 6BX) may not be formed on the front surface (2F) and rear surface (2R) of the raw body (2X). When external electrodes (6AX, 6BX) are formed on the front surface (2F) and rear surface (2R) of the raw body (2X), the top of each of the external electrodes (6AX, 6BX) is located lower than the top surface (2T) of the raw body (2X).

[0091] Each of the external electrodes (6AX, 6BX) has a lower layer (7X) formed on the raw body (2X) and a plating layer (9X) formed on the lower layer (7X). A left lower layer (7A) is formed on the left side (2P) of the raw body (2X), and a right lower layer (7X) is formed on the right side (2Q) of the raw body (2X). The left lower layer (7X) is separated from the right lower layer (7X) in the longitudinal direction (DL) of the raw body (2X). The left lower layer (7X) is connected to the internal electrode layers (3A), and the right lower layer (7X) is connected to the internal electrode layers (3B). The left lower layer (7X) is formed on the left side (2P) of the raw body (2X) and also on one or three adjacent areas of the front surface (2F), rear surface (2R), and bottom surface (2W) of the raw body (2X). The lower layer (7X) is not formed on the top surface (2T) of the raw body (2X). The right lower layer (7X) is formed on the right side (2Q) of the raw body (2X) and also on one or three adjacent areas of the front surface (2F), rear surface (2R), and bottom surface (2W) of the raw body (2X). The right lower layer (7X) is not formed on the top surface (2T) of the raw body (2X). Therefore, the lower layer (7X) can extend from the end area of ​​the bottom surface (2W) to the side (2P, 2Q) of the raw body (2X), and also to the front surface (2F) and rear surface (2R) of the raw body (2X). As illustrated in FIG. 7, the upper edge of the lower layer (7X) is lower than the upper surface (2T) of the raw body (2X) on the side (2P, 2Q) of the raw body (2X). However, the upper edge of the left lower layer (7X) is higher than the internal electrode layers (3A) on the left side (2P) of the raw body (2X), and the upper edge of the right lower layer (7X) is higher than the internal electrode layers (3B) on the right side (2Q) of the raw body (2X).

[0092] Left and right plating layers (9X) are formed on the left and right external electrodes (6AX, 6BX) to cover the left and right underlayers (7X), respectively. The left plating layer (9X) is electrically connected to the internal electrode layers (3A) through the left underlayer (7X), and the right plating layer (9X) is electrically connected to the internal electrode layers (3B) through the right underlayer (7X). Each of the plating layers (9X) may have a three-layer structure. Specifically, the plating layer (9X) may include a Cu plating layer (9AX) formed on the underlayer (7X), a Ni plating layer (9BX) formed on the Cu plating layer (9AX), and a Sn plating layer (9CX) formed on the Ni plating layer (9BX).

[0093] The structure of the upper portions of the external electrodes (6AX, 6BX) is different from their structure in the first embodiment (Fig. 2). Also, the structure of the upper portion of the unworked body (2X) is different from their structure in the first embodiment.

[0094] Next, I will explain the differences between the unworked body (2X) and the unworked body (2) (Fig. 2), and the differences between the external electrodes (6AX, 6BX) and the external electrodes (6A, 6B) (Fig. 2).

[0095] As illustrated in FIG. 7, the position of the upper end face (edge) (EU) of the base layer (7X) is different from the position of the upper end face (edge) (EM) of the plating layer (9X) in the normal direction of the side (2P) of the raw body (2X) (i.e., in the longitudinal direction (DL). That is, the position of the upper edge (EU) of the base layer (7X) is different from the position of the upper end face (EA) of the Cu plating layer (9AX), the position of the upper end face (EB) of the Ni plating layer (9BX), and the position of the upper end face (EC) of the Sn plating layer (9CX) in the longitudinal direction (DL). When external electrodes (6AX, 6BX) also extend to the front surface (2F) and rear surface (2R) of the raw body (2X), the position of the edge (EU) of the underlayer (7X) on the front surface (2F) may differ from the position of the edge (EM) of the plating layer (9X) on the front surface (2F) in the normal direction (in the width direction (DW)) of the front surface (2F), and the position of the edge (EU) of the underlayer (7X) on the rear surface (2R) may differ from the position of the edge (EM) of the plating layer (9X) on the rear surface (2R) in the normal direction (in the width direction (DW)) of the rear surface (2R). "Edge" is the end of each layer.

[0096] A step (8X) is provided on the left side (2P) of the raw body (2X) to shift the edge (EU) of the base layer (7X) from the edge (EM) of the plating layer (9X) in the longitudinal direction (DL) of the raw body (2X). For the same reason, a similar step (8X) is provided on the right side (2Q) of the raw body (2X). The step (8X) extends horizontally between the edge (EU) of the base layer (7X) and the edge (EM) of the plating layer (9X), and separates the sides (2P, 2Q) of the raw body (2X) into an upper part (upper side) (M4U) and a lower part (lower side) (M4L). The edge (EU) of the base layer (7X) is on the lower side (M4L), and the edge (EM) of the plating layer (9X) is on the upper side (M4U). Instead of a horizontal step (8X), an inclined surface may be provided between the lower side (M4L) and the upper side (M4U).

[0097] As illustrated in FIG. 7, the shape of the upper cover layer (5BX) of the raw body (2X) is different from the shape of the upper cover layer (5B) of the first embodiment. The upper cover layer (5BX) has a step (8X) along the edge (EU) of the lower layer (7X) of each of the external electrodes (6AX, 6BX). Specifically, the left side (M4U) of the upper cover layer (5BX) has a left step (8X), and the right side (M4U) of the upper cover layer (5BX) has a right step (8X). In this configuration, the raw body (2X) has two steps (8X). When the external electrodes (6AX, 6BX) also extend to the front and rear surfaces of the upper cover layer (5BX), the front surface may have a step (8X) extending forward in the width direction (DW) of the raw body (2X), and the rear surface may have a step (8X) extending backward in the width direction (DW) of the raw body (2X). In this configuration, the raw body (2X) has four steps (8X). In either configuration, the edges (EM) of the plating layers (9X) and the edges (EU) of the base layers (7X) are present in the raw body (2X), and the edges (EM) of the plating layers (9X) are closer to the center of the raw body (2X) than the edges (EU) of the base layers (7X) when viewed from above.

[0098] It should be noted that the lower cover layer (5AX) of the present embodiment is similar to the lower cover layer (5A) of the first embodiment, and the lower cover layer (5AX) has steps (8) similar to the steps (8) shown in FIG. 2. Since the raw body (2X) of the present embodiment has steps (8, 8X), the stress applied from the external electrodes (6AX, 6BX) to the lower surface (2W) and sides (2P, 2Q) of the raw body (2X) is reduced. Additionally, the height of the multilayer ceramic capacitor (1X) can be reduced. Additionally, since the upper ends of the outer electrodes (6AX, 6BX) are located on the sides (2P, 2Q) of the raw body (2X) (i.e., surfaces where the inner electrodes (3A, 3B) are exposed or draw-out surfaces of the inner electrodes (3A, 3B)), stress can be reduced at locations close to the capacitance generation zone where the inner electrodes (3A, 3B) face each other. This prevents cracking of the raw body (2X). Each end (EM) of the plating layers (9X) and each end (EU) of the underlayers (7X) are present on the raw body (2X), and the end (EM) of the plating layer (9X) is closer to the center of the raw body than the end (EU) of the underlayer (7X) in the longitudinal direction (DL).

[0099] Third embodiment

[0100] A third embodiment of the present invention will be described with reference to FIG. 8. FIG. 8 is a cross-sectional view of a multilayer ceramic capacitor (1Y) according to a third embodiment, cut in the width direction (DW) of the unprocessed body (2Y) of the capacitor (1Y).

[0101] In FIG. 8, a multilayer ceramic capacitor (1Y) has a raw body (2Y) and external electrodes (6AY, 6BY). The raw body (2Y) has a laminate (2AY), a lower cover layer (5AY), and an upper cover layer (5BY). The laminate (2AY) has internal electrode layers (3AY, 3BY) and dielectric layers (4Y). A lower cover layer (5AY) is provided below the laminate (2AY), and an upper cover layer (5BY) is provided on top of the laminate (2AY).

[0102] The internal electrode layers (3AY, 3BY) are alternately arranged in the longitudinal direction (DL) of the raw body (2Y) via the dielectric layers (4Y). Each of the internal electrode layers (3AY, 3BY) stands upright inside the raw body (2Y) (i.e., extends in the height direction (DH) of the raw body (2Y). A lead electrode (LA) is connected to the lower end of each internal electrode layer (3AY), and another lead electrode (LB) is connected to the lower end of each internal electrode layer (3BY). The positions of the lead electrodes (LB) are shifted in the width direction (DW) of the raw body (2Y) from the positions of the lead electrodes (LA). The lead electrodes (LA, LB) are exposed on the bottom face (2W) of the raw body (2Y). The lead electrodes (LA) of the internal electrode layers (3AY) are aligned with each other in the longitudinal direction (DL) of the raw body (2Y), and the lead electrodes (LB) of the internal electrode layers (3BY) are aligned with each other in the longitudinal direction (DL) of the raw body (2Y). The materials and thicknesses of the internal electrode layers (3AY, 3BY) and the dielectric layers (4Y) are the same as those of FIG. 2. The materials of the lower cover layer (5AY) and the upper cover layer (5BY) are the same as the materials of the lower cover layer (5A) and the upper cover layer (5B) shown in FIG. 2.

[0103] The external electrodes (6AY, 6BY) are formed parallel to the lower surface (2W) of the raw body (2X) and are separated (spaced apart) from each other in the width direction (DW) of the raw body (2X). Each of the external electrodes (6AY, 6BY) includes a lower layer (7Y) formed on the lower surface (2W) of the raw body (2Y) and a plating layer (9Y) formed on the lower layer (7Y). Two lower layers (7Y) are formed parallel to the lower surface (2W) of the raw body (2Y) so that the two lower layers (7Y) are separated from each other in the width direction (DW) and are connected to lead electrodes (LA, LB), respectively.

[0104] A plating layer (9Y) is formed for each of the external electrodes (6AY, 6BY) to cover the underlayer (7Y). The plating layer (9Y) is electrically connected to the internal electrode layers (3AY, 3BY) through the underlayer (7Y). The plating layer (9Y) has, for example, a three-layer structure, namely a Cu plating layer (9AY) formed on the underlayer (7Y), a Ni plating layer (9BY) formed on the Cu plating layer (9AY), and a Sn plating layer (9CY) formed on the Ni plating layer (9BY).

[0105] Each of the two underlayers (7Y) has two edges (EU) extending parallel to the longitudinal direction (DL) of the raw body (2Y). Each of the two plating layers (9Y) has two edges (EM) extending parallel to the longitudinal direction (DL) of the raw body (2Y). For each of the underlayers (7Y), the edges (EU) of the underlayer (7Y) and the edges (EM) of the plating layer (9Y) have different positions in the normal direction (height direction (DH)) of the bottom surface (2W) of the raw body (2Y). The positions of the edges (EA) of the Cu plating layer (9AY), the positions of the edges (EB) of the Ni plating layer (9BY), and the positions of the edges (EC) of the Sn plating layer (9CY) differ from the positions of the edges (EU) of the underlayer (7Y) in the width direction (DW) of the raw body (2Y). An "edge" is the end face of each layer. The edges (EM) of the plating layer (9Y) and the edges (EU) of the underlayer (7Y) exist in the raw body (2Y). The edges (EM) of the plating layer (9Y) are closer to the center of the raw body (2) than the edges (EU) of the underlayer (7Y) in the height direction (DH).

[0106] Because the height positions of the edges (EU) of the base layer (7Y) differ from the height positions of the edges (EM) of the plating layer (9Y), a step (8Y) is formed on the lower surface (2W) of the raw body (2Y) for each edge (EU) of the base layer (7Y). The step (8Y) extends vertically between the edge (EU) of the base layer (7Y) and the edge (EM) of the plating layer (9Y). Instead of a vertical step (8Y), an inclined surface may be provided on the lower surface (2W) of the raw body (2Y).

[0107] Since the raw body (2Y) has two steps (8Y) for each of the two external electrodes (6AY, 6BY), the stress applied from the external electrodes (6AY, 6BY) to the lower surface (2W) of the raw body (2Y) can be reduced. Additionally, the height of the multilayer ceramic capacitor (1Y) can be reduced. Furthermore, since the ends of the external electrodes (6AY, 6BY) are located on the surface exposing the lead electrodes (LA, LB), the stress generated at locations close to the capacitance generation zone where the internal electrodes (3AY, 3BY) face each other can be reduced. This prevents cracking in the raw body (2Y).

[0108] 4th embodiment

[0109] A fourth embodiment of the present invention will be described with reference to FIG. 9. In this embodiment, a multilayer ceramic capacitor (1) of the first embodiment is used. FIG. 9 is a cross-sectional view of a device (circuit board array) (40) having a circuit board (11) and a multilayer ceramic capacitor (1) mounted on the circuit board (11).

[0110] In FIG. 9, land electrodes (12A, 12B) are provided on the circuit board (11). The circuit board (11) may be a printed circuit board or, for example, a semiconductor substrate made of Si. A multilayer ceramic capacitor (1) is connected to the land electrodes (12A, 12B) via their respective solder layers (13A, 13B) attached to the Sn plating layers (9C) of the external electrodes (6A, 6B).

[0111] Because the unworked body (2) has steps (8) at the edges (EU) of the lower layers (7), stress load points from the lower layers (7) and stress load points from the plating layers (9) do not exist on the same plane as the unworked body (2). Therefore, even when stress is applied to the external electrodes (6A, 6B) due to bending or expansion of the circuit board (11), the stress is distributed (stress is not concentrated) and applied to the unworked body (2) via the external electrodes (6A, 6B), and cracks in the unworked body (2) can be suppressed.

[0112] Fifth embodiment

[0113] A fifth embodiment of the present invention will be described with reference to FIG. 10. FIG. 10 shows a perspective view of a ceramic electronic component (21) according to the fifth embodiment. In this embodiment, a chip inductor (21) is used as an example of a ceramic electronic component.

[0114] In FIG. 10, the chip inductor (21) comprises a raw body (22) and external electrodes (26A, 26B). The raw body (22) has a coil pattern (23), internal electrode layers (23A, 23B) and a magnetic material (24). The magnetic material (24) acts as a dielectric that insulates the internal electrode layers (23A, 23B). The shape of the raw body (22) may be a rectangular prism and may have a top surface (22T), a bottom surface (22W), a front surface (22F), a rear surface (22R), a left surface, and a right surface. The left surface and the right surface of the raw body (22) may be referred to as the opposing sides of the raw body (22). External electrodes (26A, 26B) are provided on opposite sides of the raw body (22) and are separated from each other in the longitudinal direction (DL) of the raw body (22). Specifically, the external electrode (26A) is formed on the left surface of the raw body (22) and extends to neighboring areas on the front and rear surfaces (22F, 22R) of the raw body (22) and to neighboring areas on the top and bottom surfaces (22T, 22W) of the raw body (22). The external electrode (26B) is formed on the right surface of the raw body (22) and extends to neighboring areas on the front and rear surfaces (22F, 22R) of the raw body (22) and to neighboring areas on the top and bottom surfaces (22T, 22W) of the raw body (22).

[0115] The coil pattern (23) and the internal electrode layers (23A, 23B) are covered with a magnetic material (24). However, the end of the internal electrode layer (23A) is exposed from the magnetic material (24) on the left side of the raw body (22) and connected to the external electrode (26A), and the end of the internal electrode layer (23B) is exposed from the magnetic material (24) on the right side of the raw body (22) and connected to the external electrode (26B).

[0116] The material of the coil pattern (23) and the internal electrode layers (23A, 23B) may be, for example, Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, or W, or an alloy containing these metals. The magnetic material (24) is, for example, ferrite.

[0117] Each of the external electrodes (26A, 26B) has a lower layer (27) formed on the raw body (22) and a plating layer (29) formed on the lower layer (27). The lower layers (27) are formed on opposite sides of the raw body (22) so that the lower layers (27) are separated from each other in the longitudinal direction (DL) of the raw body (22). The left lower layer (27) extends from the bottom surface (22W) of the raw body (22) across the left surface of the raw body (22) to the top surface (22T). The left lower layer (27) may also extend onto the front surface (22F) and / or rear surface (22R) of the raw body (22). The right lower layer (27) extends from the bottom surface (22W) of the raw body (22) across the right surface of the raw body (22) to the top surface (22T). The right lower layer (27) may also extend onto the front surface (22F) and / or rear surface (22R) of the raw body (22). A plating layer (29) is formed for each of the external electrodes (26A, 26B) so that the plating layer (29) covers the lower layer (27). The left plating layer (29) is electrically connected to the internal electrode layer (23A) via the left lower layer (27), and the right plating layer (29) is electrically connected to the internal electrode layer (23B) via the right lower layer (27). The edge of each lower layer (27) encircles the raw body (22).

[0118] For each of the external electrodes (26A, 26B), the raw body (22) has a step (28). The left step (28) runs along the edge of the lower layer (27) of the external electrode (26A) around the raw body (22). The right step (28) runs along the edge of the lower layer (27) of the external electrode (26B) around the raw body (22). The edge of each lower layer (27) is separated from the edge of the plating layer (29) by the step (28).

[0119] This allows avoidance of an arrangement where the stress load point from the lower layer (27) and the stress load point from the plating layer (29) exist on the same plane as the raw body (22). As a result, the stress applied to the raw body (22) through the external electrodes (26A, 26B) can be distributed. Consequently, cracks will hardly occur in the raw body (22).

[0120] In the embodiments described above, multilayer ceramic capacitors and chip inductors are described as examples of ceramic electronic components, but the present invention may be applied to other elements and devices such as chip resistors or sensor chips. In the embodiments described above, the ceramic electronic component has two external electrodes, but the present invention may be applied to a ceramic electronic component having three or more external electrodes.

[0121] It will be apparent to those skilled in the art that various modifications and variations may be made to the present invention without departing from the spirit or scope of the invention. Accordingly, the present invention is intended to encompass modifications and variations within the scope of the appended claims and their equivalents. In particular, it is explicitly anticipated that any part or whole of any two or more of the embodiments and modifications described above may be combined and considered within the scope of the present invention.

Claims

Claim 1 As a ceramic electronic component, an element body having a dielectric, a first internal electrode, and a second internal electrode—the element body having a plurality of surfaces including at least one first surface and opposing side surfaces—; and a first external electrode and a second external electrode formed on the element body, wherein the first external electrode comprises a first base layer formed on the element body such that the first base layer is connected to the first internal electrode and the edge of the first base layer exists on at least one first surface of the element body; and a first plating layer formed on the first base layer such that the edge of the first plating layer exists on at least one first surface of the element body at a position different from the position of the edge of the first base layer in a direction perpendicular to at least one first surface of the element body, and the second external electrode comprises a second base layer formed on the element body such that the second base layer is connected to the second internal electrode and the edge of the second base layer exists on at least one first surface of the element body. A ceramic electronic component comprising a second plating layer formed on a second underlayer such that the edge of the second plating layer exists on at least one first surface of the raw body at a position different from the position of the edge of the second underlayer in a direction perpendicular to at least one first surface of the raw body, wherein the thickness of the raw body measured in a direction perpendicular to at least one first surface of the raw body is thicker in the first area covered by the first underlayer than in the second area not covered by the first underlayer, and thicker in the third area covered by the second underlayer than in the second area. Claim 2 A ceramic electronic component according to claim 1, wherein the unworked body has at least one first step or inclined surface on at least one first surface between the position of the edge of the first underlayer and the position of the edge of the first plating layer, and the unworked body has at least one second step or inclined surface on at least one first surface between the position of the edge of the second underlayer and the position of the edge of the second plating layer. Claim 3 A ceramic electronic component according to claim 1, wherein the first internal electrode is exposed on one of the opposing side surfaces of the raw body, the second internal electrode is exposed on another of the opposing side surfaces of the raw body, the first external electrode is formed on one of the opposing side surfaces and extends into adjacent zones on other surfaces of the raw body including the at least one first surface, and the second external electrode is formed on another of the opposing side surfaces and extends into adjacent zones on other surfaces of the raw body including the at least one first surface. Claim 4 A ceramic electronic component according to claim 1, wherein the first internal electrode is exposed on one of the opposing side surfaces of the unworked body, the second internal electrode is exposed on another of the opposing side surfaces of the unworked body, the first external electrode is formed on one of the opposing side surfaces and extends into an adjacent zone on one of the other surfaces of the unworked body including the at least one first surface, and the second external electrode is formed on another of the opposing side surfaces and extends into an adjacent zone on one of the other surfaces of the unworked body including the at least one first surface. Claim 5 A ceramic electronic component according to claim 1, wherein the first and second internal electrodes are exposed on at least one of the first surfaces of the unworked body, and the first and second external electrodes are formed on at least one of the first surfaces and spaced apart from each other. Claim 6 delete Claim 7 A ceramic electronic component according to claim 1, wherein the difference between the position of the edge of the first plating layer and the position of the edge of the first underlayer in a direction perpendicular to at least one first surface of the unworked body is 0.5 μm to 2.0 μm, and the difference between the position of the edge of the second plating layer and the position of the edge of the second underlayer in a direction perpendicular to at least one first surface of the unworked body is 0.5 μm to 2.0 μm. Claim 8 A ceramic electronic component according to claim 1, wherein the first plating layer has a first sublayer of plating formed on the first underlayer and a second sublayer of plating formed on the first sublayer, and the second plating layer has a third sublayer of plating formed on the second underlayer and a fourth sublayer of plating formed on the third sublayer, wherein the position of the edge of the first sublayer and the position of the edge of the second sublayer are different from the position of the edge of the first underlayer in a direction perpendicular to at least one first surface of the unworked body, and the position of the edge of the third sublayer and the position of the edge of the fourth sublayer are different from the position of the edge of the second underlayer in a direction perpendicular to at least one first surface of the unworked body. Claim 9 A ceramic electronic component according to claim 8, wherein the wrap-around angle of the first sublayer from the edge of the first lower layer to at least one first surface of the unworked body is 180 to 270 degrees, and the wrap-around angle of the third sublayer from the edge of the second lower layer to at least one first surface of the unworked body is 180 to 270 degrees. Claim 10 In claim 8, the first plating layer further comprises a fifth sublayer of plating formed on the second sublayer, and the second plating layer further comprises a sixth sublayer of plating formed on the fourth sublayer, wherein the position of the edge of the first sublayer, the position of the edge of the second sublayer, and the position of the edge of the fifth sublayer are different from the position of the edge of the first underlayer in a direction perpendicular to at least one first surface of the unworked body, and the position of the edge of the third sublayer, the position of the edge of the fourth sublayer, and the position of the edge of the sixth sublayer are different from the position of the edge of the second underlayer in a direction perpendicular to at least one first surface of the unworked body, a ceramic electronic component. Claim 11 A ceramic electronic component according to claim 1, wherein each of the first and second plating layers is composed of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or is an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Claim 12 A ceramic electronic component according to claim 1, wherein each of the first and second external electrodes is composed of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or is an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, and each of the first and second internal electrodes is composed of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or is an alloy comprising at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Claim 13 A ceramic electronic component according to claim 1, wherein the main component of the dielectric is barium titanate, strontium titanate, calcium titanate, magnesium titanate, strontium barium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, or titanium dioxide. Claim 14 A ceramic electronic component according to claim 1, wherein the main component of each of the first and second lower layers is Ni. Claim 15 In claim 1, each of the first and second lower layers is a ceramic electronic component having a co-material comprising the dielectric as a main component. Claim 16 A ceramic electronic component according to claim 1, wherein the external size of the ceramic electronic component is any one of size 0201 to size 5750. Claim 17 A ceramic electronic component according to claim 1, wherein the first internal electrode comprises at least one first internal electrode layer and the second internal electrode comprises at least one second internal electrode layer, wherein a dielectric layer comprising the dielectric is interposed between each of the at least one first internal electrode layer and each of the at least one second internal electrode layer, so that the at least one first and second internal electrode layers are alternately stacked, the first external electrode is connected to the at least one first internal electrode layer, and the second external electrode is provided separately from the first external electrode and connected to the at least one second internal electrode layer. Claim 18 In claim 17, the above-mentioned raw body has a longitudinal direction perpendicular to the opposing sides and a width direction perpendicular to the longitudinal direction, and the raw body further comprises an upper cover layer comprising the dielectric and a lower cover layer comprising the dielectric, wherein the upper cover layer is provided on top of a stack of at least one first and second internal electrode layers and the lower cover layer is provided below the stack, and at least one first surface of the raw body comprises a surface of the upper cover layer and a surface of the lower cover layer, and the at least one first step or inclined surface comprises two first step or inclined surfaces, and the at least one second step or inclined surface comprises two second step or inclined surfaces, one of the two first step or inclined surfaces is formed on the surface of the upper cover layer and the other is formed on the surface of the lower cover layer, and one of the two second step or inclined surfaces is formed on the surface of the upper cover layer and the other is formed on the surface of the lower cover layer, and the raw body comprises the dielectric and the at least one first and second internal electrode layers in the width direction of the raw body A pair of margin portions sandwiching the stack are additionally included, wherein a third step or inclined surface is formed on one of the pair of margin portions such that the edge of the first plating layer exists on the surface of one of the pair of margin portions at a position different from the position of the edge of the first underlayer in the width direction of the raw body, a fourth step or inclined surface is formed on the other of the pair of margin portions such that the edge of the first plating layer exists on the surface of the other of the pair of margin portions at a position different from the position of the edge of the first underlayer in the width direction of the raw body, and wherein the edge of the second plating layer exists on one of the pair of margin portions at a position different from the position of the edge of the second underlayer in the width direction of the raw body.A ceramic electronic component having a fifth step or inclined surface formed on one surface of the pair of margin portions, and a sixth step or inclined surface formed on the other surface of the pair of margin portions such that the edge of the second plating layer exists on the other surface of the pair of margin portions at a position different from the position of the edge of the second underlayer in the width direction of the unworked body. Claim 19 An arrangement comprising: a mounting substrate; at least one solder layer attached to the mounting substrate; and a ceramic electronic component as described in claim 1, mounted on the mounting substrate via the at least one solder layer. Claim 20 A method for manufacturing a ceramic electronic component, comprising the steps of: forming a non-worked body having six surfaces including two side surfaces, wherein the non-worked body comprises a dielectric and at least one internal electrode, wherein the at least one internal electrode is exposed on each of the two side surfaces of the non-worked body; applying a base material to portions on the side surfaces and the remaining four surfaces of the non-worked body, the base material to form a base layer for each of the at least one external electrode; sintering the base material to form the base layer for each of the at least one external electrode; and etching the non-worked body in a region not covered by the base layer to form a step on the non-worked body. A method for manufacturing a ceramic electronic component, comprising the step of forming the plating layer on the underlayer such that the plating layer covers the step and the edge of the plating layer contacts the etched surface of the unworked body, wherein the etching is performed so that the underlayer does not remain on the step, and the step is a step in the normal direction of the base material coating surface other than the side surfaces.

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