Method and apparatus for optimizing scheduling of tasks sets by integrating task offloading, CPU voltage regulation, and memory placement

Abstract

A method and apparatus for optimizing the scheduling of a task set are disclosed. The method for optimizing the scheduling of a task set may include: generating initial solutions based on the execution location, CPU mode, and memory layout of each task included in the task set; selecting a plurality of solutions as parent solutions from a solution set composed of the initial solutions; generating child solutions based on the parent solutions; updating the solution set using the child solutions; and, when the solutions included in the updated solution set converge, scheduling the execution location, CPU mode, and memory layout of each task based on the converged solution.

Description

Technology Field

[0001] The present invention relates to a method and apparatus for optimizing the scheduling of a task set, and more specifically, to a method and apparatus for optimizing the execution location, CPU mode, and memory placement for each task. Background Technology

[0002] With the advancement of technologies such as the Internet of Things and cyber-physical systems, there is a demand for methods to reduce power consumption in mobile real-time systems.

[0003] Dynamic Voltage Frequency Scaling (DVFS) technology was developed to reduce power consumption in mobile devices by adjusting the CPU's processing speed. DVFS is a method of scheduling task sets to reduce CPU power consumption by lowering the clock frequency and supply voltage when the task workload is low.

[0004] However, since DVFS controls only the CPU processing speed, it had the limitation that it could not reduce power consumed by memory and networks.

[0005] Since power consumption in mobile devices occurs across the CPU, memory, and network, there is a demand for a method to schedule tasks to optimize power consumption by considering the power consumption of all three. The problem to be solved

[0006] The present invention provides a method and apparatus for maximizing power savings in a target system executing tasks by optimizing the execution location, CPU mode, and memory layout for each task by generating a solution set composed of offloading status, CPU clock frequency, and memory location for each task, and applying an evolutionary operation to the solution set. means of solving the problem

[0007] A method for optimizing the scheduling of a task set according to an embodiment of the present invention may include: generating initial solutions based on the execution location, CPU mode, and memory layout of each task included in the task set; selecting a plurality of solutions as parent solutions from a solution set composed of the initial solutions; generating child solutions based on the parent solutions; updating the solution set using the child solutions; and, when the solutions included in the updated solution set converge, scheduling the execution location, CPU mode, and memory layout of each task based on the converged solution.

[0008] The initial solutions of the task set scheduling optimization method according to one embodiment of the present invention may consist of a string indicating whether to offload for each task, a string indicating the clock frequency of the CPU, and a string indicating a memory location.

[0009] The step of generating child solutions of the task set scheduling optimization method according to one embodiment of the present invention may generate two child solutions by exchanging parts of the strings included in each of the two parent solutions.

[0010] The step of generating child solutions of the task set scheduling optimization method according to one embodiment of the present invention may generate child solutions by randomly changing the values ​​of strings included in each of the parent solutions.

[0011] A method for optimizing the scheduling of a task set according to an embodiment of the present invention further comprises the step of evaluating the fitness of each of the solutions included in the solution set based on the power consumption according to the scheduling; and the step of updating the solution set may update the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set.

[0012] The step of selecting the parent solutions of the task set scheduling optimization method according to one embodiment of the present invention may select a predetermined number of initial solutions as the parent solutions based on the fitness of each of the initial solutions.

[0013] A method for optimizing the scheduling of a task set according to an embodiment of the present invention may further include the step of testing the scheduling feasibility of each of the tasks; and the step of applying a penalty to the fitness of a solution generated based on the task that failed the test when a task among the tasks fails the scheduling feasibility test.

[0014] The step of testing the scheduling feasibility of the task set scheduling optimization method according to one embodiment of the present invention may determine a critical period based on the worst-case execution time when the task is executed on an edge server, the command time instructing the offloading of the task, and the upload time and download time of each of the tasks, and test the scheduling feasibility to guarantee the deadline of the task executed on the edge server by comparing the execution period of the task with the critical period.

[0015] The step of testing the scheduling feasibility of the task set scheduling optimization method according to one embodiment of the present invention may test the scheduling feasibility to guarantee the deadline of the task executed on the local CPU by performing a utilization test based on the worst-case execution time when the task is executed at the basic clock frequency on the local CPU, the execution period of the task, the read / write operation and read / write latency between the DRAM and the NVM, and the command time instructing the offloading of the task.

[0016] A scheduling optimization device for a task set according to an embodiment of the present invention may include a processor that generates initial solutions based on the execution location, CPU mode, and memory layout of each task included in the task set, selects a plurality of solutions as parent solutions from a solution set composed of the initial solutions, generates child solutions based on the parent solutions, updates the solution set using the child solutions, and, when the solutions included in the updated solution set converge, schedules the execution location, CPU mode, and memory layout of each task based on the converged solution.

[0017] The initial solutions of the scheduling optimization device for a task set according to one embodiment of the present invention may be composed of a string indicating whether offloading is performed for each task, a string indicating the clock frequency of the CPU, and a string indicating a memory location.

[0018] The processor of the task set scheduling optimization device according to one embodiment of the present invention can generate two child solutions by exchanging parts of the strings included in each of the two parent solutions.

[0019] The processor of the task set scheduling optimization device according to one embodiment of the present invention can generate child solutions by randomly changing the values ​​of strings included in each of the parent solutions.

[0020] The processor of the task set scheduling optimization device according to one embodiment of the present invention evaluates the fitness of each solution included in the solution set based on the power consumption according to the scheduling, and can update the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set.

[0021] The processor of the scheduling optimization device for a task set according to one embodiment of the present invention tests the scheduling feasibility of each of the tasks, and if a task among the tasks fails the scheduling feasibility test, it may apply a penalty to the fitness of the solution generated based on the task that failed the test.

[0022] The processor of the task set scheduling optimization device according to one embodiment of the present invention determines a critical period based on the worst-case execution time when a task is executed on an edge server, the command time for instructing the offloading of the task, and the upload time and download time of each of the tasks, and can test the scheduling feasibility to guarantee the deadline of the task performed on the edge server by comparing the execution period of the task with the critical period.

[0023] The processor of the task set scheduling optimization device according to one embodiment of the present invention can test the schedulability to guarantee the deadline of a task executed on a local CPU by performing a utilization test based on the worst-case execution time when the task is executed at a basic clock frequency on a local CPU, the execution period of the task, the read / write operation and read / write latency between DRAM and NVM, and the command time that instructs to proceed with offloading of the task. Effects of the invention

[0024] According to one embodiment of the present invention, by generating a solution set consisting of whether to offload, the clock frequency of the CPU, and the memory location for each task, and by applying an evolutionary operation to the solution set, the execution location, CPU mode, and memory layout for each task can be optimized to maximize power savings of the target system executing the tasks.

[0025] In addition, according to one embodiment of the present invention, a schedule achievable using only local resources without offloading in variable network situations is searched, and power saving can be maximized by optimizing offloading, DVFS, memory placement, etc. to suit changing situations. Brief explanation of the drawing

[0026] FIG. 1 is a diagram illustrating a task set scheduling optimization device according to an embodiment of the present invention. FIG. 2 is an example of a scheduling result according to an embodiment of the present invention. FIG. 3 is an example of an initial solution generated according to an embodiment of the present invention. FIG. 4 is an example of a process for generating child solutions from parent solutions according to an embodiment of the present invention. FIG. 5 is an example of power consumption according to the algorithm of each system configuration in an embodiment of the present invention. Figure 6 is an example of the change in power consumption by algorithm according to the load of the task set in one embodiment of the present invention. FIG. 7 is an example of the change in power consumption of each system configuration according to the load of the task set in one embodiment of the present invention. FIG. 8 is a flowchart illustrating a method for optimizing the scheduling of a task set according to an embodiment of the present invention. Specific details for implementing the invention

[0027] Hereinafter, embodiments are described in detail with reference to the attached drawings. However, various modifications may be made to the embodiments, and thus the scope of the patent application is not limited or restricted by these embodiments. It should be understood that all modifications, equivalents, and substitutions to the embodiments are included within the scope of the rights.

[0028] The terms used in the embodiments are for illustrative purposes only and should not be interpreted as intended to be limiting. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0029] In addition, when describing with reference to the attached drawings, identical components are assigned the same reference numeral regardless of drawing symbols, and redundant descriptions thereof are omitted. In describing the embodiments, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the embodiments, such detailed description is omitted.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0031] FIG. 1 is a diagram illustrating a task set scheduling optimization device according to an embodiment of the present invention.

[0032] A task set scheduling optimization device (100) according to one embodiment of the present invention may include an input unit (110), a processor (120), and an output unit (130) as shown in FIG. 1.

[0033] The input unit (110) can receive information related to a task to be performed on the target system. For example, the input unit (110) may be one of a communication interface that receives information via wired or wireless communication, a port that is combined with a storage medium to load information stored on the storage medium, and an input interface used by a user to input information to the processor (120). For example, the target system may be a mobile device including a CPU with a dynamic voltage frequency scaling (DVFS) function, memory composed of DRAM and NVM, and a network adapter. Additionally, the target system may be connected via wired or wireless communication to offloadable edge servers.

[0034] The processor (120) can define a task set, which is a set of tasks. A task set defined by the processor (120). It can be expressed as in mathematical formula 1.

[0035]

[0036] Tasks can be executed on a local CPU or an edge server. Therefore, a set of tasks Each of the tasks included can be classified into either LOCAL, a set of tasks running on the local CPU, or REMOTE, a set of tasks running on edge servers, based on where they are executed.

[0037] In addition, tasks can be located in either DRAM or NVM memory. Therefore, task set Each of the tasks included can be classified into one of the sets of tasks located in DRAM and the set of tasks located in NVM based on memory.

[0038] And, task It can be defined as in mathematical formula 2.

[0039]

[0040] At this time, Is It can represent the worst-case execution time when executed at the base clock frequency on the local CPU. The worst-case execution time (WCET) can be the longest time it takes to perform a task on the target hardware. That is, Is This may be the longest time among the times taken to execute at the base clock frequency on the local CPU.

[0041] also, Is Indicates the execution cycle of, It can represent data characteristics. For example, It can be defined as in mathematical formula 3.

[0042]

[0043] At this time, Is It is the memory footprint of, and Is It is input data for execution, Is After it is executed It can be the size of the output data produced as the execution result of. Also, Is It is the number of memory read and write operations during execution, and Is It can be the number of memory write operations during execution.

[0044] The local CPU is To the network adapter of the target system to perform a remote task You can request that it be sent to the edge server. The network adapter responds to the request. It can be sent to the edge server. And, at the edge server When the execution is finished, the target system's network adapter outputs from the edge server iCan receive.

[0045] Also, the deadline is It can be implicitly determined by. And, all tasks About Is It can mean the least common multiple of.

[0046] The processor (120) can test the scheduling potential of each of the tasks included in the task set.

[0047] The processor (120) can test the scheduling possibility to ensure the deadline of the task performed on the local CPU as follows.

[0048] First, the processor (120) can perform a utilization test based on the worst-case execution time when the task is executed at the basic clock frequency on the local CPU and the execution cycle of the task. Specifically, the processor (120) the task Among them, if a task performed on a local CPU runs at the maximum clock frequency on the local CPU without the help of an edge server, it is possible to check whether it satisfies a utilization test such as Equation 4.

[0049]

[0050] If a task executed on a local CPU satisfies Equation 4, the processor (120) can determine a possible schedule in the task set using the EDF (earliest deadline first) algorithm, which is a preemptive scheduling algorithm for the task set. Additionally, if the processor (120) controls the CPU processing speed using DVFS technology, the worst-case execution time of each task can be recalculated based on the CPU clock frequency. Thus, the processor (120) can check whether it satisfies an utilization test such as Equation 5.

[0051]

[0052] At this time, DVFS_Scaled(WCET i ) is a task with DVFS applied This could be the worst execution time.

[0053] Additionally, the processor (120) can perform a utilization test based on read / write operations and read / write latency between the DRAM and the NVM. When the processor (120) places memory using PM (persistent memory) technology, the processor (120) performs a task to which PM is applied. The worst execution time of It can determine. For example, the processor (120) uses mathematical formula 6 can decide.

[0054]

[0055] At this time, is the read latency difference between DRAM and NVM, and This may be the difference in write latency between DRAM and NVM. And, the processor (120) can check whether it satisfies the utilization test such as Equation 7.

[0056]

[0057] And, the processor (120) can perform a utilization test based on the command time that instructs the offloading of tasks. Since the target system can offload tasks to an edge server, the processor (120) can check whether the utilization test, such as Equation 8, is satisfied.

[0058]

[0059] At this time, The network module is every Tasks assigned to each edge server It may be a command time in which the CPU instructs to proceed with the offloading of.

[0060] That is, the processor (120) can determine that the task has passed the scheduleability test to ensure the deadline for the task to be performed on the local CPU if the task satisfies mathematical formula 8.

[0061] When the execution location and CPU mode of a task are determined, the processor (120) can schedule the tasks. At this time, the processor (120) When this starts, the CPU can schedule tasks by first issuing offloading instructions to the network module for tasks belonging to REMOTE, thereby maximizing the parallelism between local and remote task execution. If a cycle for a task classified as REMOTE begins based on the scheduling result, the network module of the target system can initiate the offloading of that task. Additionally, if a cycle for a task classified as LOCAL begins based on the scheduling result, the local CPU can execute those tasks using the EDF algorithm.

[0062] The processor (120) can test the scheduling possibility to ensure the deadline for a task performed on the edge server as follows.

[0063] The processor (120) can determine the worst-case execution time when the task is executed on an edge server. Next, the processor (120) can determine a command time to instruct the offloading of the task. Next, the processor (120) can determine a critical period based on the worst-case execution time, the command time, and the upload and download times of each of the tasks. Finally, the processor (120) can perform a schedulability test by comparing the execution period of the task with the critical period.

[0064] For example, the processor (120) has a critical period Turnaround_Time according to mathematical formula 9. i can decide.

[0065]

[0066] At this time, Is This may represent the worst-case execution time when executed on an edge server. Since the processor (120) schedules to minimize power consumption of the target system, power consumption of the edge server not included in the target system may not be considered. For example, the processor (120) may schedule so that the local CPU does not use the maximum clock frequency, and schedule the edge server to use the maximum clock frequency. Therefore, the processor may schedule at a pre-set arbitrary time, or at a time when the edge server uses the maximum clock frequency. This can be set as the worst-case execution time when executed on an edge server. The pre-configured arbitrary time may be one of the times between when the edge server uses the minimum clock frequency and when the edge server uses the maximum clock frequency.

[0067] And, the processor (120) uploads the Upload_time according to mathematical formula 10. i can decide.

[0068]

[0069] At this time, It can be the uplink bandwidth.

[0070] The processor (120) downloads the Download_time according to mathematical formula 11. i can decide.

[0071]

[0072] At this time, It can be the downlink bandwidth.

[0073] And, the processor (120) can determine that the task has passed the scheduleability test to ensure the deadline of the task performed on the edge server if the task satisfies mathematical formula 12.

[0074]

[0075] That is, the processor (120) can determine that the task has passed the scheduleability test to ensure the deadline for the task performed on the edge server when the execution cycle of the task exceeds the threshold cycle.

[0076] The processor (120) can generate initial solutions based on the execution location, CPU mode, and memory layout of each task included in the task set. At this time, the initial solutions generated by the processor (120) may consist of a string indicating whether offloading is performed for each task, a string indicating the clock frequency of the CPU, and a string indicating the memory location.

[0077] The processor (120) can evaluate the fitness of each solution included in the solution set based on the power consumption according to scheduling. At this time, if a task among the tasks fails to pass the scheduling feasibility test, the processor (120) can impose a penalty on the fitness of the solution generated based on the task that failed the test. Additionally, the processor (120) can impose a penalty on the fitness of the solution if the CPU utilization of the solution exceeds 1. For example, the processor (120) can determine the fitness Cost (i) according to Equation 13.

[0078]

[0079] In this case, Energy(i) is the power consumption of the set of tasks scheduled by solution i, α is a weight parameter, and Penalty(i) is a penalty function for the case where solution i fails the scheduleability test. For example, the penalty function can be defined as shown in Equation 14.

[0080]

[0081] In this case, β may be a weight parameter for the task's deadline overrun.

[0082] The processor (120) can select multiple solutions as parent solutions from a solution set composed of initial solutions. At this time, the processor (120) can select a predetermined number of initial solutions as parent solutions based on the fitness of each of the initial solutions. For example, if the processor is set to select four parent solutions, the processor (120) can select four initial solutions in order of highest fitness among the initial solutions and determine them as parent solutions. Additionally, the processor (120) can determine the probability of selecting a solution as a parent solution for the solutions included in the solution set such that the probability of being selected as a parent solution increases as the fitness level increases.

[0083] The processor (120) can generate child solutions based on parent solutions. At this time, the processor (120) can generate two child solutions by performing an exchange operation that exchanges parts of the strings included in each of the two parent solutions. Additionally, the processor (120) can generate child solutions by performing a mutation operation that randomly changes the values ​​of the strings included in each of the parent solutions.

[0084] The processor (110) can update the solution set using child solutions. At this time, the processor (110) can update the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set. For example, the processor (110) can update the solution set by removing existing solutions in order of lowest fitness from the solution set and adding child solutions to the solution set according to the number of child solutions.

[0085] Additionally, the processor (110) can update the solution set by sorting the existing solutions and child solutions included in the solution set according to their fitness and selecting solutions corresponding to the size of the solution set starting from the solution with the highest fitness. For example, if the fitness of solutions a, b, c, and d included in the solution set is 0.1, 0.2, 0.3, and 0.4, respectively, and the fitness of child solutions e and f generated using solutions a and b is 0.5 and 0.15, respectively, the processor (120) can update the solution set to include solutions a, b, c, and f by deleting solution d and discarding child solution e.

[0086] The processor (120) can determine whether the solutions included in the updated solution set converge. Specifically, the processor (120) can determine that the solutions converge if the fitness of each of the solutions included in the updated solution set is all included within a preset range, and the diversity of the solutions decreases below a threshold level. For example, if the difference between the maximum fitness and the minimum fitness of the solutions included in the updated solution set is 0.01, the processor (120) can determine that the solutions converge.

[0087] If the solutions included in the updated solution set do not converge, the processor (120) can repeat the process of selecting a parent solution from among the solutions included in the updated solution set, generating child solutions using the selected parent solution, and updating the solution set using the child solutions until the solutions included in the updated solution set converge.

[0088] If the solutions included in the updated solution set converge, the processor (120) has a total power consumption E total The execution location, CPU mode, and memory layout of each task can be scheduled to minimize this. The total power consumption is E total is the CPU power consumption as shown in mathematical formula 15 , memory power consumption , and network power consumption It can be determined according to.

[0089]

[0090] CPU power consumption It can be defined as in mathematical formula 16.

[0091]

[0092] At this time, CPU_Power(i) can be defined as in Equation 17.

[0093]

[0094] At this time, f i is task τ i It is the clock frequency for executing and V i is task τ i It is the supply voltage, and c can be the effective switch capacitance.

[0095] Network power consumption It can be defined as in mathematical formula 18.

[0096]

[0097] memory power consumption It can be defined as in mathematical formula 19.

[0098]

[0099] At this time, dynamic power consumption is the amount of power consumed depending on the memory read or write operation, and can be defined as in Equation 20. In addition, static power consumption is the amount of power continuously consumed regardless of memory read and write operations, and can be defined as in Equation 21.

[0100]

[0101] At this time, is the read power consumption for multiple basic access units of DRAM, and may be the write power consumption for multiple basic access units of DRAM. In addition, is the read power consumption for multiple basic access units of the PM, and may be the write power consumption for multiple basic access units of the PM.

[0102]

[0103] is the static power of DRAM per capacity, and is the static power of PM per capacity, and T can be the total execution time of the work set.

[0104] Specifically, the processor (120) can schedule the execution location, CPU mode, and memory placement of each task based on a converged solution. Since the solutions consist of strings indicating where each task is executed between the local CPU and the edge server, where each task is placed in memory, and the clock frequency of each task's CPU, as previously described, the processor (120) can determine the execution location, CPU mode, and memory where the tasks are placed using the strings included in the converged solution.

[0105] The output unit (130) can output the execution location, CPU mode, and memory layout of each of the scheduled tasks and provide them to the user. For example, the output unit (130) may be one of a communication interface that transmits information via wired or wireless communication, a port that is combined with a storage medium to store information on the storage medium, and a display.

[0106] A task set scheduling optimization device (100) can maximize power savings in a target system executing tasks by optimizing the execution location, CPU mode, and memory placement for each task by generating a solution set consisting of whether to offload, the clock frequency of the CPU, and the memory location for each task, and by applying an evolution operation to the solution set.

[0107] The task set scheduling optimization device (100) searches for a schedule that is possible with only local resources without offloading in variable network conditions, and can maximize power savings by optimizing offloading, DVFS, memory placement, etc. according to changing conditions.

[0108] FIG. 2 is an example of a scheduling result according to an embodiment of the present invention.

[0109] 3 tasks in the task set (210) , , It is included, and the worst-case execution times of each task can be 10, 5, and 2, respectively, and the execution cycles can be 24, 16, and 12, respectively.

[0110] At this time, according to mathematical formula 4, = 10 / 24 + 5 / 16 + 2 / 12 = 0.896, so it is less than 1 and can pass the scheduleability test to guarantee the deadline for tasks performed on the local CPU.

[0111] According to the scheduling result (220) by the conventional task schedule optimization device, it can be confirmed that all tasks can be processed within the deadline. In addition, according to the scheduling result (220), every You can see that empty slots of 5 unit time are generated every time.

[0112] Empty slots larger than a certain size can be reduced using DVFS technology, but empty slots generated in the scheduling result (220) may be too small to apply DVFS. Assuming the CPU's base clock frequency is 1.0 and can be adjusted in four steps of 0.5, 0.25, and 0.125, the shortest execution time Even if a clock frequency of 0.5 is applied to it It becomes 4, so the CPU utilization is = 10 / 24 + 5 / 16 + 4 / 12 = 1.0625, which is greater than 1, so scheduling may not be possible.

[0113] The task set scheduling optimization device (100) can output a scheduling result (230) by using offloading and DVFS together. The scheduling result (230) may indicate that DVFS was applied to an empty CPU slot created after offloading.

[0114] In the embodiment of FIG. 2, the clock frequency of the edge server may be 2.0, which is twice that of the local CPU. As shown in FIG. 2, the task If this is offloaded, the task The CPU clock frequency (240) for the execution is lowered to 0.25, and the empty CPU slot that occurred in the scheduling result (230) is removed, thereby reducing power consumption.

[0115] As the offloading ratio increases, the power consumption of the local CPU decreases, but if the network condition is poor, a trade-off effect may occur between the power consumption of the CPU and the network. In addition, some tasks may be impossible to offload due to their inherent characteristics and must be processed on the local CPU. Therefore, the task set scheduling optimization device (100) can optimize the offloading ratio included in the scheduling result by evaluating the suitability of each solution having different offloading ratios, updating the solution set of solutions, and scheduling the task set according to the offloading ratio stored in each converged solution.

[0116] FIG. 3 is an example of an initial solution generated according to an embodiment of the present invention.

[0117] The solutions included in the solution set may consist of a string (310) indicating whether offloading is performed per task, a string (320) indicating a memory location, and a string (330) indicating the clock frequency of the CPU.

[0118] The processor (120) can define the task offloading as a single-layer edge server and generate a string (310) by defining the state of the task as {0, 1} depending on whether the task is offloaded.

[0119] The processor (120) can generate a string (320) by indicating 0 if the memory location is DRAM and 1 if the memory location is NVM.

[0120] The processor (120) can generate a string (330) by defining the CPU execution speed as {1, 0.5, 0.25, 0.125} based on the clock frequency. For example, if the CPU execution speed is 1, the processor (120) can display 0 in the string (330), and if the CPU execution speed is 0.5, the processor (120) can display 1 in the string (330). Additionally, if the CPU execution speed is 0.25, the processor (120) can display 2 in the string (330), and if the CPU execution speed is 0.125, the processor (120) can display 3 in the string (330).

[0121] FIG. 4 is an example of a process for generating child solutions from parent solutions according to an embodiment of the present invention.

[0122] The processor (120) can select two solutions from among the solutions included in the solution set as parent solution (410) and parent solution (420).

[0123] The parent solution (410) may be composed of strings (411), (412), and (413), and the parent solution (420) may be composed of strings (421), (422), and (423). In this case, strings (411) and (421) may be strings indicating whether offloading is enabled, as in string (310) of FIG. 3. Also, strings (412) and (422) may be strings indicating memory locations, as in string (320) of FIG. 3. Furthermore, strings (413) and (423) may be strings indicating the clock frequency of the CPU, as in string (330) of FIG. 3.

[0124] In step (431), the processor (120) can extract the string (411) included in the parent solution (410) and the string (421) included in the parent solution (420), and set a cut point randomly.

[0125] In step (432), the processor (120) can generate strings (461) and (471) by replacing the part below the cut point of string (411) with the part below the cut point of string (421). At this time, string (461) may be a string formed by combining the part above the cut point of string (411) and the part below the cut point of string (421). Additionally, string (471) may be a string formed by combining the part above the cut point of string (421) and the part below the cut point of string (411).

[0126] In step (441), the processor (120) extracts the string (412) included in the parent solution (410) and the string (422) included in the parent solution (420), and can set a cut point randomly. At this time, the location of the cut point set by the processor (120) may be the same as or different from the location of the cut point set in step (431).

[0127] In step (442), the processor (120) may generate strings (462) and (472) by replacing the portion below the cut point of string (412) with the portion below the cut point of string (422). At this time, string (462) may be a string formed by combining the portion above the cut point of string (412) and the portion below the cut point of string (422). Additionally, string (472) may be a string formed by combining the portion above the cut point of string (422) and the portion below the cut point of string (412).

[0128] In step (451), the processor (120) extracts the string (413) included in the parent solution (410) and the string (423) included in the parent solution (420), and can randomly set a cut point. At this time, the location of the cut point set by the processor (120) may be the same as or different from the location of the cut point set in step (431) and the location of the cut point set in step (431).

[0129] In step (452), the processor (120) can generate strings (463) and (473) by replacing the part below the cut point of string (413) with the part below the cut point of string (423). At this time, string (463) may be a string formed by combining the part above the cut point of string (413) and the part below the cut point of string (423). Additionally, string (473) may be a string formed by combining the part above the cut point of string (423) and the part below the cut point of string (413).

[0130] Finally, the processor (120) can generate a child solution (460) by combining strings (461), string (462), and string (463). Additionally, the processor (120) can generate a child solution (470) by combining strings (471), string (472), and string (473).

[0131] According to the embodiment, a plurality of cut points may be set in steps (431, 441, 451), or the number of cut points to be set may be determined randomly. At this time, in steps (432, 442, 452), the processor (120) may generate child solutions by replacing the contents of the string (411, 412, 413) with the string (421, 422, 423) whenever a cut point is encountered while moving down from the top of the string (411, 412, 413).

[0132] That is, when the processor (120) performs a crossover operation, as shown in FIG. 4, the child solutions (460, 470) may be solutions generated by including parts of the strings of each of the parent solutions (410, 420).

[0133] Additionally, according to an embodiment, the processor (120) may generate a child solution using a mutation operation that randomly changes some of the values ​​of the strings of the parent solution. For example, if the code solution consists of the strings shown in FIG. 3, the child solution may be a solution in which the last digit of the string (320) is changed from 1 to 0.

[0134] And, the processor (120) may perform only one of the crossover operation and the mutation operation, or both.

[0135] FIG. 5 illustrates an example of power consumption (510) of tasks scheduled according to basic scheduling, power consumption (520) of tasks scheduled by applying only DVFS, power consumption (530) of tasks scheduled by applying only offloading, and power consumption (540) of tasks scheduled by a task set scheduling optimization device (100).

[0136] As illustrated in FIG. 5, the power consumption (540) of tasks scheduled by the task set scheduling optimization device (100) can be reduced compared to the power consumption (510), power consumption (520), and power consumption (530).

[0137] FIG. 6 illustrates the change in power consumption (Relative energy) of tasks as the load of the task set increases from 0.2 to 0.9. At this time, the power consumption (640) of tasks scheduled by the task set scheduling optimization device (100) may be lower than the power consumption (610) of tasks scheduled according to basic scheduling, the power consumption (620) of tasks scheduled by applying only DVFS, and the power consumption (630) of tasks scheduled by applying only offloading, even if the load of the task set increases as shown in FIG. 6.

[0138] FIG. 7 is an example of the change in power consumption of CPU power consumption (710), network power consumption (720), memory power consumption (730), and total power consumption (740) according to the load of the task set. As shown in FIG. 7, when the load is low, the memory power consumption (730) is the highest, but as the load increases, the ratio of offloading increases, and the network power consumption (720) may increase.

[0139] FIG. 8 is a flowchart illustrating a method for optimizing the scheduling of a task set according to an embodiment of the present invention.

[0140] In step (810), the processor (120) can define a task set, which is a set of tasks. At this time, the task Is Worst-case execution time when running at the default clock frequency on the local CPU, The execution cycle and It can be defined as a data characteristic.

[0141] In step (820), the processor (120) can test the schedulability of each of the tasks included in the task set. At this time, the processor (120) can test the schedulability to ensure the deadline of the task being executed on the local CPU. Specifically, the processor (120) can perform a utilization test based on the worst-case execution time when the task is executed at the basic clock frequency on the local CPU, the execution cycle of the task, the read / write operation and read / write latency between the DRAM and the NVM, and the command time instructing the offloading of the task. If the processor (120) satisfies Equation 8, it can determine that the schedulability test to ensure the deadline of the task being executed on the local CPU has been passed.

[0142] Additionally, the processor (120) can test the schedulability to ensure the deadline of the task performed on the edge server. Specifically, the processor (120) can determine a threshold period based on the worst-case execution time, command time, and the upload and download times of each task. And, if the execution period of the task exceeds the threshold period, the processor (120) can determine that the schedulability test to ensure the deadline of the task performed on the edge server has passed.

[0143] In step (830), the processor (120) may generate initial solutions based on the execution location, CPU mode, and memory layout of each task included in the task set. At this time, the initial solutions generated by the processor (120) may consist of a string indicating whether to offload for each task, a string indicating the clock frequency of the CPU, and a string indicating the memory location.

[0144] In step (840), the processor (120) can evaluate the fitness of each solution included in the solution set based on the power consumption according to scheduling. At this time, if a task among the tasks fails to pass the scheduling feasibility test, the processor (120) can apply a penalty to the fitness of the solution generated based on the task that failed the test. Additionally, the processor (120) can apply a penalty to the fitness of the solution if the CPU utilization of the solution exceeds 1.

[0145] In step (850), the processor (120) may select multiple solutions as parent solutions from a solution set composed of initial solutions. At this time, the processor (120) may select a predetermined number of initial solutions as parent solutions based on the fitness of each of the initial solutions. For example, if the selection of four parent solutions is set, the processor (120) may select four initial solutions in order of highest fitness among the initial solutions and determine them as parent solutions. Additionally, the processor (120) may determine the probability of selecting a solution as a parent solution for the solutions included in the solution set such that the probability of being selected as a parent solution increases as the fitness level increases.

[0146] In step (860), the processor (120) can generate child solutions based on the parent solutions selected in step (850). At this time, the processor (120) can generate two child solutions by performing an exchange operation that exchanges parts of the strings included in each of the two parent solutions. Additionally, the processor (120) can generate child solutions by performing a mutation operation that randomly changes the values ​​of the strings included in each of the parent solutions.

[0147] In step (870), the processor (110) can update the solution set using child solutions. At this time, the processor (110) can update the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set. For example, the processor (110) can update the solution set by removing existing solutions in order of lowest fitness from the solution set and adding child solutions to the solution set according to the number of child solutions.

[0148] Additionally, the processor (110) can update the solution set by sorting the existing solutions and child solutions included in the solution set according to fitness and selecting solutions corresponding to the size of the solution set starting from the solution with the highest fitness.

[0149] In step (880), the processor (120) can determine whether the solutions included in the updated solution set converge. Specifically, if the fitness of each of the solutions included in the updated solution set is all included within a preset range, the processor (120) can determine that the diversity of the solutions has decreased below a threshold level and converged.

[0150] If the solutions included in the updated solution set do not converge, the processor (120) can repeat the process of selecting a parent solution from among the solutions included in the updated solution set, generating child solutions using the selected parent solution, and updating the solution set using the child solutions until the solutions included in the updated solution set converge.

[0151] When the solutions included in the updated solution set converge, the processor (120) can determine the execution location of the tasks, the CPU mode, and the memory where the tasks are placed using the strings included in the converged solutions.

[0153] The present invention generates a solution set consisting of offloading status, CPU clock frequency, and memory location for each task, and by applying evolutionary operations to the solution set, optimizes the execution location, CPU mode, and memory layout for each task, thereby maximizing power savings in a target system executing tasks.

[0154] In addition, the present invention searches for a schedule achievable using only local resources without offloading in variable network situations, and can maximize power savings by optimizing offloading, DVFS, memory placement, etc., to suit changing conditions.

[0156] Meanwhile, the scheduling optimization device for a task set based on speech data or the scheduling optimization method for a task set based on speech data according to the present invention is written as a program that can be executed on a computer and can also be implemented on various recording media such as magnetic storage media, optical reading media, and digital storage media.

[0157] Implementations of the various technologies described herein may be implemented as digital electronic circuits, or as computer hardware, firmware, software, or combinations thereof. Implementations may be implemented as computer programs tangibly embodied in a computer program product, for example, a machine-readable storage device (computer-readable medium), for processing by the operation of a data processing device, e.g., a programmable processor, a computer, or a plurality of computers, or for controlling such operation. Computer programs such as the computer program(s) described above may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. Computer programs may be deployed to be processed on one computer or a plurality of computers at one site, or distributed across a plurality of sites and interconnected by a communication network.

[0158] Processors suitable for processing computer programs include, for example, both general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally, the processor will receive instructions and data from read-only memory or random access memory, or both. The elements of the computer may include at least one processor that executes instructions and one or more memory devices that store instructions and data. Generally, the computer may include one or more mass storage devices that store data, for example, magnetic, magneto-optical disks, or optical disks, or may be combined to receive data from these, transmit data to these, or both. Information carriers suitable for embodying computer program instructions and data include, for example, semiconductor memory devices, magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs (Compact Disk Read Only Memory) and DVDs (Digital Video Disks); magneto-optical media such as floptical disks; ROMs (Read Only Memory); RAMs (Random Access Memory); flash memory; EPROMs (Erasable Programmable ROM); EEPROMs (Electrically Erasable Programmable ROM); etc. Processors and memory may be supplemented by or included in special-purpose logic circuit organizations.

[0159] Additionally, a computer-readable medium may be any available medium accessible by a computer and may include all computer storage media.

[0160] Although this specification contains details of a number of specific embodiments, they should not be understood as limiting the scope of any invention or claimables, but rather as descriptions of features that may be characteristic of a specific embodiment of a specific invention. Specific features described in this specification in the context of individual embodiments may be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any appropriate sub-combination. Furthermore, while features may operate in a specific combination and be described as initially claimed, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be changed to a sub-combination or a variation of the sub-combination.

[0161] Likewise, although operations are depicted in the drawings in a specific order, this should not be understood as requiring that such operations be performed in that specific or sequential order depicted to obtain a desirable result, or that all depicted operations must be performed. In certain cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various device components of the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and devices can generally be integrated together into a single software product or packaged into multiple software products.

[0162] Meanwhile, the embodiments of the present invention disclosed in this specification and drawings are merely specific examples provided to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other variations based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein. Explanation of the symbols

[0163] 100: Task set scheduling optimizer 120: Processor

Claims

Claim 1 A step of testing the scheduling feasibility of each task included in a task set; a step of generating initial solutions based on the execution location, CPU mode, and memory layout of each of the tasks; a step of selecting multiple solutions as parent solutions from a solution set composed of the initial solutions; a step of generating child solutions based on the parent solutions; and a step of updating the solution set using the child solutions. The method includes the step of scheduling the execution location, CPU mode, and memory layout of each task based on the converged solution when the solutions included in the updated solution set converge, and the step of testing the scheduling possibility comprises: performing an utilization test based on the task execution period and the worst-case execution time (WCET) when the task is executed at the base clock frequency on the local CPU; if the utilization test based on the WCET when executed at the base clock frequency is satisfied, performing an utilization test based on the task execution period and the WCET of the task with dynamic voltage frequency scaling (DVFS) applied; performing an utilization test based on the task execution period and the WCET of the task with persistent memory (PM) technology applied; and performing an utilization test based on the task execution period and the command time instructing the task to proceed with offloading. A scheduling method for a set of tasks comprising the step of determining whether a scheduling feasibility test is passed based on whether the utilization test based on the WCET of a task to which the above DVFS is applied, the utilization test based on the WCET of a task to which the above PM technology is applied, and the utilization test based on the above command time are satisfied. Claim 2 A scheduling method for a task set according to claim 1, wherein the initial solutions consist of a string indicating whether to offload for each task, a string indicating the clock frequency of the CPU, and a string indicating a memory location. Claim 3 In paragraph 2, the step of generating the child solutions is a scheduling method of a task set that generates two child solutions by exchanging parts of the strings included in each of the two parent solutions. Claim 4 In paragraph 2, the step of generating the child solutions is a scheduling method for a task set that generates child solutions by randomly changing the values ​​of strings included in each of the parent solutions. Claim 5 A scheduling method for a task set according to claim 1, further comprising the step of evaluating the fitness of each of the solutions included in the solution set based on power consumption according to scheduling, and the step of updating the solution set is to update the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set. Claim 6 In claim 5, the step of selecting the parent solutions is a scheduling method for a task set in which a predetermined number of initial solutions are selected as the parent solutions based on the fitness of each of the initial solutions. Claim 7 In claim 5, the step of evaluating the fitness is a scheduling method for a set of tasks in which, if a task among the tasks fails to pass the scheduling feasibility test, a penalty is applied to the fitness of a solution generated based on the task that fails the test. Claim 8 In claim 7, the step of testing the schedulability is a scheduling method for a set of tasks that determines a threshold period based on the WCET when the task is executed on an edge server, the command time instructing the offloading of the task, and the upload time and download time of each of the tasks, and tests the schedulability to guarantee the deadline of the task performed on the edge server by comparing the execution period of the task with the threshold period. Claim 9 delete Claim 10 The processor includes a processor that tests the scheduleability of each task included in a task set, generates initial solutions based on the execution location, CPU mode, and memory layout of each of the tasks, selects multiple solutions as parent solutions from a solution set composed of the initial solutions, generates child solutions based on the parent solutions, updates the solution set using the child solutions, and, if the solutions included in the updated solution set converge, schedules the execution location, CPU mode, and memory layout of each task based on the converged solution; the processor performs an utilization test based on the execution period of a task and the WCET when the task is executed at a base clock frequency on a local CPU, and if the utilization test based on the WCET when executed at the base clock frequency is satisfied, performs an utilization test based on the execution period of a task and the WCET of a task to which DVFS is applied, performs an utilization test based on the execution period of a task and the WCET of a task to which PM technology is applied, and performs an utilization test based on the execution period of a task and the command time instructing the task to proceed with offloading. A scheduling device for a task set that determines whether a scheduling feasibility test is passed based on whether the utilization test based on the WCET of a task to which DVFS is applied, the utilization test based on the WCET of a task to which the PM technology is applied, and the utilization test based on the command time are satisfied. Claim 11 In paragraph 10, the above initial solutions are a scheduling device for a task set comprising a string indicating whether to offload per task, a string indicating the clock frequency of the CPU, and a string indicating a memory location. Claim 12 In paragraph 11, the processor is a scheduling device for a task set that generates two child solutions by exchanging parts of strings included in each of the two parent solutions. Claim 13 In claim 11, the processor is a scheduling device for a task set that generates child solutions by randomly changing the values ​​of strings included in each of the parent solutions. Claim 14 In claim 10, the processor evaluates the fitness of each of the solutions included in the solution set based on the power consumption according to scheduling, and updates the solution set by selecting the solutions included in the solution set and the child solutions according to the size and fitness of the solution set. Claim 15 In claim 14, the processor is a scheduling device for a set of tasks that, when a task among the tasks fails to pass a scheduling possibility test, imposes a penalty on the fitness of a solution generated based on the task that fails the test. Claim 16 In claim 15, the processor determines a threshold period based on the WCET when the task is executed on an edge server, the command time instructing the offloading of the task, and the upload time and download time of each of the tasks, and tests the schedulability of a task set to ensure the deadline of the task executed on the edge server by comparing the execution period of the task with the threshold period. Claim 17 delete

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