Display device

Abstract

A display device according to one embodiment comprises a substrate, a first conductive layer located on the substrate and including a data line, an initialization voltage line and a driving voltage line, and a semiconductor layer located on the first conductive layer, wherein the semiconductor layer comprises a first semiconductor, a second semiconductor and a third semiconductor spaced apart from each other, wherein the first semiconductor is electrically connected to the driving voltage line, the second semiconductor is electrically connected to the data line, the third semiconductor is electrically connected to the initialization voltage line, and the second semiconductor does not overlap the data line in a direction perpendicular to the surface of the substrate.

Description

Technology Field

[0001] The present disclosure relates to a display device, and more specifically, to a display device that minimizes damage to a semiconductor layer. Background Technology

[0002] A display device is a device that displays images, and includes Liquid Crystal Displays (LCDs) and Light Emitting Diodes (OLEDs). These display devices are used in a wide variety of electronic devices, such as mobile phones, navigation systems, digital cameras, e-books, portable game consoles, and various terminals.

[0003] Emissive display devices possess self-luminous characteristics and, unlike liquid crystal displays, do not require a separate light source, thereby allowing for reduced thickness and weight. Furthermore, emissive display devices offer high-quality characteristics such as low power consumption, high brightness, and fast response speeds. The problem to be solved

[0004] The embodiments are intended to provide a display device that minimizes damage to the semiconductor layer and hydrogen penetration. means of solving the problem

[0005] A display device according to one embodiment comprises a substrate, a first conductive layer located on the substrate and including a data line, an initialization voltage line and a driving voltage line, and a semiconductor layer located on the first conductive layer, wherein the semiconductor layer comprises a first semiconductor, a second semiconductor and a third semiconductor spaced apart from each other, wherein the first semiconductor is electrically connected to the driving voltage line, the second semiconductor is electrically connected to the data line, the third semiconductor is electrically connected to the initialization voltage line, and the second semiconductor does not overlap the data line in a direction perpendicular to the surface of the substrate.

[0006] The apparatus further comprises a second conductive layer located on the semiconductor layer, and a third conductive layer located on the second conductive layer and including a connecting member, wherein the connecting member is positioned to overlap both the second semiconductor and the data line, and the second semiconductor and the data line can be electrically connected through the connecting member.

[0007] The above data line is located along a second direction, and the above connecting member may be located along a first direction that intersects the second direction.

[0008] The driving voltage line is located along the second direction, and the third conductive layer further includes an upper holding electrode located between the data line and the driving voltage line in a planar manner.

[0009] The upper retaining electrode may include a protrusion protruding in a first direction intersecting the second direction.

[0010] The protrusion of the upper retaining electrode may intersect with the driving voltage line.

[0011] The protrusion of the upper retaining electrode may be electrically connected to the third semiconductor.

[0012] The above third semiconductor may not overlap with the above driving voltage line.

[0013] The third semiconductor can overlap with the initialization voltage line and be electrically connected to the initialization voltage line.

[0014] One edge where the above third semiconductor and the above initialization voltage line overlap may overlap with the above third conductive layer.

[0015] The third conductive layer further includes an initial voltage connection located in overlap with the initial voltage line, and one edge where the third semiconductor and the initial voltage line overlap may overlap with the initial voltage connection.

[0016] The first semiconductor overlaps with the driving voltage line, and one edge where the first semiconductor and the driving voltage line overlap may overlap with the third conductive layer.

[0017] The third conductive layer includes a driving voltage connection portion located in overlap with the driving voltage line, and one edge where the first semiconductor and the driving voltage line overlap may overlap with the driving voltage connection portion.

[0018] The first conductive layer further includes a lower holding electrode that overlaps with the upper holding electrode, and one side of the lower holding electrode may be located inside the boundary of the upper holding electrode in a planar view.

[0019] The first semiconductor overlaps with the lower holding electrode, and one edge where the first semiconductor and the lower holding electrode overlap may overlap with the upper holding electrode.

[0020] A display device according to another embodiment comprises a substrate, a first conductive layer positioned on the substrate and including a data line, an initialization voltage line, and a driving voltage line, a semiconductor layer positioned on the first conductive layer, and a third conductive layer positioned on the semiconductor layer and including a plurality of cover members, wherein the semiconductor layer comprises a first semiconductor, a second semiconductor, and a third semiconductor spaced apart from each other, wherein the first semiconductor is electrically connected to the driving voltage line, the second semiconductor is electrically connected to the data line, and the third semiconductor is electrically connected to the initialization voltage line, wherein the first semiconductor overlaps with the driving voltage line, and one edge where the first semiconductor and the driving voltage line overlap overlaps with the cover member.

[0021] The above cover member may not be electrically connected to the first conductive layer.

[0022] The third semiconductor overlaps with the initialization voltage line, and one edge where the third semiconductor and the initialization voltage line overlap may overlap with the cover member.

[0023] The above third semiconductor may not overlap with the above driving voltage line.

[0024] The first conductive layer further includes an upper holding electrode located between the data line and the driving voltage line in a planar manner, and the upper holding electrode includes a protrusion, and the protrusion may overlap with the third semiconductor.

[0025] The second semiconductor may not overlap with the first conductive layer. Effects of the invention

[0026] According to the embodiments, a display device that minimizes damage to the semiconductor layer and hydrogen penetration is provided. Brief explanation of the drawing

[0027] FIG. 1 is a circuit diagram of a pixel of a light-emitting display device according to one embodiment. FIG. 2 is a plan view illustrating a part of a light-emitting display device according to one embodiment. FIG. 3 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the line III-III' of FIG. 2. FIG. 4 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the line IV-IV' of FIG. 2. FIG. 5 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the V-V' line of FIG. 2. Figures 6 and 7 are images of a damaged semiconductor layer when the first conductive layer and the semiconductor layer overlap. Figure 8 illustrates the process of hydrogen penetrating into the semiconductor layer due to damage to the semiconductor layer and the inorganic film. FIG. 9 briefly illustrates a case where the semiconductor layer is connected to the third conductive layer without overlapping with the first conductive layer, as shown in the cross-sections of FIG. 3 and FIG. 5. FIG. 10 briefly illustrates a case where the upper part of the portion where the semiconductor layer overlaps with the first conductive layer, as in the cross-section of FIG. 4, is covered by the third conductive layer. FIG. 11 is a layout diagram of a display device according to another embodiment. FIG. 12 is a cross-sectional view taken along the line XII-XII' of FIG. 11. FIG. 13 is a cross-sectional view illustrating a light-emitting display device according to one embodiment in its entirety. FIGS. 14 to 16 illustrate the color filter stacking process in a light-emitting display device according to the embodiment of FIG. 13 in a step-by-step manner. Specific details for implementing the invention

[0028] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0029] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0030] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0031] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity.

[0032] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0033] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0034] FIG. 1 is a circuit diagram of a pixel of a light-emitting display device according to one embodiment.

[0035] Figure 1 shows a circuit diagram of three pixels (PXa, PXb, PXc) including a group of light-emitting diodes (EDa, EDb, EDc).

[0036] A plurality of pixels may include a first pixel (PXa), a second pixel (PXb), and a third pixel (PXc). Each of the first pixel (PXa), the second pixel (PXb), and the third pixel (PXc) includes a plurality of transistors (T1, T2, T3), a holding capacitor (Cst), and a light-emitting diode (EDa, EDb, EDc) which is a light-emitting element. Here, a single pixel (PXa, PXb, PXc) may be divided into a light-emitting diode (EDa, EDb, EDc) and a pixel circuit, and the pixel circuit may include a plurality of transistors (T1, T2, T3) and a holding capacitor (Cst) in FIG. 1. Additionally, according to an embodiment, a light-emitting capacitor connected to both ends of the light-emitting diode (EDa, EDb, EDc) may be further included, and the light-emitting capacitor may not be included in the pixel circuit and may be included in the light-emitting diode (EDa, EDb, EDc).

[0037] A plurality of transistors (T1, T2, T3) are formed by one driving transistor (T1; also called the first transistor) and two switching transistors (T2, T3), and the two switching transistors are divided into an input transistor (T2; also called the second transistor) and an initialization transistor (T3; also called the third transistor). Each transistor (T1, T2, T3) includes a gate electrode, a first electrode, and a second electrode, respectively, and also includes a semiconductor layer including a channel, so that current flows or is blocked in the channel of the semiconductor layer depending on the voltage of the gate electrode. Here, depending on the voltage applied to each transistor (T1, T2, T3), one of the first electrode and the second electrode may be a source electrode and the other may be a drain electrode.

[0038] The gate electrode of the driving transistor (T1) is connected to one end of the holding capacitor (Cst) and is also connected to the second electrode (output side electrode) of the input transistor (T2). Additionally, the first electrode of the driving transistor (T1) is connected to a driving voltage line (172v) that transmits a driving voltage (ELVDD), and the second electrode of the driving transistor (T1) is connected to the anode of the light-emitting diode (EDa, EDb, EDc), the other end of the holding capacitor (Cst), and the first electrode of the initialization transistor (T3). The driving transistor (T1) receives data voltages (DVa, DVb, DVc) to its gate electrode according to the switching operation of the input transistor (T2), and can supply a driving current to the light-emitting diode (EDa, EDb, EDc) according to the voltage of the gate electrode. At this time, the holding capacitor (Cst) stores and maintains the voltage of the gate electrode of the driving transistor (T1).

[0039] The gate electrode of the input transistor (T2) is connected to the first scan signal line (151) that transmits the first scan signal (SC). The first electrode of the input transistor (T2) is connected to the data lines (171a, 171b, 171c) that transmit the data voltages (DVa, DVb, DVc), and the second electrode of the input transistor (T2) is connected to one end of the holding capacitor (Cst) and the gate electrode of the driving transistor (T1). The multiple data lines (171a, 171b, 171c) each transmit different data voltages (DVa, DVb, DVc), and the input transistor (T2) of each pixel (PXa, PXb, PXc) is connected to the different data lines (171a, 171b, 171c). The gate electrode of the input transistor (T2) of each pixel (PXa, PXb, PXc) is connected to the same first scan signal line (151) to receive the first scan signal (SC) of the same timing. Even if the input transistor (T2) of each pixel (PXa, PXb, PXc) is turned on simultaneously by the first scan signal (SC) of the same timing, different data voltages (DVa, DVb, DVc) are transmitted through different data lines (171a, 171b, 171c) to the gate electrode of the driving transistor (T1) of each pixel (PXa, PXb, PXc) and one end of the holding capacitor (Cst).

[0040] The embodiment of FIG. 1 is an embodiment in which the gate electrode of the initialization transistor (T3) receives a scan signal different from the gate electrode of the input transistor (T2).

[0041] The gate electrode of the initialization transistor (T3) is connected to a second scan signal line (151-1) that transmits a second scan signal (SS). The first electrode of the initialization transistor (T3) is connected to the other end of the holding capacitor (Cst), the second electrode of the driving transistor (T1), and the anode of the light-emitting diode (EDa, EDb, EDc), and the second electrode of the initialization transistor (T3) is connected to an initialization voltage line (173) that transmits an initialization voltage (VINT). The initialization transistor (T3) is turned on according to the second scan signal (SS) to transmit the initialization voltage (VINT) to the anode of the light-emitting diode (EDa, EDb, EDc) and the other end of the holding capacitor (Cst), thereby initializing the voltage of the anode of the light-emitting diode (EDa, EDb, EDc).

[0042] The initialization voltage line (173) may perform the role of a sensing wire (SL) by performing an operation to sense the voltage of the anode of the light-emitting diode (EDa, EDb, EDc) before applying the initialization voltage (VINT). Through the sensing operation, it can be confirmed whether the voltage of the anode is maintained at the target voltage. The sensing operation and the initialization operation of transmitting the initialization voltage (VINT) may be performed separately in time, and the initialization operation may be performed after the sensing operation is performed.

[0043] In the embodiment of FIG. 1, the turn-on intervals of the initialization transistor (T3) and the input transistor (T2) can be distinguished, so that the write operation performed by the input transistor (T2) and the initialization operation (and / or detection operation) performed by the initialization transistor (T3) can be performed at different timings.

[0044] One end of the holding capacitor (Cst) is connected to the gate electrode of the driving transistor (T1) and the second electrode of the input transistor (T2), and the other end is connected to the first electrode of the initialization transistor (T3), the second electrode of the driving transistor (T1), and the anode of the light-emitting diode (EDa, EDb, EDc). In FIG. 1, reference numerals are shown for one end and the other end of the holding capacitor (Cst), so as to clearly indicate which part in FIG. 2 and the like corresponds to the holding capacitor (Cst). Briefly, one end of the holding capacitor (Cst) is formed integrally with the gate electrode (155a, 155b, 155c) of the driving transistor (T1), and the other end of the holding capacitor (Cst) is located at the lower holding electrode (125a, 125b, 125c) and the upper holding electrode (175a, 175b, 175c). Referring to FIG. 2, the cross-sectional structure of the holding capacitor (Cst) has a lower holding electrode (125a, 125b, 125c) located at the very bottom, an insulated gate electrode (155a, 155b, 155c) of a driving transistor (T1) located above it, and an insulated upper holding electrode (175a, 175b, 175c) located above it. An insulating layer (120, 140, 160) located between these three layers acts as a dielectric layer, and the lower holding electrode (125a, 125b, 125c) and the upper holding electrode (175a, 175b, 175c) are electrically connected to each other so that they can have the same voltage.

[0045] The cathode of the light-emitting diode (EDa, EDb, EDc) receives a driving low voltage (ELVSS) through the driving low voltage line (174V), and the light-emitting diode (EDa, EDb, EDc) emits light according to the output current of the driving transistor (T1) to display a grayscale.

[0046] In addition, in one embodiment, a light-emitting capacitor (not shown) is formed at both ends of the light-emitting diodes (EDa, EDb, EDc) so that the voltage at both ends of the light-emitting diodes (EDa, EDb, EDc) can be maintained constant, thereby allowing the light-emitting diodes (EDa, EDb, EDc) to display a constant brightness.

[0047] Below, we will briefly examine the operation of a pixel having a circuit as shown in Fig. 1.

[0048] In FIG. 1, each transistor (T1, T2, T3) is an N-type transistor and has the characteristic of turning on when a high-level voltage is applied to the gate electrode. However, depending on the embodiment, each transistor (T1, T2, T3) may be a P-type transistor.

[0049] As the light emission period ends, one frame begins. After that, a high-level second scan signal (SS) is supplied, and the initialization transistor (T3) is turned on. When the initialization transistor (T3) is turned on, an initialization operation and / or a detection operation can be performed.

[0050] The following describes an embodiment in which both initialization and detection operations are performed.

[0051] A detection operation may be performed before the initialization operation is performed. That is, as the initialization transistor (T3) is turned on, the initialization voltage line (173) acts as the detection wire (SL) to detect the voltage of the anode of the light-emitting diode (EDa, EDb, EDc). Through the detection operation, it can be confirmed whether the voltage of the anode is maintained at the target voltage.

[0052] After that, an initialization operation may be performed, and the voltage of the other end of the holding capacitor (Cst), the second electrode of the driving transistor (T1), and the anode of the light-emitting diode (EDa, EDb, EDc) is changed to the initialization voltage (VINT) transmitted from the initialization voltage line (173) to perform the initialization.

[0053] In this way, the sensing operation and the initialization operation that transmits the initialization voltage (VINT) are performed separately in time, allowing the pixel to perform various operations while using a minimum number of transistors and reducing the area occupied by the pixel. As a result, the resolution of the display panel can be improved.

[0054] Along with the initialization operation or at a separate timing, the first scan signal (SC) is also applied while changing to a high level, so that the input transistor (T2) is turned on and a write operation is performed. That is, through the turned-on input transistor (T2), data voltages (DVa, DVb, DVc) from the data lines (171a, 171b, 171c) are input to the gate electrode of the driving transistor (T1) and one end of the holding capacitor (Cst) and stored.

[0055] Data voltages (DVa, DVb, DVc) and initialization voltages (VINT) are applied to both ends of the holding capacitor (Cst), respectively, through the initialization operation and the write operation. When the initialization transistor (T3) is turned on, even if an output current is generated from the driving transistor (T1), it can be output externally through the initialization transistor (T3) and the initialization voltage line (173) and thus not input to the light-emitting diodes (EDa, EDb, EDc). Additionally, according to the embodiment, during the write interval in which a high-level first scan signal (SC) is supplied, the driving voltage (ELVDD) may be applied at a low-level voltage, or the driving low voltage (ELVSS) may be applied at a high-level voltage so that current does not flow to the light-emitting diodes (EDa, EDb, EDc).

[0056] After that, when the first scan signal (SC) changes to a low level, the driving transistor (T1) generates and outputs an output current by the high-level driving voltage (ELVDD) applied to the driving transistor (T1) and the gate voltage of the driving transistor (T1) stored in the holding capacitor (Cst). The output current of the driving transistor (T1) is input to the light-emitting diodes (EDa, EDb, EDc), and a light-emitting section proceeds in which the light-emitting diodes (EDa, EDb, EDc) emit light.

[0057] The specific structure of the pixel circuit portion among the pixels (PXa, PXb, PXc) having a circuit structure as shown in FIG. 1 is examined in detail through FIG. 2 to 5. FIG. 2 is a plan view showing a part of a light-emitting display device according to one embodiment, FIG. 3 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the line III-III' of FIG. 2, FIG. 4 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the line IV-IV' of FIG. 2. FIG. 5 is a cross-sectional view of a light-emitting display device according to one embodiment shown along the line V-V' of FIG. 2.

[0058] As illustrated in FIG. 2, each pixel circuit is arranged in the y-axis direction. Referring to FIG. 2, the first pixel circuit belonging to the first pixel (PXa) is located at the top, the second pixel circuit belonging to the second pixel (PXb) is located below it, and the third pixel circuit belonging to the third pixel (PXc) is located at the bottom. Hereinafter, the three pixels (PXa, PXb, PXc) are also referred to as a group of pixels.

[0059] First, let's take a schematic look at the stacked structure of the light-emitting display device with reference to FIGS. 2 to 5.

[0060] A light-emitting display device according to one embodiment may include a substrate (110). The substrate (110) may include an insulating material such as glass or plastic and may have flexibility.

[0061] A first conductive layer, a first insulating layer (120), a semiconductor layer, a second insulating layer (140), a second conductive layer, a third insulating layer (160), a third conductive layer, and a fourth insulating layer (180) are sequentially formed on the substrate (110). Here, the first insulating layer (120), the second insulating layer (140), and the third insulating layer (160) may be inorganic insulating layers containing an inorganic insulating material, and the fourth insulating layer (180) may be an organic insulating layer containing an organic insulating material. According to the embodiment, each insulating layer may be formed as a plurality of layers, and according to the embodiment, the third insulating layer (160) may be an organic insulating layer. Here, the inorganic insulating material may include silicon nitride (SiNx), silicon oxide (SiOx), silicon nitrate (SiON), etc., and the organic insulating material may include polyimide, an acrylic polymer, a siloxane polymer, etc. Additionally, the first conductive layer, the second conductive layer, and the third conductive layer may include at least one of the following metals: copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. Each of the first conductive layer, the second conductive layer, and the third conductive layer may be composed of a single layer or multiple layers. For example, it may have a multilayer structure including a lower layer containing titanium and an upper layer containing copper. Meanwhile, the semiconductor layer may include semiconductor materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductors. In this embodiment, the semiconductor layer containing an oxide semiconductor is described with focus. The second insulating layer (140) may be formed by the same process as the second conductive layer and may have the same planar shape as the second conductive layer. That is, the second insulating layer (140) can be positioned overlapping with the second conductive layer.

[0062] Below, with reference to FIGS. 2 to 5, we will examine in detail each component included in the pixel circuit of a group of pixels.

[0063] The first scan signal line (151) extends in the x-axis direction, is formed one per group of pixel circuits, and is formed as a single layer on the third conductive layer. Additionally, the second scan signal line (151-1) also extends in the x-axis direction, is formed one per group of pixel circuits, and is formed as a single layer on the third conductive layer. Meanwhile, according to the embodiment, the first scan signal line (151) and the second scan signal line (151-1) may be formed as a plurality of layers, such as a double-layer structure.

[0064] The first scan signal line (151) is electrically connected to the gate electrode (156) located in the second conductive layer through the opening. The first scan signal (SC) is transmitted along the first scan signal line (151) and controls a plurality of input transistors (T2) included in a group of pixel circuits simultaneously through the gate electrode (156) electrically connected to the first scan signal line (151).

[0065] Meanwhile, the second scan signal line (151-1) is electrically connected to the gate electrode (157) located in the second conductive layer through the opening. The second scan signal (SS) is transmitted along the second scan signal line (151-1), and through the gate electrode (157) electrically connected to the second scan signal line (151-1), a plurality of initialization transistors (T3) included in a group of pixel circuits are controlled simultaneously.

[0066] The data lines (171a, 171b, 171c) extend in the y-axis direction, and all three data lines (171a, 171b, 171c) are located on one side of the pixel circuit (right side in FIG. 2). The data lines (171a, 171b, 171c) have a single-layer structure and are formed on the first conductive layer. Depending on the embodiment, they may be formed in multiple layers, such as a double-layer structure.

[0067] The data lines (171a, 171b, 171c) are each electrically connected to the second semiconductor (132a, 132b, 132c) through a connecting member (177a, 177b, 177c) located in the third conductive layer. Through this structure, even if three pixels (PXa, PXb, PXc) belonging to a group of pixels are controlled by a single first scan signal line (151), different data voltages (DVa, DVb, DVc) can be applied through different data lines (171a, 171b, 171c). As a result, each light-emitting diode (EDa, EDb, EDc) belonging to each pixel (PXa, PXb, PXc) can display different brightness.

[0068] The connecting members (177a, 177b, 177c) can be positioned along the x-axis direction, allowing the second semiconductor (132a, 132b, 132c) and the data lines (171a, 171b, 171c) to be connected without overlapping each other. Thus, the problem of the semiconductor layer being cut or the inorganic insulating layer above the semiconductor layer being cut due to the step difference of the first conductive layer as the semiconductor layer passes over the first conductive layer can be resolved. Specific configurations and effects will be described separately later.

[0069] The driving voltage line (172v) that transmits the driving voltage (ELVDD) may include a driving voltage line (172v) extended in the y-axis direction and an additional driving voltage line (172h) extended in the x-axis direction. The additional driving voltage line (172h) may be located in the third conductive layer, such as the additional driving low voltage line (174h) described later. That is, according to this embodiment, the driving voltage line (172v) located in the first conductive layer may be electrically connected to the additional driving voltage line (172h) located in the third conductive layer through an opening formed in the first insulating layer (120) and the third insulating layer (160). By transmitting the driving voltage (ELVDD) in the x-axis and y-axis directions in this way, it is possible to prevent the voltage value of the driving voltage (ELVDD) from dropping at a specific location.

[0070] According to the embodiment of FIG. 2, the driving voltage line (172v) extending in the y-axis direction is formed in a first conductive layer and may have a double-layer structure in some sections. That is, a driving voltage connection part (172-3v) located in a third conductive layer is further included above the driving voltage line (172v) located in the first conductive layer. The driving voltage connection part (172-3v) is electrically connected to the driving voltage line (172v) through an opening formed in the first insulating layer (120) and the third insulating layer (160), so that the driving voltage (ELVDD) is transmitted to the double layer of the driving voltage line (172v) and the driving voltage connection part (172-3v) in some sections, thus having the advantage of reducing wiring resistance. Additionally, the driving voltage connection part (172-3v) electrically connects the driving voltage line (172v) to the first semiconductor (131a, 131b, 131c) through an opening formed in the third insulating layer (160), so that the driving voltage (ELVDD) is transmitted to the first semiconductor (131a, 131b, 131c). As shown in FIG. 2, the driving voltage connection part (172-3v) may be positioned in multiple locations spaced apart from each other.

[0071] As will be explained separately later, the protrusions (1751a, 1751b, 1751c) of the upper holding electrodes (175a, 175b, 175c) may be positioned between the mutually spaced driving voltage connection portions (172-3v). The protrusions (1751a, 1751b, 1751c) allow the third semiconductor (133a, 133b, 133c) and the upper holding electrodes (175a, 175b, 175c) to be electrically connected without the third semiconductor (133a, 133b, 133c) overlapping with the driving voltage line (172v).

[0072] An initial voltage line (173) that transmits an initial voltage (VINT) is located to the left of the pixel circuit section, is located in the first conductive layer, and extends in the y-axis direction. The initial voltage line (173) of this embodiment includes a section having a double-layer structure. That is, it further includes an initial voltage connection section (173-3v) located in the third conductive layer above the initial voltage line (173) located in the first conductive layer. The initial voltage connection section (173-3v) is electrically connected to the initial voltage line (173) through an opening formed in the first insulating layer (120) and the third insulating layer (160). In some sections, the initial voltage (VINT) is transmitted to the double layer of the initial voltage line (173) and the initial voltage connection section (173-3v), so there is an advantage of reduced wiring resistance. In addition, the initial voltage connection (173-3v) is electrically connected to the third semiconductor (133a, 133b, 133c) through an opening formed in the third insulating layer (160) so that the initial voltage (VINT) is transmitted to the third semiconductor (133a, 133b, 133c).

[0073] Meanwhile, referring to the embodiment of FIG. 2, a driving low voltage line (174v) that transmits a driving low voltage (ELVSS) applied to the cathode of a light-emitting diode (EDa, EDb, EDc) is formed in the pixel circuit.

[0074] The driving low voltage line (174v) that transmits the driving low voltage (ELVSS) may include a driving low voltage line (174v) extended in the y-axis direction and an additional driving low voltage line (174h) extended in the x-axis direction. The driving low voltage line (174v) located in the first conductive layer is electrically connected to the additional driving low voltage line (174h) located in the third conductive layer through an opening formed in the first insulating layer (120) and the third insulating layer (160). By transmitting the driving low voltage (ELVSS) in the x-axis and y-axis directions in this way, it is possible to prevent the voltage value of the driving low voltage (ELVSS) from dropping at a specific location.

[0075] The driving low voltage line (174v) includes a section having a triple-layer structure. That is, the part (174-2v) located in the second conductive layer and the part (174-3v) located in the third conductive layer are electrically connected through an opening above the driving low voltage line (174v) located in the first conductive layer. Specifically, the driving low voltage line (174v) is electrically connected to the part (174-3v) located in the third conductive layer through an opening formed in the first insulating layer (120) and the third insulating layer (160), and the part (174-3v) located in the third conductive layer is electrically connected to the part (174-2v) located in the second conductive layer through an opening formed in the third insulating layer (160). In this embodiment, the driving low voltage line (174v) located in the first conductive layer and the portion (174-2v) located in the second conductive layer are not directly connected, but can be connected through the portion (174-3v) located in the third conductive layer. According to such a triple-layer structure, since the driving low voltage (ELVSS) is transmitted through the triple layer, there is an advantage in that the wiring resistance is reduced.

[0076] Additionally, an additional driving low voltage line (174h) located in the third conductive layer is electrically connected to the cathode of a light-emitting diode (EDa, EDb, EDc) by an opening (186) located in the fourth insulating layer (180), so that the driving low voltage (ELVSS) is transmitted to the cathode. Depending on the embodiment, a cathode connection part (not shown) located on the fourth insulating layer (180) and connecting the cathode of a light-emitting diode (EDa, EDb, EDc) may be further included.

[0077] Meanwhile, referring to Fig. 1, a driving low voltage (ELVSS) can also be applied to one electrode of the light-emitting capacitor.

[0078] A plurality of transistors (T1, T2, T3) have the same stacked structure and include a gate electrode located in a second conductive layer, a channel located in a semiconductor layer, and first and second regions located on both sides of the channel and doped to have characteristics identical or similar to those of a conductor. Here, the first and second regions located in the semiconductor layer may correspond to the first electrode and second electrode described in FIG. 1.

[0079] Specifically, a look at each transistor is as follows.

[0080] The driving transistor (T1) has a channel, a first region, and a second region in a first semiconductor (131a, 131b, 131c) located on a first insulating layer (120), and the first region and the second region are doped to have conductivity characteristics identical or similar to those of a conductor. The first region of the first semiconductor (131a, 131b, 131c) is electrically connected to a driving voltage line (172v) through an opening and a driving voltage connection (172-3v) to receive a driving voltage (ELVDD). Specifically, the driving voltage line (172v) is connected to the driving voltage connection part (172-3v) through an opening formed in the first insulating layer (120) and the third insulating layer (160), and the driving voltage connection part (172-3v) is electrically connected to the first semiconductor (131a, 131b, 131c) through an opening formed in the third insulating layer (160). Meanwhile, the second region of the first semiconductor (131a, 131b, 131c) is electrically connected to the upper holding electrode (175a, 175b, 175c) through an opening formed in the third insulating layer (160). Meanwhile, the upper holding electrodes (175a, 175b, 175c) are electrically connected to the lower holding electrodes (125a, 125b, 125c) through an opening formed in the first insulating layer (120) and the third insulating layer (160), and the upper holding electrodes (175a, 175b, 175c) are also electrically connected to the third semiconductor (133a, 133b, 133c) through an opening formed in the third insulating layer (160). As a result, the first semiconductor (131a, 131b, 131c) is also electrically connected to the lower holding electrodes (125a, 125b, 125c) and the first region of the third semiconductor (133a, 133b, 133c).

[0081] Gate electrodes (155a, 155b, 155c) are formed on the first semiconductor (131a, 131b, 131c). At this time, a second insulating layer (140) may be positioned between the first semiconductor (131a, 131b, 131c) and the gate electrodes (155a, 155b, 155c). A channel is formed in the first semiconductor (131a, 131b, 131c) that overlaps with the gate electrodes (155a, 155b, 155c) in a planar view, and the channel is covered by the gate electrodes (155a, 155b, 155c) and is not doped. The gate electrodes (155a, 155b, 155c) have protrusions, and the protrusions are electrically connected to the second semiconductor (132a, 132b, 132c) through openings and connecting members (176a, 176b, 176c). Specifically, the gate electrodes (155a, 155b, 155c) located in the second conductive layer are electrically connected to the connecting members (176a, 176b, 176c) located in the third conductive layer through openings formed in the third insulating layer (160), and the connecting members (176a, 176b, 176c) are electrically connected to the second semiconductor (132a, 132b, 132c) through openings formed in the third insulating layer (160). The connecting members (176a, 176b, 176c) are located in the same layer as the upper retaining electrodes (175a, 175b, 175c) and are made of the same material.

[0082] According to the embodiment of FIG. 2, the three gate electrodes (155a, 155b, 155c) included in the three pixels (PXa, PXb, PXc) may have different planar structures.

[0083] That is, focusing on the part where the three gate electrodes (155a, 155b, 155c) are electrically connected to the second semiconductor (132a, 132b, 132c), the gate electrode (155a) of the driving transistor (T1) of the first pixel (PXa) has a structure in which it is electrically connected to the second semiconductor (132a) from the upper side, the gate electrode (155b) of the driving transistor (T1) of the second pixel (PXb) has a structure in which it is electrically connected to the second semiconductor (132b) from the upper side, and the gate electrode (155c) of the driving transistor (T1) of the third pixel (PXc) has a structure in which it is electrically connected to the second semiconductor (132c) from the lower side.

[0084] The structure of each gate electrode (155a, 155b, 155c) is examined in detail as follows.

[0085] The gate electrode (155a) of the driving transistor (T1) of the first pixel (PXa) includes a portion that overlaps with the first semiconductor (131a) and a portion that extends from thereto and overlaps with the lower holding electrode (125a) and the upper holding electrode (175a) to form the other electrode of the holding capacitor (Cst). Additionally, the gate electrode (155a) of the driving transistor (T1) of the first pixel (PXa) further includes a protrusion that protrudes and is electrically connected to a connecting member (176a) through an opening formed in the third insulating layer (160). Additionally, the upper holding electrode (175a) may include a portion that is removed so that it can be electrically connected to the lower holding electrode (125a) through an opening formed in the first insulating layer (120) and the third insulating layer (160).

[0086] Here, the boundary line of the gate electrode (155a) of the driving transistor (T1) of the first pixel (PXa) may be located inward in a planar view from the boundary line of the lower holding electrode (125a) and / or the boundary line of the upper holding electrode (175a) that overlaps therewith, except for the protrusion. That is, the gate electrode (155a) has a structure protected by the lower holding electrode (125a) and / or the upper holding electrode (175a), so that the lower holding electrode (125a) and / or the upper holding electrode (175a) mainly form parasitic capacitance with the adjacent pixel (PXb). This is because the gate electrode (155a) of the driving transistor (T1) of the first pixel (PXa) is obscured by the lower holding electrode (125a) and / or the upper holding electrode (175a) located above and below, and also because most of the generated power lines are connected to the lower holding electrode (125a) and / or the upper holding electrode (175a) before entering the gate electrode (155a).

[0087] The gate electrode (155b) of the driving transistor (T1) of the second pixel (PXb) includes a portion that overlaps with the first semiconductor (131b) and a portion that extends from thereto and overlaps with the lower holding electrode (125b) and the upper holding electrode (175b) to form the other electrode of the holding capacitor (Cst). Additionally, the gate electrode (155b) of the driving transistor (T1) of the second pixel (PXb) further includes a protrusion that protrudes and is electrically connected to the connecting member (176b) through an opening formed in the third insulating layer (160). Additionally, the upper holding electrode (175b) may include a portion that is removed so that it can be electrically connected to the lower holding electrode (125b) through an opening formed in the first insulating layer (120) and the third insulating layer (160).

[0088] Here, the boundary line of the gate electrode (155b) of the driving transistor (T1) of the second pixel (PXb) may be located inward in a planar view than the boundary line of the lower holding electrode (125b) and / or the boundary line of the upper holding electrode (175b) that overlaps therewith, except for the protrusion. The gate electrode (155b) has a structure protected by the lower holding electrode (125b) and / or the upper holding electrode (175b), so that the lower holding electrode (125b) and / or the upper holding electrode (175b) mainly form parasitic capacitance with the adjacent pixels (PXa, PXc). This is because the gate electrode (155b) of the driving transistor (T1) of the second pixel (PXb) is obscured by the lower holding electrode (125b) and / or the upper holding electrode (175b) located above and below, and also because most of the generated power lines are connected to the lower holding electrode (125b) and / or the upper holding electrode (175b) before entering the gate electrode (155b).

[0089] The gate electrode (155c) of the driving transistor (T1) of the third pixel (PXc) includes a portion that overlaps with the first semiconductor (131c) and a portion that extends from thereto and overlaps with the lower holding electrode (125c) and the upper holding electrode (175c) to form the other electrode of the holding capacitor (Cst). Additionally, the gate electrode (155c) of the driving transistor (T1) of the third pixel (PXc) further includes a protrusion that protrudes and is electrically connected to a connecting member (176c) through an opening formed in the third insulating layer (160). Furthermore, the upper holding electrode (175c) may include a portion that is removed so that it can be electrically connected to the lower holding electrode (125c) through an opening formed in the first insulating layer (120) and the third insulating layer (160).

[0090] Here, the boundary line of the gate electrode (155c) of the driving transistor (T1) of the third pixel (PXc) may be located inward in a planar view from the boundary line of the lower holding electrode (125c) and / or the boundary line of the upper holding electrode (175c) that overlaps therewith, except for the protrusion. That is, the gate electrode (155c) has a structure protected by the lower holding electrode (125c) and / or the upper holding electrode (175c), so that the lower holding electrode (125c) and / or the upper holding electrode (175c) mainly form parasitic capacitance with the adjacent pixel (PXb). This is because the gate electrode (155c) of the driving transistor (T1) of the third pixel (PXc) is obscured by the lower holding electrode (125c) and / or the upper holding electrode (175c) located above and below, and also because most of the generated power lines are connected to the lower holding electrode (125c) and / or the upper holding electrode (175c) before entering the gate electrode (155c).

[0091] According to FIG. 2, the boundary of the lower holding electrode (125a, 125b, 125c) is located further inward than that of the upper holding electrode (175a, 175b, 175c). That is, the boundary line of the lower holding electrode (125a, 125b, 125c) may be located further inward in the planar view than the boundary line of the upper holding electrode (175a, 175b, 175c). This is intended to prevent hydrogen, etc. from penetrating into the semiconductor layer by covering the upper surface of the semiconductor layer passing over the lower holding electrode (125a, 125b, 125c) with the upper holding electrode (175a, 175b, 175c), as will be explained separately later. In addition, even if the semiconductor layer crossing the lower retaining electrodes (125a, 125b, 125c) is broken or the inorganic insulating layer is damaged due to the step difference of the lower retaining electrodes (125a, 125b, 125c), the upper retaining electrodes (175a, 175b, 175c) cover the upper surface of the damaged portion, thereby preventing hydrogen from penetrating into the semiconductor layer.

[0092] The input transistor (T2) has a channel, a first region, and a second region in a second semiconductor (132a, 132b, 132c) located on the first insulating layer (120), and the first region and the second region are doped to have conductivity characteristics identical or similar to those of a conductor. The first region of the second semiconductor (132a, 132b, 132c) is electrically connected to a connecting member (177a, 177b, 177c) through an opening formed in the third insulating layer (160), and the connecting member (177a, 177b, 177c) is electrically connected to a data line (171a, 171b, 171c) through an opening formed in the first insulating layer (120) and the third insulating layer (160) to receive a data voltage (DVa, DVb, DVc). A second region of the second semiconductor (132a, 132b, 132c) is electrically connected to an opening and a connecting member (176a, 176b, 176c) formed in the third insulating layer (160), and the connecting member (176a, 176b, 176c) is electrically connected to a gate electrode (155a, 155b, 155c) through an opening formed in the third insulating layer (160). According to an embodiment, the connecting member (176a, 176b, 176c) may have a structure that extends toward the channel of the second semiconductor (132a, 132b, 132c) and covers the channel of the second semiconductor (132a, 132b, 132c).

[0093] As shown in FIG. 2, the second semiconductor (132a, 132b, 132c) may not overlap with the data lines (171a, 171b, 171c). The second semiconductor (132a, 132b, 132c) does not pass over or intersect the upper surface of the data lines (171a, 171b, 171c).

[0094] The second semiconductor (132a, 132b, 132c) is connected to the data line (171a, 171b, 171c) through a connecting member (177a, 177b, 177c) located along the x-axis direction. The connecting member (177a, 177b, 177c) may be located along the x-axis direction, and the second semiconductor (132a, 132b, 132c) and the data line (171a, 171b, 171c) may be connected through an opening that overlaps with the connecting member (177a, 177b, 177c).

[0095] That is, the second semiconductor (132a, 132b, 132c) and the data line (171a, 171b, 171c) can be connected by the connecting member (177a, 177b, 177c) without overlapping each other. Therefore, the problem of the semiconductor layer being cut or the inorganic insulating layer above the semiconductor layer being damaged due to the step difference of the first conductive layer as the semiconductor layer passes over the first conductive layer can be resolved. Specific effects will be described separately later.

[0096] A gate electrode (156) is formed on the second semiconductor (132a, 132b, 132c). At this time, a second insulating layer (140) may be positioned between the second semiconductor (132a, 132b, 132c) and the gate electrode (156). A channel is formed in the second semiconductor (132a, 132b, 132c) that overlaps with the gate electrode (156) in a planar view, and the channel is covered by the gate electrode (156) and is not doped. The gate electrode (156) is extended and electrically connected to a first scan signal line (151) located in the third conductive layer through an opening formed in the third insulating layer (160).

[0097] The initialization transistor (T3) has a channel, a first region, and a second region in a third semiconductor (133a, 133b, 133c) located on the first insulating layer (120), and the first region and the second region are doped to have conductivity characteristics identical or similar to those of a conductor. The first region of the third semiconductor (133a, 133b, 133c) is connected to a protrusion (1751a, 1751b, 1751c) extending in the x-axis direction through an opening formed in the third insulating layer (160) of the upper retaining electrode (175a, 175b, 175c). Meanwhile, the upper holding electrodes (175a, 175b, 175c) are electrically connected to the lower holding electrodes (125a, 125b, 125c) through an opening formed in the first insulating layer (120) and the third insulating layer (160), and are also electrically connected to the first semiconductor (131a, 131b, 131c) through an opening formed in the third insulating layer (160). The second region of the third semiconductor (133a, 133b, 133c) is electrically connected to the initial voltage connection part (173-3v) through an opening formed in the third insulating layer (160) to receive the initial voltage (VINT). A gate electrode (157) is formed on the third semiconductor (133a, 133b, 133c). At this time, a second insulating layer (140) may be positioned between the third semiconductor (133a, 133b, 133c) and the gate electrode (157). A channel is formed in the third semiconductor (133a, 133b, 133c) that overlaps with the gate electrode (157) in a planar view, and the channel is covered by the gate electrode (157) and is not doped. The gate electrode (157) is extended and electrically connected to a second scan signal line (151-1) located in the third conductive layer through an opening formed in the third insulating layer (160).

[0098] As illustrated in FIG. 2, the third semiconductor (133a, 133b, 133c) may not overlap with the driving voltage line (172v). As illustrated in FIG. 2, the driving voltage line (172v) may include a portion that is removed so as not to overlap with the third semiconductor (133a, 133b, 133c). The third semiconductor (133a, 133b, 133c) does not overlap with the driving voltage line (172v) and does not cross the driving voltage line (172v).

[0099] Instead, the upper retaining electrodes (175a, 175b, 175c) include protrusions (1751a, 1751b, 1751c) extending in the x-axis direction. Each protrusion (1751a, 1751b, 1751c) may overlap with the third semiconductor (133a, 133b, 133c) across the driving voltage line (172v). The protrusions (1751a, 1751b, 1751c) may be located between spaced-apart driving voltage connections (172-3v). The protrusions (1751a, 1751b, 1751c) are electrically connected to the third semiconductor (133a, 133b, 133c) through the opening, so the third semiconductor (133a, 133b, 133c) can be electrically connected to the upper holding electrode (175a, 175b, 175c) without overlapping with the driving voltage line (172v).

[0100] As the upper retaining electrode (175a, 175b, 175c) and the third semiconductor (133a, 133b, 133c) are connected by the protrusions (1751a, 1751b, 1751c) extending in the x-axis direction, the third semiconductor (133a, 133b, 133c) may not cross the driving voltage line (172v) located in the first conductive layer. Therefore, the problem of the semiconductor layer being broken or the inorganic insulating layer above the semiconductor layer being broken due to the step difference of the first conductive layer can be resolved.

[0101] The holding capacitor (Cst) includes holding capacitor 1 (Cst1) and holding capacitor 2 (Cst2).

[0102] The holding capacitor 1 (Cst1) is composed of a gate electrode (155a, 155b, 155c) located on the second conductive layer, a third insulating layer (160) located thereon, and an upper holding electrode (175a, 175b, 175c) located thereon. Additionally, the holding capacitor 2 (Cst2) is composed of a lower holding electrode (125a, 125b, 125c) located on the first conductive layer, a first insulating layer (120) located thereon, and a gate electrode (155a, 155b, 155c) located thereon. As a result, it has a triple-layer structure of two holding electrodes (upper holding electrode (175a, 175b, 175c) and lower holding electrode (125a, 125b, 125c)) that overlap vertically in a planar view while sharing the gate electrode (155a, 155b, 155c).

[0103] The lower holding electrodes (125a, 125b, 125c) and the upper holding electrodes (175a, 175b, 175c) are electrically connected to each other through openings formed in the first insulating layer (120) and the third insulating layer (160), and since the gate electrodes (155a, 155b, 155c) are commonly included in the holding capacitor 1 (Cst1) and the holding capacitor 2 (Cst2), the holding capacitor 1 (Cst1) and the holding capacitor 2 (Cst2) have a structure in which they are connected in parallel in terms of circuit structure. Since they have a structure in which they are connected in parallel in terms of circuit structure, the total capacitance of the holding capacitor (Cst) has the sum of the capacitance of the holding capacitor 1 (Cst1) and the capacitance of the holding capacitor 2 (Cst2).

[0104] The upper retaining electrodes (175a, 175b, 175c) are formed integrally and are electrically connected to the anode (not shown) of a light-emitting diode (EDa, EDb, EDc) through an opening (185a, 185b, 185c) formed in the fourth insulating layer (180). Depending on the embodiment, an additional member (anode connecting member) connecting the upper retaining electrodes (175a, 175b, 175c) and the anode may be further included.

[0105] The light-emitting diodes (EDa, EDb, EDc) include an anode (see 191 in FIG. 13), a light-emitting layer (see 370 in FIG. 13), and a cathode (see 270 in FIG. 13), and the anode is positioned on top of a fourth insulating layer (180). Additionally, a partition (see 350 in FIG. 13) may be formed to separate the light-emitting diodes from each other, and the partition (350) may have a structure in which the anode is exposed through an opening, the light-emitting layer (370) is formed through the exposed portion, and the cathode (270) is formed thereon.

[0106] According to the embodiment, the light-emitting layer may be formed only within the opening of the partition, but according to the embodiment of FIG. 13, the light-emitting layer (370) is also formed on the exposed anode (191) and the partition (350). The cathode (270) is formed on the light-emitting layer (370). According to the embodiment of FIG. 13, the light-emitting layer (370) and the cathode (270) are formed entirely so that a mask may not be used.

[0107] The upper part of the light-emitting diode (EDa, EDb, EDc) may include an encapsulation layer, a color conversion layer, or a color filter, and such a structure will be examined in Fig. 13, which will be described later.

[0108] In the above, the structure of the pixels (PXa, PXb, PXc) of a display device according to one embodiment was examined in detail.

[0109] The main feature of the present invention is that the semiconductor layer is not overlapped with the first conductive layer, thereby preventing damage to the semiconductor layer and the upper inorganic layer caused by the step difference of the first conductive layer.

[0110] Referring to FIG. 3, the second semiconductor (132a) according to the present embodiment does not overlap in a direction perpendicular to the data line (171a) and the substrate (110).

[0111] Referring to FIG. 2 and FIG. 3 simultaneously, the second semiconductor (132a) is connected to the data line (171a) and the second semiconductor (132a) through a connecting member (177a) that overlaps with both. That is, the second semiconductor (132a) is connected to the data line (171a) by an opening that overlaps with the connecting member (177a) and receives a data voltage.

[0112] This is also the same in FIG. 5. Referring to FIG. 5, the third semiconductor (133a) according to the present embodiment does not overlap the driving voltage line (172v) and the substrate (110) in a direction perpendicular to them. Instead, a protrusion (1751a) extending from the upper holding electrode (175a) overlaps the driving voltage line (172v) and the third semiconductor (133a). The third semiconductor (133a) is connected to the upper holding electrode (175a) through an opening that overlaps with the protrusion (1751a).

[0113] Also, with reference to FIG. 4, the first semiconductor (131a) is positioned overlapping the driving voltage line (172v), which is the first conductive layer, and the lower holding electrode (125a). However, in this case, the edge where the first semiconductor (131a) overlaps with the driving voltage line (172v) is covered by the driving voltage connection part (172-3v). That is, the part where the first semiconductor (131a) and the driving voltage line (172v) begin to overlap is covered by the driving voltage connection part (172-3v), which is the third conductive layer. Likewise, the edge where the first semiconductor (131a) overlaps with the lower holding electrode (125a) is covered by the upper holding electrode (175a), which is the third conductive layer.

[0114] That is, in the part where the semiconductor layer overlaps with the first conductive layer, such as the first semiconductor (131a), the upper part of the overlapping boundary region is covered by the third conductive layer. Therefore, even if the inorganic insulating layer breaks in the overlapping part, the upper part of the inorganic insulating layer is covered by the third conductive layer, so the penetration path of hydrogen can be blocked by the third conductive layer.

[0115] That is, as can be seen in FIGS. 3 and 5, the display device according to the present embodiment does not have a portion of the second semiconductor (132a) and the third semiconductor (133a) overlapping with the first conductive layer. Therefore, when the second semiconductor (132a) and the third semiconductor (133a) overlap with the first conductive layer, the phenomenon of the semiconductor layer being damaged or the inorganic insulating layer being torn due to the step difference of the first conductive layer can be prevented.

[0116] Alternatively, as can be seen in FIG. 4, the edge of the region where the first semiconductor (131a) overlaps with the first conductive layer is covered by the third conductive layer. In this case, even if the semiconductor layer is damaged or the inorganic insulating layer is torn due to the step difference of the first conductive layer, the torn region is covered by the third conductive layer, so that hydrogen can be prevented from diffusing into the semiconductor layer. That is, the diffusion path of hydrogen can be blocked by the third conductive layer.

[0117] Figures 6 and 7 are images showing damage to the semiconductor layer when the first conductive layer and the semiconductor layer overlap. As can be seen in Figure 6, the semiconductor layer (ACT) is positioned over the light-blocking member (BML), which is the first conductive layer.

[0118] At this time, a portion of the semiconductor layer (ACT) may be damaged due to the step difference of the light-blocking member (BML). In Fig. 6, the damaged portion is indicated by a dotted circle.

[0119] In the case of Fig. 6, residual particles may be generated at the end of the light-blocking member (BML), which can worsen the coverage of the upper inorganic layer. Consequently, the semiconductor layer (ACT) itself may break, or even if the semiconductor layer (ACT) does not break, the coverage of the inorganic layer formed over the semiconductor layer (ACT) may be poor, which can lead to damage to the inorganic layer.

[0120] Fig. 7 also shows that a semiconductor layer (ACT) is positioned over a light-blocking member (BML), which is a first conductive layer. At this time, the light-blocking member (BML) can be formed as a double film, for example, a Ti / Cu double film. In this case, due to the difference in etching ratio between Ti and Cu, Cu may be pushed inward relative to Ti, and the taper may not be uniform. Due to such non-uniform taper, the semiconductor layer (ACT) or the upper inorganic layer may be damaged.

[0121] Referring to FIGS. 6 and 7, in the case of a structure where a semiconductor layer (ACT) overlaps with a light-blocking member (BML), which is a first conductive layer, the semiconductor layer (ACT), the inorganic layer, and the third conductive layer (SD) may be damaged at the interface where they overlap with the first conductive layer. Hydrogen contained in the upper organic layer may diffuse into the semiconductor layer (ACT) through the region where the semiconductor layer (ACT) and the inorganic layer are damaged. In this case, the conductivity of the semiconductor layer (ACT) may be affected by hydrogen, and the reliability of the transistor composed of the semiconductor layer (ACT) may be reduced.

[0122] FIG. 8 illustrates the process of hydrogen penetrating into the semiconductor layer (ACT) due to damage to the semiconductor layer (ACT) and the inorganic layer (ILD). Referring to FIG. 8, the semiconductor layer (ACT) overlapping with the light-shielding member (BML), which is the first conductive layer, is susceptible to damage due to the step difference, particles, or uneven taper of the light-shielding member (BML), as previously explained. The semiconductor layer (ACT) may be damaged, or even if the semiconductor layer (ACT) is not damaged, the inorganic layer (ILD) located above it may be damaged. In FIG. 8 to 10, the buffer layer (BUF) may correspond to the first insulating layer (120), the inorganic layer (ILD) to the second insulating layer (140), the protective film (PVX) to the third insulating layer (160), and the organic layer (VIA) to the fourth insulating layer (180). In FIGS. 8 and 10, the inorganic layer (ILD) is shown as being located over the entire semiconductor layer (ACT), but according to the embodiment, the inorganic layer (ILD) may be located as a pattern on the channel region of the semiconductor layer (ACT).

[0123] In the stacked structure of the display device, an organic layer (VIA) is located above an inorganic layer (ILD), and the organic layer (VIA) contains a large amount of hydrogen. At this time, the hydrogen contained within the organic layer (VIA) can diffuse into the semiconductor layer (ACT) through the damaged inorganic layer (ILD) and affect the performance of the transistor. In Fig. 8, the damaged part of the inorganic layer (ILD) is shown in black.

[0124] However, as previously discussed, the display device according to the present embodiment prevents the second semiconductor (132a) and the third semiconductor (133a) from overlapping with the first conductive layer, and the portion where the first semiconductor (131a) overlaps with the first conductive layer is covered by the third conductive layer to prevent the diffusion of hydrogen.

[0125] FIG. 9 briefly illustrates a case where the semiconductor layer is connected to the third conductive layer without overlapping with the first conductive layer, as shown in the cross-sections of FIG. 3 and FIG. 5. Referring to FIG. 9, the semiconductor layer (ACT) does not overlap with the light-shielding member (BML), which is the first conductive layer, and the semiconductor layer (ACT) is connected to the third conductive layer (SD). Therefore, the semiconductor layer (ACT) is not damaged by the step difference, particles, non-uniform taper, etc. of the first conductive layer. Even if the buffer layer (BUF) or the inorganic layer (ILD) is damaged at the edge of the light-shielding member (BML), which is the first conductive layer in FIG. 9, the damaged area is covered by the third conductive layer (SD). Therefore, the third conductive layer (SD) can block the penetration path of hydrogen contained in the organic layer (VIA). Accordingly, hydrogen does not penetrate into the semiconductor layer (ACT), and the transistor can operate stably.

[0126] FIG. 10 briefly illustrates a case where the upper portion of the semiconductor layer overlapping with the first conductive layer is covered by a third conductive layer, as shown in the cross-section of FIG. 4. As illustrated in FIG. 10, damage to the buffer layer (BUF), the semiconductor layer (ACT), or the inorganic layer (ILD) may occur in the region where the semiconductor layer (ACT) overlaps with the light-blocking member (BML), which is the first conductive layer. However, as illustrated in FIG. 10, the boundary where such damage occurs is covered by the third conductive layer (SD). Therefore, the path for hydrogen contained in the organic layer (VIA) to penetrate is blocked by the third conductive layer (SD), and the penetration of hydrogen into the semiconductor layer (ACT) can be reduced, allowing the transistor to operate stably.

[0127] In the above description, an embodiment was described in which the upper part of the boundary region where the first semiconductor (131a, 131b, 131c) overlaps with the first conductive layer is covered by the third conductive layer, and a part of the second semiconductor layer and the third semiconductor layer does not overlap with the first conductive layer.

[0128] FIG. 11 is a layout diagram of a display device according to another embodiment. Referring to FIG. 11, the display device according to the present embodiment does not include a driving voltage connection part (172-3v) and an initialization voltage connection part (173-3v), and includes a cover member (178) located at the boundary where the semiconductor layer and the first conductive layer overlap. As shown in FIG. 11, the cover member (178) is formed in the region where the driving voltage line (172v), which is the first conductive layer, intersects with the first semiconductor (131a, 131b, 131c). As previously explained, when the semiconductor layer passes over the first conductive layer, the semiconductor layer or the inorganic insulating layer located on the semiconductor layer may be damaged due to the step difference of the first conductive layer. At this time, due to such damage to the semiconductor layer and the inorganic insulating layer, hydrogen contained in the upper organic layer may diffuse into the semiconductor layer and reduce the performance of the device.

[0129] However, the display device according to the present embodiment has a cover member (178) positioned at the boundary portion where the first semiconductor (131a, 131b, 131c) and the driving voltage line (172v) overlap, as shown in FIG. 11. That is, by covering the upper part of the area where the semiconductor layer or the inorganic insulating layer located on the semiconductor layer may be damaged with the cover member (178), the diffusion path of hydrogen is blocked.

[0130] Likewise, the cover member (178) is also located at the boundary where the third semiconductor (133a, 133b, 133c) and the initial voltage line (173) overlap. As shown in FIG. 11, the cover member (178) is located at the boundary where the third semiconductor (133a, 133b, 133c) and the initial voltage line (173) overlap. Therefore, even if the semiconductor layer or the inorganic insulating layer is damaged at the edge where the third semiconductor (133a, 133b, 133c) and the initial voltage line (173) begin to overlap, the diffusion path of hydrogen is blocked by the cover member (178), so the semiconductor layer can operate stably.

[0131] FIG. 12 is a cross-sectional view taken along the line XII-XII' of FIG. 11. Referring to FIG. 12, a cover member (178) is positioned above the boundary surface where the third semiconductor (133a) and the initialization voltage line (173) begin to overlap. Therefore, even if the third semiconductor (133a) is damaged due to the step difference, residual particles, or non-uniform taper of the initialization voltage line (173), the inflow of hydrogen is blocked by the cover member (178), thereby maintaining the performance of the transistor. At this time, the width (H) of the cover member (178) can satisfy the following mathematical formula 1.

[0132] [Mathematical Formula 1]

[0133] H =

[0134] In the above mathematical formula 1, skew is the skew value during etching of the first and third conductive layers, and CD deviation and overlay tolerance may be unique values ​​derived from each process. That is, the width (H) of the cover member (178) may vary depending on the material and process environment of each conductive layer constituting the display device.

[0135] As described above, the display device according to the present embodiment connects the semiconductor layer and the first conductive layer to the third conductive layer so that the semiconductor layer and the first conductive layer do not overlap, or covers the boundary of the overlapping region of the semiconductor layer and the first conductive layer with the third conductive layer. Accordingly, damage to the semiconductor layer or the inorganic insulating layer above the semiconductor layer is prevented in the overlapping region of the semiconductor layer and the first conductive layer, and even if the semiconductor layer or the inorganic insulating layer is damaged, the upper part of the damaged region is covered with the third conductive layer to prevent hydrogen from diffusing into the semiconductor layer. Therefore, the performance of the transistor can be maintained stably.

[0136] Meanwhile, the light-emitting display device has a light-emitting diode formed on the fourth insulating layer, comprising an anode, a light-emitting layer, and a cathode, and may additionally include an encapsulation layer, a color conversion layer, or a color filter on the light-emitting diode. Below, the cross-sectional structure of the entire light-emitting display device will be examined in detail through FIG. 13.

[0137] FIG. 13 is a cross-sectional view illustrating a light-emitting display device according to one embodiment in its entirety.

[0138] In FIG. 13, the pixel circuit portion of the configuration of the light-emitting display device according to the previously described embodiment is omitted, and the anode (191) constituting the light-emitting diodes (EDa, EDb, EDc) is shown in general.

[0139] The display device according to FIG. 13 includes a display panel (100) and a color conversion panel (200). The display panel (100) will be described first below.

[0140] As shown in FIG. 13, an anode (191) is formed on each pixel (PXa, PXb, PXc) on the first substrate (110). A pixel circuit structure, such as a plurality of transistors and an insulating layer located between the first substrate (110) and the anode (191), has been omitted, and, for example, they can be arranged as shown in FIG. 2 to FIG. 5.

[0141] A bulkhead (350) is positioned above the anode (191), and the bulkhead (350) includes an opening that exposes a part of the anode (191).

[0142] A light-emitting layer (370) may be positioned on the anode (191) and the partition (350), and in this embodiment, the light-emitting layer (370) is positioned over the entire area. At this time, the light-emitting layer (370) may be a light-emitting layer that emits a first color light, which may be blue light. According to the embodiment, the light-emitting layer (370) may be a multilayer structure. At this time, the light-emitting layer (370) may be a multilayer structure that emits blue light and green light. Alternatively, the light-emitting layer (370) may be a structure in which layers emitting blue light are formed in multiple layers. According to the embodiment, the light-emitting layer (370) may be a structure in which layers emitting blue light, green light, and red light are stacked.

[0143] Additionally, depending on the embodiment, the light-emitting layer (370) may be formed separately from each other with the opening of each pixel as the center, and in this case, the light-emitting layer of each pixel may emit light of a different color. A cathode (270) may be positioned over the light-emitting layer (370).

[0144] A sealing layer (380) comprising a plurality of insulating layers (381, 382, ​​383) may be positioned on the cathode (270). The insulating layer (381) and the insulating layer (383) may include an inorganic insulating material, and the insulating layer (382) located between the insulating layer (381) and the insulating layer (383) may include an organic insulating material.

[0145] A filling layer (390) containing a filling agent may be located on top of the bag layer (380).

[0146] The filling layer (390) may be a layer that combines a display panel (100) including a first substrate (110) and a color conversion panel (200) including a second substrate (210).

[0147] The color conversion panel (200) is described below.

[0148] Referring to FIG. 13, a second substrate (210) facing the first substrate (110) is positioned. A color filter (230) including a blue color filter (230B), a red color filter (230R), and a green color filter (230G) is positioned on the second substrate (210).

[0149] Referring to FIG. 13, a blue dummy color filter (231R) is located on the same layer as the blue color filter (230B). The blue color filter (230B) is located in the blue light-emitting region (BLA), and the blue dummy color filter (231R) may be located in the non-light-emitting region (NLA) that overlaps with the bank (320). In FIG. 13, the blue color filter (230B) and the blue dummy color filter (231B) are depicted as separate components, but in reality, they may be connected.

[0150] FIGS. 14 to 16 illustrate the stacking order of a blue color filter (230B), a red color filter (230R), and a green color filter (230G). In FIG. 16, the cross-section shown by cutting along the line XIII-XIII' may correspond to FIG. 13.

[0151] Referring to FIG. 14, the blue color filter is located in the entire area excluding the green light-emitting region (GLA) and the red light-emitting region (RLA). Among these blue color filters, the blue color filter located in the blue light-emitting region (BLA) is the blue color filter (230B), and the blue color filter located in the non-light-emitting region (NLA) is the blue dummy color filter (231B). In FIG. 13, the two edges of the blue color filter (230B) are the non-light-emitting region (NLA) that overlaps with the bank (320), and are the blue dummy color filter (231B).

[0152] Next, referring to FIG. 13 and FIG. 15 simultaneously, a red color filter (230R) and a red dummy color filter (231R) are positioned on top of a blue color filter (230B) and a dummy color filter (231B). Referring to FIG. 15, the red color filter is positioned in the entire area excluding the green light-emitting region (GLA) and the blue light-emitting region (BLA). Among these red color filters, the red color filter located in the red light-emitting region (RLA) is the red color filter (230R), and the red color filter located in the non-light-emitting region (NLA) is the red dummy color filter (231R). In FIG. 13, the two edges of the red color filter (230R) are the non-light-emitting region (NLA) that overlaps with the bank (320), and thus are the red dummy color filter (231R).

[0153] Next, referring to FIG. 13 and FIG. 16 simultaneously, a green color filter (230G) and a green dummy color filter (231G) are positioned on top of a blue color filter (230B) and a blue dummy color filter (231B), a red color filter (230R) and a red dummy color filter (231R). Referring to FIG. 16, the green color filter is positioned in the entire area excluding the blue light-emitting region (BLA) and the red light-emitting region (RLA). Among these green color filters, the green color filter located in the green light-emitting region (GLA) is the green color filter (230G), and the green color filter located in the non-light-emitting region (NLA) is the green dummy color filter (231G). In FIG. 13, the two edges of the green color filter (230G) are the non-light-emitting region (NLA) that overlaps with the bank (320), and thus are the green dummy color filter (231G).

[0154] Referring to FIG. 13, a blue dummy color filter (231B), a red dummy color filter (231R), and a green dummy color filter (231G) are superimposed in an area overlapping with the bank (320). These blue dummy color filter (231B), red dummy color filter (231R), and green dummy color filter (231G) superimpose to form a color filter superposition (A). This color filter superposition (A) can function as a light-blocking member. That is, the color filter superposition (A) can block light in a non-luminous area (NLA).

[0155] At this time, the blue dummy color filter (231B) may be positioned closer to the second substrate (210) than the red dummy color filter (231R) and the green dummy color filter (231G). The direction in which the user views the image is toward the second substrate (210), and the blue dummy color filter (231B) may be positioned on the surface where the image is viewed. This is because, compared to green or red, blue has the lowest reflectivity for the entire light and can block light most effectively.

[0156] Referring to FIG. 13, a low-refractive index layer (351) may be positioned on the color filter (230). The low-refractive index layer (351) may have a refractive index of 1.2 or less. The low-refractive index layer (351) may be a mixture of organic and inorganic materials.

[0157] A plurality of banks (320) are positioned on the low-refractive index layer (351). The banks (320) may be positioned spaced apart from each other with a plurality of openings in between, and each opening may overlap in a direction perpendicular to the surface of each color filter (230R, 230G, 230B) and the second substrate (210).

[0158] The bank (320) may include scatterers. The scatterers may be one or more selected from the group consisting of SiO2, BaSO4, Al2O3, ZnO, ZrO2, and TiO2. The bank (320) may include a polymer resin and scatterers contained in the polymer resin. The content of the scatterers may be 0.1 wt% to 20 wt%. More preferably, the content of the scatterers may be 5 wt% to 10 wt%. A bank (320) containing scatterers within this range may scatter light emitted from a display panel to increase luminous efficiency. In another embodiment, the bank (320) may include a black material to block light and prevent color mixing between adjacent light-emitting regions.

[0159] A red color conversion layer (330R) and a transmission layer (330B) are located in the region between the mutually spaced banks (320). In FIG. 13, the red color conversion layer (330R) is located in the region overlapping with the red light emission region (RLA). The red color conversion layer (330R) can convert the supplied light into red. The red color conversion layer (330R) may include quantum dots. Similarly, in FIG. 13, the green color conversion layer (330G) is located in the region overlapping with the green light emission region (GLA). The green color conversion layer (330G) can convert the supplied light into green. The green color conversion layer (330G) may include quantum dots.

[0160] Then, quantum dots will be explained below.

[0161] The core of the quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0162] Group II-VI compounds are diatomic compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; ternary compounds selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; and may be selected from the group consisting of four-element compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0163] III-V compounds may be selected from the group consisting of diatomic compounds selected from GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

[0164] Group IV-VI compounds may be selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds may be ternary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0165] In this case, the binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or they may exist within the same particle with concentration distributions partially divided into different states. Additionally, the structure may have a core / shell configuration where one quantum dot surrounds another. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases towards the center.

[0166] In some embodiments, the quantum dot may have a core-shell structure comprising a core containing the aforementioned nanocrystal and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of the shell of the quantum dot include oxides of metals or non-metals, semiconductor compounds, or combinations thereof.

[0167] For example, the oxides of the metal or nonmetal mentioned above are SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, and Mn3O 4 Examples of diatomic compounds such as CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, and CoMn2O4 may be given, but the present invention is not limited thereto.

[0168] In addition, the above semiconductor compounds may be examples of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present invention is not limited thereto.

[0169] Quantum dots can have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and color purity or color reproducibility can be improved in this range. In addition, since the light emitted through these quantum dots is emitted in all directions, the viewing angle can be improved.

[0170] In addition, the shape of the quantum dots is not specifically limited to shapes commonly used in the field, but more specifically, shapes such as spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate particles may be used.

[0171] Quantum dots can control the color of the light they emit depending on their particle size, and accordingly, they can have various emission colors such as blue, red, and green.

[0172] Referring to FIG. 13, the color conversion layer is not located in the portion corresponding to the blue light-emitting region (BLA) within the space partitioned by the bank (320). Instead, a transparent layer (330B) may be located therein. The transparent layer (330B) may include a scatterer. The scatterer may be one or more selected from the group consisting of SiO2, BaSO4, Al2O3, ZnO, ZrO2, and TiO2. The transparent layer (330B) may include a polymer resin and a scatterer contained in the polymer resin. For example, the transparent layer (330B) may include TiO2, but is not limited thereto. The transparent layer (330B) can transmit light incident from the display panel.

[0174] In the color conversion panel and display device including the same according to the present embodiment, the red light emitting region (RLA) converts the incident light into red and emits it. Additionally, the green light emitting region (GLA) converts the incident light into green and emits it. However, the blue light emitting region (BLA) transmits the incident light without converting it into color. The incident light may include blue light. The incident light may be blue light alone, or a mixture of blue light and green light. Alternatively, it may include blue light, green light, and red light.

[0176] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0178] 131a, 131b, 131c: 1st semiconductor 132a, 132b, 132c: 2nd semiconductor 133a, 133b, 133c: Third semiconductor 172v: Driving voltage line 173: Initialization voltage line 174v: Driving low voltage line 151: 1st scan signal line 151-1: 2nd scan signal line 175a, 175b, 175c: Upper retaining electrodes 125a, 125b, 125c: Lower retaining electrodes 178: Cover missing

Claims

Claim 1 A display device comprising: a substrate; a first conductive layer located on the substrate and including a data line, an initial voltage line, and a driving voltage line; a semiconductor layer located on the first conductive layer, wherein the semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor spaced apart from each other, wherein the first semiconductor is electrically connected to the driving voltage line, the second semiconductor is electrically connected to the data line, the third semiconductor is electrically connected to the initial voltage line, and the second semiconductor does not overlap the data line in a direction perpendicular to the surface of the substrate; a second conductive layer located on the semiconductor layer, wherein the second semiconductor does not overlap the data line and the surface of the substrate; and a third conductive layer located on the second conductive layer and including a connecting member, wherein the driving voltage line is located along a second direction, and the third conductive layer includes an upper holding electrode located between the data line and the driving voltage line in a planar manner, wherein the upper holding electrode includes a protrusion protruding in a first direction intersecting the second direction, and the protrusion of the upper holding electrode is electrically connected to the third semiconductor. Claim 2 A display device according to claim 1, wherein the connecting member is positioned to overlap both the second semiconductor and the data line, and the second semiconductor and the data line are electrically connected through the connecting member. Claim 3 A display device according to paragraph 2, wherein the data line is positioned along a second direction, and the connecting member is positioned along a first direction intersecting the second direction. Claim 4 delete Claim 5 In claim 1, the protrusion of the upper retaining electrode is a display device that intersects the driving voltage line. Claim 6 delete Claim 7 In claim 1, the third semiconductor is a display device that does not overlap with the driving voltage line. Claim 8 In claim 1, the third semiconductor overlaps with the initialization voltage line and is a display device electrically connected to the initialization voltage line. Claim 9 In claim 8, a display device in which one edge overlapping the third semiconductor and the initialization voltage line overlaps with the third conductive layer. Claim 10 In claim 8, the third conductive layer further includes an initial voltage connection portion positioned overlapping with the initial voltage line, and a display device in which one edge overlapping with the third semiconductor and the initial voltage line overlaps with the initial voltage connection portion. Claim 11 A display device according to claim 1, wherein the first semiconductor overlaps with the driving voltage line, and one edge where the first semiconductor and the driving voltage line overlap overlaps with the third conductive layer. Claim 12 In claim 11, the third conductive layer includes a driving voltage connection portion positioned overlapping with the driving voltage line, and a display device in which one edge overlapping with the first semiconductor and the driving voltage line overlaps with the driving voltage connection portion. Claim 13 A display device according to claim 1, wherein the first conductive layer further comprises a lower holding electrode that overlaps with the upper holding electrode, and one side of the lower holding electrode is located inside the boundary of the upper holding electrode in a planar view. Claim 14 In paragraph 13, the first semiconductor overlaps with the lower holding electrode, and the edge where the first semiconductor and the lower holding electrode overlap overlaps with the upper holding electrode, forming a display device. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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