Logic Built In Self Test Apparatus

Abstract

The present embodiment is a Logic Built-In Self Test (LBIST) device, wherein the LBIST device comprises: a linear feedback shift register that generates a k-bit random signal and generates a selection signal therefrom; a subvector storage unit that stores a plurality of subvectors generated by dividing a deterministic seed in a priority order according to error detection efficiency; a plurality of mux blocks that are controlled by the selection signal and each select and output one subvector from among those stored in the subvector storage unit; and a decompressor that combines the subvectors output by the mux blocks to generate a test pattern, wherein each of the mux blocks selects the subvector with a higher priority with a higher probability compared to other subvectors (k: natural number).

Description

Technology Field

[0001] The present disclosure generally relates to an embedded logic self-test device. Background Technology

[0002] With the advancement of semiconductor manufacturing technology, the integration density and complexity of semiconductor chips are increasing, leading to a growing risk of failure; consequently, analyzing failures occurring in semiconductor devices is becoming increasingly important.

[0003] Semiconductor testing has traditionally been performed using dedicated external equipment; however, because using external equipment for every test is difficult and costly, embedded in-house testing methods have emerged. When testing semiconductors, embedded tests for memory are called MBIST, while those for logic are called LBIST. These embedded in-house tests are designed to perform tests only when the user desires; extensive research has been conducted on this method, and it is currently widely used for testing. The problem to be solved

[0004] Conventional built-in self-test (BIST) circuits provide a deterministic pattern designed to have high fault coverage to the device under test (DUT), and detect faults by capturing and analyzing the DUT's output.

[0005] The built-in self-test (BIST) received a random number pattern from a pseudo-random number pattern generator, input it into the DUT, captured it, analyzed it, and terminated. Therefore, performing multiple tests to achieve high test coverage consumed a long amount of time.

[0006] In addition, unlike decision patterns, the pseudo-random patterns generated by the pseudo-random pattern generator of the built-in self-test (BIST) have "0" and "1" randomly arranged, resulting in low test coverage.

[0007] This embodiment is intended to resolve the difficulties of the prior art and to provide an embedded logic self-test device capable of obtaining high test coverage through embedded self-testing. means of solving the problem

[0008] The present embodiment is a Logic Built-In Self Test (LBIST) device, wherein the LBIST device comprises: a linear feedback shift register that generates a k-bit random signal and generates a selection signal therefrom; a subvector storage unit that stores a plurality of subvectors generated by dividing a deterministic seed in a priority order according to error detection efficiency; a plurality of multiplexer (mux) blocks that are controlled by the selection signal and each select and output one subvector from among those stored in the subvector storage unit; and a decompressor that combines the subvectors output by the mux blocks to generate a test pattern, wherein each of the mux blocks selects the subvector with a higher priority with a higher probability compared to other subvectors (k: natural number).

[0009] According to one aspect of the present embodiment, the linear feedback shift register (100) comprises a plurality of D flip-flops connected in series; one or more XOR gates that receive D flip-flop outputs at predetermined positions and generate a feedback signal, and provides the feedback signal as an input to the first D flip-flop.

[0010] According to one aspect of the present embodiment, the priority of the subvectors is determined by measuring the reduction in error detection rate when each subvector generated from the deterministic seed is individually removed, and assigning a higher priority starting from the subvector with the largest reduction in error detection rate.

[0011] According to one aspect of the present embodiment, each of the mux blocks includes a plurality of first-stage muxes in which a plurality of sub-vectors are provided from the sub-vector storage unit, and a second-stage mux that selects and outputs one of the outputs of the plurality of first-stage muxes, and is configured such that the output of one first-stage mux, into which the sub-vector with a higher priority than other sub-vectors is input among the plurality of first-stage muxes, is selected with a higher probability than the output of another first-stage mux. In this aspect, each of the mux blocks receives as a plurality of inputs the output of one first-stage mux, into which the sub-vector with a higher priority than other first-stage mux outputs is input.

[0012] According to one aspect of the present embodiment, the linear feedback shift register divides the k-bit random signal and combines a plurality of divided random signals to generate the selection signal. Effects of the invention

[0013] According to the present embodiment, by performing an embedded self-test using a deterministic pattern with a high failure detection rate and selecting a high-priority subvector with high probability, the error detection rate is improved, area overhead is reduced, and test efficiency is increased. Brief explanation of the drawing

[0014] FIG. 1 is a block diagram illustrating an overview of the LBIST device of the present embodiment. Figure 2 is a diagram illustrating an overview of an LFSR. Figure 3 is a block diagram illustrating an overview of a mux block included in a multiplexing unit. Figure 4 is a diagram schematically illustrating a method of forming a selection signal by applying a selection signal superposition technique. Specific details for implementing the invention

[0015] The present embodiment will be described below with reference to the attached drawings. FIG. 1 is a block diagram illustrating an overview of the LBIST (logic Built-In Self Test) device (10) of the present embodiment. Referring to FIG. 1, the LBIST device (10) of the present embodiment includes an LFSR (100), mux blocks (mux0, mux1, mux2, mux3), a subvector storage unit (150), and a decompressor (160).

[0016] FIG. 2 is a diagram illustrating an overview of a Linear Feedback Shift Register (100) LFSR. Referring to FIG. 1 and FIG. 2, the LFSR (100) generates a selection signal for generating a pseudo-random test pattern. The LFSR (100) includes a plurality of D flip-flops (D0, D1, ..., D15) connected in a cascade. In the illustrated embodiment, 16 D flip-flops are connected in a cascade. Each D flip-flop operates in synchronization with a clock signal (CLK) and stores one bit of information. All D flip-flops share the same clock signal and perform shift operations simultaneously.

[0017] The output (Q) of each D flip-flop (D0, D1, ..., D15) is connected to the data input (D) of the next stage D flip-flop. That is, the output of the first D flip-flop (D0) is sequentially connected to the input of the second D flip-flop (D1), and the output of the second D flip-flop (D1) is sequentially connected to the input of the third D flip-flop (D2). With this structure, whenever a clock signal is applied, all stored bit information is shifted one step in one direction.

[0018] The LFSR (100) has a feedback structure. The outputs of the D flip-flops at fixed positions are connected to the input of the XOR gate to generate a feedback signal. In this embodiment, in the 16-bit LFSR, the outputs of D14 and D15 are input to the XOR gate, the output of the XOR gate and the output of the D12 flip-flop are input to the XOR gate, and the output of the XOR gate is input to the output of D2 and the XOR gate to feed back the output of the XOR gate to D0.

[0019] When an initial value (seed) is set, the LFSR (100) generates a random bit sequence according to the clock signal. In the case of a 16-bit LFSR, there are 2^16-1 = 65,535 different states, and a certain state repeats at specific intervals according to a specific initial value. A new 16-bit value is generated for each clock cycle, and these values ​​have statistically random characteristics.

[0020] The generated bit sequence has a uniform distribution characteristic, with 0 and 1 appearing with similar probability. In addition, the correlation between consecutive bits is very low, exhibiting characteristics similar to a true random sequence. As will be described later, the 16-bit outputs of D0, D1, ..., D15 in the LFSR (100) are used as selection signals for mux control.

[0021] The LFSR (100) operates in synchronization with the system clock. On the rising edge of the clock, all D flip-flops simultaneously latch new values, and a new bit calculated by the feedback logic is input to the first flip-flop. This operation is repeated every clock cycle to generate a continuous random sequence.

[0022] The clock frequency can be adjusted according to test requirements and generally operates in the range of several MHz to tens of MHz. For high-speed operation, a timing design that considers the setup / hold times of D flip-flops and the propagation delay time of XOR gates is required.

[0023] Referring again to FIG. 1, the subvector storage unit (150) stores a plurality of subvectors (v0, v1, ..., v11) generated by dividing a deterministic pattern into equal lengths. In one embodiment, when dividing the deterministic pattern into equal lengths, duplicate subvectors are removed, and missing bits are padded by inserting don't care bits.

[0024] In this embodiment, 12 subvectors (v0, v1, ..., v11) are stored, and each subvector is placed according to priority. The priority of the subvectors is determined based on error detection efficiency. The priority determination process is as follows: First, one subvector is removed and the fault coverage is measured. The greater the reduction in fault coverage resulting from the removal of the subvector, the higher the priority of that subvector. Subvectors with a small reduction in fault coverage are not effective for error detection, so they are removed or assigned a low priority.

[0025] The priority sub-vectors are stored in the sub-vector storage unit (150) according to the assigned priority. In one embodiment, the sub-vector storage unit (150) may be a register bank. In the illustrated embodiment, sub-vectors with higher priority are placed on the left, but this is merely an example, and other variations are possible.

[0026] FIG. 3 is a block diagram illustrating an overview of a mux block (mux0) included in a multiplexing unit (120). Referring to FIG. 1 and FIG. 3, the multiplexing unit (120) of the present embodiment includes a plurality of mux blocks (mux0, mux1, mux2, mux3). Each of the mux blocks (mux0, mux1, mux2, mux3) selects and outputs one of 12 subvectors according to a selection signal provided by an LFSR.

[0027] Each of the mux blocks (mux0, mux1, mux2, mux3) has three 4:1 muxes (mux0_1, mux0_2, mux0_3) that receive 12 subvectors as input, and another 4:1 mux (mux0_4) that selects and outputs the output of each mux block (mux0, mux1, mux2). The mux blocks (mux1, mux2, mux3) can also have the same internal structure.

[0028] In one embodiment, mux0_1 receives subvectors v0, v1, v2, v3, mux0_2 receives subvectors v4, v5, v6, v7, and mux0_3 receives subvectors v8, v9, v10, v11.

[0029] mux0_1, mux0_2, and mux0_3 are controlled by a 2-bit select signal output by an LFSR to select one of the four inputs and output it to mux0_4. mux0_4 receives the output of mux0_1, which has the highest priority due to the highest fault detection rate, as two inputs.

[0030] The outputs of mux0_2 and mux0_3 are provided as the remaining inputs. mux0_4 also selects one of the four inputs as the final output based on the 2-bit select signal output by the LFSR. Therefore, the probability that any one of the high-priority subvectors v0, v1, v2, and v3 is selected is 1 / 4 × 2 / 4 = 2 / 16, which is twice as high as the selection probability of the other subvectors (1 / 16).

[0031] While the existing 12:1 mux requires 4 select signals, the 2-stage structure according to this embodiment requires only a total of 8 select signals (4 of which are 2 bits at each stage), and the 4:1 muxes are provided in an optimized form from the standard cell library, resulting in high area efficiency. In other words, although the number of muxes used increases, the overall area is reduced (4 of the 4:1 structures compared to the prior art). In addition, it prevents the size of the LFSR from increasing due to select signal overlap. As the number of select signals increases from 4 to 8, the size of the LFSR is prevented by utilizing the select signals in overlap.

[0032] FIG. 4 is a diagram schematically illustrating a method of forming a selection signal by applying a selection signal superposition technique. As illustrated in FIG. 4, since four sub-vectors are input to mux0_1, mux0_2, and mux0_3, a 2-bit selection signal must be input to each of them in order for mux0_1, mux0_2, and mux0_3 to each output one sub-vector. Similarly, since four inputs are provided to mux0_4, a 2-bit selection signal must be input to output one sub-vector. Therefore, an 8-bit selection signal must be provided to one mux block, and a 32-bit selection signal must be provided to the multiplexer (120) containing four mux blocks.

[0033] Since the selection signal output bits of the LFSR (100) are a total of 16 bits, this embodiment generates a 32-bit selection signal by applying the selection signal superposition technique exemplified in FIG. 4.

[0034] Since mux0_1, mux0_2, mux0_3, and mux0_4 of this embodiment must each be provided with a 2-bit select signal, the mux block (mux0) requires an 8-bit select signal, and the four multiplexing blocks (mux0, mux1, mux2, mux3) require a total of 32-bit select signals.

[0035] In this embodiment, the illustrated LFSR generates a 16-bit random number to provide a selection signal. In one embodiment, the LFSR generates and outputs a total of 16-bit selection signals from [0:15]. The LFSR provides 8 bits from [0:7] of the generated 16-bit selection signal as a selection signal to multiplexing block mux0. Additionally, it provides 8 bits from [4:11] of the generated 16-bit selection signal as a selection signal to multiplexing block mux1. In the same way, the LFSR provides 8 bits from [8:15] of the generated 16-bit selection signal as a selection signal to multiplexing block mux2. Additionally, it provides 8 bits from the generated 16-bit selection signal, including four bits from [12:15] and four bits from [0:3], as a selection signal to multiplexing block mux3. As exemplified, by using bit overlap, a 16-bit LFSR can be used to provide select signals to four multiplexing blocks (mux0, mux1, mux2, mux3).

[0036] The illustrated embodiment generated a selection signal by overlapping two adjacent four bits at the output of the LFSR. However, an unillustrated embodiment may generate a selection signal by summing non-adjacent bits at the output of the LFSR.

[0037] Since mux0, mux1, mux2, and mux3 (mux) are composed of two stages, the output of the LFSR maintains randomness even after cyclic shifting or bit rearrangement. The correlation coefficient between each transformed signal pair is theoretically close to zero. In addition, by using the structure described above, area overhead can be minimized or reduced, and this advantage increases as the number of subvectors increases, thereby increasing the effect of minimizing area overhead.

[0038] Referring again to FIG. 1, the four sub-vectors (si0, si1, si2, si3) output by the multiplexer (120) are provided to the decompressor (160), and the decompressor (160) combines the four sub-vectors to generate a test vector.

[0039] To aid in understanding the present invention, the embodiments illustrated in the drawings have been described with reference to the examples shown; however, these are merely illustrative examples for implementation, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the appended claims. Explanation of the symbols

[0040] 10: LBIST device 100: LFSR 120: Multiplexer 150: Sub-vector storage 160: Decompressor

Claims

Claim 1 LBIST (Logic Built In Self Test) device, wherein the LBIST device comprises: a linear feedback shift register that generates a k-bit random signal and generates a selection signal therefrom; a subvector storage unit that stores a plurality of subvectors generated by dividing a deterministic seed in a priority order according to error detection efficiency; a plurality of mux blocks that are controlled by the selection signal and each select and output one subvector from among those stored in the subvector storage unit; and a decompressor that combines the subvectors output by the mux blocks to generate a test pattern, wherein each of the mux blocks selects the subvector with a higher priority with a higher probability compared to other subvectors, and the priority of the subvectors is determined by measuring the reduction in error detection rate when each subvector generated from the deterministic seed is individually removed, and assigning a higher priority starting from the subvector with the largest reduction in error detection rate. (k: natural number) Claim 2 In claim 1, the linear feedback shift register (100) comprises a plurality of D flip-flops connected in series; and one or more XOR gates that receive D flip-flop outputs at predetermined positions to generate a feedback signal, and an LBIST device that provides the feedback signal as an input to the first D flip-flop. Claim 3 delete Claim 4 An LBIST device according to claim 1, wherein each of the mux blocks comprises a plurality of first-stage muxes in which a plurality of sub-vectors are provided from the sub-vector storage unit, and a second-stage mux that selects and outputs one of the outputs of the plurality of first-stage muxes, and configured such that the output of one first-stage mux, into which the sub-vector with a higher priority than other sub-vectors among the plurality of first-stage muxes is input, is selected with a higher probability than the output of another first-stage mux. Claim 5 In paragraph 4, each of the above mux blocks is an LBIST device that receives as multiple inputs the output of a single one-stage mux into which the sub-vector with a higher priority than the output of the other one-stage mux is input. Claim 6 In claim 1, the linear feedback shift register is an LBIST device that divides the k-bit random signal and combines a plurality of divided random signals to generate the selection signal.

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