Smart IC substrate, smart IC module and IC card including the same

Abstract

A smart IC substrate according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; a first circuit pattern disposed on the first surface; and a space area between the first circuit patterns, wherein the substrate comprises a plurality of via holes penetrating the first surface and the second surface, wherein the substrate is defined with a first region and a second region other than the first region, wherein the first circuit pattern comprises a first circuit pattern portion and a second circuit pattern portion having different thicknesses, wherein the thickness of the first circuit pattern portion is greater than the thickness of the second circuit pattern portion, wherein the first circuit pattern portion is disposed in the first region and the second region, wherein the second circuit pattern portion is disposed only in the first region, and wherein the second circuit pattern portion is disposed at least one of a position that overlaps with the via hole and a position that does not overlap in the thickness direction of the substrate.

Description

Technology Field

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the same. Background Technology

[0002] An IC card can be formed by combining a smart IC module and a card module.

[0003] A smart IC module is a circuit board equipped with an IC that stores personal security information required for electronic ID cards, credit cards, SIM cards, etc., and it can transmit this information to a reader in the form of an electrical signal.

[0004] The above smart IC module can be classified into single type and dual type depending on the structure of the substrate, and can be classified into contact, contactless, hybrid, and combi cards depending on the form of the card used.

[0005] Specifically, contact-type smart IC modules transmit and receive information through physical contact, contactless smart IC modules transmit and receive information without physical contact using NFC (transportation card, etc.) functions, and combi-smart IC modules and hybrid smart IC modules include both physical contact functions and NFC functions without physical contact.

[0006] Identification patterns such as characters, symbols, and numbers may be displayed on the smart IC module for the identification of the IC card. For example, by using the circuit pattern of the smart IC module to display identification patterns such as characters, symbols, and numbers on the smart IC module, it is possible to identify the issuing authority, purpose, etc. of the IC card from the outside.

[0007] Meanwhile, a plurality of via holes, etc., may be formed in the smart IC module to connect the circuit patterns of the contact surface and the bonding surface.

[0008] Accordingly, when forming an identification pattern using the above circuit pattern, the space and location where the identification pattern is formed may be limited by the via hole. In addition, if the identification pattern is formed using a separate dummy pattern, there is a problem that the size of the smart IC module becomes unnecessarily large.

[0009] Therefore, a smart IC substrate with a new structure capable of solving the above-mentioned problems, a smart IC module, and an IC card including the same are required. The problem to be solved

[0010] The embodiment aims to provide a smart IC substrate, a smart IC module, and an IC card including the same, which can easily form identification patterns such as various characters, symbols, and numbers, and improve the freedom of external design. means of solving the problem

[0011] A smart IC substrate according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; a first circuit pattern disposed on the first surface; and a space area between the first circuit patterns, wherein the substrate comprises a plurality of via holes penetrating the first surface and the second surface, wherein the substrate is defined with a first region and a second region other than the first region, wherein the first circuit pattern comprises a first circuit pattern portion and a second circuit pattern portion having different thicknesses, wherein the thickness of the first circuit pattern portion is greater than the thickness of the second circuit pattern portion, wherein the first circuit pattern portion is disposed in the first region and the second region, wherein the second circuit pattern portion is disposed only in the first region, and wherein the second circuit pattern portion is disposed at least one of a position that overlaps with the via hole and a position that does not overlap in the thickness direction of the substrate.

[0012] A smart IC substrate according to an embodiment comprises: a substrate including a first surface and a second surface opposite to the first surface; and a first circuit pattern disposed on the first surface; The substrate includes a space area between the first circuit pattern and the first circuit pattern, and the substrate includes a plurality of via holes penetrating the first surface and the second surface, and the substrate is defined with a first region and a second region other than the first region, and the first circuit pattern includes a first circuit pattern portion, a second-1 circuit pattern portion, and a second-2 circuit pattern portion having different thicknesses, and the thickness of the first circuit pattern portion and the thickness of the second-2 circuit pattern portion are greater than the thickness of the second-1 circuit pattern portion, and the first circuit pattern portion is disposed in the second region, and the second-1 circuit pattern portion and the second-2 circuit pattern portion are disposed only in the first region, and the second-1 circuit pattern portion is disposed at least one of a position that overlaps with the via hole and a position that does not overlap in the thickness direction of the substrate. Effects of the invention

[0013] The smart IC substrate, smart IC module, and IC card according to the embodiment may include an identification pattern.

[0014] Specifically, the circuit patterns of the smart IC substrate, the smart IC module, and the IC card can be etched to form an identification pattern in the shape of intaglio or relief.

[0015] Accordingly, when a user sees the IC card from the outside, the information on the IC card can be easily identified through the identification pattern.

[0016] In addition, the identification pattern can be formed by partially etching the circuit pattern. Accordingly, the identification pattern can be formed at various locations regardless of the location of the via holes of the smart IC substrate.

[0017] In addition, the identification pattern can be recognized in a color different from other circuit patterns. Accordingly, a user can easily identify the identification pattern from the outside.

[0018] In addition, the identification pattern may have a different color from other circuit patterns. Accordingly, a user can easily identify the identification pattern from the outside.

[0019] In addition, a reinforcing part made of resin or metal material may be placed on the identification pattern. Accordingly, corrosion of the circuit pattern can be prevented. Furthermore, the freedom of appearance design can be enhanced by applying various colors to the reinforcing part. Brief explanation of the drawing

[0020] FIG. 1 is a top view of an IC card according to an embodiment. FIG. 2 is a top view of the first surface of a smart IC substrate according to an embodiment. FIG. 3 is a drawing showing another top view of the first surface of a smart IC substrate according to an embodiment. FIGS. 4 and 5 are top view drawings of a second surface of a smart IC substrate according to an embodiment. FIGS. 6 and 7 are top view drawings of the bonding surface of a smart IC module in which a chip is placed on the second surface of a smart IC substrate. Figure 8 is a cross-sectional view showing the AA' region of Figures 2 and 6. Figure 9 is a cross-sectional view showing the AA' region of Figures 2 and 7. FIG. 10 is a cross-sectional view showing the BB' region of FIG. 3 and FIG. 6. FIG. 11 is a cross-sectional view showing the BB' region of FIG. 3 and FIG. 7. FIG. 12 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 6. FIG. 13 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 7. FIG. 14 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 6. FIG. 15 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 7. FIG. 16 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 6. FIG. 17 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 7. FIG. 18 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 6. FIG. 19 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 7. FIG. 20 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 6. FIG. 21 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 7. FIG. 22 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 6. FIG. 23 is a drawing showing another cross-sectional view of the AA' region of FIG. 2 and FIG. 7. FIG. 24 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 6. FIG. 25 is a drawing showing another cross-sectional view of the BB' region of FIG. 3 and FIG. 7. FIG. 26 is a drawing showing another cross-sectional view of the AA' region of FIG. 2. FIG. 27 is a drawing showing another cross-sectional view of the BB' region of FIG. 3. Specific details for implementing the invention

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0022] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0023] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “A and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0024] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0025] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0026] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0027] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0029] Hereinafter, a smart IC substrate, a smart IC module, and an IC card including the same according to an embodiment will be described with reference to the drawings.

[0030] FIG. 1 is a top view of an IC card according to an embodiment.

[0031] Referring to FIG. 1, the IC card (1000) may include a card body (1100), a smart IC substrate (1200) accommodated in the card body (1100), a chip (1300), a microcontroller unit (MCU, 1400), a connection circuit pattern (1350) electrically connecting the chip (1300) and the microcontroller unit (1400), a fingerprint sensor (1500), an antenna (1600), and a battery (1700).

[0032] The smart IC substrate (1200) can be accommodated in the card body (1100). Specifically, an opening (OA) for accommodating the smart IC substrate (1200) is formed in the card body (1100), and the smart IC substrate (1200) can be inserted and bonded into the opening (OA).

[0033] Accordingly, either one of the sides of the smart IC substrate (1200) and the other side may be exposed to the outside of the IC card.

[0034] The IC card may include a fingerprint sensor (1500). The fingerprint sensor (1500) can recognize the user's fingerprint and match it with fingerprint information stored in the chip (1300).

[0035] That is, one or more fingerprint information of a predetermined user is stored in the chip (1300), and the fingerprint recognized through the fingerprint sensor (1500) can be matched with the fingerprint information stored in the chip (1300) and compared.

[0036] For example, when a user's finger comes into contact with the fingerprint sensor (1500), power is supplied from the battery (1700) to the micro control unit (1400), and the fingerprint sensor (1500), which is powered by the micro control unit (1400), can be driven.

[0037] Next, the micro control unit (1300) receives fingerprint information recognized through the fingerprint sensor (1500), and the authentication process of the recognized fingerprint information can be carried out.

[0038] Next, when the recognized fingerprint information and the fingerprint information stored in the chip (1300) match, the smart IC substrate (1200) connected to the chip (1300) and acting as a contact pad is activated, and the function of the IC card can also be activated.

[0039] On the other hand, if the recognized fingerprint information and the fingerprint information stored in the chip (1300) do not match, the smart IC substrate (1200) connected to the chip (1300) is deactivated, and the function of the IC card may also be deactivated.

[0040] However, the embodiments are not limited thereto, and the IC card may not include a fingerprint sensor (1500), and the IC card may have its functions activated without separate fingerprint authentication.

[0041] Additionally, the IC card may include an antenna (1600). Accordingly, the IC smart card can operate as a contactless card. That is, through the antenna of the IC card, information can be transmitted and received wirelessly with a server even in a contactless state with a card reader.

[0042] However, the embodiments are not limited thereto, and the IC card may not include an antenna (1600), and the IC card may operate as a contact card. That is, the IC card may be inserted into a reader and transmit and receive information to and from a server through contact with a circuit board.

[0044] FIGS. 2 to 5 are top view drawings of one side and the other side of a smart IC substrate according to an embodiment.

[0045] Referring to FIGS. 2 through 5, the smart IC substrate (1200) may include one side and another side opposite to the one side. A chip may be mounted on the smart IC substrate (1200) to form a smart IC module. The one side may be the contact side of the smart IC substrate (1200). Additionally, the other side may be the bonding side of the smart IC substrate (1200).

[0046] That is, the above-mentioned surface may be a surface capable of recognizing information of a smart IC module through direct or indirect contact with the IC card, and the other surface may be a surface on which a chip is mounted and which is bonded to the card body (2000).

[0047] The smart IC substrate (1200) may include a substrate (100) and a plurality of circuit patterns.

[0048] The substrate (100) may include a resin material. The substrate (100) may include a first surface (1S) and a second surface (2S) opposite to the first surface (1S). The first surface (1S) may be defined as a surface corresponding to the contact surface of the smart IC substrate (1200) described above, i.e., the surface corresponding to the contact surface of the smart IC substrate (1200), and the second surface (2S) may be defined as a surface corresponding to the bonding surface of the smart IC substrate (1200) described above.

[0049] The substrate (100) may include a prepreg containing glass fibers. Specifically, the substrate (100) may include an epoxy resin and a material in which glass fibers and a silicon-based filler (Si filler) are dispersed in the epoxy resin.

[0050] Additionally, the substrate (100) may be rigid or flexible. For example, the substrate (100) may include glass or plastic. Specifically, the substrate (100) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0051] Additionally, the substrate (100) may include an optically isotropic film. For example, the substrate (100) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0052] Additionally, the substrate (100) may be bent while having a partially curved surface. That is, the substrate (100) may be bent while having a partially flat surface and a partially curved surface. Specifically, the end of the substrate (100) may be bent while having a curved surface or may be bent or curved while having a surface that includes random curvature.

[0053] Additionally, the substrate (100) may be a flexible substrate having flexible properties. Additionally, the substrate (100) may be a curved or bent substrate.

[0055] An adhesive layer (210, 220) may be disposed on the first surface (1S) and the second surface (2S) of the substrate (100). The adhesive layer (210, 220) may be disposed on the front surface of the first surface (1S) and the second surface (2S) of the substrate (100). Specifically, the adhesive layer (210, 220) may be disposed on the front surface of the first surface (1S) and the second surface (2S) of the substrate, excluding the area where a via is formed.

[0056] The adhesive layer (210, 220) may include a resin material. For example, the adhesive layer (210, 220) may include at least one of epoxy resin, acrylic resin, and polyimide resin. Additionally, the adhesive layer (210, 220) may further include additives such as natural rubber, plasticizers, curing agents, and flame retardants such as phosphorus-based agents to impart flexibility to the adhesive layer (210, 220).

[0058] Referring to FIGS. 2 to 11, circuit patterns (300, 400) may be disposed on the substrate (100). Specifically, circuit patterns may be disposed on the first surface (1S) and the second surface (2S) of the substrate (100), respectively. For example, a first circuit pattern (300) may be disposed on the first surface (1S) of the substrate, and a second circuit pattern (400) may be disposed on the second surface (2S) of the substrate. That is, the first circuit pattern (300) may be disposed on the contact surface of the smart IC substrate, and the second circuit pattern (400) may be disposed on the bonding surface of the smart IC substrate.

[0059] Referring to FIGS. 2, FIGS. 3 and FIGS. 8 through 11, the first circuit pattern (300) can be placed on the first adhesive layer (210) on the substrate (100).

[0060] The first circuit pattern (300) may include a first metal layer (310) and a second metal layer (320). Specifically, the first circuit pattern (300) may include a first metal layer (310) on the first adhesive layer (210) and a second metal layer (320) on the first metal layer (310).

[0061] The first metal layer (310) may include a metal material. Specifically, the first metal layer (310) may include a metal material with high electrical conductivity. For example, the first metal layer (310) may include at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first metal layer (310) may include copper (Cu).

[0062] The second metal layer (320) may be placed on the first metal layer (310). The second metal layer (320) may be placed on the first metal layer (310) to protect the first metal layer (310). That is, the second metal layer (320) may be placed on the first metal layer (310) to prevent corrosion of the first metal layer (310). That is, the second metal layer (320) may serve as a protective layer for the first circuit pattern (300).

[0063] The second metal layer (320) may include nickel-gold (Ni-Au) or nickel-palladium (Ni-Pd), but the embodiments are not limited thereto. For example, the second metal layer (320) may be formed by forming a nickel (Ni) layer on the first metal layer (310) and then placing a gold (Au) layer on the nickel layer, or by forming a nickel layer on the first metal layer (310) and then placing a palladium layer on the nickel layer. At this time, a nickel-gold alloy layer may be formed between the nickel layer and the gold layer, and a nickel-palladium alloy layer may be formed between the nickel layer and the palladium layer.

[0064] The first metal layer (310), the second metal layer (320), and the first adhesive layer (210) may have different thicknesses.

[0065] Specifically, the thickness of the first metal layer (310) may be greater than the thickness of the second metal layer (320) and the thickness of the first adhesive layer (210). Additionally, the thickness of the first adhesive layer (210) may be greater than the thickness of the second metal layer (320).

[0066] For example, the thickness of the first metal layer (310) may be 35㎛ to 70㎛, the thickness of the second metal layer (320) may be 1㎛ to 3㎛, and the thickness of the first adhesive layer (210) may be 15㎛ to 30㎛.

[0068] Referring to FIGS. 4 to 11, the second circuit pattern (400) may be placed on the second adhesive layer (210) on the substrate (100).

[0069] The second circuit pattern (400) may include a third metal layer (410) and a fourth metal layer (420). Specifically, the second circuit pattern (400) may include a third metal layer (410) on the second adhesive layer (220) and a fourth metal layer (420) on the third metal layer (410).

[0070] The third metal layer (410) may include a metal material. Specifically, the third metal layer (410) may include a metal material with high electrical conductivity. The third metal layer (410) may include the same or different metal material among the metal materials included in the first metal layer (310) described above. Preferably, the third metal layer (410) may include copper (Cu).

[0071] The fourth metal layer (420) may be placed on the third metal layer (410). The fourth metal layer (420) may be placed on the third metal layer (410) to protect the third metal layer (410). That is, the fourth metal layer (420) may be placed on the third metal layer (410) to prevent corrosion of the third metal layer (410). That is, the fourth metal layer (420) may serve as a protective layer for the second circuit pattern (400).

[0072] The above-mentioned fourth metal layer (420) may include the same or different metal material among the metal materials included in the above-mentioned second metal layer (320).

[0073] The third metal layer (410), the fourth metal layer (420), and the second adhesive layer (220) may have different thicknesses.

[0074] Specifically, the thickness of the third metal layer (410) may be greater than the thickness of the fourth metal layer (420) and the thickness of the second adhesive layer (220). Additionally, the thickness of the second adhesive layer (220) may be greater than the thickness of the fourth metal layer (420).

[0075] For example, the thickness of the third metal layer (410) may be 35 µm to 70 µm, the thickness of the fourth metal layer (420) may be 3 µm to 8 µm, and the thickness of the second adhesive layer (220) may be 15 µm to 30 µm.

[0076] The thickness of the fourth metal layer (420) may be greater than the thickness of the second metal layer (320). That is, the fourth metal layer (420) disposed on the bonding surface of the smart IC substrate (1200) may be greater than the thickness of the second metal layer (320).

[0078] Referring to FIGS. 2 and FIGS. 3, the first circuit pattern (300) may include a plurality of circuit patterns. Specifically, the first circuit pattern (300) may include a plurality of circuit patterns spaced apart from each other.

[0079] Referring to FIGS. 2 and 3, the first circuit pattern (300) may include a first-1 circuit pattern (301), a first-2 circuit pattern (302), a first-3 circuit pattern (303), a first-4 circuit pattern (304), a first-5 circuit pattern (305), and a first-6 circuit pattern (306).

[0080] In FIGS. 2 and 3, the first-1 circuit pattern (301), the first-2 circuit pattern (302), the first-3 circuit pattern (303), the first-4 circuit pattern (304), the first-5 circuit pattern (305) and the first-6 circuit pattern (306) are illustrated, but the embodiments are not limited thereto, and the first circuit pattern (300) may include fewer than 6 or more than 6 circuit patterns.

[0081] The above 1-1 circuit pattern (301), the above 1-2 circuit pattern (302), the above 1-3 circuit pattern (303), the above 1-4 circuit pattern (304), the above 1-5 circuit pattern (305), and the above 1-6 circuit pattern (306) may be spaced apart from each other.

[0082] Specifically, space areas (SA) in which no circuit patterns are placed are formed between the first-1 circuit pattern (301), the first-2 circuit pattern (302), the first-3 circuit pattern (303), the first-4 circuit pattern (304), the first-5 circuit pattern (305) and the first-6 circuit pattern (306), and the first-1 circuit pattern (301), the first-2 circuit pattern (302), the first-3 circuit pattern (303), the first-4 circuit pattern (304), the first-5 circuit pattern (305) and the first-6 circuit pattern (306) can be spaced apart from each other by the space areas (SA). That is, the spacer area (SA) may be the interval between the first-1 circuit pattern (301), the first-2 circuit pattern (302), the first-3 circuit pattern (303), the first-4 circuit pattern (304), the first-5 circuit pattern (305), and the first-6 circuit pattern (306).

[0083] The above spacer region (SA) may have a set size. For example, the above spacer region (SA) may be 100 μm to 250 μm.

[0084] Accordingly, the first-1 circuit pattern (301), the first-2 circuit pattern (302), the first-3 circuit pattern (303), the first-4 circuit pattern (304), the first-5 circuit pattern (305) and the first-6 circuit pattern (306) may be arranged so as not to be electrically connected on the first surface (1S) of the substrate (100).

[0086] Additionally, referring to FIGS. 4 and 5, the second circuit pattern (400) may include a second-1 circuit pattern (401), a second-2 circuit pattern (402), a second-3 circuit pattern (403), a second-4 circuit pattern (404), a second-5 circuit pattern (405), and a second-6 circuit pattern (406).

[0087] In FIGS. 4 and 5, the 2-1 circuit pattern (401), the 2-2 circuit pattern (402), the 2-3 circuit pattern (403), the 2-4 circuit pattern (404), the 2-5 circuit pattern (405), and the 2-6 circuit pattern (406) are illustrated, but the embodiments are not limited thereto, and the 2-2 circuit pattern (400) may include fewer than 6 or more than 6 2-2 circuit patterns.

[0088] The above 2-1 circuit pattern (401), the above 2-2 circuit pattern (402), the above 2-3 circuit pattern (403), the above 2-4 circuit pattern (404), the above 2-5 circuit pattern (405), and the above 2-6 circuit pattern (406) may be spaced apart from each other.

[0089] Referring to FIGS. 4 and 5, a chip mounting area may be formed on the second-1 circuit pattern (401), the second-2 circuit pattern (402), the second-3 circuit pattern (403), the second-4 circuit pattern (404), the second-5 circuit pattern (405) and the second-6 circuit pattern (406) disposed on the second surface (2S) of the substrate (100).

[0090] Referring to FIGS. 6 and 7, a chip (C) electrically connected to the first circuit pattern (300) and the second circuit pattern (400) can be placed in the chip mounting area to form a smart IC module.

[0091] The chip (C) can be placed on the second circuit pattern (400) and connected to the second circuit pattern (400). That is, the chip (C) and the second circuit pattern (400) can be electrically connected by direct contact.

[0092] Additionally, the chip (C) may be connected to the first circuit pattern (300). At least one via hole may be formed to connect the chip (C) and the first circuit pattern (300).

[0093] For example, a plurality of via holes may be formed in the substrate (100) through which the first surface (1S) and the second surface (2S) penetrate.

[0094] Referring to FIGS. 4 and FIGS. 6, a plurality of via holes may be formed in the substrate (100). Specifically, a plurality of via holes corresponding to each first circuit pattern (300) may be formed in the substrate (100).

[0095] Specifically, the substrate (100) has a first via hole (V1) formed in an area overlapping the thickness direction of the substrate (100) with the first-1 circuit pattern (301), a second via hole (V2) formed in an area overlapping the thickness direction of the substrate (100) with the first-2 circuit pattern (302), a third via hole (V3) formed in an area overlapping the thickness direction of the substrate (100) with the first-3 circuit pattern (303), a fourth via hole (V4) formed in an area overlapping the thickness direction of the substrate (100) with the first-4 circuit pattern (304), a fifth via hole (V5) formed in an area overlapping the thickness direction of the substrate (100) with the first-5 circuit pattern (305), and a sixth via hole (V6) formed in an area overlapping the thickness direction of the substrate (100) with the first-6 circuit pattern (306). It can be formed.

[0096] Referring to FIGS. 6 and FIGS. 8, the chip (C) and the first circuit pattern (300) can be connected by wire bonding. That is, the chip (C) and the first circuit pattern can be electrically connected through a plurality of wires (500) passing through the via hole.

[0097] A pad portion (350) for wire bonding may be disposed on the first circuit pattern (300) connected to the chip (C) by wire bonding.

[0098] Additionally, referring to FIG. 8, the first circuit pattern (300) and the second circuit pattern (400) can be electrically connected through a conductive layer (800) inside a via hole penetrating the substrate (100).

[0100] Alternatively, referring to FIGS. 5, 7 and 9, a plurality of via holes may be formed in the substrate (100). Specifically, a plurality of via holes corresponding to each first circuit pattern (300) may be formed in the substrate (100).

[0101] Specifically, the substrate (100) has a first via hole (V1) formed in an area overlapping the thickness direction of the substrate (100) with the first-1 circuit pattern (301), a second via hole (V2) formed in an area overlapping the thickness direction of the substrate (100) with the first-2 circuit pattern (302), a third via hole (V3) formed in an area overlapping the thickness direction of the substrate (100) with the first-3 circuit pattern (303), a fourth via hole (V4) formed in an area overlapping the thickness direction of the substrate (100) with the first-4 circuit pattern (304), a fifth via hole (V5) formed in an area overlapping the thickness direction of the substrate (100) with the first-5 circuit pattern (305), and a sixth via hole (V6) formed in an area overlapping the thickness direction of the substrate (100) with the first-6 circuit pattern (306). It can be formed.

[0102] Referring to FIGS. 5, 7 and 9, a plating layer (600) may be disposed on the inner side of the first via hole (V1), the second via hole (V2), the third via hole (V3), the fourth via hole (V4), the fifth via hole (V5) and the sixth via hole (V6).

[0103] The plating layer (600) can be connected to the first circuit pattern (300) and the second circuit pattern (400). Accordingly, the chip (C) can be electrically connected to the first circuit pattern (300) and the second circuit pattern (400).

[0105] Meanwhile, the smart IC substrate (1200) may include an identification pattern (IP) capable of identifying information of an IC card. Specifically, the identification pattern (IP) may be placed on a first surface (1S) of the substrate (100). More specifically, the identification pattern (IP) may be placed on a contact surface of the smart IC substrate (1200). For example, the substrate (100) may be defined with a first area (1A) where the identification pattern (IP) is placed and a second area (2A) other than the first area (1A), and the identification pattern (IP) may be placed in the first area (1A).

[0106] Accordingly, the user can identify the information on the IC card through the contact surface exposed to the outside of the IC card.

[0107] The identification pattern (IP) can be formed by the first circuit pattern (300). Specifically, the identification pattern (IP) can be formed by partially etching the first circuit pattern (300). That is, the identification pattern (IP) can be a part of the first circuit pattern (300). That is, the identification pattern (IP) can be a region of the first circuit pattern (300).

[0108] The identification pattern (IP) can be formed by various methods. Specifically, the identification pattern (IP) can be formed in various shapes according to the etching method of the first circuit pattern (300).

[0110] First, with reference to FIGS. 2 and FIGS. 6 to 9, an identification pattern of a smart IC substrate according to a first embodiment will be described.

[0111] Referring to FIGS. 2, 6 to 9, the first circuit pattern (300) may be defined with a first circuit pattern section (300a), a second circuit pattern section (300b), and a third circuit pattern section (300c) according to the thickness of the first circuit pattern (300).

[0112] The thicknesses of the first circuit pattern section (300a), the second circuit pattern section (300b), and the third circuit pattern section (300c) may differ from each other. For example, the thickness of the first circuit pattern section (300a) may be greater than the thickness of the second circuit pattern section (300b) and the third circuit pattern section (300c). Additionally, the thickness of the second circuit pattern section (300b) may be greater than the thickness of the third circuit pattern section (300c).

[0113] The first circuit pattern portion (300a) may include the first metal layer (310) and the second metal layer (320). The first circuit pattern portion (300a) may be an area where the first circuit pattern (300) is not etched.

[0114] The first circuit pattern portion (300a) may be placed in at least one of the first region (1A) and the second region (2A). Specifically, the first circuit pattern portion (300a) may be placed in both the first region (1A) and the second region (2A).

[0115] The second circuit pattern portion (300b) may include the first metal layer (310) and the second metal layer (320).

[0116] The second circuit pattern section (300b) may be placed in the first area (1A). Specifically, the second circuit pattern section (300b) may be placed only in the first area (1A).

[0117] Additionally, the thickness of the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second circuit pattern section (300b) may differ. Specifically, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second circuit pattern section (300b).

[0118] Accordingly, the first circuit pattern portion (300a) and the second circuit pattern portion (300b) may have a thickness difference according to the thickness difference of the first metal layer (310).

[0119] Specifically, the thickness of the second circuit pattern portion (300b) may be 10% to 50% of the thickness of the first circuit pattern portion (300a). It may be difficult to implement the thickness of the second circuit pattern portion (300b) to exceed 50% of the thickness of the first circuit pattern portion (300a) during the etching process. Additionally, if the thickness of the second circuit pattern portion (300b) is less than 10% of the thickness of the first circuit pattern portion (300a), conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second circuit pattern portion (300b).

[0120] Additionally, the thickness difference between the first circuit pattern portion (300a) and the second circuit pattern portion (300b) may be 3.5㎛ to 18㎛. It may be difficult to implement a thickness difference of less than 3.5㎛ in the etching process, and if the thickness difference between the first circuit pattern portion (300a) and the second circuit pattern portion (300b) exceeds 18㎛, conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second circuit pattern portion (300b).

[0121] In addition, the width of the second circuit pattern section (300b) may be similar in size to or greater than the width of the space area (SA).

[0123] The second circuit pattern portion (300b) may be an area where the first circuit pattern (300) is etched. Specifically, the second circuit pattern portion (300b) may be an area where the first metal layer (310) of the first circuit pattern (300) is partially etched. The second circuit pattern portion (300b) may correspond to the identification pattern (IP). That is, a pattern of characters, symbols, numbers, etc., may be formed on the smart IC substrate (1200) by the second circuit pattern portion (300b). That is, an identification pattern (IP), such as characters, symbols, numbers, etc., in an engraved shape may be formed on the smart IC substrate (1200).

[0124] The second circuit pattern portion (300b) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6, V). Specifically, the second circuit pattern portion (300b) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6, V) in the thickness direction of the substrate (120).

[0125] Alternatively, the second circuit pattern portion (300b) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6). Specifically, the second circuit pattern portion (300b) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100).

[0126] That is, the second circuit pattern portion (300b) may be placed at least one location that overlaps with or does not overlap with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100). For example, the second circuit pattern portion (300b) may be placed at both a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100) and a location that does not overlap. In other words, the location of the second circuit pattern portion (300b) may be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6). That is, the identification pattern (IP) formed by the second circuit pattern portion (300b) may be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6).

[0127] Accordingly, when forming an identification pattern on the IC card, the identification pattern can be formed at various locations regardless of the location of the via hole formed on the substrate. Accordingly, the design freedom of the identification pattern can be improved.

[0128] The first circuit pattern portion (300a) and the second circuit pattern portion (300b) may be perceived as different colors. Specifically, the first circuit pattern portion (300a) and the second circuit pattern portion (300b) may have different thicknesses due to the difference in thickness of the first metal layer (310). Accordingly, the first circuit pattern portion (300a) and the second circuit pattern portion (300b) have a difference in brightness due to the difference in thickness, and the user may perceive the first circuit pattern portion (300a) and the second circuit pattern portion (300b) as different colors from the outside due to the difference in brightness.

[0129] Therefore, various colors can be implemented on the first surface (1S) exposed to the outside of the IC card, thereby improving design freedom. In addition, since the first circuit pattern portion (300a) and the second circuit pattern portion (300b) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0130] The third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched. Specifically, the third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched all or almost all of. That is, the first circuit pattern (300) may not remain in the third circuit pattern portion (300c) or may remain in a small amount. That is, the thickness of the first circuit pattern (300) placed in the third circuit pattern portion (300c) may be 0 or close to 0.

[0131] Here, the meaning of the third circuit pattern portion (300c) remaining is that after etching, the first circuit pattern (300) on the first surface (1S) of the substrate (100) is not connected to adjacent circuit patterns and remains in a small amount such that a plating layer is not formed by the plating process.

[0132] The third circuit pattern section (300c) may correspond to the space area (SA). That is, the third circuit pattern section (300c) may be the space area (SA). That is, the first circuit pattern (300) may be divided into a plurality of circuit patterns by the third circuit pattern section (300c).

[0134] Hereinafter, with reference to FIGS. 3, 6, 7, 10, and 11, an identification pattern of a smart IC substrate according to a second embodiment will be described.

[0135] Referring to FIGS. 3, 6, 7, 10 and 11, the first circuit pattern (300) may be defined with a first circuit pattern section (300a), a second-first circuit pattern section (300b1), a second-second circuit pattern section (300b2) and a third circuit pattern section (300c) according to the thickness of the first circuit pattern (300).

[0136] The thicknesses of the first circuit pattern section (300a), the second-first circuit pattern section (300b1), the second-second circuit pattern section (300b2), and the third circuit pattern section (300c) may differ from each other. For example, the thickness of the first circuit pattern section (300a) may be greater than the thickness of the second-first circuit pattern section (300b1) and the third circuit pattern section (300c).

[0137] Additionally, the thickness of the 2-1 circuit pattern section (300b1) may be greater than the thickness of the 3-3 circuit pattern section (300c). Also, the thicknesses of the 1-2 circuit pattern section (300a) and the 2-2 circuit pattern section (300b2) may be the same or within a tolerance range. Additionally, the thickness of the 2-2 circuit pattern section (300b2) may be greater than the thickness of the 2-1 circuit pattern section (300b1).

[0138] The first circuit pattern portion (300a) may include the first metal layer (310) and the second metal layer (320). The first circuit pattern portion (300a) may be an area where the first circuit pattern (300) is not etched.

[0139] The first circuit pattern portion (300a) may be placed in the second area (2A). Specifically, the first circuit pattern portion (300a) may be placed only in the second area (2A).

[0140] The above 2-1 circuit pattern portion (300b1) may include the first metal layer (310) and the second metal layer (320).

[0141] The above 2-1 circuit pattern section (300b1) may be placed in the above 1 area (1A). Specifically, the above 2-1 circuit pattern section (300b1) may be placed only in the above 1 area (1A).

[0142] Additionally, the thickness of the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second-first circuit pattern section (300b1) may differ. Specifically, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second-first circuit pattern section (300b1).

[0143] Accordingly, the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) may have a thickness difference according to the thickness difference of the first metal layer (310).

[0144] Specifically, the thickness of the second-1 circuit pattern portion (300b1) may be 10% to 50% of the thickness of the first circuit pattern portion (300a). It may be difficult to implement the thickness of the second-1 circuit pattern portion (300b1) to exceed 50% of the thickness of the first circuit pattern portion (300a) during the etching process. Additionally, if the thickness of the second-1 circuit pattern portion (300b1) is less than 10% of the thickness of the first circuit pattern portion (300a), conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second-1 circuit pattern portion (300b1).

[0145] Additionally, the thickness difference between the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) may be 3.5㎛ to 18㎛. It may be difficult to implement a thickness difference of less than 3.5㎛ between the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) during the etching process, and if the thickness difference between the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) exceeds 18㎛, conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second-first circuit pattern portion (300b1).

[0146] In addition, the width of the 2-1 circuit pattern section (300b1) may be similar in size to or greater than the width of the space area (SA).

[0148] The above 2-1 circuit pattern portion (300b1) may be an area where the above 1 circuit pattern (300) is etched. Specifically, the above 2-1 circuit pattern portion (300b1) may be an area where the first metal layer (310) of the above 1 circuit pattern (300) is partially etched.

[0149] The above 2-1 circuit pattern portion (300b1) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6). Specifically, the above 2-1 circuit pattern portion (300b1) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100).

[0150] Alternatively, the second-1 circuit pattern portion (300b1) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6). Specifically, the second-1 circuit pattern portion (300b1) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100).

[0151] That is, the second-1 circuit pattern portion (300b1) can be placed at both a position that overlaps with the via holes (V1, V2, V3, V4, V5, V6) and a position that does not overlap with the thickness direction of the substrate (100). In other words, the position of the second-1 circuit pattern portion (300b1) can be placed regardless of the position of the via holes (V1, V2, V3, V4, V5, V6).

[0152] The first circuit pattern section (300a) and the second-first circuit pattern section (300b1) may be perceived as different colors. Specifically, the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) may have different thicknesses due to the difference in thickness of the first metal layer (310). Accordingly, the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) have a difference in brightness due to the difference in thickness, and the user may perceive the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) as different colors from the outside due to the difference in brightness.

[0153] Therefore, various colors can be implemented on the first surface (1S) exposed to the outside of the IC card, thereby improving design freedom. In addition, since the first circuit pattern portion (300a) and the second-1 circuit pattern portion (300b1) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0155] The above second-2 circuit pattern portion (300b2) may include the first metal layer (310) and the second metal layer (320). The above second-2 circuit pattern portion (300b2) may be an area where the first circuit pattern (300) is not etched.

[0156] The above 2-2 circuit pattern section (300b2) may be placed in the above 1 area (1A). Specifically, the above 2-2 circuit pattern section (300b2) may be placed only in the above 1 area (1A).

[0157] That is, the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) may be disposed in the 1 area (1A) where the identification pattern (IP) is formed.

[0158] Accordingly, an identification pattern (IP) can be formed in the first region (1A) by the second-1 circuit pattern section (300b1) and the second-2 circuit pattern section (300b2).

[0159] Specifically, an identification pattern (IP) can be formed in the first region (1A) by the second-1 circuit pattern section (300b1) and the second-2 circuit pattern section (300b2), which have different thicknesses of the first circuit pattern (300).

[0160] That is, a pattern of characters, symbols, numbers, etc. can be formed on the smart IC substrate (1200) by the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2). That is, an identification pattern (IP) of characters, symbols, numbers, etc. in an embossed shape can be formed on the smart IC substrate (1200).

[0161] The color of the above 2-1 circuit pattern section (300b1) can be recognized as a different color of at least one of the above 1 circuit pattern section (300a) and the above 2-2 circuit pattern section (300b2).

[0162] For example, the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) may be perceived as different colors. Specifically, the 1 circuit pattern section (300a) and the 2-1 circuit pattern section (300b1) may have different thicknesses due to the difference in thickness of the 1 metal layer (310). Accordingly, the 1 circuit pattern section (300a) and the 2-1 circuit pattern section (300b1) have a difference in brightness due to the difference in thickness, and the user may perceive the 1 circuit pattern section (300a) and the 2-1 circuit pattern section (300b1) as different colors from the outside due to the difference in brightness.

[0163] Therefore, since the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0164] In addition, the user can recognize the identification pattern (IP) in two or more colors, thereby improving the freedom of the appearance design of the identification pattern.

[0165] In addition, since the 2-1 circuit pattern section (300b1) of the 1-1 region (1A) can be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6), the identification pattern (IP) formed by the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) can also be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6).

[0166] Accordingly, when forming an identification pattern on the IC card, the identification pattern can be formed at various locations regardless of the location of the via hole formed on the substrate. Accordingly, the design freedom of the identification pattern can be improved.

[0167] The third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched. Specifically, the third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched all or almost all of. That is, the first circuit pattern (300) may not remain in the third circuit pattern portion (300c) or may remain in a small amount. That is, the thickness of the first circuit pattern (300) placed in the third circuit pattern portion (300c) may be 0 or close to 0.

[0168] Here, the meaning of the third circuit pattern portion (300c) remaining is that after etching, the first circuit pattern (300) remains in a small amount on the first surface (1S) of the substrate (100) so that it is not connected to adjacent circuit patterns and a plating layer is not formed by the plating process.

[0169] The third circuit pattern section (300c) may correspond to the space area (SA). That is, the third circuit pattern section (300c) may be the space area (SA). That is, the first circuit pattern (300) may be divided into a plurality of circuit patterns by the third circuit pattern section (300c).

[0171] Hereinafter, with reference to FIGS. 3, 6, 7, 12, and 13, an identification pattern of a smart IC substrate according to a third embodiment will be described.

[0172] Referring to FIGS. 3, 6, 7, 12 and 13, the first circuit pattern (300) may be defined with a first circuit pattern section (300a), a second-first circuit pattern section (300b1), a second-second circuit pattern section (300b2) and a third circuit pattern section (300c) according to the thickness of the first circuit pattern (300).

[0173] The thicknesses of the first circuit pattern section (300a), the second-first circuit pattern section (300b1), the second-second circuit pattern section (300b2), and the third circuit pattern section (300c) may differ from each other. For example, the thickness of the first circuit pattern section (300a) may be greater than the thickness of the second-first circuit pattern section (300b1), the second-second circuit pattern section (300b2), and the third circuit pattern section (300c).

[0174] Additionally, the thickness of the second-2 circuit pattern section (300b2) may be greater than the thickness of the second-1 circuit pattern section (300b1) and the third circuit pattern section (300c).

[0175] Additionally, the thickness of the 2-1 circuit pattern section (300b1) may be greater than the thickness of the 3 circuit pattern section (300c).

[0176] The first circuit pattern portion (300a) may include the first metal layer (310) and the second metal layer (320). The first circuit pattern portion (300a) may be an area where the first circuit pattern (300) is not etched.

[0177] The first circuit pattern portion (300a) may be placed in the second area (2A). Specifically, the first circuit pattern portion (300a) may be placed only in the second area (2A).

[0178] The above 2-1 circuit pattern portion (300b1) may include the first metal layer (310) and the second metal layer (320).

[0179] The above 2-1 circuit pattern section (300b1) may be placed in the above 1 area (1A). Specifically, the above 2-1 circuit pattern section (300b1) may be placed only in the above 1 area (1A).

[0180] Additionally, the thickness of the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second-first circuit pattern section (300b1) may differ. Specifically, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second-first circuit pattern section (300b1).

[0181] Accordingly, the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) may have a thickness difference according to the thickness difference of the first metal layer (310).

[0182] Specifically, the thickness of the second-1 circuit pattern portion (300b1) may be 10% to 50% of the thickness of the first circuit pattern portion (300a). It may be difficult to implement the thickness of the second-1 circuit pattern portion (300b1) to exceed 50% of the thickness of the first circuit pattern portion (300a) during the etching process. Additionally, if the thickness of the second-1 circuit pattern portion (300b1) is less than 10% of the thickness of the first circuit pattern portion (300a), conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second-1 circuit pattern portion (300b1).

[0183] Additionally, the thickness difference between the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b) may be 3.5㎛ to 18㎛. It may be difficult to implement a thickness difference of less than 3.5㎛ in the etching process, and if the thickness difference between the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) exceeds 18㎛, conductivity may be reduced due to a decrease in the thickness of the first metal layer (310) of the second-first circuit pattern portion (300b1).

[0184] In addition, the width of the 2-1 circuit pattern section (300b1) may be similar in size to or greater than the width of the space area (SA).

[0186] The above 2-1 circuit pattern portion (300b1) may be an area where the above 1 circuit pattern (300) is etched. Specifically, the above 2-1 circuit pattern portion (300b1) may be an area where the above 1 metal layer (310) of the above 1 circuit pattern (300) is partially etched.

[0187] The above 2-1 circuit pattern portion (300b1) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6). Specifically, the above 2-1 circuit pattern portion (300b1) may be positioned at a location that overlaps with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100).

[0188] Alternatively, the second-1 circuit pattern portion (300b1) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6). Specifically, the second-1 circuit pattern portion (300b1) may be positioned so as not to overlap with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100).

[0189] That is, the second-1 circuit pattern portion (300b1) can be placed at a position that overlaps with or does not overlap with the via holes (V1, V2, V3, V4, V5, V6) in the thickness direction of the substrate (100). In other words, the position of the second-1 circuit pattern portion (300b1) can be placed regardless of the position of the via holes (V1, V2, V3, V4, V5, V6).

[0190] The first circuit pattern section (300a) and the second-first circuit pattern section (300b1) may be perceived as different colors. Specifically, the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) may have different thicknesses due to the difference in thickness of the first metal layer (310). Accordingly, the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) have a difference in brightness due to the difference in thickness, and the user may perceive the first circuit pattern section (300a) and the second-first circuit pattern section (300b1) as different colors from the outside due to the difference in brightness.

[0191] Therefore, the degree of design freedom of the first surface (1S) exposed to the outside of the IC card can be improved.

[0192] The above 2-2 circuit pattern portion (300b2) may include the first metal layer (310) and the second metal layer (320).

[0193] For example, the second-2 circuit pattern portion (300b2) may be an area where the first circuit pattern (300) is etched. Specifically, the second-2 circuit pattern portion (300b2) may be an area where the first metal layer (310) of the first circuit pattern (300) is partially etched.

[0194] The thickness of the first metal layer (310) of the second-2 circuit pattern section (300b2) may be greater than the thickness of the first metal layer (310) of the second-1 circuit pattern section (300b1). That is, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second-2 circuit pattern section (300b2), and the thickness of the first metal layer (310) of the second-2 circuit pattern section (300b2) may be greater than the thickness of the first metal layer (310) of the second-1 circuit pattern section (300b1).

[0195] Additionally, the difference in thickness between the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second-first circuit pattern section (300b1) may be greater than the difference in thickness between the first metal layer (310) of the second-second circuit pattern section (300b2) and the first metal layer (310) of the second-first circuit pattern section (300b1).

[0196] The above 2-2 circuit pattern section (300b2) may be placed in the above 1 area (1A). Specifically, the above 2-2 circuit pattern section (300b2) may be placed only in the above 1 area (1A).

[0197] That is, the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) may be disposed in the 1 area (1A) where the identification pattern (IP) is formed.

[0198] Accordingly, an identification pattern (IP) can be formed in the first region (1A) by the second-1 circuit pattern section (300b1) and the second-2 circuit pattern section (300b2).

[0199] Specifically, an identification pattern (IP) can be formed in the first region (1A) by the second-1 circuit pattern section (300b1) and the second-2 circuit pattern section (300b2), which have different thicknesses of the first circuit pattern (300).

[0200] That is, a pattern of characters, symbols, numbers, etc. can be formed on the smart IC substrate (1200) by the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2). That is, an identification pattern (IP) of characters, symbols, numbers, etc. in an embossed shape can be formed on the smart IC substrate (1200).

[0201] The above-mentioned 2-1 circuit pattern section (300b1) and the above-mentioned 2-2 circuit pattern section (300b2) may be perceived as different colors. Specifically, the above-mentioned 1-circuit pattern section (300a) and the above-mentioned 2-1 circuit pattern section (300b1) may have different thicknesses due to the difference in thickness of the above-mentioned 1 metal layer (310). Accordingly, the above-mentioned 1-circuit pattern section (300a) and the above-mentioned 2-1 circuit pattern section (300b1) have a difference in brightness due to the difference in thickness, and the user may perceive the above-mentioned 1-circuit pattern section (300a) and the above-mentioned 2-1 circuit pattern section (300b1) as different colors from the outside due to the difference in brightness.

[0202] Therefore, since the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0203] In addition, since the first circuit pattern portion (300a), the second-1 circuit pattern portion (300b1), and the second-2 circuit pattern portion (300b2) have different thicknesses, the user can recognize at least three colors from the outside, thereby improving the freedom of the external design of the IC card.

[0205] In addition, since the 2-1 circuit pattern section (300b1) of the 1-1 region (1A) can be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6), the identification pattern (IP) formed by the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) can also be placed regardless of the location of the via holes (V1, V2, V3, V4, V5, V6).

[0206] Accordingly, when forming an identification pattern on the IC card, the identification pattern can be formed at various locations regardless of the location of the via hole formed on the substrate. Accordingly, the design freedom of the identification pattern can be improved.

[0207] Additionally, the thickness of the 2-1 circuit pattern portion (300b1) and the 2-2 circuit pattern portion (300b2) placed in the 1st region (1A) may both be smaller than the thickness of the 1st circuit pattern portion (300a) placed in the 2nd region (2A).

[0208] Accordingly, a difference in brightness may occur in the first area (1A) and the second area (2A) due to a difference in thickness. That is, a difference in brightness may occur due to the difference in thickness between the second-2 circuit pattern part (300b2) having the shape of an identification pattern (IP) in the first area (1A) and the first circuit pattern part (300a). Accordingly, a user can easily recognize the identification pattern (IP) placed in the first area (1A) from the outside, and can form identification patterns of more diverse designs by utilizing the difference in brightness.

[0209] The third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched. Specifically, the third circuit pattern portion (300c) may be an area where the first circuit pattern (300) is etched all or almost all of. That is, the first circuit pattern (300) may not remain in the third circuit pattern portion (300c) or may remain in a small amount. That is, the thickness of the first circuit pattern (300) placed in the third circuit pattern portion (300c) may be 0 or close to 0.

[0210] Here, the meaning of the third circuit pattern portion (300c) remaining is that after etching, the first circuit pattern (300) is not connected to adjacent circuit patterns on the first surface (1S) of the substrate (100) and remains in a small amount so that a plating layer is not formed by the plating process.

[0211] The third circuit pattern section (300c) may correspond to the space area (SA). That is, the third circuit pattern section (300c) may be the space area (SA). That is, the first circuit pattern (300) may be divided into a plurality of circuit patterns by the third circuit pattern section (300c).

[0213] Hereinafter, with reference to FIGS. 2, 6, 7, 14, and 15, an identification pattern of a smart IC substrate according to a fourth embodiment will be described.

[0214] In the description of the identification pattern of the smart IC substrate according to the fourth embodiment, descriptions identical or similar to the identification pattern of the smart IC substrate according to the first embodiment described above are omitted.

[0215] Referring to FIGS. 2, FIGS. 6, FIGS. 7, FIGS. 14 and FIGS. 15, the smart IC substrate according to the fourth embodiment may further include a reinforcing portion (700), unlike the smart IC substrate according to the first embodiment.

[0216] The reinforcing member (700) may be placed on the second circuit pattern member (300b). Specifically, the reinforcing member (700) may be placed extending along the shape of the identification pattern (IP).

[0217] The reinforcing member (700) may include a resin material or a metal material. The reinforcing member (700) may be placed on the second metal layer (320) of the second circuit pattern member (300b).

[0218] As previously explained, the second metal layer (320) is placed on the first metal layer (310) and serves as a protective layer to prevent corrosion of the first metal layer (310). Since the first metal layer (320) is partially removed, the second circuit pattern section (300b) may have a step difference from the first circuit pattern section (300a). As a result, the side of the first circuit pattern section (300a) may have the first metal layer (310) exposed, and the first circuit pattern section (300a) may be corroded by external moisture or oxygen.

[0219] Accordingly, a reinforcing member (700) may be placed on the second metal layer (310) of the second circuit pattern section (300b), and the reinforcing member (700) may be placed in contact with the side of the first circuit pattern section (300a). By doing so, the first circuit pattern section (300a) may be prevented from being corroded by the reinforcing member (700).

[0220] The reinforcing member (700) may have color. For example, the reinforcing member (700) may include a colored resin material or a metal material having a different color coordinate from the metal of the first metal layer (310) and the second metal layer (320).

[0221] Accordingly, the second circuit pattern portion (300b) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0223] Hereinafter, with reference to FIGS. 2, FIGS. 6, FIGS. 7, FIGS. 16, and FIGS. 17, an identification pattern of a smart IC substrate according to the fifth embodiment will be described.

[0224] In the description of the identification pattern of the smart IC substrate according to the 5th embodiment, descriptions that are identical or similar to the identification patterns of the smart IC substrates according to the 1st and 4th embodiments described above are omitted.

[0225] Referring to FIGS. 2, FIGS. 6, FIGS. 7, FIGS. 16 and FIGS. 17, the smart IC substrate according to the fifth embodiment may further include a reinforcing portion (700), unlike the smart IC substrate according to the first embodiment.

[0226] The reinforcing member (700) may be placed on the second circuit pattern member (300b). Specifically, the reinforcing member (700) may be placed extending along the shape of the identification pattern (IP).

[0227] The reinforcing member (700) may include a resin material or a metal material. The reinforcing member (700) may be placed on the second metal layer (320) of the second circuit pattern member (300b).

[0228] As previously explained, the second metal layer (320) is placed on the first metal layer (310) and serves as a protective layer to prevent corrosion of the first metal layer (310). Since the first metal layer (320) is partially removed, the second circuit pattern section (300b) may have a step difference from the first circuit pattern section (300a). As a result, the side of the first circuit pattern section (300a) may have the first metal layer (310) exposed, and the first circuit pattern section (300a) may be corroded by external moisture or oxygen.

[0229] Accordingly, a reinforcing member (700) may be placed on the second metal layer (310) of the second circuit pattern section (300b), and the reinforcing member (700) may be placed in contact with the side of the first circuit pattern section (300a). By doing so, the first circuit pattern section (300a) may be prevented from being corroded by the reinforcing member (700).

[0230] The reinforcing member (700) may have color. For example, the reinforcing member (700) may include a colored resin material or a metal material having a different color coordinate from the metal of the first metal layer (310) and the second metal layer (320).

[0231] Accordingly, the second circuit pattern portion (300b) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0232] Additionally, the reinforcing member (700) may be positioned protrudingly. Specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the circuit pattern. Specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the first circuit pattern (300). More specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the second metal layer (320).

[0233] That is, the upper surface of the reinforcing member (700) can be positioned to protrude with respect to the upper surface of the second metal layer (320). Accordingly, the reinforcing member (700), which extends along the shape of the identification pattern (IP), can be positioned to protrude with respect to the upper surface of the smart IC substrate (1200).

[0234] Accordingly, the user can easily identify the identification pattern (IP) from the outside due to the difference in brightness resulting from the height difference between the reinforcing part (700) and the smart IC substrate (1200). In addition, the user can recognize the identification pattern (IP) from the outside not only by sight but also by touch through the reinforcing part (700) that extends along the shape of the identification pattern (IP), thereby diversifying the functions of the identification pattern (IP).

[0236] Hereinafter, with reference to FIGS. 3, 6, 7, 18, and 19, an identification pattern of a smart IC substrate according to the 6th embodiment will be described.

[0237] In the description of the identification pattern of the smart IC substrate according to the 6th embodiment, descriptions identical or similar to the identification pattern of the smart IC substrate according to the 2nd embodiment described above are omitted.

[0238] Referring to FIGS. 3, FIGS. 6, FIGS. 7, FIGS. 18 and FIGS. 19, the smart IC substrate according to the 6th embodiment may further include a reinforcing portion (700), unlike the smart IC substrate according to the 1st embodiment.

[0239] The reinforcing member (700) may be placed on the second circuit pattern member (300b). Specifically, the reinforcing member (700) may be placed extending along the shape of the identification pattern (IP).

[0240] The reinforcing member (700) may include a resin material or a metal material. The reinforcing member (700) may be placed on the second metal layer (320) of the second-1 circuit pattern member (300b1).

[0241] As previously explained, the second metal layer (320) is placed on the first metal layer (310) and serves as a protective layer to prevent corrosion of the first metal layer (310). Since the first metal layer (320) is partially removed, the second-1 circuit pattern section (300b1) may have a step difference from the first circuit pattern section (300a). As a result, the side of the first circuit pattern section (300a) may have the first metal layer (310) exposed, and the first circuit pattern section (300a) may be corroded by external moisture or oxygen.

[0242] Accordingly, a reinforcing member (700) may be placed on the second metal layer (310) of the second-first circuit pattern section (300b1), and the reinforcing member (700) may be placed in contact with the side of the first circuit pattern section (300a). By doing so, the first circuit pattern section (300a) may be prevented from being corroded by the reinforcing member (700).

[0243] The reinforcing member (700) may have color. For example, the reinforcing member (700) may include a colored resin material or a metal material having a different color coordinate from the metal of the first metal layer (310) and the second metal layer (320).

[0244] Accordingly, the second-1 circuit pattern portion (300b1) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0246] Hereinafter, with reference to FIGS. 3, 6, 7, 20, and 21, an identification pattern of a smart IC substrate according to the 7th embodiment will be described.

[0247] In the description of the identification pattern of the smart IC substrate according to the 7th embodiment, descriptions identical or similar to the identification patterns of the smart IC substrate according to the 2nd and 6th embodiments described above are omitted.

[0248] Referring to FIGS. 3, FIGS. 6, FIGS. 7, FIGS. 20 and FIGS. 21, the smart IC substrate according to the 7th embodiment may further include a reinforcing portion (700), unlike the smart IC substrate according to the 1st embodiment.

[0249] The reinforcing member (700) may be placed on the second circuit pattern member (300b). Specifically, the reinforcing member (700) may be placed extending along the shape of the identification pattern (IP).

[0250] The reinforcing member (700) may include a resin material or a metal material. The reinforcing member (700) may be placed on the first metal layer (310) of the second-first circuit pattern member (300b1).

[0251] As previously explained, the second metal layer (320) is placed on the first metal layer (310) and serves as a protective layer to prevent corrosion of the first metal layer (310). Since the first metal layer (320) is partially removed, the second-1 circuit pattern section (300b1) may have a step difference from the first circuit pattern section (300a). As a result, the side of the first circuit pattern section (300a) may have the first metal layer (310) exposed, and the first circuit pattern section (300a) may be corroded by external moisture or oxygen.

[0252] Accordingly, a reinforcing member (700) may be placed on the second metal layer (310) of the second-first circuit pattern section (300b1), and the reinforcing member (700) may be placed in contact with the side of the first circuit pattern section (300a). By doing so, the first circuit pattern section (300a) may be prevented from being corroded by the reinforcing member (700).

[0253] The reinforcing member (700) may have color. For example, the reinforcing member (700) may include a colored resin material or a metal material having a different color coordinate from the metal of the first metal layer (310) and the second metal layer (320).

[0254] Accordingly, the second-1 circuit pattern portion (300b1) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0255] Additionally, the reinforcing member (700) may be positioned protrudingly. Specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the circuit pattern. Specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the first circuit pattern (300). More specifically, the reinforcing member (700) may be positioned protrudingly with respect to the upper surface of the second metal layer (320).

[0256] That is, the upper surface of the reinforcing member (700) can be positioned to protrude with respect to the upper surface of the second metal layer (320). Accordingly, the reinforcing member (700), which extends along the shape of the identification pattern (IP), can be positioned to protrude with respect to the upper surface of the smart IC substrate (1200).

[0257] Accordingly, the user can easily identify the identification pattern (IP) from the outside due to the difference in brightness resulting from the height difference between the reinforcing part (700) and the smart IC substrate (1200). In addition, the user can recognize the identification pattern (IP) from the outside not only by sight but also by touch through the reinforcing part (700) that extends along the shape of the identification pattern (IP), thereby diversifying the functions of the identification pattern (IP).

[0259] Hereinafter, with reference to FIGS. 2, 6, 7, 22, and 23, an identification pattern of a smart IC substrate according to the 8th embodiment will be described.

[0260] In the description of the identification pattern of the smart IC substrate according to the 8th embodiment, descriptions identical or similar to the identification pattern of the smart IC substrate according to the 1st embodiment described above are omitted.

[0261] Referring to FIGS. 2, FIGS. 6, FIGS. 7, FIGS. 22 and FIGS. 23, the smart IC substrate according to the eighth embodiment may have a second circuit pattern portion (300b) that includes only the first metal layer (310), unlike the smart IC substrate according to the first embodiment.

[0262] The first circuit pattern (300) may have a first circuit pattern section (300a), a second circuit pattern section (300b), and a third circuit pattern section (300c) defined according to the thickness of the first circuit pattern (300).

[0263] The second circuit pattern portion (300b) may include only the first metal layer (310). That is, unlike the first circuit pattern portion (300a), the second circuit pattern portion (300b) may not include the second metal layer (320).

[0264] That is, the smart IC substrate according to the first embodiment forms a first metal layer, then partially etches the first metal layer and forms a second metal layer, so that the first circuit pattern (300) of the second circuit pattern portion (300b) includes both the first metal layer and the second metal layer. On the other hand, the smart IC substrate according to the eighth embodiment forms both the first metal layer and the second metal layer, then etches a portion of the second metal layer and the first metal layer, so that the first circuit pattern (300) of the second circuit pattern portion (300b) may include only the first metal layer.

[0265] The second circuit pattern section (300b) may be placed in the first area (1A). Specifically, the second circuit pattern section (300b) may be placed only in the first area (1A).

[0266] Additionally, the thickness of the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second circuit pattern section (300b) may differ. Specifically, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second circuit pattern section (300b).

[0267] Accordingly, the first circuit pattern portion (300a) and the second circuit pattern portion (300b) may have a thickness difference depending on the thickness difference of the first metal layer (310) and the presence or absence of the second metal layer (320).

[0268] The first circuit pattern section (300a) and the second circuit pattern section (300b) may have different colors. Specifically, the first circuit pattern section (300a) may have a color according to the material of the second metal layer (320). Additionally, the second circuit pattern section (300b) may have a color according to the material of the first metal layer (310). That is, the first surface (1S) on which the first circuit pattern (300) is placed may have at least two colors.

[0269] Therefore, various colors can be implemented on the first surface (1S) exposed to the outside of the IC card, thereby improving design freedom. In addition, since the first circuit pattern portion (300a) and the second circuit pattern portion (300) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0270] Although not illustrated in FIGS. 21 and 22, the reinforcing part described above may be placed on the second circuit pattern part (300b).

[0271] Since the second metal layer (320) is removed from the second circuit pattern section (300b), the second circuit pattern section (300b), where the first metal layer (310) is exposed, may be susceptible to corrosion compared to other circuit pattern sections.

[0272] Accordingly, a reinforcing member is placed on the first metal layer (310) of the second circuit pattern part (300b), and the second circuit pattern part (300b) can be prevented from being corroded by the reinforcing member.

[0273] In addition, by applying color to the reinforcing part, the second circuit pattern part (300b) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0274] Additionally, the reinforcing member may be positioned lower than, coplanar with, or protruding from the upper surface of the circuit pattern. For example, the reinforcing member may be positioned protruding from the upper surface of the first circuit pattern (300). More specifically, the reinforcing member may be positioned protruding from the upper surface of the second metal layer (320).

[0275] Accordingly, the user can easily identify the identification pattern (IP) from the outside due to the difference in brightness resulting from the height difference between the reinforcing part and the smart IC substrate (1200). In addition, the user can recognize the identification pattern (IP) from the outside not only by sight but also by touch through the reinforcing part (700) that extends along the shape of the identification pattern (IP), thereby diversifying the functions of the identification pattern (IP).

[0277] Hereinafter, with reference to FIGS. 3, 6, 7, 24, and 25, an identification pattern of a smart IC substrate according to the ninth embodiment will be described.

[0278] In the description of the identification pattern of the smart IC substrate according to the ninth embodiment, descriptions identical or similar to the identification pattern of the smart IC substrate according to the second embodiment described above are omitted.

[0279] Referring to FIGS. 3, 6, 7, 24, and 25, the smart IC substrate according to the ninth embodiment may have a second-1 circuit pattern portion (300b1) that includes only a first metal layer (310), unlike the smart IC substrate according to the second embodiment.

[0280] That is, the smart IC substrate according to the second embodiment forms a first metal layer, then partially etches the first metal layer and forms a second metal layer, so that the first circuit pattern (300) of the second circuit pattern portion (300b) includes both the first metal layer and the second metal layer. On the other hand, the smart IC substrate according to the ninth embodiment forms both the first metal layer and the second metal layer, then etches a portion of the second metal layer and the first metal layer, so that the first circuit pattern (300) of the second circuit pattern portion (300b) may include only the first metal layer.

[0281] The first circuit pattern (300) may have a first circuit pattern section (300a), a second-first circuit pattern section (300b1), a second-second circuit pattern section (300b2), and a third circuit pattern section (300c) defined according to the thickness of the first circuit pattern (300).

[0282] The above 2-1 circuit pattern portion (300b1) may include only the first metal layer (310). That is, unlike the first circuit pattern portion (300a), the above 2-1 circuit pattern portion (300b1) may not include the second metal layer (320).

[0283] The above 2-1 circuit pattern section (300b1) may be placed in the above 1 area (1A). Specifically, the above 2-1 circuit pattern section (300b1) may be placed only in the above 1 area (1A).

[0284] Additionally, the thickness of the first metal layer (310) of the first circuit pattern section (300a) and the first metal layer (310) of the second-first circuit pattern section (300b1) may differ. Specifically, the thickness of the first metal layer (310) of the first circuit pattern section (300a) may be greater than the thickness of the first metal layer (310) of the second-first circuit pattern section (300b1).

[0285] Accordingly, the first circuit pattern portion (300a) and the second-first circuit pattern portion (300b1) may have a thickness difference depending on the thickness difference of the first metal layer (310) and the presence or absence of the second metal layer (320).

[0286] The first circuit pattern section (300a) and the second-first circuit pattern section (300b1) may have different colors. Specifically, the first circuit pattern section (300a) may have a color according to the material of the second metal layer (320). Additionally, the second-first circuit pattern section (300b1) may have a color according to the material of the first metal layer (320). That is, the first surface (1S) on which the first circuit pattern (300) is placed may have at least two colors.

[0287] Therefore, the degree of design freedom of the first surface (1S) exposed to the outside of the IC card can be improved.

[0288] Additionally, the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) may have different colors. Specifically, the 2-1 circuit pattern section (300b1) may have a color according to the material of the 1 metal layer (310). Additionally, the 2-2 circuit pattern section (300b2) may have a color according to the material of the 2 metal layer (320). That is, the 1 area (1A) where the identification pattern (IP) is placed may have at least two colors.

[0289] Therefore, since the 2-1 circuit pattern section (300b1) and the 2-2 circuit pattern section (300b2) are distinguished by a difference in color in addition to a difference in thickness, the user can easily identify the identification pattern of the IC card from the outside.

[0290] Although not illustrated in FIGS. 23 and 24, the reinforcing part described above may be placed on the 2-1 circuit pattern part (300b1).

[0291] Since the second metal layer (320) is removed from the second-1 circuit pattern section (300b1), the second-1 circuit pattern section (300b1), where the first metal layer (310) is exposed, may be susceptible to corrosion compared to other circuit pattern sections.

[0292] Accordingly, a reinforcing member is placed on the first metal layer (310) of the second-1 circuit pattern section (300b1), and the second circuit pattern section (300b) can be prevented from being corroded by the reinforcing member.

[0293] In addition, by applying color to the reinforcing part, the second-1 circuit pattern part (300b1) having the shape of the identification pattern (IP) can be implemented in various colors. Accordingly, the identification pattern (IP) can be implemented in various colors to improve design freedom, and the user can easily identify the identification pattern (IP) from the outside.

[0294] Additionally, the reinforcing member may be positioned lower than, coplanar with, or protruding from the upper surface of the circuit pattern. For example, the reinforcing member may be positioned protruding from the upper surface of the first circuit pattern (300). More specifically, the reinforcing member may be positioned protruding from the upper surface of the second metal layer (320).

[0295] Accordingly, the user can easily identify the identification pattern (IP) from the outside due to the difference in brightness resulting from the height difference between the reinforcing part and the smart IC substrate (1200). In addition, the user can recognize the identification pattern (IP) from the outside not only by sight but also by touch through the reinforcing part (700) that extends along the shape of the identification pattern (IP), thereby diversifying the functions of the identification pattern (IP).

[0297] Meanwhile, in the preceding description, a dual-type smart IC substrate, smart IC module, and IC card in which circuit patterns are arranged on both the first surface (1S) and the second surface (2S) of the substrate (100) were described, but the embodiments are not limited thereto. Specifically, referring to FIGS. 26 and FIGS. 27, the embodiments can also be applied to single-type smart IC substrates, smart IC modules, and IC cards.

[0298] That is, referring to FIGS. 26 and 27, in the embodiment, a circuit pattern may be placed only on the first surface (1S) of the smart IC substrate, smart IC module, and IC card. Additionally, only a chip (C) may be placed on the second surface (2S). Furthermore, the circuit pattern placed on the first surface (1S) can implement an identification pattern by partial etching as described above.

[0299] That is, the smart IC substrate, smart IC module, and IC card according to the embodiment can be applied to both single and dual types.

[0301] The smart IC substrate, smart IC module, and IC card according to the embodiment may include an identification pattern.

[0302] Specifically, the circuit patterns of the smart IC substrate, the smart IC module, and the IC card can be etched to form an identification pattern in the shape of intaglio or relief.

[0303] Accordingly, when a user sees the IC card from the outside, they can easily identify the information on the IC card by looking at the identification pattern.

[0304] In addition, the identification pattern can be formed by partially etching the circuit pattern. Accordingly, the identification pattern can be formed at various locations regardless of the location of the via holes of the smart IC substrate.

[0305] In addition, the identification pattern can be recognized in a color different from other circuit patterns. Accordingly, a user can easily identify the identification pattern from the outside.

[0306] In addition, the identification pattern may have a different color from other circuit patterns. Accordingly, a user can easily identify the identification pattern from the outside.

[0307] In addition, a reinforcing part made of resin or metal material may be placed on the identification pattern. Accordingly, corrosion of the circuit pattern can be prevented. Furthermore, the freedom of appearance design can be enhanced by applying various colors to the reinforcing part.

[0309] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0310] Furthermore, although the invention has been described above with reference to embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

Claims

Claim 1 A smart IC substrate comprising: a substrate; and a first circuit pattern disposed on the substrate, wherein the substrate comprises a plurality of via holes penetrating the upper and lower surfaces of the substrate, and the first circuit pattern comprises: a first metal layer disposed on the substrate; and a second metal layer disposed on the first metal layer, wherein the first metal layer comprises a first portion and a second portion having a thickness smaller than the thickness of the first portion, and the second portion of the first metal layer is disposed at least one of a position that overlaps with the via holes and a position that does not overlap in the thickness direction of the substrate. Claim 2 A smart IC substrate according to claim 1, wherein the first metal layer is provided on the upper surface of the first metal layer and includes a concave recess facing the lower surface of the first metal layer, and the second portion of the first metal layer is the portion where the recess is formed. Claim 3 A smart IC substrate according to claim 1, wherein the thickness of the second portion of the first metal layer is 10% to 50% of the thickness of the first portion. Claim 4 A smart IC substrate according to claim 1, wherein the thickness difference between the first portion and the second portion of the first metal layer is 3.5 μm to 18 μm. Claim 5 A smart IC substrate according to claim 1, wherein the second portion of the first metal layer is an identification pattern displaying a logo, character, or symbol. Claim 6 In claim 1, the first circuit pattern is a smart IC substrate connected to a chip through a wire passing through at least one of the plurality of via holes. Claim 7 A smart IC substrate according to claim 1, further comprising a second circuit pattern disposed under the substrate, wherein the second circuit pattern is connected to the first circuit pattern through a plating layer disposed inside at least one of the plurality of via holes. Claim 8 In claim 2, the second circuit pattern comprises a third metal layer disposed under the substrate and a fourth metal layer disposed under the third metal layer, and the thickness of the fourth metal layer is greater than the thickness of the second metal layer, for a smart IC substrate. Claim 9 A smart IC substrate according to claim 2, further comprising a reinforcing member disposed on the second portion of the first metal layer and filling the recess, wherein the color of the reinforcing member is different from the color of the second metal layer. Claim 10 In claim 1, the second metal layer is disposed on the first portion and the second portion of the first metal layer, respectively, of a smart IC substrate. Claim 11 In claim 1, the second metal layer is a smart IC substrate disposed on the first portion excluding the second portion of the first metal layer. Claim 12 In claim 11, the color of the second part of the first metal layer is another smart IC substrate of the second metal layer. Claim 13 A smart IC substrate according to claim 1, wherein the upper surface of the substrate is defined with a first region and a second region other than the first region, the first region of the substrate is provided with both the first portion and the second portion of the first metal layer, and the second region of the substrate is provided with only the first portion of the first metal layer. Claim 14 In claim 1, the first circuit pattern comprises a plurality of circuit patterns spaced apart from each other with a space area in between, a smart IC substrate. Claim 15 A smart IC substrate according to claim 9, wherein the height of the upper surface of the reinforcing part is the same as the height of the upper surface of the second metal layer. Claim 16 A smart IC substrate according to claim 9, wherein the height of the upper surface of the reinforcing part is greater than the height of the upper surface of the second metal layer. Claim 17 A smart IC substrate according to claim 1, further comprising an adhesive layer disposed between the substrate and the first circuit pattern. Claim 18 A smart IC substrate according to claim 1, wherein the first metal layer and the second metal layer comprise different metals. Claim 19 A smart IC substrate according to claim 7, further comprising an adhesive layer disposed between the substrate and the second circuit pattern. Claim 20 A smart IC module comprising: a smart IC substrate according to any one of claims 1 to 19; and a chip disposed on the smart IC substrate and electrically connected to the first circuit pattern.

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