Display device, display panel, and subpixel circuit

Abstract

Embodiments of the present disclosure relate to a touch display device, a display panel, and a subpixel circuit, and more specifically, may provide a display device comprising: a display panel including a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a subpixel circuit having a plurality of switching transistors arranged therein to control the driving of the driving transistor; a gate driving circuit that supplies a light-emitting signal and a plurality of scan signals to the display panel; a data driving circuit that supplies a data voltage to the display panel; and a timing controller that controls the gate driving circuit and the data driving circuit, wherein the plurality of switching transistors are controlled by a first scan signal, and the first switching transistor having a dual-gate structure connecting a gate node and a drain node of the driving transistor, and a stabilizing transistor that is controlled by a stabilizing scan signal and connecting a gate node of the driving transistor and a common node of the first switching transistor.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a display device, a display panel, and a subpixel circuit, and more specifically, to a display device, a display panel, and a subpixel circuit capable of improving image quality by reducing luminance deviation caused by leakage current. Background Technology

[0003] As the information society develops, there is an increasing demand for display devices that display images, and various types of display devices, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays, are being utilized.

[0004] Among these display devices, organic light-emitting display devices utilize self-emissive organic light-emitting diodes, offering fast response speeds and advantages in contrast ratio, luminous efficiency, brightness, and viewing angle.

[0005] This organic light-emitting display device includes an organic light-emitting diode placed in each of a plurality of subpixels arranged on a display panel, and can display an image by controlling the brightness represented by each subpixel by emitting light through the control of the current flowing through the organic light-emitting diode.

[0006] In such a display device, subpixel circuits for driving a light-emitting element may be disposed on the display panel. For example, a subpixel circuit includes a driving transistor that controls the driving current flowing through the light-emitting element and at least one switching transistor that controls the operation of the driving transistor according to a scan signal. The switching transistor of the subpixel circuit may be controlled by a gate signal output from a gate driving circuit.

[0007] In this case, some nodes of the driving transistor may operate as floating nodes depending on the operation of the switching transistor; however, there is a problem in that potential fluctuations caused by leakage current can lead to brightness deviations. The problem to be solved

[0009] Accordingly, the inventors of the present disclosure have invented a display device, a display panel, and a subpixel circuit capable of reducing luminance deviation caused by leakage current and improving image quality.

[0010] Embodiments of the present disclosure can provide a display device, a display panel, and a subpixel circuit that can reduce brightness deviation caused by leakage current and improve image quality by using a transistor capable of stabilizing the gate node potential of a driving transistor.

[0011] The embodiments of the present disclosure can provide a display device, a display panel, and a subpixel circuit capable of reducing luminance deviation and improving image quality by using a stabilizing transistor to maintain the gate node of a driving transistor at a stable potential prior to the light emission period. means of solving the problem

[0013] Embodiments of the present disclosure may provide a display device comprising: a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a subpixel circuit having a plurality of switching transistors arranged therein to control the driving of the driving transistor; a gate driving circuit that supplies a light-emitting signal and a plurality of scan signals to the display panel; a data driving circuit that supplies a data voltage to the display panel; and a timing controller that controls the gate driving circuit and the data driving circuit, wherein the plurality of switching transistors are controlled by a first scan signal, and the first switching transistor having a dual-gate structure connecting a gate node and a drain node of the driving transistor, and a stabilizing transistor that is controlled by a stabilization scan signal and connecting a gate node of the driving transistor and a common node of the first switching transistor.

[0014] Embodiments of the present disclosure may provide a display panel comprising a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, a plurality of subpixels arranged with a plurality of switching transistors that control the driving of the driving transistor, a plurality of data lines that supply a data voltage to the plurality of subpixels, and a plurality of gate lines that supply a light-emitting signal and a plurality of scan signals to the plurality of subpixels, wherein the plurality of switching transistors are controlled by a first scan signal, and the first switching transistor has a dual-gate structure connecting a gate node and a drain node of the driving transistor, and the first switching transistor is controlled by a stabilization scan signal and connects a gate node of the driving transistor and a common node of the first switching transistor.

[0015] Embodiments of the present disclosure may provide a subpixel circuit comprising a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors that control the driving of the driving transistor, wherein the plurality of switching transistors are controlled by a first scan signal, and the first switching transistor has a dual-gate structure connecting the gate node and the drain node of the driving transistor, and the stabilization transistor is controlled by a stabilization scan signal and connects the gate node of the driving transistor and the common node of the first switching transistor. Effects of the invention

[0017] According to the embodiments of the present disclosure, there is an effect of providing a display device, a display panel, and a subpixel circuit capable of reducing luminance deviation caused by leakage current and improving image quality.

[0018] In addition, according to the embodiments of the present disclosure, by using a transistor capable of stabilizing the gate node potential of a driving transistor, it is possible to reduce brightness deviation caused by leakage current and improve image quality.

[0019] In addition, according to the embodiments of the present disclosure, by using a stabilization transistor to maintain the gate node of the driving transistor at a stable potential before the light emission period, it is possible to reduce the brightness deviation and improve image quality. Brief explanation of the drawing

[0021] FIG. 1 is a schematic diagram showing a display device according to embodiments of the present disclosure. FIG. 2 is a system example drawing of a display device according to embodiments of the present disclosure. FIG. 3 is a diagram illustrating an example of a subpixel circuit of a display device according to embodiments of the present disclosure. FIG. 4 is a signal waveform diagram showing the operation of a subpixel circuit in a display device according to embodiments of the present disclosure. FIG. 5 is a signal waveform diagram experimentally showing the change in driving current in a display device according to embodiments of the present disclosure, when there is no stabilization transistor in the subpixel circuit and when there is. FIG. 6 is a diagram illustrating another subpixel circuit structure as an example in a display device according to embodiments of the present disclosure. FIG. 7 is a signal waveform diagram showing the operation of another subpixel circuit in a display device according to embodiments of the present disclosure. Specific details for implementing the invention

[0022] Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the present invention, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0023] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are used merely to distinguish the components from other components, and the essence, order, sequence, or number of the components are not limited by such terms.

[0024] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0025] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0026] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0027] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0028] FIG. 1 is a schematic diagram showing a display device according to embodiments of the present disclosure.

[0029] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110) and a driving circuit for driving the display panel (110).

[0030] The display panel (110) may include a display area (DA) where an image is displayed and a bezel area (BA) where an image is not displayed. The bezel area (BA) may also be referred to as a non-display area.

[0031] The display panel (110) may include a plurality of subpixels (SP) for displaying images. For example, a plurality of subpixels (SP) may be placed in a display area (DA). In some cases, at least one subpixel (SP) may be placed in a bezel area (BA). The at least one subpixel (SP) placed in the bezel area (BA) is also referred to as a dummy subpixel.

[0032] The display panel (110) may include a plurality of signal lines for driving a plurality of subpixels (SP). For example, the plurality of signal lines may include a plurality of data lines (DL) and a plurality of gate lines (GL). Depending on the structure of the subpixel (SP), the signal lines may further include a plurality of data lines (DL) and a plurality of gate lines (GL) and other signal lines. For example, other signal lines may include driving voltage lines and reference voltage lines, etc.

[0033] A plurality of data lines (DL) and a plurality of gate lines (GL) may intersect each other. Each of the plurality of data lines (DL) may be arranged to extend in a first direction. Each of the plurality of gate lines (GL) may be arranged to extend in a second direction. Here, the first direction may be the column direction and the second direction may be the row direction. In this specification, the column direction and the row direction are relative. For example, the column direction may be the vertical direction and the row direction may be the horizontal direction. As another example, the column direction may be the horizontal direction and the row direction may be the vertical direction.

[0034] The driving circuit may include a data driving circuit (130) for driving a plurality of data lines (DL) and a gate driving circuit (120) for driving a plurality of gate lines (GL). The driving circuit may further include a timing controller (140) for controlling the data driving circuit (130) and the gate driving circuit (120).

[0035] The data driving circuit (130) is a circuit for driving a plurality of data lines (DL) and can output a data signal (also called a data voltage) corresponding to an image signal to the plurality of data lines (DL). The gate driving circuit (120) is a circuit for driving a plurality of gate lines (GL) and can generate gate signals and output the gate signals to the plurality of gate lines (GL). The gate signals may include one or more scan signals and light emission signals.

[0036] The timing controller (140) can start scanning according to the timing implemented in each frame and control data driving at an appropriate time in accordance with the scan. The timing controller (140) can convert input image data input from the outside to match the data signal format used by the data driving circuit (130) and supply the converted image data (DATA) to the data driving circuit (130).

[0037] The timing controller (140) can receive display driving control signals from an external host system (200) along with input image data. For example, the display driving control signals may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a clock signal, etc.

[0038] The timing controller (140) can generate a data drive control signal (DCS) and a gate drive control signal (GCS) based on display drive control signals input from the host system (200). The timing controller (140) can control the drive operation and drive timing of the data drive circuit (130) by supplying the data drive control signal (DCS) to the data drive circuit (130). The timing controller (140) can control the drive operation and drive timing of the gate drive circuit (120) by supplying the gate drive control signal (GCS) to the gate drive circuit (120).

[0039] The data driving circuit (130) may include one or more source driving integrated circuits (SDICs). Each source driving integrated circuit may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. Each source driving integrated circuit may, in some cases, further include an analog to digital converter (ADC).

[0040] For example, each source driving integrated circuit may be connected to the display panel (110) by Tape Automated Bonding (TAB) method, connected to the bonding pads of the display panel (110) by Chip On Glass (COG) or Chip On Panel (COP) method, or implemented by Chip On Film (COF) method and connected to the display panel (110).

[0041] The gate driving circuit (120) can output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the timing controller (140). The gate driving circuit (120) can sequentially drive a plurality of gate lines (GL) by sequentially supplying a gate signal of a turn-on level voltage to a plurality of gate lines (GL).

[0042] The gate driving circuit (120) may include one or more gate driving integrated circuits (GDICs).

[0043] The gate driving circuit (120) may be connected to the display panel (110) via a tape automatic bonding (TAB) method, connected to a bonding pad of the display panel (110) via a chip-on-glass (COG) or chip-on-panel (COP) method, or connected to the display panel (110) via a chip-on-film (COF) method. Alternatively, the gate driving circuit (120) may be formed in the bezel area (BA) of the display panel (110) as a Gate In Panel (GIP) type. The gate driving circuit (120) may be placed on a substrate or connected to a substrate. That is, if the gate driving circuit (120) is of the Gate In Panel (GIP) type, it may be placed in the bezel area (BA) of the substrate. If the gate driving circuit (120) is of the Chip-on-Glass (COG) type, Chip-on-Film (COF) type, etc., it may be connected to a substrate.

[0044] Meanwhile, at least one of the data driving circuit (130) and the gate driving circuit (120) may be placed in the display area (DA). For example, at least one of the data driving circuit (130) and the gate driving circuit (120) may be placed so as not to overlap with the subpixels (SP), or may be placed so as to partially or entirely overlap with the subpixels (SP).

[0045] The data driving circuit (130) may be connected to one side (e.g., the upper side or the lower side) of the display panel (110). Depending on the driving method, panel design method, etc., the data driving circuit (130) may be connected to both sides (e.g., the upper side and the lower side) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0046] The gate driving circuit (120) may be connected to one side (e.g., left or right) of the display panel (110). Depending on the driving method, panel design method, etc., the gate driving circuit (120) may be connected to both sides (e.g., left and right) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0047] The timing controller (140) may be implemented as a separate component from the data driving circuit (130), or it may be implemented as an integrated circuit integrated together with the data driving circuit (130). The timing controller (140) may be a controller used in conventional display technology, a control device capable of performing other control functions including the timing controller, or a circuit within the control device. The timing controller (140) may be implemented as various circuits or electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0048] The timing controller (140) is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to a data driving circuit (130) and a gate driving circuit (120) through the printed circuit board, the flexible printed circuit, etc. The timing controller (140) can transmit and receive signals to and from the data driving circuit (130) according to one or more predetermined interfaces. Here, for example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI interface, a SP (Serial Peripheral Interface), etc.

[0049] A display device (100) according to embodiments of the present disclosure may be a self-emissive display device in which a display panel (110) emits light on itself. If the display device (100) according to embodiments of the present disclosure is a self-emissive display device, each of a plurality of subpixels (SP) may include a light-emitting element. For example, the display device (100) according to embodiments of the present disclosure may be an organic light-emitting display device in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device (100) according to embodiments of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is implemented as an inorganic-based light-emitting diode. As yet another example, the display device (100) according to embodiments of the present disclosure may be a quantum dot display device in which the light-emitting element is implemented as a quantum dot, which is a semiconductor crystal that emits light on itself.

[0050] FIG. 2 is a system example drawing of a display device according to embodiments of the present disclosure.

[0051] Referring to FIG. 2, the display device (100) according to embodiments of the present disclosure shows a case in which the data driving circuit (130) is implemented in a COF (Chip On Film) manner among various methods (TAB, COG, COF, etc.) and the gate driving circuit (120) is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

[0052] When the gate driving circuit (120) is implemented in the form of a GIP, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit (120) can be directly formed in the bezel area of ​​the display panel (110). At this time, the gate driving integrated circuits (GDICs) can receive various signals (clock, gate high signal, gate low signal, etc.) required for generating a scan signal through gate driving related signal wiring placed in the bezel area.

[0053] Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit (130) may each be mounted on a source film (SF), and one side of the source film (SF) may be electrically connected to a display panel (110). Additionally, wiring for electrically connecting the source driving integrated circuit (SDIC) and the display panel (110) may be arranged on the upper side of the source film (SF).

[0054] The display device (100) may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electrical devices for circuit connection between a plurality of source driving integrated circuits (SDIC) and other devices.

[0055] At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be electrically connected to the display panel (110), and the other side can be electrically connected to the source printed circuit board (SPCB).

[0056] A timing controller (140) and a power management circuit (150) may be mounted on a control printed circuit board (CPCB). The timing controller (140) can control the operation of a data driving circuit (130) and a gate driving circuit (120). The power management circuit (150) may supply a driving voltage or current to a display panel (110), a data driving circuit (130), and a gate driving circuit (120), and may control the supplied voltage or current.

[0057] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be circuitously connected through at least one connecting member, and the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In addition, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be implemented by integrating them into a single printed circuit board.

[0058] The display device (100) may further include a set board (170) electrically connected to a control printed circuit board (CPCB). In this case, the set board (170) may also be referred to as a power board. A main power management circuit (160) that manages the total power of the display device (100) may be present on this set board (170). The main power management circuit (160) may be linked with a power management circuit (150).

[0059] In the case of a display device (100) configured as above, the driving voltage is generated at the set board (170) and transmitted to the power management circuit (150) within the control printed circuit board (CPCB). The power management circuit (150) transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) via the flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is supplied to emit light or sense a specific subpixel (SP) within the display panel (110) via the source driving integrated circuit (SDIC).

[0060] At this time, each subpixel (SP) arranged in the display panel (110) within the display device (100) may be composed of a light-emitting element and a circuit element such as a driving transistor for driving it.

[0061] The types and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided functions and design methods.

[0062] The display device (100) of the present disclosure can reduce brightness deviation caused by leakage current and improve image quality by stably maintaining the gate node of the driving transistor constituting the subpixel (SP).

[0063] FIG. 3 is a diagram illustrating an example of a subpixel circuit of a display device according to embodiments of the present disclosure, and FIG. 4 is a signal waveform diagram illustrating the operation of the subpixel circuit.

[0064] Referring to FIGS. 3 and 4, the subpixel circuit of the display device (100) according to embodiments of the present disclosure may include a plurality of switching transistors (T1-T5), a driving transistor (DRT), a storage capacitor (Cst), and a light-emitting element (ED).

[0065] A light-emitting device (ED) can be a self-luminous device capable of emitting light on its own, such as an organic light-emitting diode (OLED), for example.

[0066] Here, the case in which the subpixel circuit is implemented based on six transistors (T1-T5, DRT) is described as an example, but the technical concept of the present disclosure is not limited thereto.

[0067] A subpixel circuit according to embodiments of the present disclosure may operate in the order of an initialization period (P1), a sampling period (P2), a retention period (P3), a stabilization period (P4), and a light emission period (P5).

[0068] The initialization period (P1) is a period for initializing the gate node of the driving transistor (DRT). The sampling period (P2) is a period for initializing the light-emitting element (ED) while sampling the threshold voltage (Vth) of the driving transistor (DRT). The maintenance period (P3) is a period for maintaining the data voltage (Vdata) applied through the data line (DL) at a specific node. The stabilization period (P4) is a period for maintaining the gate node of the driving transistor (DRT) at a stable potential. The light emission period (P5) is a period for emitting light from the light-emitting element (ED) through the driving current generated based on the data voltage (Vdata).

[0069] The first switching transistor (T1) is turned on or off according to the first scan signal (SCAN1), and in the turned-on state, the gate node (N1) of the driving transistor corresponding to the other side of the storage capacitor (Cst) and the drain node (N3) of the driving transistor (DRT) are electrically connected.

[0070] The first switching transistor (T1) is turned on during the initialization period (P1) to initialize the gate node (N1) of the driving transistor (DRT), and is turned on during the sampling period (P2) to form a current path between the gate node (N1) of the driving transistor (DRT) and the drain node (N3) of the driving transistor (DRT). At this time, the first switching transistor (T1) may have a dual gate structure to suppress high-temperature leakage current.

[0071] At this time, the common node (N2) of the first switching transistor (T1) of the dual-gate structure may be in a floating state depending on the operating state of the first switching transistor (T1). Since the operation of the first switching transistor (T1) may become unstable when the common node (N2) of the first switching transistor (T1) is in a floating state, the common node (N2) of the first switching transistor (T1) and the driving voltage (VDD) may be connected to a stabilization capacitor (Cs) in order to stabilize the common node (N2) of the first switching transistor (T1).

[0072] The second switching transistor (T2) is turned on or off according to the second scan signal (SCAN2), and in the turned-on state, supplies a data voltage (Vdata) to one side of the storage capacitor (Cst). The output node (e.g., drain node) of the second switching transistor (T2) can be connected to the output node (e.g., drain node) of the third switching transistor (T3). The second switching transistor (T2) is turned on during the sampling period (P2) to form a current path between the data line (DL) and the storage capacitor (Cst).

[0073] The third switching transistor (T3) is turned on or turned off according to the light emission signal (EM), and in the turned-on state, supplies a reference voltage (Vref) supplied from the reference voltage line (RVL) to the output node of the second switching transistor (T2). That is, the third switching transistor (T3) is turned on during the initialization period (P1) and the light emission period (P5) to supply a reference voltage (Vref) to the output node of the second switching transistor (T2).

[0074] The fourth switching transistor (T4) is turned on or off according to the light emission signal (EM), and in the turned-on state, the drain node (N3) of the driving transistor (DRT) and the anode electrode (N4) of the light-emitting element (ED) are connected to each other. At this time, the source node of the fourth switching transistor (T4) can be connected to the drain node (N3) of the driving transistor (DRT).

[0075] The fourth switching transistor (T4) is turned on during the initialization period (P1) and the light emission period (P5) to form a current path between the drain node (N3) of the driving transistor (DRT) and the anode electrode (N4) of the light-emitting element (ED).

[0076] The fifth switching transistor (T5) is turned on or turned off according to the second scan signal (SCAN2), and in the turned-on state, supplies a reference voltage (Vref) to the anode node (N4) of the light-emitting element (ED). That is, the fifth switching transistor (T5) is turned on during the initialization period (P1) and the sampling period (P2) to supply a reference voltage (Vref) to the anode electrode (N4) of the light-emitting element (ED).

[0077] The driving transistor (DRT) applies a driving voltage (VDD) to the source node and controls the driving current supplied to the light-emitting element (ED) according to the voltage of the gate node (N1), thereby controlling the degree of light emission of the light-emitting element (ED).

[0078] The storage capacitor (Cst) is connected between the output node of the second switching transistor (T2) and the gate node (N1) of the driving transistor (DRT). The anode electrode (N4) of the light-emitting element (ED) is connected to the drain nodes of the fourth switching transistor (T4) and the fifth switching transistor (T5), and a base voltage (VSS) is applied to the cathode electrode.

[0079] The stabilization capacitor (Cs) connects the common node (N2) of the first switching transistor (T1) to the driving voltage (VDD). However, this stabilization capacitor (Cs) may be omitted depending on the subpixel circuit.

[0080] The common node (N2) of the first switching transistor (T1) may be in a floating state depending on the operation of the first switching transistor (T1), and in this case, the potential may be determined according to the driving transistor (DRT) and the first switching transistor (T1).

[0081] When the common node (N2) of the first switching transistor (T1) becomes floating, leakage current may flow from the drain node of the stabilization capacitor (Cs) or the driving transistor (DRT) through the first switching transistor (T1) to the gate node (N1) of the driving transistor (DRT). This leakage current may cause the potential of the gate node (N1) of the driving transistor (DRT) to fluctuate, which can cause image defects due to brightness deviation.

[0082] To reduce the brightness deviation caused by such leakage current, a sixth switching transistor (T6) can be placed to maintain the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the first switching transistor (T1) at the same potential.

[0083] The sixth switching transistor (T6) is turned on or off according to the third scan signal (SCAN3), and in the turned-on state, the common node (N2) of the first switching transistor (T1) and the gate node (N1) of the driving transistor (DRT) are connected to each other.

[0084] The sixth switching transistor (T6) is turned on during the stabilization period (P4) prior to the light emission period (P5) to form a current path between the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the first switching transistor (T1).

[0085] Therefore, during the stabilization period (P4), the gate node (N1) of the driving transistor (DRT) maintains the same potential as the common node (N2) of the first switching transistor (T1).

[0086] On the other hand, P-type transistors have the advantage of being relatively more reliable than N-type transistors, making it easier to supply current stably. Although the example illustrated here uses P-type transistors to configure the transistors (T1-T5, DRT) constituting the subpixel circuit, it is also possible to configure at least some of the transistors using N-type transistors.

[0087] During the initialization period (P1), the second scan signal (SCAN2) and the third scan signal (SCAN3) are output at a high level corresponding to the gate off voltage, and the first scan signal (SCAN1) and the light emission signal (EM) are output at a low level corresponding to the gate on voltage.

[0088] Accordingly, the third and fourth switching transistors (T3, T4) are turned on by the light emission signal (EM), and the first and fifth switching transistors (T2, T5) are turned on by the first scan signal (SCAN1). As a result, the reference voltage (Vref) is supplied to the gate node (N1) of the driving transistor (DRT) through the third switching transistor (T3) to be initialized, and the reference voltage (Vref) is supplied to the anode electrode (N4) of the light-emitting element (ED) through the fifth switching transistor (T5) to be initialized to the reference voltage (Vref). Additionally, the reference voltage (Vref) is supplied to the drain node (N3) of the driving transistor (DRT) through the turned-on fourth switching transistor (T4) to be initialized to the reference voltage (Vref). In addition, a reference voltage (Vref) is supplied to the common node (N2) of the first switching transistor (T1) by the first switching transistor (T1) that is turned on, and is initialized to the reference voltage (Vref).

[0089] During the sampling period (P2), the first scan signal (SCAN1) and the second scan signal (SCAN2) are output at a low level corresponding to the gate-on voltage, and the light emission signal (EM) and the third scan signal (SCAN3) are output at a high level corresponding to the gate-off voltage.

[0090] During the sampling period (P2), the first switching transistor (T1), the second switching transistor (T2), and the fifth switching transistor (T5) are turned on in response to the first scan signal (SCAN1) and the second scan signal (SCAN2), while the third switching transistor (T3) and the fourth switching transistor (T4) remain turned off in response to the light emission signal (EM). Accordingly, the data voltage (Vdata) is supplied to the storage capacitor (Cst) through the first switching transistor (T1). The driving transistor (DRT) samples the difference (VDD-Vth) between the driving voltage (VDD) and the threshold voltage (Vth) of the driving transistor (DRT) by the turned-on second switching transistor (T2) and supplies it to the gate node (N1) of the driving transistor (DRT).

[0091] During the maintenance period (P3), the first scan signal (SCAN1), the second scan signal (SCAN2), the third scan signal (SCAN3), and the light emission signal (EM) are all output at a high level, which is the gate-off voltage.

[0092] The maintenance period (P3) is a period during which the sampling period (P2) and the light emission period (P5) do not overlap by having a predetermined time difference between the sampling period (P2) and the light emission period (P5).

[0093] During the stabilization period (P4), the first scan signal (SCAN1), the second scan signal (SCAN2), and the light emission signal (EM) are output at a high level, which is the gate off voltage, and the third scan signal (SCAN3) is output at a low level, which is the gate on voltage.

[0094] During the stabilization period (P4), the first switching transistor (T1) is turned off by the first scan signal (SCAN1), and the sixth switching transistor (T6) is turned on by the third scan signal (SCAN3), which is a low level corresponding to the gate-on voltage. Accordingly, the gate node (N1) of the driving transistor (DRT) maintains the same potential as the common node (N2) of the first switching transistor (T1). As a result, even if the common node (N2) of the first switching transistor (T1) becomes floating and leakage current flows, the gate node (N1) of the driving transistor (DRT) remains stable, thereby reducing brightness deviation and improving image quality.

[0095] During the light emission period (P5), the first scan signal (SCAN1), the second scan signal (SCAN2), and the third scan signal (SCAN3) are all output at a high level, which is the gate-off voltage, and the light emission signal (EM) is output at a low level, which is the gate-on voltage.

[0096] Accordingly, the third switching transistor (T3) and the fourth switching transistor (T4) are turned on. As a result, a reference voltage (Vref) is applied to one side of the storage capacitor (Cst) through the third switching transistor (T3), and the difference (Vref-Vdata) between the reference voltage (Vref) and the data voltage (Vdata) is reflected at the gate node (N1) of the driving transistor (DRT). Thus, during the light emission period (P4), a driving current (Id) corresponding to the gate-source voltage of the driving transistor (DRT) flows through the light-emitting element (ED).

[0097] In this way, a subpixel circuit consisting of 7 transistors (DRT, T1-T6) and 2 capacitors (Cst, Cs) can be called a 7T2C structure.

[0098] As described above, the display device (100) of the present disclosure can reduce brightness deviation caused by leakage current and improve image quality by turning on the sixth switching transistor (T6) before the light emission section (P5) to maintain the gate node (N1) of the driving transistor (DRT) at a stable potential. Accordingly, the sixth switching transistor (T6) for maintaining the gate node (N1) of the driving transistor (DRT) at a stable potential may be called a stabilizing transistor, and the third scan signal (SCAN3) may be called a stabilizing scan signal.

[0099] FIG. 5 is a signal waveform diagram experimentally showing the change in driving current in a display device according to embodiments of the present disclosure, when there is no stabilization transistor in the subpixel circuit and when there is.

[0100] Referring to FIG. 5, a display device (100) according to embodiments of the present disclosure may connect the gate node (N1) and drain node (N3) of a driving transistor (DRT) constituting a subpixel circuit to a second switching transistor (T2). At this time, the second switching transistor (T2) may be formed with a dual gate structure, and the common node (N2) of the second switching transistor (T2) may be in a floating state depending on the operation of the second switching transistor (T2).

[0101] At this time, if there is no sixth switching transistor (T6) to maintain the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the second switching transistor (T2) at the same potential, leakage current may flow to the gate node (N1) of the driving transistor (DRT) through the second switching transistor (T2) during the edge interval where the light emission signal (EM) transitions.

[0102] This leakage current causes the potential of the gate node (N1) of the driving transistor (DRT) to fluctuate, thereby causing the driving current (Id1) flowing through the light-emitting element (ED) to fluctuate, which can result in image defects caused by brightness deviation.

[0103] On the other hand, when a sixth switching transistor (T6) is arranged to maintain the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the second switching transistor (T2) at the same potential, the sixth switching transistor (T6) is turned on before the light emission period (P5) to maintain the gate node (N1) of the driving transistor (DRT) at the same potential as the common node (N2) of the second switching transistor (T2), thereby reducing the leakage current.

[0104] As a result, fluctuations in the potential of the gate node (N1) of the driving transistor (DRT) are reduced, and the driving current (Id2) flowing through the light-emitting element (ED) is maintained stably, thereby reducing brightness deviation and improving image quality.

[0105] Meanwhile, the subpixel circuit according to the embodiments of the present disclosure may also be applied to other structures.

[0106] FIG. 6 is a diagram illustrating the structure of another subpixel circuit as an example in a display device according to embodiments of the present disclosure.

[0107] Referring to FIG. 6, the subpixel circuit of the display device (100) according to embodiments of the present disclosure includes first to seventh switching transistors (T1-T7), a driving transistor (DRT), a storage capacitor (Cst), and a light-emitting element (ED).

[0108] A light-emitting device (ED) can be a self-luminous device capable of emitting light on its own, such as an organic light-emitting diode (OLED).

[0109] In a subpixel circuit according to embodiments of the present disclosure, the second to sixth switching transistors (T2-T6) and the driving transistor (DRT) may be P-type transistors. Additionally, the first switching transistor (T1) and the seventh switching transistor (T7) may be N-type transistors.

[0110] P-type transistors are relatively more reliable than N-type transistors. In the case of P-type transistors, since the drain node is electrically connected to a high-potential driving voltage (VDD), there is an advantage that the current flowing to the light-emitting element (ED) is not fluctuated by the storage capacitor (Cst). Therefore, it is easy to supply current stably.

[0111] For example, the fourth switching transistor (T4) and the sixth switching transistor (T6) can be connected to the anode electrode of the light-emitting element (ED). In this case, when the switching transistors (T4, T6) connected to the light-emitting element (ED) operate in the saturation region, a constant current can be supplied regardless of changes in the current and threshold voltage of the light-emitting element (ED), so reliability is relatively high.

[0112] In the structure of such subpixel circuits, the N-type transistors (T1, T7) may be oxide transistors formed using a semiconducting oxide (e.g., transistors having a channel formed from a semiconducting oxide such as indium, gallium, zinc oxide or IGZO), and the other P-type transistors (DRT, T2-T6) may be silicon transistors formed from a semiconductor such as silicon (e.g., transistors having a polysilicon channel formed using a low-temperature process referred to as LTPS or low-temperature polysilicon).

[0113] Since oxide transistors have the characteristic of having relatively lower leakage current than silicon transistors, when implementing a transistor using oxide transistors, it is possible to reduce image quality defects such as flicker by preventing current leakage from the gate node of the driving transistor (DRT).

[0114] Meanwhile, the remaining P-type transistors (DRT, T2-T6), excluding the first switching transistor (T1) and the seventh switching transistor (T7) which correspond to N-type transistors, can be made of low-temperature polysilicon.

[0115] The gate node of the first switching transistor (T1) receives the first scan signal (SCAN1). The drain node of the first switching transistor (T1) is connected to the gate node (N1) of the driving transistor (DRT). The source node of the first switching transistor (T1) is connected to the source node (N3) of the driving transistor (DRT).

[0116] The first switching transistor (T1) is turned on by the first scan signal (SCAN1) and controls the operation of the driving transistor (DRT) through the high-potential driving voltage (VDD) stored in the storage capacitor (Cst). The high-potential driving voltage (VDD) can have a value of 2V to 3V and can be at a level lower than the bias voltage (VOBS).

[0117] The first switching transistor (T1) can be made of an N-type MOS transistor to form an oxide transistor. Since the N-type MOS transistor uses electrons rather than holes as carriers, it has a faster mobility compared to the P-type MOS transistor, so the switching speed can also be faster.

[0118] The first switching transistor (T1) may have a dual-gate structure to suppress high-temperature leakage current. In this case, the common node (N2) of the first switching transistor (T1) with the dual-gate structure may be in a floating state depending on the operating state of the first switching transistor (T1). When the common node (N2) of the first switching transistor (T1) is in a floating state, the operation of the first switching transistor (T1) may become unstable.

[0119] Accordingly, a seventh switching transistor (T7) may be included so that the potential of the gate node (N1) of the driving transistor (DRT) can be stably maintained before the subpixel (SP) emits light.

[0120] The seventh switching transistor (T7) is turned on or off according to the fifth scan signal (SCAN5), and in the turned-on state, forms a current path between the common node (N2) of the first switching transistor (T1) and the gate node (N1) of the driving transistor (DRT). Accordingly, the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the first switching transistor (T1) are maintained at the same potential before the subpixel (SP) emits light. Therefore, the seventh switching transistor (T7) for maintaining the gate node (N1) of the driving transistor (DRT) at a stable potential can be called a stabilizing transistor, and the fifth scan signal (SCAN5) can be called a stabilizing scan signal.

[0121] At this time, in order to stabilize the common node (N2) of the first switching transistor (T1), a stabilization capacitor (Cs) may be connected between the common node (N2) of the first switching transistor (T1) and the driving voltage (VDD). However, this stabilization capacitor (Cs) may be omitted depending on the subpixel circuit.

[0122] The gate node of the second switching transistor (T2) receives the second scan signal (SCAN2). The source node of the second switching transistor (T2) can receive the data voltage (Vdata). The drain node of the second switching transistor (T2) is connected to the drain node (N5) of the driving transistor (DRT).

[0123] The second switching transistor (T2) is turned on by the second scan signal (SCAN2) and supplies the data voltage (Vdata) to the drain node (N5) of the driving transistor (DRT).

[0124] The gate node of the third switching transistor (T3) receives a light emission signal (EM). The source node of the third switching transistor (T3) receives a high potential driving voltage (VDD). The drain node of the third switching transistor (T3) is connected to the drain node (N5) of the driving transistor (DRT).

[0125] The third switching transistor (T3) is turned on by the light emission signal (EM) and supplies a high potential driving voltage (VDD) to the drain node (N5) of the driving transistor (DRT).

[0126] The gate node of the fourth switching transistor (T4) receives a light emission signal (EM). The drain node of the fourth switching transistor (T4) is connected to the drain node (N3) of the driving transistor (DRT). The source node of the fourth switching transistor (T4) is connected to the anode electrode (N4) of the light-emitting element (ED).

[0127] The fourth switching transistor (T4) is turned on by the light emission signal (EM) and supplies a driving current to the anode electrode (N4) of the light-emitting element (ED).

[0128] The gate node of the fifth switching transistor (T5) receives the third scan signal (SCAN3).

[0129] The source node of the fifth switching transistor (T5) is supplied with a bias voltage (VOBS). The bias voltage (VOBS) can have a value between 5.5V and 7V and can be a level higher than the high potential driving voltage (VDD). The drain node of the fifth switching transistor (T5) is connected to the drain node (N3) of the transistor (DRT).

[0130] The fifth switching transistor (T5) is turned on by the third scan signal (SCAN3) and supplies a bias voltage (VOBS) to the drain node (N3) of the driving transistor (DRT).

[0131] The gate node of the 6th switching transistor (T6) receives the 4th scan signal (SCAN4).

[0132] Here, the fourth scan signal (SCAN4) may be the third scan signal (SCAN3) supplied to a subpixel (SP) at a different location. For example, if the third scan signal (SCAN3) is applied to the n-th gate line (GL), the fourth scan signal (SCAN4) may be the third scan signal (SCAN3) applied to the n+1-th gate line (GL). That is, the fourth scan signal (SCAN4) may use the third scan signal (SCAN3) which changes the gate line (GL) according to the phase in which the display panel (110) is driven.

[0133] The source node of the 6th switching transistor (T6) is supplied with a reset voltage (VAR). The drain node of the 6th switching transistor (T6) is connected to the anode electrode (N4) of the light-emitting element (ED).

[0134] The 6th switching transistor (T6) is turned on by the 4th scan signal (SCAN4) and supplies a reset voltage (VAR) to the anode electrode (N4) of the light-emitting element (ED).

[0135] The gate node (N1) of the driving transistor (DRT) is connected to the drain node of the first switching transistor (T1). The source node (N5) of the driving transistor (DRT) is connected to the drain node of the second switching transistor (T2). The drain node (N3) of the driving transistor (DRT) is connected to the source node of the first switching transistor (T1).

[0136] The driving transistor (DRT) is turned on by the voltage difference between the source node and the drain node of the first switching transistor (T1), and accordingly, a driving current (Id) is applied to the light-emitting element (ED).

[0137] One side of the storage capacitor (Cst) is to which a high potential driving voltage (VDD) is applied, and the other side is connected to the gate node (N1) of the driving transistor (DRT). The storage capacitor (Cst) stores the voltage of the gate node (N1) of the driving transistor (DRT).

[0138] The anode electrode (N4) of the light-emitting element (ED) is connected to the source node of the fourth switching transistor (T4) and the drain node of the sixth switching transistor (T6). A low-potential base voltage (VSS) is applied to the cathode electrode (N4) of the light-emitting element (ED).

[0139] The light-emitting element (ED) emits light with a predetermined brightness by the driving current (Id) flowing through the driving transistor (DRT).

[0140] At this time, the reset voltage (VAR) is supplied to reset the anode electrode (N4) of the light-emitting element (ED).

[0141] When a fourth switching transistor (T4), located between the anode electrode (N4) of the light-emitting element (ED) and the driving transistor (DRT), is turned off by a light-emitting signal (EM), and a reset voltage (VAR) is supplied to the anode electrode (N4) of the light-emitting element (ED), the anode electrode (N4) of the light-emitting element (ED) can be reset.

[0142] In order for the driving operation of the driving transistor (DRT) and the operation of resetting the anode electrode (N4) of the light-emitting element (ED) to be performed separately, the third scan signal (SCAN3) for driving the driving transistor (DRT) or applying a bias voltage (VOBS) and the fourth scan signal (SCAN4) for controlling the supply of a reset voltage (VAR) to the anode electrode (N4) of the light-emitting element (ED) may have different phases.

[0143] At this time, when turning on the switching transistors (T5, T6) that supply the bias voltage (VOBS) and reset voltage (VAR), the fourth switching transistor (T4) connecting the drain node (N3) of the driving transistor (DRT) and the anode electrode (N4) of the light-emitting element (ED) is turned off, thereby blocking the driving current (Id) of the driving transistor (DRT) from flowing to the anode electrode (N4) of the light-emitting element (ED) and ensuring that there is no influence from voltages other than the reset voltage (VAR).

[0144] In this way, a subpixel circuit consisting of 8 transistors (DRT, T1-T7) and 2 capacitors (Cst, Cs) can be called an 8T2C structure. In this case, if the stabilization capacitor (Cs) is not formed, it will be an 8T1C structure.

[0145] Here, among various subpixel circuit structures, the 8T2C structure is shown as an example, and the structure and number of transistors and capacitors constituting the subpixel circuit may vary. Meanwhile, each of the multiple subpixels (SP) may have the same structure, and some of the multiple subpixels (SP) may have different structures.

[0146] FIG. 7 is a signal waveform diagram showing the operation of another subpixel circuit in a display device according to embodiments of the present disclosure.

[0147] Referring to FIG. 7, a display device (100) according to embodiments of the present disclosure may display an image by a data voltage (Vdata) during a light-emitting period. On the other hand, a bias voltage (VOBS) and a reset voltage (VAR) may be applied during a non-light-emitting period, and a sampling process that compensates for a characteristic value (threshold voltage or mobility) of a driving transistor (DRT) may be performed.

[0148] For example, when the first switching transistor (T1) is turned on by the first scan signal (SCAN1) and the gate node (N1) and drain node (N3) of the driving transistor (DRT) are electrically connected, the gate node (N1) and drain node (N3) of the driving transistor (DRT) have substantially equal potentials.

[0149] At this time, when the second switching transistor (T2) is turned on by the second scan signal (SCAN2) and the data voltage (Vdata) is supplied, a current path is formed until the voltage difference between the gate node (N1) and the drain node (N3) of the driving transistor (DRT) reaches the threshold voltage of the driving transistor (DRT). Accordingly, the voltages of the gate node (N1) and the drain node (N3) of the driving transistor (DRT) are charged.

[0150] That is, when a data voltage (Vdata) is supplied to the source node (N5) of the driving transistor (DRT), the voltages of the gate node (N1) and drain node (N3) of the driving transistor (DRT) rise to the difference voltage between the data voltage (Vdata) and the threshold voltage. As a result, the threshold voltage of the driving transistor (DRT) can be compensated.

[0151] In this way, the process of compensating for the characteristic value of the driving transistor (DRT) through the sampling process can correspond to internal compensation.

[0152] Meanwhile, a bias voltage (VOBS) may be applied to mitigate hysteresis effects that may occur in the driving transistor (DRT) and to improve response characteristics.

[0153] For example, the driving transistor (DRT) can be in an on-bias state where a peak white grayscale voltage is applied to the gate node (N1) and a large current flows between the drain node (N3) and the source node (N5) of the driving transistor (DRT).

[0154] On the other hand, the driving transistor (DRT) can be in an off-bio state where almost no current flows between the drain node (N3) and the source node (N5) of the driving transistor (DRT) when a peak black grayscale voltage is applied to the gate node (N1).

[0155] The peak white gradation voltage refers to the voltage applied to the gate node (N1) of the driving transistor (DRT) so that the light-emitting element (ED) emits light in the peak white gradation, and the peak black gradation voltage refers to the voltage applied to the gate node (N1) of the driving transistor (DRT) so that the light-emitting element (ED) emits light in the peak black gradation. For example, if the gradation value is expressed as an 8-bit digital value, the peak black gradation may mean the minimum value "0", and the peak white gradation may mean the maximum value "255".

[0156] At this time, since the sweep curves of the on-bias state and the off-bias state of the P-type driving transistor (DRT) are not identical, a difference in the current flowing between the drain node (N3) and the source node (N5) of the driving transistor (DRT) may appear in the same gradation.

[0157] At this time, the phenomenon in which the current characteristics flowing between the drain node (N3) and the source node (N5) of the driving transistor (DRT) differ between the on-bias state and the off-bias state due to the voltage difference between the gate node (N1) and the drain node (N3) of the driving transistor (DRT) in the Gray representation is called hysteresis, and this can be the cause of afterimages.

[0158] In addition, the difference in driving current (Id) flowing through the drain node (N3) and source node (N5) of the driving transistor (DRT) may not stabilize the driving characteristics of the light-emitting element (ED) and may cause a difference in brightness.

[0159] In particular, when the display device (100) is driven at a high-speed driving frequency and then changes to a low-speed driving frequency, an afterimage due to hysteresis can be easily seen.

[0160] Accordingly, in order to minimize the visibility of afterimages caused by hysteresis, one or more bias sections (OBS1, OBS2) may be performed to set the driving transistor (DRT) to an on-bias state before the emission period by the low-level emission signal (EM) begins.

[0161] To do this, the driving transistor (DRT) can be set to an on-bias state by applying a bias voltage (VOBS) to the drain node (N3) of the driving transistor (DRT) before the light-emitting period begins.

[0162] For example, a bias voltage (VOBS) can be applied to the drain node (N3) of the driving transistor (DRT) before the light emission period begins.

[0163] Meanwhile, since flicker may occur when the operating time at a low driving frequency is prolonged, the anode electrode (N4) of the light-emitting element (ED) can be reset to a certain level of resen voltage (VAR).

[0164] In this subpixel circuit, the common node (N2) of the first switching transistor (T1), which is composed of a dual-gate structure, can be in a floating state depending on the operating state of the first switching transistor (T1).

[0165] When the common node (N2) of the first switching transistor (T1) becomes floating, leakage current may flow from the drain node (N3) of the stabilization capacitor (Cs) or the driving transistor (DRT) through the first switching transistor (T1) to the gate node (N1) of the driving transistor (DRT). This leakage current may cause the potential of the gate node (N1) of the driving transistor (DRT) to fluctuate, which can cause image defects due to brightness deviation.

[0166] To reduce such leakage current, the seventh switching transistor (T7) can be turned on by a high-level fifth scan signal (SCAN5) before the light emission period proceeds by a low-level light emission signal (EM). Accordingly, the gate node (N1) of the driving transistor (DRT) maintains the same potential as the common node (N2) of the first switching transistor (T1). As a result, even if the common node (N2) of the first switching transistor (T1) becomes floating and leakage current flows, the gate node (N1) of the driving transistor (DRT) remains stable, thereby reducing brightness deviation and improving image quality.

[0167] The embodiments of the present disclosure described above are briefly explained as follows.

[0168] A display device (100) according to embodiments of the present disclosure comprises: a display panel (110) comprising a light-emitting element (ED), a driving transistor (DRT) that provides a driving current (Id) to the light-emitting element (ED) using a driving voltage (VDD), and a plurality of subpixel circuits having a plurality of switching transistors that control the driving of the driving transistor (DRT); a gate driving circuit (120) that supplies a light-emitting signal (EM) and a plurality of scan signals (SCAN) to the display panel (110); a data driving circuit (130) that supplies a data voltage (Vdata) to the display panel (110); and a timing controller (140) that controls the gate driving circuit (120) and the data driving circuit (130), wherein the plurality of switching transistors are controlled by a first scan signal (SCAN1), and a first switching transistor (T1) having a dual gate structure that connects the gate node (N1) and the drain node (N3) of the driving transistor (DRT), and is controlled by a stabilization scan signal. It may include a stabilization transistor connecting the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the first switching transistor (T1).

[0169] The plurality of switching transistors may further include a second switching transistor (T2) that is controlled by a second scan signal (SCAN2) and connects a data line (DL) and a storage capacitor (Cst); a third switching transistor (T3) that is controlled by the light emission signal (EM) and connects between the drain node of the second switching transistor (T2) and a reference voltage line (RVL); a fourth switching transistor (T4) that is controlled by the light emission signal (EM) and connects between the drain node (N3) of the driving transistor (DRT) and the anode electrode (N4) of the light-emitting element (ED); and a fifth switching transistor (T5) that is controlled by the first scan signal (SCAN1) and connects between the reference voltage line (RVL) and the anode electrode (N4) of the light-emitting element (ED).

[0170] The plurality of subpixel circuits above may further include a stabilization capacitor (Cs) connecting the common node (N2) of the first switching transistor (T1) and the driving voltage (VDD).

[0171] The above stabilization transistor is turned on before the light emission period, so that the gate node (N1) of the driving transistor (DRT) and the common node (T2) of the first switching transistor (T1) can be maintained at the same potential.

[0172] The first switching transistor (T1) and the stabilization transistor may be P-type transistors.

[0173] The plurality of switching transistors may further include a second switching transistor (T2) controlled by a second scan signal (SCAN2) and connected between a data voltage and a source node of the driving transistor (DRT); a third switching transistor (T3) controlled by the light emission signal (EM) and connected between a driving voltage (VDD) and a source node of the driving transistor (DRT); a fourth switching transistor (T4) controlled by the light emission signal (EM) and connected between a drain node (N3) of the driving transistor (DRT) and an anode electrode (N4) of the light-emitting element (ED); a fifth switching transistor (T5) controlled by a third scan signal (SCAN3) and connected between a bias voltage (VOBS) and a drain node (N3) of the driving transistor (DRT); and a sixth switching transistor (T6) controlled by a fourth scan signal (SCAN4) and connected between a reset voltage (VAR) and an anode electrode (N4) of the light-emitting element (ED). there is.

[0174] The first switching transistor (T1) and the stabilization transistor may be N-type transistors.

[0175] Additionally, a display panel (110) according to embodiments of the present disclosure comprises a light-emitting element (ED), a driving transistor (DRT) that provides a driving current (Id) to the light-emitting element (ED) using a driving voltage (VDD), a plurality of subpixels (SP) in which a plurality of switching transistors are arranged to control the driving of the driving transistor (DRT), a plurality of data lines (DL) that supply a data voltage (Vdata) to the plurality of subpixels (SP), and a plurality of gate lines (GL) that supply a light-emitting signal (EM) and a plurality of scan signals (SCAN) to the plurality of subpixels (SP), wherein the plurality of switching transistors may include a first switching transistor (T1) having a dual-gate structure that is controlled by a first scan signal (SCAN1) and connects a gate node (N1) and a drain node (N3) of the driving transistor (DRT), and a stabilization transistor that is controlled by a stabilization scan signal and connects a gate node (N1) of the driving transistor (DRT) and a common node (N2) of the first switching transistor (T1). there is.

[0176] Additionally, a subpixel circuit according to embodiments of the present disclosure may include a light-emitting element (ED), a driving transistor (DRT) that provides a driving current (Id) to the light-emitting element (ED) using a driving voltage (VDD), and a plurality of switching transistors that control the driving of the driving transistor (DRT), wherein the plurality of switching transistors may include a first switching transistor (T1) having a dual-gate structure that is controlled by a first scan signal (SCAN1) and connects the gate node (N1) and the drain node (N3) of the driving transistor (DRT), and a stabilization transistor that is controlled by a stabilization scan signal and connects the gate node (N1) of the driving transistor (DRT) and the common node (N2) of the first switching transistor (T1).

[0177] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and thus the scope of the technical concept of the present invention is not limited by these embodiments. Explanation of the symbols

[0179] 100: Display device 110: Display panel 120: Gate driving circuit 130: Data driving circuit 140: Timing Controller 150: Power management circuit 160: Main Power Management Circuit 170: Set Board 200: Host System

Claims

Claim 1 A display device comprising: a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a plurality of subpixel circuits having a plurality of switching transistors arranged therein to control the driving of the driving transistor; a gate driving circuit that supplies a light-emitting signal and a plurality of scan signals to the display panel; a data driving circuit that supplies a data voltage to the display panel; and a timing controller that controls the gate driving circuit and the data driving circuit, wherein the plurality of switching transistors are controlled by a first scan signal and are formed in a dual-gate structure in which two transistors are serially connected through a common node, and a first switching transistor that connects the gate node and the drain node of the driving transistor; and a stabilizing transistor that is controlled by a stabilizing scan signal and connects the gate node of the driving transistor and the common node of the first switching transistor. Claim 2 A display device according to claim 1, further comprising: a second switching transistor that is controlled by a second scan signal and connects a data line and a storage capacitor; a third switching transistor that is controlled by the light emission signal and connects between the drain node of the second switching transistor and a reference voltage line; a fourth switching transistor that is controlled by the light emission signal and connects between the drain node of the driving transistor and the anode electrode of the light-emitting element; and a fifth switching transistor that is controlled by the first scan signal and connects between the reference voltage line and the anode electrode of the light-emitting element. Claim 3 A display device according to claim 1, further comprising a stabilization capacitor connecting the common node of the first switching transistor and the driving voltage. Claim 4 A display device according to claim 1, wherein the stabilization transistor is turned on prior to the light emission period to maintain the gate node of the driving transistor and the common node of the first switching transistor at the same potential. Claim 5 In claim 2, the display device wherein the first switching transistor and the stabilization transistor are P-type transistors. Claim 6 A display device according to claim 1, further comprising: a second switching transistor controlled by a second scan signal and connected between a data voltage and a source node of the driving transistor; a third switching transistor controlled by the light emission signal and connected between the driving voltage and a source node of the driving transistor; a fourth switching transistor controlled by the light emission signal and connected between the drain node of the driving transistor and an anode electrode of the light-emitting element; a fifth switching transistor controlled by the third scan signal and connected between a bias voltage and a drain node of the driving transistor; and a sixth switching transistor controlled by the fourth scan signal and connected between a reset voltage and an anode electrode of the light-emitting element. Claim 7 In claim 6, the display device wherein the first switching transistor and the stabilization transistor are N-type transistors. Claim 8 A display panel comprising: a plurality of subpixels arranged with a light-emitting element, a driving transistor that provides a driving current to the light-emitting element using a driving voltage, and a plurality of switching transistors that control the driving of the driving transistor; a plurality of data lines that supply a data voltage to the plurality of subpixels; and a plurality of gate lines that supply a light-emitting signal and a plurality of scan signals to the plurality of subpixels, wherein the plurality of switching transistors are controlled by a first scan signal and are formed in a dual-gate structure in which two transistors are serially connected through a common node, thereby connecting the gate node and drain node of the driving transistor; and a stabilization transistor that is controlled by a stabilization scan signal and connects the gate node of the driving transistor and the common node of the first switching transistor. Claim 9 In claim 8, the plurality of switching transistors further comprises: a second switching transistor controlled by a second scan signal and connecting a data voltage and a storage capacitor; a third switching transistor controlled by the light emission signal and connected between a drain node of the second switching transistor and a reference voltage line; a fourth switching transistor controlled by the light emission signal and connected between a drain node of the driving transistor and an anode electrode of the light-emitting element; and a fifth switching transistor controlled by the first scan signal and connected between a reference voltage line and an anode electrode of the light-emitting element. Claim 10 In claim 8, a display panel further comprising a stabilization capacitor connecting the common node of the first switching transistor and the driving voltage. Claim 11 In claim 8, the stabilization transistor is turned on prior to the light emission period, thereby maintaining the gate node of the driving transistor and the common node of the first switching transistor at the same potential in a display panel. Claim 12 In claim 9, the first switching transistor and the stabilization transistor are P-type transistors in the display panel. Claim 13 In claim 8, the plurality of switching transistors further comprises: a second switching transistor controlled by a second scan signal and connected between a data voltage and a source node of the driving transistor; a third switching transistor controlled by the light emission signal and connected between a driving voltage and a source node of the driving transistor; a fourth switching transistor controlled by the light emission signal and connected between a drain node of the driving transistor and an anode electrode of the light-emitting element; a fifth switching transistor controlled by a third scan signal and connected between a bias voltage and a drain node of the driving transistor; and a sixth switching transistor controlled by a fourth scan signal and connected between a reset voltage and an anode electrode of the light-emitting element. Claim 14 In claim 13, the display panel wherein the first switching transistor and the stabilization transistor are N-type transistors. Claim 15 A subpixel circuit comprising: a light-emitting element; a driving transistor that provides a driving current to the light-emitting element using a driving voltage; and a plurality of switching transistors that control the driving of the driving transistors, wherein the plurality of switching transistors are controlled by a first scan signal and are formed in a dual-gate structure in which two transistors are connected in series through a common node, and a first switching transistor that connects the gate node and the drain node of the driving transistor; and a stabilizing transistor that is controlled by a stabilization scan signal and connects the gate node of the driving transistor and the common node of the first switching transistor. Claim 16 In claim 15, the plurality of switching transistors further comprises: a second switching transistor controlled by a second scan signal and connecting a data voltage and a storage capacitor; a third switching transistor controlled by a light emission signal and connected between a drain node of the second switching transistor and a reference voltage line; a fourth switching transistor controlled by the light emission signal and connected between a drain node of the driving transistor and an anode electrode of the light-emitting element; and a fifth switching transistor controlled by the first scan signal and connected between a reference voltage line and an anode electrode of the light-emitting element. Claim 17 In claim 15, a subpixel circuit further comprising a stabilization capacitor connecting the common node of the first switching transistor and the driving voltage. Claim 18 In claim 15, the stabilization transistor is turned on prior to the light emission period, and the subpixel circuit maintains the gate node of the driving transistor and the common node of the first switching transistor at the same potential. Claim 19 In claim 15, the plurality of switching transistors further comprises: a second switching transistor controlled by a second scan signal and connected between a data voltage and a source node of the driving transistor; a third switching transistor controlled by a light emission signal and connected between a driving voltage and a source node of the driving transistor; a fourth switching transistor controlled by the light emission signal and connected between a drain node of the driving transistor and an anode electrode of the light-emitting element; a fifth switching transistor controlled by a third scan signal and connected between a bias voltage and a drain node of the driving transistor; and a sixth switching transistor controlled by a fourth scan signal and connected between a reset voltage and an anode electrode of the light-emitting element.

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