Display panel

Abstract

The display panel of the present invention may include a first semiconductor pattern comprising either a silicon semiconductor or an oxide semiconductor and a first transistor comprising a first gate electrode that overlaps with the first semiconductor pattern in a plane, a second transistor comprising a second semiconductor pattern different from the first semiconductor pattern and a second gate electrode that overlaps with the second semiconductor pattern in a plane, a first upper electrode that overlaps with the first gate electrode in a plane, a first connecting electrode connected to the first semiconductor pattern by penetrating at least one insulating layer, and a light-emitting element disposed on the first connecting electrode. A single insulating layer may be disposed between the light-emitting element of the display panel and the first connecting electrode, and the first connecting electrode and the light-emitting element may be connected through a through hole penetrating the single insulating layer.

Description

Technology Field

[0001] The present invention relates to a display panel comprising a plurality of pixels. Background Technology

[0002] A display panel includes a plurality of pixels that display an image. Each pixel may include a pixel driving circuit and a display element connected to the pixel driving circuit. The pixel driving circuit may include at least one thin-film transistor and a capacitor. The thin-film transistor and capacitor constituting the pixel driving circuit can control the display element according to an electrical signal provided from the driving circuit. The problem to be solved

[0003] The present invention aims to provide a display panel that is manufactured through a simplified process and has improved electrical and display characteristics. means of solving the problem

[0004] One embodiment provides a display panel comprising: a first semiconductor pattern including either a silicon semiconductor or an oxide semiconductor; a first transistor including a first gate electrode that overlaps with the first semiconductor pattern in a plane; a second transistor including a second semiconductor pattern different from the first semiconductor pattern and a second gate electrode that overlaps with the second semiconductor pattern in a plane; a first upper electrode that overlaps with the first gate electrode in a plane; a first connecting electrode that is connected to the first semiconductor pattern by penetrating at least one insulating layer; and a light-emitting element disposed on the first connecting electrode, wherein a single insulating layer is disposed between the light-emitting element and the first connecting electrode, and the first connecting electrode and the light-emitting element are connected through a through hole penetrating the single insulating layer.

[0005] The first gate electrode comprises a plurality of layers, and the uppermost layer among the plurality of layers is titanium nitride (TiN xIt may include ).

[0006] The above at least one insulating layer may include a first insulating layer disposed between the first semiconductor pattern and the first gate electrode, and a second insulating layer disposed on the first gate electrode.

[0007] The first insulating layer can be placed between the second semiconductor pattern and the second gate electrode.

[0008] The above at least one insulating layer further includes a third insulating layer disposed on the second insulating layer, the second insulating layer disposed below the second semiconductor pattern, and the third insulating layer may be disposed between the second semiconductor pattern and the second gate electrode.

[0009] The second gate electrode may be disposed on the same layer as the first gate electrode.

[0010] The second gate electrode may be positioned above the first gate electrode.

[0011] The first upper electrode may be placed on the same layer as the first connecting electrode.

[0012] The first upper electrode may be placed on the same layer as the second gate electrode.

[0013] The first upper electrode can be disposed on the same layer as the second semiconductor pattern.

[0014] The above display panel further includes a second upper electrode that overlaps the first upper electrode on a plane, the first upper electrode is positioned between the first gate electrode and the second upper electrode, and the second upper electrode may be positioned on the same layer as the first connecting electrode.

[0015] The above display panel further includes a second connecting electrode connected to the second semiconductor pattern by penetrating the at least one insulating layer, and the second connecting electrode may be disposed on the same layer as the first connecting electrode.

[0016] The above display panel further includes a second connecting electrode connected to the second semiconductor pattern by penetrating the at least one insulating layer, and the second connecting electrode may be disposed on the same layer as the light-emitting element.

[0017] The above display panel further includes a blocking layer disposed on the same layer as the first gate electrode, and the blocking layer may overlap with the second semiconductor pattern on a plane.

[0018] The second semiconductor pattern is disposed between the blocking layer and the second gate electrode, and the blocking layer can be electrically connected to the second gate electrode.

[0019] It may further include a first signal line disposed on the same layer as the first gate electrode and containing the same material as the first gate electrode; and a second signal line disposed on the same layer as the first connecting electrode and containing the same material as the first connecting electrode.

[0020] One embodiment provides a display panel comprising: a first transistor including a silicon semiconductor pattern and a first gate electrode overlapping in a plane with the silicon semiconductor pattern; a second transistor including an oxide semiconductor pattern and a second gate electrode overlapping in a plane with the oxide semiconductor pattern; a first capacitor including a first electrode integrally connected to the first gate electrode and a second electrode overlapping to the first electrode; a first connecting electrode connected to the silicon semiconductor pattern; a second connecting electrode connected to the oxide semiconductor pattern; a first insulating layer disposed between the oxide semiconductor pattern and the second gate electrode; a second insulating layer disposed between the first electrode and the second electrode; a third insulating layer disposed on the first connecting electrode; and a pixel electrode connected to the first connecting electrode through a first contact hole penetrating the third insulating layer, wherein the second connecting electrode is disposed on the same layer as the pixel electrode and is connected to the oxide semiconductor through a second contact hole penetrating the first to third insulating layers.

[0021] One embodiment provides a display panel comprising: a first transistor including a silicon semiconductor pattern and a first gate electrode overlapping in a plane with the silicon semiconductor pattern; a second transistor including an oxide semiconductor pattern and a second gate electrode overlapping in a plane with the oxide semiconductor pattern; a connecting electrode connected to the silicon semiconductor pattern; a first upper electrode forming a capacitor with the first gate electrode; a second upper electrode forming a capacitor with the first upper electrode; a first insulating layer disposed between the silicon semiconductor pattern and the first gate electrode; a second insulating layer disposed between the first gate electrode and the first upper electrode; a third insulating layer disposed between the oxide semiconductor pattern and the second upper electrode; and a fourth insulating layer disposed between the first upper electrode and the second upper electrode, wherein the connecting electrode is disposed on the same layer as the second upper electrode.

[0022] The first upper electrode is disposed on the same layer as the second gate electrode, and the third insulating layer can overlap with the first upper electrode in a plane.

[0023] The first upper electrode is disposed on the same layer as the oxide semiconductor pattern, and the third insulating layer can be non-overlapping with the first upper electrode in a planar manner. Effects of the invention

[0024] The present invention can simplify the display panel process steps and reduce costs by reducing the number of masks required to form a plurality of transistors and capacitors including different semiconductor patterns.

[0025] The present invention is manufactured using a simplified process, and at the same time, the capacitor capacity can be increased and the pixel driving speed can be improved, thereby enhancing electrical characteristics and display characteristics. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram of a display panel according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are equivalent circuit diagrams of a pixel according to one embodiment of the present invention. FIGS. 3a and FIGS. 3b are cross-sectional views of a display panel according to one embodiment of the present invention. FIGS. 4a and 4b are cross-sectional views of a display panel according to one embodiment of the present invention. FIGS. 5a to 5p are cross-sectional views corresponding to the manufacturing steps of a display panel according to one embodiment of the present invention. FIGS. 6a to 6m are cross-sectional views corresponding to the manufacturing steps of a display panel according to one embodiment of the present invention. Specific details for implementing the invention

[0027] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0028] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0029] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0030] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0031] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0032] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0034] Hereinafter, a pixel and a display panel according to an embodiment of the present invention will be described with reference to the drawings.

[0035] FIG. 1 is a block diagram of a display device according to one embodiment. The display device (DD) may be a device that is activated by an electrical signal and displays an image. For example, the display device (DD) may be included in large devices such as televisions and external billboards, as well as in small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. Meanwhile, the embodiments of the display device (DD) are exemplary and are not limited to any one of them as long as they do not deviate from the concept of the present invention.

[0036] The display device (DD) may include a timing control unit (TC), a scanning driver (SDC), a data driver (DDC), and a display panel (DP). At least one of the timing control unit (TC), the scanning driver (SDC), and the data driver (DDC) may be provided in the form of a driver chip or formed directly on the display panel (DP).

[0037] The timing control unit (TC) receives input video signals and can generate video data (D-RGB) by converting the data format of the input video signals to match the interface specifications with the scanning drive unit (SDC). The timing control unit (TC) can output video data (D-RGB) and various control signals (DCS, SCS).

[0038] The scanning drive unit (SDC) can receive a scanning control signal (SCS) from the timing control unit (TC). The scanning control signal (SCS) may include a vertical start signal that initiates the operation of the scanning drive unit (SDC), a clock signal that determines the timing of the output of signals, etc.

[0039] The scanning driver (SDC) can generate a plurality of scan signals and sequentially output the scan signals to corresponding signal lines (SL1 to SLn, GL1 to GLn, HL1 to HLn). Additionally, the scanning driver (SDC) can generate a plurality of light emission control signals in response to a scanning control signal (SCS) and output the light emission control signals to corresponding light emission lines (EL1 to ELn).

[0040] Although FIG. 1 illustrates that a plurality of scan signals and a plurality of light emission control signals are output from a single scanning drive unit (SDC), the embodiment is not limited thereto. For example, a plurality of scanning drive circuits may be provided to divide and output scan signals and divide and output light emission control signals. In addition, in one embodiment, the driving circuit that generates and outputs scan signals and the driving circuit that generates and outputs light emission control signals may be distinguished separately.

[0041] The data driver (DDC) can receive a data control signal (DCS) and image data (D-RGB) from the timing control unit (TC). The data driver (DDC) can convert the image data (D-RGB) into data signals and output the data signals to a plurality of data lines (DL1 to DLm). The data signals may be analog voltages corresponding to the grayscale values ​​of the image data (D-RGB).

[0042] A display panel (DP) may include a plurality of groups of signal lines. When any one of the plurality of groups of signal lines is defined as a first signal line, another may be defined as a second signal line, and yet another may be defined as a third signal line. Hereinafter, names of the signal lines are defined to distinguish the plurality of groups of signal lines.

[0043] A plurality of groups of signal lines may include first group scanning lines (SL1 to SLn), second group scanning lines (GL1 to GLn), third group scanning lines (HL1 to HLn), light emission lines (EL1 to ELn), data lines (DL1 to DLm), first voltage line (PL), second voltage line (VL1), and third voltage line (VL2). The first group scanning lines (SL1 to SLn), second group scanning lines (GL1 to GLn), third group scanning lines (HL1 to HLn), and light emission lines (EL1 to ELn) may be extended in a first direction (DR1) and arranged in a second direction (DR2) that intersects the first direction (DR1). Multiple data lines (DL1 to DLm) may intersect insulatedly with the first group of scanning lines (SL1 to SLn), the second group of scanning lines (GL1 to GLn), the third group of scanning lines (HL1 to HLn), and the light emission lines (EL1 to ELn).

[0044] Each of the first voltage line (PL), the second voltage line (VL1), and the third voltage line (VL2) may include at least one of a line extended in the first direction (DR1) and a line extended in the second direction (DR2). The structure and shape of the first voltage line (PL), the second voltage line (VL1), and the third voltage line (VL2) may be designed independently of each other.

[0045] Each of the plurality of pixels (PX) may be electrically connected to a corresponding signal line among the aforementioned signal lines. Each of the plurality of pixels (PX) may be connected to a corresponding scanning line among the first to third groups of scanning lines (SL1 to SLn, GL1 to GLn, HL1 to HLn), a corresponding light-emitting line among the light-emitting lines (EL1 to ELn), and a corresponding data line among the data lines (DL1 to DLm). Depending on the configuration of the driving circuit of the pixels (PX), the connection relationship between the pixels (PX) and the signal lines may be changed.

[0046] Pixels (PX) are connected to a first voltage line (PL) and can receive a first power supply voltage (ELVDD) applied to the first voltage line (PL). Pixels (PX) can receive a second power supply voltage (ELVSS), and the second power supply voltage (ELVSS) may have a lower level than the first power supply voltage (ELVDD).

[0047] Pixels (PX) are connected to a second voltage line (VL1) and can receive a first initialization voltage (Vint) applied to the second voltage line (VL1). Pixels (PX) are connected to a third voltage line (VL2) and can receive a second initialization voltage (VAint) applied to the third voltage line (VL2). Each of the first initialization voltage (Vint) and the second initialization voltage (VAint) may have a level lower than the first power supply voltage (ELVDD). The first initialization voltage (Vint) and the second initialization voltage (VAint) may be bias voltages having a constant level. The first initialization voltage (Vint) and the second initialization voltage (VAint) may have different levels. For example, the second initialization voltage (VAint) may have a lower voltage than the first initialization voltage (Vint).

[0048] A display panel (DP) can display an image according to an electrical signal. Each pixel (PX) constituting the display panel (DP) may include an organic light-emitting diode and a pixel driving circuit that controls the light emission of the organic light-emitting diode. The pixel driving circuit may include a plurality of thin-film transistors and at least one capacitor. At least one of the scanning driving unit (SDC) and the data driving unit (DDC) may include thin-film transistors formed through the same process as the pixel driving circuit.

[0049] Pixels (PX) can receive data voltages in response to scan signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals. The light emission time of the pixels (PX) can be controlled by the light emission signals. Accordingly, the display panel (DP) can output an image through the pixels (PX).

[0050] Pixels (PX) may include multiple groups that generate light of different colors. For example, the multiple pixels (PX) may include red pixels that generate red light, green pixels that generate green light, and blue pixels that generate blue light. The light-emitting elements of the red pixels, the light-emitting elements of the green pixels, and the light-emitting elements of the blue pixels may include light-emitting layers formed of different materials. However, the embodiments are not necessarily limited thereto.

[0051] In this embodiment, the first group of scanning lines (SL1 to SLn), the second group of scanning lines (GL1 to GLn), the third group of scanning lines (HL1 to HLn), the light-emitting lines (EL1 to ELn), the data lines (DL1 to DLm), the first voltage line (PL), the second voltage line (VL1), the third voltage line (VL2), the pixels (PX), the scanning driver (SDC), and the data driver (DDC) may be formed through a plurality of photolithography processes on a single base substrate to be described later. However, this is described as an example, and the scanning driver (SDC) or the data driver (DDC) may be mounted on a separate circuit board or the like and electrically connected to a display panel (DP) through an attachment process.

[0052] FIGS. 2A and 2B are equivalent circuit diagrams of a pixel according to one embodiment. FIGS. 2A and 2B respectively illustrate an exemplary pixel (PXij) connected to the i-th scan line (SLi) of the first group of scan lines (SL1 to SLn) and connected to the j-th data line (DLj) of the plurality of data lines (DL1 to DLm). Here, i and j represent natural numbers.

[0053] A pixel (PXij) may include a light-emitting element (OLED), a plurality of transistors, and at least one capacitor. The transistors and at least one capacitor can control the amount of current flowing through the light-emitting element (OLED). The light-emitting element (OLED) can generate light having a predetermined brightness according to the amount of current provided. Depending on the configuration of the equivalent circuit diagram of the pixel (PXij), the number and connection type of transistors and capacitors included in the pixel (PXij) may vary.

[0054] Referring to FIG. 2a, the driving circuit of a pixel (PXij) of one embodiment may include a light-emitting element (OLED), first to seventh transistors (T1 to T7), and first and second capacitors (CAP1, CAP2).

[0055] The first transistor (T1), the second transistor (T2), and the fifth transistor (T5) to the seventh transistor (T7) are P-type transistors, and the third transistor (T3) and the fourth transistor (T4) may be N-type transistors. However, not limited thereto, the first to seventh transistors (T1 to T7) may be implemented as either P-type transistors or N-type transistors.

[0056] In the following, the input region (or input electrode) of an N-type transistor is described as a drain (or drain region), the input region of a P-type transistor is described as a source (or source region), the output region (or output electrode) of an N-type transistor is described as a source (or source region), and the output region of a P-type transistor is described as a drain (or drain region). Meanwhile, at least one of the first to seventh transistors (T1 to T7) may be omitted.

[0057] The first transistor (T1) may be defined as a driving transistor, and the second transistor (T2) may be defined as a switching transistor. The first capacitor (CAP1) may be electrically connected between the gate of the first transistor (T1) and a first voltage line (PL) that receives a first power supply voltage (ELVDD). The second capacitor (CAP2) may be electrically connected between the first capacitor (CAP1) and the second transistor (T2). The gate of the first transistor (T1), the first capacitor (CAP1), and the second capacitor (CAP2) may each be connected to a reference node. The first transistor (T1) may be electrically connected between the first voltage line (PL) and one electrode (e.g., an anode (AE)) of a light-emitting element (OLED). In this specification, "electrically connected between a transistor and a signal line or between a transistor and a transistor" means that "the source, drain, and gate of the transistor have an integral shape with the signal line or are connected through a connecting electrode."

[0058] The source of the first transistor (T1) may be electrically connected to the first voltage line (PL). Another transistor may be placed or omitted between the source of the first transistor (T1) and the first voltage line (PL). The drain of the first transistor (T1) may be electrically connected to the anode (AE) of the light-emitting element (OLED). Another transistor may be placed or omitted between the drain of the first transistor (T1) and the anode (AE) of the light-emitting element (OLED). The gate of the first transistor (T1) may be electrically connected to a reference node. The first transistor (T1) can control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the reference node applied to the gate of the first transistor (T1).

[0059] The second transistor (T2) can be electrically connected between the j-th data line (DLj) and the source of the first transistor (T1). The source of the second transistor (T2) is electrically connected to the j-th data line (DLj), and the drain of the second transistor (T2) is electrically connected to the source of the first transistor (T1). The gate of the second transistor (T2) can be electrically connected to the i-th scan line (SLi) of the first group.

[0060] The second transistor (T2) can be turned on by the i-th write scan signal (GWSi) applied through the i-th scan line (SLi) of the first group to electrically connect the source of the first transistor (T1) to the data line (DLj). The second transistor (T2) can perform a switching operation to provide the data voltage (Vd) applied through the data line (DLj) to the source of the first transistor (T1).

[0061] The third transistor (T3) may be electrically connected between the reference node and the drain of the first transistor (T1). The drain of the third transistor (T3) may be electrically connected to the drain of the first transistor (T1), and the source of the third transistor (T3) may be electrically connected to the reference node. The gate of the third transistor (T3) may be electrically connected to the i-th scan line (GLi) of the second group. Meanwhile, although the third transistor (T3) is illustrated as having one gate, the embodiment is not limited thereto, and the third transistor (T3) may have multiple gates.

[0062] The third transistor (T3) can be defined as a compensation transistor. The third transistor (T3) can be turned on by the i-th compensation scan signal (GCSi) applied through the i-th scan line (GLi) of the second group to electrically connect the drain of the first transistor (T1) and the gate of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in the form of a diode.

[0063] The fourth transistor (T4) may be electrically connected between the reference node and the second voltage line (VL1). The drain of the fourth transistor (T4) may be electrically connected to the reference node, and the source of the fourth transistor (T4) may be electrically connected to the second voltage line (VL1). The gate of the fourth transistor (T4) may be electrically connected to the i-th scan line (HLi) of the third group. Meanwhile, although the fourth transistor (T4) is illustrated as having one gate, the embodiment is not limited thereto, and the fourth transistor (T4) may have multiple gates.

[0064] The fourth transistor (T4) can be defined as an initialization transistor. The fourth transistor (T4) can be turned on by the i-th initialization scan signal (GISi) applied through the i-th scan line (HLi) of the third group and provide the first initialization voltage (Vint1) applied through the second voltage line (VL1) as a reference node.

[0065] The fifth transistor (T5) can be electrically connected between the first voltage line (PL) and the source of the first transistor (T1). The source of the fifth transistor (T5) can be electrically connected to the first voltage line (PL), and the drain of the fifth transistor (T5) can be electrically connected to the source of the first transistor (T1). The gate of the fifth transistor (T5) can be electrically connected to the i-th light-emitting line (ELi).

[0066] The sixth transistor (T6) can be electrically connected between the drain of the first transistor (T1) and the light-emitting element (OLED). The source of the sixth transistor (T6) can be electrically connected to the drain of the first transistor (T1), and the drain of the sixth transistor (T6) can be electrically connected to the anode (AE) of the light-emitting element (OLED). The gate of the sixth transistor (T6) can be electrically connected to the i-th light-emitting line (ELi). Meanwhile, not limited thereto, the gate of the sixth transistor (T6) may be connected to a signal line different from the gate of the fifth transistor (T5).

[0067] The fifth transistor (T5) and the sixth transistor (T6) can be defined as light-emitting control transistors. The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the i-th light-emitting signal (ESi) applied through the i-th light-emitting line (ELi). By turning on the fifth transistor (T5) and the sixth transistor (T6), a first voltage (ELVDD) is provided to the light-emitting element (OLED), so that a driving current can flow to the light-emitting element (OLED) and the light-emitting element (OLED) can emit light.

[0068] When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing through the first transistor (T1) can be determined according to the voltage stored in the plurality of capacitors (CAP1, CAP2). As the pixel (PXij) includes the plurality of capacitors (CAP1, CAP2), the capacitance of the pixel (PXij) can be expanded. Meanwhile, the embodiment is not limited thereto, and the second capacitor (CAP2) may be omitted.

[0069] The seventh transistor (T7) can be electrically connected between the drain of the sixth transistor (T6) and the third voltage line (VL2). The source of the seventh transistor (T7) is electrically connected to the drain of the sixth transistor (T6), and the drain of the seventh transistor (T7) is electrically connected to the third voltage line (VL2). The gate of the seventh transistor (T7) can be electrically connected to the i-1th scan line (SLi-1) of the first group. The i-1th write scan line (SLi-1) of the first group can be defined as the write scan line of the stage preceding the i-1th write scan line (SLi) of the first group.

[0070] The seventh transistor (T7) can be turned on by the i-1th write scan signal (GWSi-1) applied through the i-1th scan line (SLi-1) of the first group to provide the second initialization voltage (VAint) received through the third voltage line (VL2) to the anode (AE) of the light-emitting element (OLED). In an embodiment of the present invention, the second initialization voltage (VAint) may have the same level as the first initialization voltage (Vint1), but is not limited thereto and may have a different level from the first initialization voltage (Vint1).

[0071] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and accordingly, the black expression capability can be improved. Meanwhile, in another embodiment of the present invention, the seventh transistor (T7) may be omitted.

[0072] Referring to FIG. 2b, the driving circuit of a pixel (PXij) of one embodiment may include a light-emitting element (OLED), first to eleven transistors (T1 to T11), and first and second capacitors (CAP1, CAP2). The first to eleven transistors (T1 to T11) may be implemented as either P-type transistors or N-type transistors. Meanwhile, at least one of the first to eleven transistors (T1 to T11) may be omitted.

[0073] The driving circuit of the pixel (PXij) can be divided into a first circuit portion and a second circuit portion based on the first capacitor (CAP1). For example, the first circuit portion may be a portion connected to the first electrode of the first capacitor (CAP1), and the second circuit portion may be a portion connected to the second electrode of the first capacitor (CAP1). The second circuit portion may be connected to a light-emitting element (OLED).

[0074] The first capacitor (CAP1) can be electrically connected between the gate of the first transistor (T1) and the second capacitor (CAP2). The second capacitor (CAP2) can be electrically connected between the first voltage line (PL) receiving the first power supply voltage (ELVDD) and the first capacitor (CAP1). The first electrode of the second capacitor (CAP2) and the first electrode of the first capacitor (CAP1) can be connected to a first node, and the second electrode of the first capacitor (CAP1) and the gate of the first transistor (T1) can be connected to a second node.

[0075] The source of the first transistor (T1) can be electrically connected to the first voltage line (PL). The first transistor (T1) can be electrically connected to the first voltage line (PL) via the ninth transistor (T9). The drain of the first transistor (T1) can be electrically connected to the anode (AE) of the light-emitting element (OLED). The first transistor (T1) can be connected to the anode (AE) of the light-emitting element (OLED) via the sixth transistor (T6). The gate of the first transistor (T1) can be electrically connected to the second node.

[0076] The second transistor (T2) can be electrically connected between the source of the first transistor (T1) and the j-th data line (DLj). The source of the second transistor (T2) is electrically connected to the j-th data line (DLj), and the drain of the second transistor (T2) can be electrically connected to the tenth transistor (T10). The gate of the second transistor (T2) can be electrically connected to the i-th scan line (SLi) of the first group.

[0077] The third transistor (T3) can be electrically connected between the second node and the drain of the first transistor (T1). The source of the third transistor (T3) is electrically connected to the drain of the first transistor (T1), and the drain of the third transistor (T3) can be electrically connected to the second node via the eleventh transistor (T11). The gate of the third transistor (T3) can be electrically connected to the i-th scan line (GLi) of the second group.

[0078] The fourth transistor (T4) can be electrically connected between the second node and the second voltage line (VL1). The drain of the fourth transistor (T4) is electrically connected to the second node via the eleventh transistor (T11), and the source of the fourth transistor (T4) can be electrically connected to the second voltage line (VL1). The gate of the fourth transistor (T4) can be electrically connected to the i-th scan line (HLi) of the third group. The second voltage line (VL1) can transmit the first initialization voltage (Vint1) to the pixel (PXij).

[0079] The fifth transistor (T5) can be electrically connected between the fourth voltage line (VL3) and the second transistor (T2). The source of the fifth transistor (T5) can be electrically connected to the fourth voltage line (VL3). The fourth voltage line (VL4) can transmit a reference voltage (Vref) to the pixel (PXij). The drain of the fifth transistor (T5) can be electrically connected to the drain of the second transistor (T2) with the third node in between. The gate of the fifth transistor (T5) can be electrically connected to the i-th scan line (GLi) of the second group. The fifth transistor (T5) can be turned on by a scan signal received through the i-th scan line (GLi) of the second group to transmit a reference voltage (Vref) to the third node.

[0080] The sixth transistor (T6) can be electrically connected between the drain of the first transistor (T1) and the light-emitting element (OLED). The source of the sixth transistor (T6) can be electrically connected to the drain of the first transistor (T1), and the drain of the sixth transistor (T6) can be electrically connected to the anode (AE) of the light-emitting element (OLED). The gate of the sixth transistor (T6) can be electrically connected to the i-th light-emitting line (EL1i) of the first group.

[0081] The seventh transistor (T7) may be electrically connected between the drain of the sixth transistor (T6) and the third voltage line (VL2). The source of the seventh transistor (T7) is electrically connected to the drain of the sixth transistor (T6), and the drain of the seventh transistor (T7) is electrically connected to the third voltage line (VL2). The third voltage line (VL2) may transmit the second initialization voltage (VAint) to the pixel (PXij). The gate of the seventh transistor (T7) may be electrically connected to the i-1th scan line (SLi-1) of the first group. However, not limited thereto, the gate of the seventh transistor (T7) may be connected to a separate group of scan lines.

[0082] The eighth transistor (T8) can be electrically connected between the fifth voltage line (VL4) and the source of the first transistor (T1). The source of the eighth transistor (T8) can be electrically connected to the fifth voltage line (VL4). The fifth voltage line (VL4) can transmit a bias voltage (Vbias) to the pixel (PXij). The drain of the eighth transistor (T8) can be electrically connected to the source of the first transistor (T1). The gate of the eighth transistor (T8) can be electrically connected to the i-th scan line (EMLi) of the fourth group.

[0083] The ninth transistor (T9) can be electrically connected between the first voltage line (PL) and the source of the first transistor (T1). The source of the ninth transistor (T9) can be electrically connected to the first voltage line (PL). The first voltage line (PL) can transmit the first power supply voltage (ELVDD) to the pixel (PXij). The drain of the ninth transistor (T9) can be electrically connected to the source of the first transistor (T1). The gate of the ninth transistor (T9) can be electrically connected to the i-th light-emitting line (EL2i) of the second group.

[0084] The 10th transistor (T10) can be electrically connected between the 1st capacitor (CAP1) and the 2nd transistor (T2). The source of the 10th transistor (T10) can be electrically connected to the 1st node. The drain of the 10th transistor (T10) can be electrically connected to the drain of the 2nd transistor (T2). The gate of the 10th transistor (T10) can be electrically connected to the i-th scan line (GL2i) of the 5th group.

[0085] The eleventh transistor (T11) can be electrically connected between the first capacitor (CAP1) and the fourth transistor (T4). The source of the eleventh transistor (T11) can be electrically connected to the drain of the fourth transistor (T4). The drain of the eleventh transistor (T11) can be electrically connected to the second node. The gate of the eleventh transistor (T11) can be electrically connected to the i-th scan line (GL2i) of the fifth group.

[0086] Meanwhile, the driving circuits of the pixels shown in FIG. 2a and FIG. 2b are merely examples, and the configuration of the driving circuit can be implemented with various modifications.

[0087] FIGS. 3A and 3B are cross-sectional views of a display panel according to one embodiment. FIGS. 3A and 3B illustrate a base substrate (BS), a plurality of insulating layers (ILD1 to ILD5), a first transistor (T1), a second transistor (T2), a first capacitor (CAP1), a second capacitor (CAP2), and a light-emitting element (OLED) among the components of a display panel (DP) for convenience of explanation.

[0088] Meanwhile, the expressions "first and second" here are intended to distinguish the configurations of the transistors and are not limited to the first transistor (T1) and second transistor (T2) of FIG. 2a and FIG. 2b. Each of the first transistor (T1) and second transistor (T2) described later may correspond to any one of the aforementioned multiple transistors.

[0089] Referring to FIGS. 3a and 3b, a base substrate (BS) may provide a base surface on which first and second transistors (T1, T2) are formed. The base substrate (BS) may include an insulating material. For example, the base substrate (BS) may include a glass substrate, a plastic substrate, an organic / inorganic composite material substrate, etc. In one embodiment, the base substrate (BS) may have a single-layer or multi-layer structure.

[0090] An inorganic layer constituting a barrier layer and / or a buffer layer may be disposed on the upper surface of the base substrate (BS). FIGS. 3a and 3b illustrate a buffer layer (BFL) disposed on the base substrate (BS). For example, the buffer layer (BFL) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the buffer layer (BFL) is not limited to the above examples. The buffer layer (BFL) can improve the bonding strength between the base substrate (BS) and the semiconductor patterns (SP1, SP2) of the transistors (T1, T2).

[0091] Meanwhile, although not separately described, the display panel (DP) may further include a blocking layer disposed between the buffer layer (BFL) and the base substrate (BS). The blocking layer may be disposed over the first semiconductor pattern (SP1) of the first transistor (T1) and may prevent the first semiconductor pattern (SP1) of the first transistor (T1) from being damaged by external light.

[0092] A plurality of insulating layers (ILD1 to ILD5) may include first to fifth insulating layers (ILD1 to ILD5) laminated on a base substrate (BS). Each of the first to fifth insulating layers (ILD1 to ILD5) may include an organic film or an inorganic film. For example, the inorganic film of the insulating layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic film of the insulating layer may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a polymer in combination with these. However, the material of the first to fifth insulating layers (ILD1 to ILD5) is not limited to the above examples. Meanwhile, the configuration of the plurality of insulating layers is not limited to that illustrated, and additional insulating layers may be included in addition to the first to fifth insulating layers (ILD1 to ILD5), or any one of the first to fifth insulating layers (ILD1 to ILD5) may be omitted.

[0093] In the manufacturing step of the display panel (DP), an insulating layer, a semiconductor layer, and a conductive layer can be formed by a coating or deposition process, and subsequently, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by a photolithography process. Through the above processes, semiconductor patterns (SP1, SP2), conductive patterns, signal lines, etc. constituting the display panel (DP) can be formed.

[0094] Referring to FIGS. 3a and 3b, the first transistor (T1) may include a first semiconductor pattern (SP1) and a first gate electrode (GE1), and the second transistor (T2) may include a second semiconductor pattern (SP2) and a second gate electrode (GE2).

[0095] The first semiconductor pattern (SP1) may be disposed on a base substrate (BS). In one embodiment, the first semiconductor pattern (SP1) may be disposed on a buffer layer (BFL). The first semiconductor pattern (SP1) may include a plurality of regions with different electrical properties depending on whether or not it is doped. The first semiconductor pattern (SP1) may include an active region (A11) and conductive regions (A12, A13) spaced apart from the active region (A11). One of the conductive regions (A12, A13) may correspond to the source region of the semiconductor pattern (SP1), and the other may correspond to the drain region.

[0096] Specifically, the first semiconductor pattern (SP1) may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration compared to the first region.

[0097] The conductivity of the first region is greater than that of the second region, and the first region may substantially correspond to the source and drain of the transistor. The second region may substantially correspond to the active (or channel) of the transistor.

[0098] The first semiconductor pattern (SP1) may include a silicon semiconductor pattern. For example, the first semiconductor pattern (SP1) may include polysilicon or amorphous silicon. However, it is not limited thereto, and the first semiconductor pattern (SP1) may include a metal oxide.

[0099] The first insulating layer (ILD1) covers the first semiconductor pattern (SP1) and can be disposed on the buffer layer (BFL). In one embodiment, the first insulating layer (ILD1) is silicon nitride (SiN x) and silicon oxide (SiO x It may be an inorganic film comprising at least one of ), but the examples are not necessarily limited thereto.

[0100] The first gate electrode (GE1) can be placed on the first insulating layer (ILD1). The first gate electrode (GE1) can be superimposed on the active region (A11) of the first semiconductor pattern (SP1). The first gate electrode (GE1) can function as a mask in the process of doping the first semiconductor pattern (SP1).

[0101] The first gate electrode (GE1) may include a plurality of layers. In one embodiment, the first gate electrode (GE1) may include a first layer (G1) and a second layer (G2) that are sequentially stacked in the thickness direction. The first layer (G1) may include a conductive material. For example, the first layer (G1) may include titanium (Ti), aluminum (Al), etc. However, the material of the first layer (G1) is not limited to the above examples. The first layer (G1) may have a multilayer structure in which a plurality of conductive layers are stacked.

[0102] The second layer (G2) can come into contact with the upper surface of the first layer (G1). During the manufacturing process of the display panel (DP), the second layer (G2) can prevent the first layer (G1) from being damaged, and this will be explained in detail in the subsequent description of the manufacturing process. In one embodiment, the second layer (G2) is titanium nitride (TiN x It may include ). However, the material of the second layer (G2) is not limited to the above example.

[0103] The aforementioned scan lines (SL1 to SLn, GL1 to GLn, HL1 to HLn, see FIG. 1) can be formed through the same process as the first gate electrode (GE1) and disposed on the same layer. The scan lines (SL1 to SLn, GL1 to GLn, HL1 to HLn, see FIG. 1) may include the same material as the first gate electrode (GE1). Accordingly, the first layer (G1) of the first gate electrode (GE1) may include a conductive material with relatively low resistance. By forming the first gate electrode (GE1) and the scan lines (SL1 to SLn, GL1 to GLn, HL1 to HLn, see FIG. 1) in the same process step, the number of masks required for the process can be reduced, and the process can be simplified, thereby reducing process costs.

[0104] The display panel (DP) may further include a blocking layer (BML) disposed on the same layer as the first gate electrode (GE1). The blocking layer (BML) can be formed through the same process as the first gate electrode (GE1) without adding a separate process step, thereby simplifying the process and reducing process costs.

[0105] The blocking layer (BML) may include the same material as the first gate electrode (GE1). For example, the blocking layer (BML) may include a first layer (B1) and a second layer (B2) disposed on the first layer (B1), and the first layer (B1) and the second layer (B2) of the blocking layer (BML) may each include the same material as the first layer (G1) and the second layer (G2) of the first gate electrode (GE1).

[0106] The blocking layer (BML) can be superimposed on the second semiconductor pattern (SP2) of the second transistor (T2). The blocking layer (BML) can prevent the second semiconductor pattern (SP2) of the second transistor (T2) from being damaged by external light.

[0107] The blocking layer (BML) can be superimposed on the active region (A21) of the second semiconductor pattern (SP2). That is, the active region (A21) of the second semiconductor pattern (SP2) is positioned between the blocking layer (BML) and the second gate electrode (GE2) in the thickness direction, so that it can be superimposed on the blocking layer (BML) and the second gate electrode (GE2), respectively. In one embodiment, the blocking layer (BML) is electrically connected to the second gate electrode (GE2) and the second semiconductor pattern (SP2) of the second transistor (T2) and can function as an additional gate electrode. By the blocking layer (BML) functioning as an additional gate electrode, rapid output synchronization of the second transistor (T2) can be achieved, and accordingly, the electrical characteristics of the pixel can be improved.

[0108] The second insulating layer (ILD2) covers the first gate electrode (GE1) and the blocking layer (BML) and may be disposed on the first insulating layer (ILD1). In one embodiment, the second insulating layer (ILD2) is silicon nitride (SiN x ) and silicon oxide (SiO x It may be an inorganic film comprising at least one of ). For example, the second insulating layer (ILD2) is silicon nitride (SiN x ) and silicon oxide (SiO x Each of the inorganic films may have a stacked multilayer structure. However, the material of the second insulating layer (ILD2) is not limited to the above examples.

[0109] The second semiconductor pattern (SP2) may be disposed on a layer different from the first semiconductor pattern (SP1). In one embodiment, the second semiconductor pattern (SP2) may be disposed on the second insulating layer (ILD2).

[0110] The second semiconductor pattern (SP2) may include a semiconductor pattern different from the first semiconductor pattern (SP1). For example, the first semiconductor pattern (SP1) may include a silicon semiconductor pattern, and the second semiconductor pattern (SP1) may include an oxide semiconductor pattern. For example, the oxide semiconductor may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. In one embodiment, the oxide semiconductor may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0111] The second semiconductor pattern (SP2) may include a metal oxide and may include multiple regions with different electrical properties depending on whether it is doped or reduced. The second semiconductor pattern (SP2) may include an active region (A21) and conductive regions (A22, A23) spaced apart from the active region (A21). One of the conductive regions (A22, A23) may correspond to the source region of the semiconductor pattern (SP1), and the other may correspond to the drain region.

[0112] Specifically, the second semiconductor pattern (SP2) may include a plurality of regions distinguished by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, reduced region) may have greater conductivity than the region where it is not reduced (hereinafter, non-reduced region). The reduced region may substantially correspond to the source and drain of the transistor. The non-reduced region may substantially correspond to the active (or channel) of the transistor.

[0113] A third insulating layer (ILD3) may be disposed on the second insulating layer (ILD2) to cover the second semiconductor pattern (SP2). A second gate electrode (GE2) may be disposed on the third insulating layer (ILD3). The second gate electrode (GE2) may overlap the active region (A21) of the second semiconductor pattern (SP2). In one embodiment, the second gate electrode (GE2) may function as a mask in a process of doping the second semiconductor pattern (SP2).

[0114] Referring to FIG. 3a, the third insulating layer (ILD3) can be superimposed on the first transistor (T1). That is, the third insulating layer (ILD3) can be placed on the first gate electrode (GE1) to cover the first gate electrode (GE1).

[0115] However, the embodiments are not limited thereto, and as illustrated in FIG. 3b, the third insulating layer (ILD3a) may be provided in the form of an insulating pattern. Hereinafter, the third insulating layer (ILD3a) in FIG. 3b will be referred to as the insulating pattern (ILD3a). The second gate electrode (GE2) may be spaced apart from the active region (A21) of the second semiconductor pattern (SP2) on a cross-sectional side with the insulating pattern (ILD3a) in between. After forming an insulating layer and a conductive layer on the second semiconductor pattern (SP2) of the second transistor (T2), the second gate electrode (GE2) and the insulating pattern (ILD3a) may be formed by patterning. The second gate electrode (GE2) may be used as a mask in the process of forming the insulating pattern (ILD3a).

[0116] The insulating pattern (ILD3a) may not overlap the first transistor (T1). That is, the third insulating layer (ILD3a), provided in the form of an insulating pattern, may not overlap the first transistor (T1). Accordingly, the patterned third insulating layer (ILD3a) may not be placed within the area where the first transistor (T1) is placed, and the fourth insulating layer (ILD4) may be placed directly above the second insulating layer (ILD2) within the area where the first transistor (T1) is placed.

[0117] The second gate electrode (GE2) may include a conductive material. For example, the second gate electrode (GE2) may include molybdenum (Mo), titanium (Ti), etc. However, the material of the second gate electrode (GE2) is not limited to the above examples.

[0118] The second gate electrode (GE2) may have a multilayer structure in which a plurality of conductive layers are stacked. In one embodiment, the second gate electrode (GE2) may have a stacked structure different from the stacked structure of the first gate electrode (GE1). For example, the second gate electrode (GE2) may include two conductive layers composed of Mo / Ti, and the first gate electrode (GE1) may include a first layer (G1) composed of Ti / AL and titanium nitride (TiN x It may include a second layer (G2) including ). However, the embodiment of the second gate electrode (GE2) is not necessarily limited thereto.

[0119] The fourth insulating layer (ILD4) covers the second gate electrode (GE2) and can be disposed on the third insulating layer (ILD3). In one embodiment, the fourth insulating layer (ILD4) is silicon nitride (SiN x ) and silicon oxide (SiO x It may be an inorganic film comprising at least one of ). For example, the fourth insulating layer (ILD4) is silicon nitride (SiN x ) and silicon oxide (SiO xEach of these may be an inorganic film with a multilayer structure. However, the material of the fourth insulating layer (ILD4) is not limited to the above examples.

[0120] The fourth insulating layer (ILD4) may contain the same material as the second insulating layer (ILD2). In one embodiment, the fourth insulating layer (ILD4) may be formed under the same conditions as the process of forming the second insulating layer (ILD2), and the stacked structure of the fourth insulating layer (ILD4) may be the same as the stacked structure of the second insulating layer (ILD2). However, the embodiment of the fourth insulating layer (ILD4) is not necessarily limited thereto.

[0121] The display panel (DP) may include connecting electrodes (CE1, CE2) each connected to semiconductor patterns (SP1, SP2) of the first and second transistors (T1, T2). FIGS. 3a and 3b exemplarily illustrate a first connecting electrode (CE1) connected to the first semiconductor pattern (SP1) and a second connecting electrode (CE2) connected to the second semiconductor pattern (SP2).

[0122] The first connecting electrode (CE1) may be placed on a layer different from the first semiconductor pattern (SP1) and connected to the first semiconductor pattern (SP1) through a through hole (CH1) that penetrates at least one insulating layer. Referring to FIGS. 3a and 3b, the first connecting electrode (CE1) may be placed on a fourth insulating layer (ILD4) and connected to the first semiconductor pattern (SP1) through a through hole (CH1) that penetrates the first to fourth insulating layers (ILD1 to ILD4).

[0123] The second connecting electrode (CE2) may be placed on a layer different from the second semiconductor pattern (SP2) and connected to the second semiconductor pattern (SP2) through a through hole (CH3) that penetrates at least one insulating layer. Referring to FIGS. 3a and 3b, the second connecting electrode (CE2) may be placed on a fourth insulating layer (ILD4) and connected to the second semiconductor pattern (SP2) through a through hole (CH3) that penetrates the third and fourth insulating layers (ILD3, ILD4).

[0124] In one embodiment, the second connecting electrode (CE2) can be connected to the second gate electrode (GE2) and the blocking layer (BML), respectively. The second connecting electrode (CE2) can be connected to the second gate electrode (GE2) through a through hole (CH2-1) penetrating the fourth insulating layer (ILD4). Additionally, the second connecting electrode (CE2) can be connected to the blocking layer (BML) through a through hole (CH2-2) penetrating the second to fourth insulating layers (ILD2 to ILD4). Through this, the second connecting electrode (CE2) can electrically connect the second gate electrode (GE2) and the blocking layer (BML), and the blocking layer (BML) can function as an additional gate electrode.

[0125] A through hole (CH2-2) that exposes a portion of the blocking layer (BML) can be formed by penetrating the second layer (B2) of the blocking layer (BML). The second layer (B2) can act as a sacrificial layer protecting the first layer (B1) of the blocking layer (BML) during the process of forming the through holes (CH1, CH2-1, CH2-2), and accordingly, a portion of the second layer (B2) can be removed. As a result, a portion of the first layer (B1) of the blocking layer (BML) can be exposed, and the second connecting electrode (CE2) can be connected to the first layer (B1) of the blocking layer (BML), which has relatively high conductivity.

[0126] Each of the first connecting electrode (CE1) and the second connecting electrode (CE2) may include a conductive material. Each of the first connecting electrode (CE1) and the second connecting electrode (CE2) may have a multilayer structure in which a plurality of conductive layers are stacked. For example, each of the first connecting electrode (CE1) and the second connecting electrode (CE2) may include three conductive layers composed of Ti / Al / Ti. However, the materials of the first connecting electrode (CE1) and the second connecting electrode (CE2) are not limited to the above examples.

[0127] The first connecting electrode (CE1) and the second connecting electrode (CE2) can be placed on the same layer. The first connecting electrode (CE1) and the second connecting electrode (CE2) can be formed simultaneously through the same process and may contain the same material. The first connecting electrode (CE1) and the second connecting electrode (CE2) can be formed simultaneously using a single mask, thereby simplifying the process of the first connecting electrode (CE1) and the second connecting electrode (CE2).

[0128] The fifth insulating layer (ILD5) may be disposed on the first and second connecting electrodes (CE1, CE2). In one embodiment, the fifth insulating layer (ILD5) may include an organic film and may provide a flat upper surface for the light-emitting element (OLED) to be disposed on the fifth insulating layer (ILD5). The fifth insulating layer (ILD5) may be a single insulating layer. This simplifies the deposition process for forming the fifth insulating layer (ILD5). However, embodiments of the fifth insulating layer (ILD5) are not necessarily limited thereto.

[0129] The aforementioned data lines (DL1 to DLn, see FIG. 1) can be formed through the same process as the first connecting electrode (CE1) and placed on the same layer. The data lines (DL1 to DLn, see FIG. 1) may contain the same material as the first connecting electrode (CE1). By forming the first connecting electrode (CE1) and the data lines (DL1 to DLn, see FIG. 1) in the same process step, the number of masks required for the process can be reduced, and the process can be simplified, thereby reducing process costs.

[0130] A display panel (DP) may include at least one capacitor formed by electrodes that overlap each other on a plane. Referring to FIGS. 3a and 3b, in one embodiment, the display panel (DP) may include first and second capacitors (CAP1, CAP2).

[0131] As illustrated in FIGS. 3a and 3b, the first and second capacitors (CAP1, CAP2) may be stacked along the cross-section of the display panel (DP). The first and second capacitors (CAP1, CAP2) may be formed by a first gate electrode (GE1), a first upper electrode (C2), and a second upper electrode (C3).

[0132] The first upper electrode (C2) can form a first capacitor (CAP1) by overlapping with the first gate electrode (GE1) on a plane. That is, the first electrode (C1) of the first capacitor (CAP1) can be defined by a part of the first gate electrode (GE1) that overlaps with the first upper electrode (C2) on a plane. The first electrode (C1) and the first gate electrode (GE1) of the first capacitor (CAP1) can be provided in the form of electrodes formed integrally on the first insulating layer (ILD1). The second electrode of the first capacitor (CAP1) can correspond to the first upper electrode (C2).

[0133] The second upper electrode (C3) can form a second capacitor (CAP2) by overlapping with the first upper electrode (C2) on a plane. The first upper electrode (C2) can be one electrode of the first capacitor (CAP1) and at the same time one electrode of the second capacitor (CAP2).

[0134] Meanwhile, although the present embodiment exemplarily illustrates a structure in which the first transistor (T1) and the first and second capacitors (CAP1, CAP2) are sequentially stacked, it is not limited thereto, and the first transistor (T1) and the first and second capacitors (CAP1, CAP2) may be arranged on a plane in a partially overlapping or non-overlapping manner. In this case, a portion of the first gate electrode (GE1) that overlaps with the active region (A11) may constitute the first transistor (T1), and another portion of the first gate electrode (GE1) may overlap with the first upper electrode (C2) to constitute the first capacitor (CAP1). In a display panel (DP) according to an embodiment of the present invention, the first and second capacitors (CAP1, CAP2) may be arranged at various positions on a plane if formed by the first gate electrode (GE1), the first upper electrode (C2), and the second upper electrode (C3), and are not limited to any one embodiment.

[0135] The display panel (DP) can sufficiently secure the capacitance capacity of the pixel by forming the first and second capacitors (CAP1, CAP2). In addition, by forming the second electrode of the first capacitor (CAP1) and the first electrode of the second capacitor (CAP2) using a single electrode, the process for forming the first and second capacitors (CAP1, CAP2) can be simplified and the pixel integration density can be improved. Meanwhile, the embodiment is not limited thereto, and the display panel (DP) can form a single capacitor corresponding to the pixel, in which case one of the first upper electrode (C2) and the second upper electrode (C3) may be omitted.

[0136] The stacking position of the first upper electrode (C2) may vary depending on the embodiment of the display panel (DP). FIGS. 3a and FIGS. 3b respectively illustrate embodiments in which the stacking position of the first upper electrode (C2) forming the first capacitor (CAP1) and the second capacitor (CAP2) is different.

[0137] Referring to FIG. 3a, the first upper electrode (C2) may be placed on the same layer as the second gate electrode (GE2). The first upper electrode (C2) may contain the same material as the second gate electrode (GE2). The first upper electrode (C2) and the second gate electrode (GE2) may be formed through the same process using a single mask. Accordingly, the process for forming the first capacitor (CAP1) can be simplified and process costs can be reduced.

[0138] In cross-section, the second insulating layer (ILD2) and the third insulating layer (ILD3) overlap the first gate electrode (GE1) and the first upper electrode (C2), and can be disposed between the first gate electrode (GE1) and the first upper electrode (C2). That is, the second insulating layer (ILD2) and the third insulating layer (ILD3) can be disposed between the electrodes forming the first capacitor (CAP1). Accordingly, the capacitance and efficiency of the first capacitor (CAP1) may be affected by the material, thickness, dielectric constant, etc., of the second insulating layer (ILD2) and the third insulating layer (ILD3), respectively. By adjusting the material and thickness of the second insulating layer (ILD2) and the third insulating layer (ILD3), the first capacitor (CAP1) having the required capacitance can be formed.

[0139] The inorganic film included in the second insulating layer (ILD2) can be formed to have a predetermined dielectric constant. For example, the second insulating layer (ILD2) is silicon nitride (SiN x ) and silicon oxide (SiO x It may include silicon nitride (SiN xThe dielectric constant of ) can be 6 or more and 8 or less, and silicon oxide (SiO x The permittivity of ) can be 3.8 or higher and 5 or lower.

[0140] The inorganic film included in the third insulating layer (ILD3) can be formed to have a predetermined dielectric constant. In one embodiment, the third insulating layer (ILD3) is silicon oxide (SiO₂). x It can be a single inorganic film containing ), and silicon oxide (SiO x The dielectric constant of ) may be 3.8 or greater and 5 or less. However, it is not limited thereto, and the third insulating layer (ILD3) may be silicon nitride (SiN x ) and silicon oxide (SiO x It may also include ).

[0141] Each of the second insulating layer (ILD2) and the third insulating layer (ILD3) may have a predetermined thickness. For example, the thickness of the second insulating layer (ILD2) may be 1,000 Angstroms or more and 10,000 Angstroms or less. The thickness of the third insulating layer (ILD3) may be 500 Angstroms or more and 5,000 Angstroms or less. However, the thicknesses of the second insulating layer (ILD2) and the third insulating layer (ILD3) are not necessarily limited to the above examples.

[0142] The second insulating layer (ILD2) may include a plurality of inorganic films, and the capacitance of the first capacitor (CAP1) may vary depending on the thickness of each of the inorganic films included in the second insulating layer (ILD2). For example, the second insulating layer (ILD2) may be at least one silicon nitride (SiN x ) layer and at least one silicon oxide (SiO x It may include a ) layer, and silicon nitride (SiN) constituting the second insulating layer (ILD2) x The sum of the thicknesses of the layers is the silicon oxide (SiO₂) constituting the second insulating layer (ILD2). xThe sum of the thicknesses of the layers may be between 1 and 20 times. In one embodiment, silicon nitride (SiN) included in the second insulating layer (ILD2) x The thickness of the layer may be at least 500 Angstroms. However, embodiments of the second insulating layer (ILD2) are not necessarily limited to this.

[0143] In one embodiment, the third insulating layer (ILD3) may include a plurality of inorganic films. For example, the third insulating layer (ILD3) may be silicon nitride (SiN x ) layer and silicon oxide (SiO x It may include a ) layer. In one embodiment, silicon nitride (SiN) included in the third insulating layer (ILD3). x The thickness of the layer can be up to 300 Angstroms. However, embodiments of the third insulating layer (ILD3) are not necessarily limited to this.

[0144] Referring to FIG. 3a, the second upper electrode (C3) may be placed on the same layer as the first connecting electrode (CE1). The second upper electrode (C3) may contain the same material as the first connecting electrode (CE1). The second upper electrode (C3) and the first connecting electrode (CE1) can be formed through the same process using a single mask. Therefore, it is not necessary to add a separate process step using a mask to form the second capacitor (CAP2), and the process can be simplified and process costs reduced.

[0145] In cross-section, the fourth insulating layer (ILD4) overlaps the first upper electrode (C2) and the second upper electrode (C3) and can be placed between the first upper electrode (C2) and the second upper electrode (C3). That is, the fourth insulating layer (ILD4) can be placed between the electrodes (C2, C3) forming the second capacitor (CAP2). Accordingly, the capacitance and efficiency of the second capacitor (CAP2) can be influenced by the material, thickness, dielectric constant, etc. of the fourth insulating layer (ILD4). By adjusting the material and thickness of the fourth insulating layer (ILD4), a second capacitor (CAP2) having the required capacitance can be formed.

[0146] The fourth insulating layer (ILD4) may include at least one inorganic film having a predetermined thickness, and the at least one inorganic film included in the fourth insulating layer (ILD4) may be formed to have a predetermined dielectric constant. The description regarding the composition and thickness of the inorganic film included in the fourth insulating layer (ILD4) may be applied in the same way as the description regarding the second insulating layer (ILD2).

[0147] Referring to FIG. 3b, the first upper electrode (C2) may be placed on the same layer as the second semiconductor pattern (SP2). The first upper electrode (C2) may contain the same material as the second semiconductor pattern (SP2). For example, the first upper electrode (C2) may contain a metal oxide. The first upper electrode (C2) and the second semiconductor pattern (SP2) may be formed through the same process using a single mask. Accordingly, the process for forming one electrode of the first capacitor (CAP1) can be simplified, and the process cost can be reduced.

[0148] In cross-section, the second insulating layer (ILD2) can be disposed between the first gate electrode (GE1) and the first upper electrode (C2). That is, the second insulating layer (ILD2) can be disposed between the electrodes (C1, C2) forming the first capacitor (CAP1). Compared to the embodiment of the first capacitor (CAP1) of FIG. 3a, the thickness of the insulating layer disposed between the electrodes (C1, C2) of the first capacitor (CAP1) of FIG. 3b can be reduced. Assuming that the first capacitor (CAP1) of FIG. 3a and the first capacitor (CAP1) of FIG. 3b each include a first electrode (C1) and a first upper electrode (C2) of the same area, the capacitance of the first capacitor (CAP1) of FIG. 3b can be greater than that of the first capacitor (CAP1) of FIG. 3a.

[0149] As described above, the third insulating layer (ILD3a) of FIG. 3b can be provided in the form of an insulating pattern. Accordingly, the third insulating layer (ILD3a) may not be placed between the first upper electrode (C2) placed on the second insulating layer (ILD2) and the second upper electrode (C3) placed on the fourth insulating layer (ILD4). That is, the third insulating layer (ILD3a) may not overlap between the electrodes (C2, C3) forming the second capacitor (CAP2) in a planar plane. Therefore, only the fourth insulating layer (ILD4) may be placed between the first upper electrode (C2) and the second upper electrode (C3) in a cross-section.

[0150] Again, referring to FIGS. 3a and 3b, a light-emitting element (OLED) may be disposed on a fifth insulating layer (ILD5). The light-emitting element (OLED) may include a pixel electrode (AE), a light-emitting layer (EML), and a counter electrode (CE). The pixel electrode (AE) of the light-emitting element (OLED) may be the anode (AE) of FIGS. 2a and 2b, and the counter electrode (CE) may be the cathode (CE) of FIGS. 2a and 2b.

[0151] A pixel electrode (AE) may be disposed on a fifth insulating layer (ILD5). The pixel electrode (AE) may be connected to a first connecting electrode (CE1) through a contact hole (CH4) penetrating the fifth insulating layer (ILD5). The fifth insulating layer (ILD5) disposed between the pixel electrode (AE) and the first connecting electrode (CE1) may be a single insulating layer.

[0152] A pixel defining film (PDL) that exposes at least a portion of the pixel electrode (AE) may be disposed on the pixel electrode (AE) and the fifth insulating layer (ILD5). A light-emitting opening (OP-P) for exposing a portion of the pixel electrode (AE) may be defined in the pixel defining film (PDL). In this embodiment, the portion of the pixel electrode (AE) exposed by the light-emitting opening (OP-P) may correspond to a light-emitting region.

[0153] The pixel defining film (PDL) may include organic materials. Not limited thereto, the pixel defining film (PDL) may further include inorganic materials. The pixel defining film (PDL) of one embodiment may have a predetermined color. For example, the pixel defining film (PDL) may include a base resin and a black pigment and / or a black dye mixed in the base resin. However, embodiments of the pixel defining film (PDL) are not limited thereto.

[0154] The light-emitting layer (EML) may be disposed on the pixel electrode (AE). The light-emitting layer (EML) may have a light-emitting pattern shape disposed in an area corresponding to the light-emitting aperture (OP-P). However, it is not limited thereto, and the light-emitting layer (EML) may be provided in a single form corresponding to a plurality of pixels. The light-emitting layer (EML) may include organic and / or inorganic quantum dots, quantum rods, etc. The light-emitting layer (EML) may generate any one of red, green, and blue light.

[0155] The counter electrode (CE) may be disposed on the light-emitting layer (EML). A portion of the counter electrode (CE) may be disposed on the upper surface of the pixel defining film (PDL). The counter electrode (CE) may be provided as a common layer disposed in common for a plurality of pixels.

[0156] Each of the pixel electrode (AE) and the counter electrode (CE) may comprise at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, two or more compounds selected from these, two or more mixtures selected from these, or oxides thereof.

[0157] Each of the pixel electrode (AE) and the counter electrode (CE) may be a transmissive electrode, a semitransmissive electrode, or a reflective electrode. The transmissive electrode may include a transparent metal oxide, for example, ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. The semitransmissive electrode or the reflective electrode may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, Yb, W, or a compound or mixture containing these (e.g., AgMg, AgYb, or MgYb).

[0158] Each of the pixel electrode (AE) and the counter electrode (CE) may be a transmissive electrode, a semitransmissive electrode, or a reflective electrode. The transmissive electrode may include a transparent metal oxide, for example, ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. The semitransmissive electrode or the reflective electrode may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, Yb, W, or a compound or mixture containing these (e.g., AgMg, AgYb, or MgYb).

[0159] The pixel electrode (AE) and the counter electrode (CE) may each have a plurality of layer structures including a reflective film or a semi-transparent film formed of the above material and a transparent conductive film formed of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. For example, the electrodes of the plurality of layer structures may have a three-layer structure of ITO / Ag / ITO, but are not limited thereto.

[0160] A first voltage (ELVDD, see FIG. 1) can be applied to the pixel electrode (AE), and a second voltage (ELVSS, see FIG. 1) can be applied to the counter electrode (CE). Holes and electrons injected into the light-emitting layer (EML) combine to form excitons, and as the excitons transition to the ground state, the light-emitting element (OLED) can emit light. As the light-emitting element (OLED) emits light, the display panel (DP) can display an image through the display surface.

[0161] Meanwhile, the light-emitting element (OLED) may further include at least one functional layer disposed between the pixel electrode (AE) and the counter electrode (CE). For example, the light-emitting element (OLED) may further include a hole control layer disposed between the pixel electrode (AE) and the light-emitting layer (EML), and an electronic control layer disposed between the light-emitting layer (EML) and the counter electrode (CE). The hole control layer may include at least one of a hole transport layer and a hole injection layer, and the electronic control layer may include at least one of an electron transport layer and an electron injection layer.

[0162] Although not separately described, the display panel (DP) may further include a sealing film disposed on the light-emitting element (OLED). The sealing film may include at least one of an inorganic film and an organic film, and can protect the light-emitting element (OLED) from foreign substances such as moisture, oxygen, or dust introduced from the outside.

[0163] FIGS. 4a and 4b are cross-sectional views of a display panel according to one embodiment. The display panels (DP) shown in FIGS. 4a and 4b include substantially the same configuration as the display panels (DP) shown in FIGS. 3a and 3b, with differences in the stacking positions of some components. The following description will focus on the differences between the embodiments and will omit repetitive descriptions.

[0164] Referring to FIGS. 4a and 4b, the display panel (DP) may include a base substrate (BS), a plurality of insulating layers (ILD1 to ILD4), a first transistor (T1), a second transistor (T2), a first capacitor (CAP1), and a light-emitting element (OLED).

[0165] Referring to FIG. 4a, a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2) may be placed on different layers. The first semiconductor pattern (SP1) may be placed on a buffer layer (BFL) and covered by a first insulating layer (ILD1). The second semiconductor pattern (SP2) may be placed on the first insulating layer (ILD1). Accordingly, the second semiconductor pattern (SP2) may be placed above the first semiconductor pattern (SP1).

[0166] However, not limited thereto, as illustrated in FIG. 4b, the first insulating layer (ILD1) may be omitted. That is, the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) may be placed on the same layer. The first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) may be placed on a buffer layer (BFL), and the second insulating layer (ILD2) may contact the buffer layer (BLF) and cover the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2).

[0167] As the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) are placed on the same layer, the stacking of insulating layers between the semiconductor patterns can be omitted, and the number of insulating layers stacked on the base substrate (BS) can be reduced. Accordingly, the thickness of the display panel (DP) can be reduced, the pixel density can be improved, and the manufacturing process of the display panel (DP) can be simplified.

[0168] Meanwhile, although not separately described, a display panel (DP) of one embodiment may further include a blocking layer disposed between a buffer layer (BFL) and a base substrate (BS). The blocking layer may be disposed overlapping the first semiconductor pattern (SP1) of the first transistor (T1) and the second semiconductor pattern (SP2) of the second transistor (T2). An entire blocking layer may overlap the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2). However, it is not limited thereto, and the blocking layer may include blocking portions spaced apart from each other on the same layer, and one blocking portion may overlap the first semiconductor pattern (SP1) and another blocking portion may overlap the second semiconductor pattern (SP2). The blocking layer can prevent the semiconductor patterns (SP1, SP2) from being damaged by external light.

[0169] Referring to FIGS. 4a and 4b, the first gate electrode (GE1) and the second gate electrode (GE2) are formed through the same process and can be placed on the same layer. In one embodiment, the first gate electrode (GE1) and the second gate electrode (GE2) can be placed on the second insulating layer (ILD2). The first gate electrode (GE1) and the second gate electrode (GE2) can be formed in the same process step using a single mask. Thus, the process for forming the first gate electrode (GE1) and the second gate electrode (GE2) can be simplified.

[0170] The first gate electrode (GE1) and the second gate electrode (GE2) may each contain the same material. Each of the first gate electrode (GE1) and the second gate electrode (GE2) may include a first layer (G1) and a second layer (G2) that are sequentially stacked in the thickness direction. The description of the first layer (G1) and the second layer (G2) may be applied in the same way as the description of the first layer (G1) and the second layer (G2) described with reference to FIGS. 3a and 3b.

[0171] The third insulating layer (ILD3) covers the first gate electrode (GE1) and the second gate electrode (GE2) and may be disposed on the second insulating layer (ILD2). The first connecting electrode (CE1) may be disposed on the third insulating layer (ILD3). The first connecting electrode (CE1) may be connected to the first semiconductor pattern (SP1) through a through hole (CH1) penetrating the first to third insulating layers (ILD1 to ILD3) as shown in FIG. 4a, or connected to the first semiconductor pattern (SP1) through a through hole (CH1) penetrating the second and third insulating layers (ILD2, ILD3) as shown in FIG. 4b.

[0172] The display panel (DP) may further include a connection line (CL) connected to the second gate electrode (GE2). The connection line (CL) may extend in a plane and be connected to a driving element connected to the second gate electrode (GE2) of the second transistor (T2).

[0173] The connection line (CL) is formed through the same process as the first connection electrode (CE1) and can be placed on the same layer. The connection line (CL) can be connected to the second gate electrode (GE2) through a through hole (CH2) that penetrates the third insulating layer (ILD3). The through hole (CH2) that overlaps the connection line (CL) can be formed by penetrating the second layer (G2) of the second gate electrode (GE2). The second layer (G2) of the second gate electrode (GE2) can act as a sacrificial layer protecting the first layer (G1) during the process of forming the through holes (CH1, CH2), and a portion of the second layer (G2) can be removed to expose a portion of the first layer (G1). Accordingly, the connection line (CL) can be connected to the first layer (G1) of the second gate electrode (GE2), which has relatively high conductivity.

[0174] Referring to FIGS. 4a and 4b, the display panel (DP) may include a first capacitor (CAP1). The display panel (DP) may include a first gate electrode (GE1) and a first upper electrode (C2) that overlaps in a plane. The first gate electrode (GE1) and the first upper electrode (C2) that overlap each other in a plane may form the first capacitor (CAP1).

[0175] A third insulating layer (ILD3) may be disposed between the electrodes (C1, C2) forming the first capacitor (CAP1) in cross-section. Accordingly, the capacitance and efficiency of the first capacitor (CAP1) may be affected by the material, thickness, dielectric constant, etc. of each of the third insulating layer (ILD3), and the first capacitor (CAP1) having the required capacitance can be formed by adjusting the material and thickness of the third insulating layer (ILD3).

[0176] The inorganic film included in the third insulating layer (ILD3) can be formed to have a predetermined dielectric constant. For example, the third insulating layer (ILD3) is silicon nitride (SiN x ) and silicon oxide (SiO x It may include silicon nitride (SiN x The dielectric constant of ) can be 6 or more and 8 or less, and silicon oxide (SiO x The permittivity of ) can be 3.8 or higher and 5 or lower.

[0177] The third insulating layer (ILD3) may have a predetermined thickness. For example, the thickness of the third insulating layer (ILD3) may be 1,000 Angstroms or more and 10,000 Angstroms or less. The third insulating layer (ILD3) may include a plurality of inorganic films, and the capacitance of the first capacitor (CAP1) may vary depending on the thickness of each of the inorganic films included in the third insulating layer (ILD3). For example, the third insulating layer (ILD3) may be silicon nitride (SiN x ) layer and silicon oxide (SiO xIt may include a ) layer, and silicon nitride (SiN) constituting the third insulating layer (ILD3) x The sum of the thicknesses of the ) layers is silicon oxide (SiO x The sum of the thicknesses of the layers may be 1 to 20 times. However, the embodiment of the third insulating layer (ILD3) is not necessarily limited to this.

[0178] The embodiments of the display panel (DP) shown in FIGS. 4a and 4b may include a relatively smaller number of capacitors compared to the embodiments of the display panel (DP) shown in FIGS. 3a and 3b. Accordingly, the number of masks required to manufacture the display panel (DP) may be reduced, and the stacking process of the display panel (DP) may be simplified.

[0179] The fourth insulating layer (ILD4) covers the first upper electrode (C2) and the first connecting electrode (CE1) and may be disposed on the third insulating layer (ILD3). In one embodiment, the fourth insulating layer (ILD4) may include an organic film and may provide a flat upper surface to the light-emitting element (OLED) to be disposed on the fourth insulating layer (ILD4). The fourth insulating layer (ILD4) may be a single insulating layer.

[0180] The pixel electrode (AE) of the light-emitting element (OLED) can be connected to the first connecting electrode (CE1) through a through hole (CH4) penetrating the fourth insulating layer (ILD4). The description regarding the light-emitting element (OLED) can be applied in the same way as the description above.

[0181] A second connecting electrode (CE2) that is disposed on a layer different from the second semiconductor pattern (SP2) and connected to the second semiconductor pattern (SP2) may be disposed on a layer different from the first connecting electrode (CE1). In one embodiment, the second connecting electrode (CE2) may be disposed on the same layer as the pixel electrode (AE). The second connecting electrode (CE2) may be disposed on a fourth insulating layer (ILD4) that provides a flat upper surface. The second connecting electrode (CE2) may be connected to the second semiconductor pattern (SP2) through a through hole (CH3) that penetrates the second to fourth insulating layers (ILD2 to ILD4).

[0182] The second connecting electrode (CE2) is formed through the same process as the pixel electrode (AE) and can be placed on the same layer. The second connecting electrode (CE2) may include the same material as the pixel electrode (AE). The through-hole (CH3) connecting the second connecting electrode (CE2) and the second semiconductor pattern (SP2), and the through-hole (CH4) connecting the first connecting electrode (CE1) and the pixel electrode (AE) can be formed through the same process using a single mask. Additionally, the second connecting electrode (CE2) and the pixel electrode (AE) can be formed through the same process using a single mask. Thus, the second connecting electrode (CE2) can be formed without an additional mask, and the formation process of the second connecting electrode (CE2) can be simplified. Furthermore, the number of multiple insulating layers stacked between the base substrate (BS) and the light-emitting element (OLED) can be reduced.

[0183] FIGS. 5a to 5p are cross-sectional views sequentially illustrating the manufacturing steps of a display panel according to an embodiment of the present invention. A display panel (DP) of an embodiment formed through the manufacturing steps illustrated in FIGS. 5a to 5p may correspond to a display panel (DP) illustrated in FIG. 3a.

[0184] Referring to FIG. 5a, a first pre-semiconductor layer (P1-SP1) can be deposited on a buffer layer (BFL) to form a first semiconductor pattern (SP1, FIG. 5d). In one embodiment, the first pre-semiconductor layer (P1-SP1) may include a silicon semiconductor material. After forming the first pre-semiconductor layer (P1-SP1), a first photoresist layer (PR1) can be applied on the first pre-semiconductor layer (P1-SP1).

[0185] To pattern the first pre-semiconductor layer (P1-SP1), a first mask (MSK1) in which a first opening (OP-M1) is defined corresponding to the area where the first semiconductor pattern (SP1, FIG. 5D) is formed can be provided on the first photoresist layer (PR1). Subsequently, an exposure process can be performed to provide light onto the first mask (MSK1), and through the exposure process, light can pass through the first opening (OP-M1) and be irradiated onto a part of the first photoresist layer (PR1) and the first pre-semiconductor layer (P1-SP1) corresponding to the first opening (OP-M1).

[0186] Subsequently, a portion of the first photoresist layer (PR1) that overlaps the first opening (OP-M1) by the developer provided in the development process remains, and another portion of the first photoresist layer (PR1) that is not irradiated with light by overlapping the first mask (MSK1) can be removed. Accordingly, a portion of the first pre-semiconductor layer (P1-SP1) can be exposed by the first photoresist layer (PR1) from which a portion has been removed in correspondence with the first mask (MSK1), and subsequently, the exposed portion of the first pre-semiconductor layer (P1-SP1) can be removed through an etching process. Subsequently, the remaining first photoresist layer (PR1) can be removed to pattern the first pre-semiconductor layer (P1-SP1) to correspond to the first opening (OP-M1).

[0187] Meanwhile, although the description was based on a positive photo process in which a pattern corresponding to the opening of the mask is formed, it is not limited thereto, and the first preliminary semiconductor pattern (P-SP1) may also be formed by a negative photo process in which the portion corresponding to the opening of the mask is removed. Furthermore, the photo processes described below are described based on a positive photo process, but at least one of them may proceed as a negative photo process.

[0188] FIG. 5b illustrates a first pre-semiconductor layer patterned through the process of 5a, which can be defined as a first pre-semiconductor pattern (P-SP1). Here, the first pre-semiconductor pattern (P-SP1) may correspond to a semiconductor pattern before the doping process is performed. The first pre-semiconductor pattern (P-SP1) may correspond to a first opening (OP-M1, see FIG. 5a) of a first mask (MSK1, see FIG. 5a).

[0189] Referring to FIG. 5c, a first insulating layer (ILD1) can be deposited on a first pre-semiconductor pattern (P-SP1). Subsequently, to form a first gate electrode (GE1, see FIG. 5d), a first pre-gate electrode layer (P-GE1) can be deposited on the first insulating layer (ILD1).

[0190] The first preliminary gate electrode layer (P-GE1) may include a first layer (P-G1) containing a conductive material and a second layer (P-G2) deposited on the first layer (P-G1) and protecting the first layer (P-G1). In one embodiment, the second layer (P-G2) is titanium nitride (TiN x It may include ). The thickness of the second layer (P-G2) may be deposited thinner than the thickness of the first layer (P-G1).

[0191] A second photoresist layer (PR2a) may be applied on a first pre-gate electrode layer (P-GE1). To pattern the first pre-gate electrode layer (P-GE1), a second mask (MSK2a) with second openings (OP-M2) defined therein may be provided on the second photoresist layer (PR2a). At least some of the second openings (OP-M2) may overlap with the first pre-semiconductor pattern (P-SP1), which may correspond to an area defined as an active region (A11, FIG. 5d) to be formed thereafter.

[0192] Meanwhile, in the step of forming the first gate electrode (GE1, see FIG. 5d), a blocking layer (BML, see FIG. 5d) can be simultaneously formed using the same second mask (MSK2a). Thus, some of the second openings (OP-M2) may correspond to the area where the blocking layer (BML, see FIG. 5d) is formed. Subsequently, a first conductive pattern having a pattern corresponding to the second openings (OP-M2) can be formed through exposure, development, and etching processes.

[0193] Referring to FIG. 5d, a portion of the first conductive pattern may be formed as a first gate electrode (GE1), and another portion of the first conductive pattern may be formed as a blocking layer (BML). After forming the first gate electrode (GE1), the first gate electrode (GE1) may be used as a mask to dope the first preliminary semiconductor pattern (P-SP1), and a first semiconductor pattern (SP1) including conductive regions (A12, A13) and an active region (A11) may be formed by the doping process. The first semiconductor pattern (SP1) and the first gate electrode (GE1) may be defined as the aforementioned first transistor (T1).

[0194] Referring to FIG. 5e, a second insulating layer (ILD2) can be deposited on a first gate electrode (GE1) and a blocking layer (BML). Subsequently, to form a second pre-semiconductor pattern (P-SP2, see FIG. 5f), a second pre-semiconductor layer (P1-SP2) and a third photoresist layer (PR3a) can be formed on the second insulating layer (ILD2).

[0195] The second preliminary semiconductor layer (P1-SP2) may include an oxide semiconductor material. In one embodiment, the second preliminary semiconductor layer (P1-SP2) may include an oxide semiconductor material and a transparent conductive material having an amorphous crystal structure.

[0196] To pattern the second pre-semiconductor layer (P1-SP2), a third mask (MSK3a) with a third opening (OP-M3) defined therein can be provided on the third photoresist layer (PR3a). The third opening (OP-M3) may correspond to an area where the second pre-semiconductor pattern (P-SP2) is formed. Subsequently, through exposure, development, and etching processes, the second pre-semiconductor pattern (P-SP2) corresponding to the third openings (OP-M3) can be formed as shown in FIG. 5f. Here, the second pre-semiconductor pattern (P-SP2) may correspond to a semiconductor pattern before the doping process is performed.

[0197] Referring to FIG. 5g, a third insulating layer (ILD3) can be deposited on a second pre-semiconductor pattern (P-SP2). Subsequently, to form a second gate electrode (GE2, see FIG. 5h), a second pre-gate electrode layer (P-GE2) and a fourth photoresist layer (PR4a) can be formed on the third insulating layer (ILD3).

[0198] To pattern the second preliminary semiconductor pattern (P-SP2), a fourth mask (MSK4a) with defined fourth openings (OP-M4) can be provided on the fourth photoresist layer (PR4a). At least some of the fourth openings (OP-M4) may overlap the second preliminary semiconductor pattern (P-SP2) and may correspond to an area defined as an active region (A21, see FIG. 5h) to be formed thereafter.

[0199] Meanwhile, in the step of forming the second gate electrode (GE2, see FIG. 5h), the first upper electrode (C2, see FIG. 5h) can be formed simultaneously using the same fourth mask (MSK4a). Thus, some of the fourth openings (OP-M4) may correspond to the area where the first upper electrode (C2, see FIG. 5h) is formed. In one embodiment, some of the fourth openings (OP-M4) may overlap with the first gate electrode (GE1) in a plane. Subsequently, a second conductive pattern having a pattern corresponding to the fourth openings (OP-M4) can be formed through exposure, development, and etching processes.

[0200] Referring to FIG. 5h, a portion of the second conductive pattern may be formed as a second gate electrode (GE2), and another portion of the second conductive pattern may be formed as a first upper electrode (C2). The second gate electrode (GE2) may be used as a mask to dope the second preliminary semiconductor pattern (P-SP2), and a second semiconductor pattern (SP2) including conductive regions (A22, A23) and an active region (A21) may be formed by the doping process. The second semiconductor pattern (SP2) and the second gate electrode (GE2) may be defined as the aforementioned second transistor (T2).

[0201] A first gate electrode (GE1) and a first upper electrode (C2) that overlap at least partially on a plane can form a first capacitor (CAP1). By forming the first upper electrode (C2) through the same process as the second gate electrode (GE2), the first capacitor (CAP1) can be formed without increasing the number of masks.

[0202] Referring to FIG. 5i, the fourth insulating layer (ILD4) can be deposited on the second gate electrode (GE2) and the first upper electrode (C2). To form a contact hole overlapping the first semiconductor pattern (SP1), a fifth photoresist layer (PR5a) can be applied on the fourth insulating layer (ILD4).

[0203] A fifth mask (MSK5a) may be provided, in which fifth openings (OP-M5) are defined on a fifth photoresist layer (PR5a). Some of the fifth openings (OP-M5) may overlap the first semiconductor pattern (SP1), other parts of the fifth openings (OP-M5) may overlap the blocking layer (BML), and yet another part may overlap the second gate electrode (GE2). That is, contact holes (CH1, CH2-1, CH2-2, see FIG. 5j) corresponding to the semiconductor pattern (SP1), the blocking layer (BML), and the second gate electrode (GE2) can be formed using one fifth mask (MSK5a).

[0204] Referring to FIG. 5j, a contact hole (CH1) penetrating the first to fourth insulating layers (ILD1 to ILD4) can be formed by exposing a portion of the first semiconductor pattern (SP1) through a photolithography process using the fifth mask (MSK5a). During the process of forming the contact hole (CH1) that exposes a portion of the first semiconductor pattern (SP1), a phenomenon in which the upper part of the first semiconductor pattern (SP1) is partially oxidized may occur. Therefore, a Buffered Oxide Etch (BOE) process can be performed as a subsequent process to remove the oxidized portion of the upper part of the first semiconductor pattern (SP1). Meanwhile, the first gate electrode (GE1) and the blocking layer (BML) may be affected during the BOE process, and the first gate electrode (GE1) and the blocking layer (BML) are each titanium nitride (TiN x By including a second layer (G2, B2) containing ), the second layer (G2, B2) can function as a sacrificial layer and be etched instead. Thus, a contact hole (CH2-2) overlapping the blocking layer (BML) can be formed by penetrating the second layer (B2) of the blocking layer (BML). As a result, the first gate electrode (GE1) and the first layers (G1, B1) of the blocking layer (BML) can be protected.

[0205] After forming a contact hole (CH1) that exposes a part of the first semiconductor pattern (SP1), a contact hole (CH3, see FIG. 5k) that exposes a part of the second semiconductor pattern (SP2) can be formed using a different mask. The process of forming the contact hole (CH1) that exposes a part of the first semiconductor pattern (SP1) and the process of forming the contact hole (CH3, see FIG. 5k) that exposes a part of the second semiconductor pattern (SP2) may have different etching conditions, and accordingly, they may be carried out through a separate process using a separate mask.

[0206] A sixth mask (MSK6a) may be provided, in which a sixth opening (OP-M6) is defined on a sixth photoresist layer (PR6a) disposed on a fourth insulating layer (ILD4). The sixth opening (OP-M6) may be superimposed on a second semiconductor pattern (SP2).

[0207] Referring to FIG. 5k, a preliminary connection electrode layer (P-CE) and a seventh photoresist layer (PR7a) can be formed on the fourth insulating layer (ILD4). To pattern the preliminary connection electrode layer (P-CE), a seventh mask (MSK7a) with defined seventh openings (OP-M7) can be provided. The seventh openings (OP-M7) can overlap contact holes (CH1, CH2-1, CH2-2, CH3) in a plane. Some of the seventh openings (OP-M7) correspond to the area for forming the first connection electrode (CE1, see FIG. 5l), and other parts of the seventh openings (OP-M7) may correspond to the area for forming the second connection electrode (CE2, see FIG. 5l).

[0208] Referring to FIG. 5L, a first connecting electrode (CE1) connected to a first semiconductor pattern (SP1) and a second connecting electrode (CE2) connected to a second semiconductor pattern (SP2) can simultaneously form a preliminary connecting electrode layer (P-CE) patterning using the same seventh mask (MSK7a). Additionally, a second upper electrode (C3) superimposed on a first upper electrode (C2) can be formed simultaneously during the process of forming the first connecting electrode (CE1).

[0209] A first upper electrode (C2) and a second upper electrode (C3) that overlap at least partially on a plane can form a second capacitor (CAP2). By forming the second upper electrode (C3) through the same process as the first and second connecting electrodes (CE1, CE2), the second capacitor (CAP2) can be formed without increasing the number of masks.

[0210] Referring to FIG. 5m, a fifth insulating layer (ILD5) can be deposited on the first and second connecting electrodes (CE1, CE2). In one embodiment, the fifth insulating layer (ILD5) may be formed as a single organic film. However, the embodiment is not limited thereto. To form a contact hole (CH4, see FIG. 5n) penetrating the fifth insulating layer (ILD5), an eighth photoresist layer (PR8a) may be applied on the fifth insulating layer (ILD5), and then an eighth mask (MSK8a) may be provided on the eighth photoresist layer (PR8a), in which an eighth opening (OP-M8) corresponding to the contact hole (CH4, see FIG. 5n) formation area is defined.

[0211] Referring to FIG. 5n, after forming a contact hole (CH4) that penetrates the fifth insulating layer (ILD5) and exposes a portion of the first connecting electrode (CE1), a preliminary pixel electrode layer (P-AE) and a ninth photoresist layer (PR9a) can be formed on the fifth insulating layer (ILD5). A ninth mask (MSK9a) can be provided on the ninth photoresist layer (PR9a), in which a ninth opening (OP-M9) corresponding to a pixel electrode (AE, see FIG. 5o) formation area is defined. Subsequently, through exposure, development, and etching processes, a pixel electrode (AE) connected to the first connecting electrode (CE1) can be formed as shown in FIG. 5o.

[0212] Referring to FIG. 5o, in order to form a pixel defining film (PDL, see FIG. 5p) on a pixel electrode (AE) and a fifth insulating layer (ILD5), a preliminary pixel defining film layer (P-PDL) and a tenth photoresist layer (PR10a) may be formed. To pattern the preliminary pixel defining film layer (P-PDL), a tenth mask (MSK10a) in which a tenth aperture (OP-M10) is defined on the tenth photoresist layer (PR10a) may be provided. The tenth aperture (OP-M10) may correspond to a region for forming a light-emitting aperture (OP-P, see FIG. 5p). Subsequently, through exposure, development, and etching processes, a light-emitting aperture (OP-P) penetrating the pixel defining film (PDL) and exposing at least a portion of the pixel electrode (AE) may be formed as shown in FIG. 5p.

[0213] Subsequently, although not separately illustrated, the display panel (DP) of FIG. 3a can be formed through a process of forming a light-emitting layer (EML) and a counter electrode (CE) on a pixel electrode (AE).

[0214] FIGS. 6a to 6M are cross-sectional views sequentially illustrating the manufacturing steps of a display panel according to an embodiment of the present invention. A display panel (DP) of an embodiment formed through the manufacturing steps illustrated in FIGS. 6a to 6M may correspond to a display panel (DP) illustrated in FIG. 4b.

[0215] Referring to FIG. 6a, a first preliminary semiconductor pattern (P-SP1) can be formed on a buffer layer (BFL) through the process steps illustrated in FIG. 5a and FIG. 5b. Subsequently, a second preliminary semiconductor pattern layer (P1-SP2) can be formed on the buffer layer (BFL). A portion of the second preliminary semiconductor pattern layer (P1-SP2) can be superimposed on the first preliminary semiconductor pattern (P-SP1) in a planar manner.

[0216] After forming the second pre-semiconductor layer (P1-SP2), a second photoresist layer (PR2b) can be applied on the second pre-semiconductor layer (P1-SP2). To pattern the second pre-semiconductor layer (P1-SP2), a second mask (MSK2b) in which a second opening (OP-M2) is defined corresponding to the area where the second semiconductor pattern (SP2, FIG. 6b) is formed can be provided on the second photoresist layer (PR2b). Subsequently, the second pre-semiconductor pattern (SP2) can be formed through exposure, development, and etching processes. Referring to FIG. 6b, the first pre-semiconductor pattern (SP1) and the second pre-semiconductor pattern (SP2) can be formed on the same layer.

[0217] Referring to FIGS. 6c and 6d, a second insulating layer (ILD2) corresponding to the second insulating layer (ILD2) of FIG. 4b may be applied on the first pre-semiconductor pattern (SP1) and the second pre-semiconductor pattern (SP2). Since the first pre-semiconductor pattern (SP1) and the second pre-semiconductor pattern (SP2) are formed on the same layer, the process of forming the first insulating layer (ILD1) of FIG. 4a may be omitted.

[0218] The preliminary gate electrode layer (P-GE) and the third photoresist layer (PR3b) may be formed on the second insulating layer (ILD2). The description regarding the preliminary gate electrode layer (P-GE) may be applied in the same way as the description of the first preliminary gate electrode layer (P-GE1, see FIG. 5c) described above.

[0219] To pattern the preliminary gate electrode layer (P-GE), a third mask (MSK3b) with defined third openings (OP-M3) can be provided on the third photoresist layer (PR3b). Some of the third openings (OP-M3) may overlap the first preliminary semiconductor pattern (SP1), and other parts of the third openings (OP-M3) may overlap the second preliminary semiconductor pattern (SP2).

[0220] The first gate electrode (GE1) of the first transistor (T1) and the second gate electrode (GE2) of the second transistor (T2) can be formed simultaneously using the same third mask (MSK3b). Accordingly, the first gate electrode (GE1) and the second gate electrode (GE2) may contain the same material and may be placed on the same layer. By forming the first gate electrode (GE1) and the second gate electrode (GE2) in the same process step, the number of masks for forming the first gate electrode (GE1) and the second gate electrode (GE2) can be reduced and the process can be simplified.

[0221] Referring to FIGS. 6e and 6f, a third insulating layer (ILD3) and a fourth photoresist layer (PR4b) can be formed on the first gate electrode (GE1) and the second gate electrode (GE2). A fourth mask (MSK4b) with fourth openings (OP-M4) defined on the fourth photoresist layer (PR4b) can be provided. Through holes (CH1, CH2) exposing a portion of the first semiconductor pattern (SP1) and a portion of the second gate electrode (GE2) can be formed using the fourth mask (MSK4b). As described above, the second layer (G2) of the first gate electrode (GE1) and the second layer (G2) of the second gate electrode (GE2) can act as sacrificial layers during the process of forming the through holes (CH1, CH2) to protect the first layer (G1) of the first and second gate electrodes (GE1, GE2).

[0222] After forming through holes (CH1, CH2), a preliminary connection electrode layer (P-CE) and a fifth photoresist layer (PR5b) can be formed on the third insulating layer (ILD3). A fifth mask (MSK5b) with fifth openings (OP-M5) defined on the fifth photoresist layer (PR5b) can be provided.

[0223] Referring to FIG. 6g, a first connecting electrode (CE1) and a first upper electrode (C2) can be formed using the same fifth mask (MSK5b). A first gate electrode (GE1) and a first upper electrode (C2) that overlap at least partially on a plane can form a first capacitor (CAP1). Thus, the first capacitor (CAP1) can be formed without a separate additional process, and the display panel (DP) manufacturing process can be simplified. A portion of the patterned preliminary connecting electrode layer (P-CE) can be formed into a connecting line (CL) connected to a second gate electrode (GE2).

[0224] Referring to FIGS. 6h and 6i, a fourth insulating layer (ILD4) can be deposited on the first connecting electrode (CE1) and the first upper electrode (C2). In one embodiment, the fourth insulating layer (ILD4) may be formed as a single organic film. However, the embodiment is not limited thereto. To form a contact hole (CH4) penetrating the fourth insulating layer (ILD4), a sixth photoresist layer (PR6b) may be formed on the fourth insulating layer (ILD4), and then a sixth mask (MSK6b) may be provided on the sixth photoresist layer (PR6b), in which a sixth opening (OP-M6) corresponding to the contact hole (CH4) formation area is defined.

[0225] In one embodiment, a contact hole (CH3) corresponding to a second semiconductor pattern (SP2) can be formed simultaneously during the process of forming a contact hole (CH4) that exposes a part of the first connecting electrode (CE1). The contact hole (CH4) that exposes a part of the first connecting electrode (CE1) can be formed by penetrating only the fourth insulating layer (ILD4) provided as an organic film, but the contact hole (CH3) corresponding to the second semiconductor pattern (SP2) must be formed by penetrating the second to fourth insulating layers (ILD2 to ILD4). Therefore, during the process of forming the contact hole (CH3) corresponding to the second semiconductor pattern (SP2), a problem may occur in which the fourth insulating layer (ILD4) provided as an organic film is etched or damaged more than required. Therefore, to prevent damage to the fourth insulating layer (ILD4) during the etching process, a hard mask layer (HFL) can be placed on the fourth insulating layer (ILD4).

[0226] The hard mask layer (HFL) may include a material with a high selectivity ratio relative to the second semiconductor pattern (SP2). Through this, the hard mask layer (HFL) can prevent the insulating layers or the second semiconductor pattern (SP2) from being excessively etched.

[0227] Referring to FIG. 6j and FIG. 6k, after forming contact holes (CH3, CH4) penetrating the fourth insulating layer (ILD4), the hard mask layer (HFL) can be removed. On the fourth insulating layer (ILD4) from which the hard mask layer (HFL) has been removed, a preliminary pixel electrode layer (P-AE) and a seventh photoresist layer (PR7b) can be formed.

[0228] A seventh mask (MSK7b) may be provided on the seventh photoresist layer (PR7b) in which seventh openings (OP-M7) are defined. Some of the seventh openings (OP-M7) may correspond to a pixel electrode (AE) formation area. During the pixel electrode (AE) formation process, a second connecting electrode (CE2) connected to the second semiconductor pattern (SP2) may be formed simultaneously. Thus, some of the seventh openings (OP-M7) may correspond to a second connecting electrode (CE) formation area.

[0229] By forming the second connecting electrode (CE2) simultaneously during the formation step of the pixel electrode (AE), it is not necessary to additionally laminate a separate insulating layer or use a separate mask to form the second connecting electrode (CE2), and the number of masks required for manufacturing the display panel can be reduced and the manufacturing process of the display panel can be simplified.

[0230] Referring to FIGS. 6L and FIGS. 6M, a preliminary pixel defining film layer (P-PDL) and an eighth photoresist layer (PR8b) may be formed to form a pixel defining film (PDL) having a light-emitting aperture (OP-P) defined on a pixel electrode (AE) and a fourth insulating layer (ILD4). For patterning the preliminary pixel defining film layer (P-PDL), an eighth mask (MSK8b) having an eighth aperture (OP-M8) defined on the eighth photoresist layer (PR8b) may be provided. The eighth aperture (OP-M8) may correspond to a region for forming a light-emitting aperture (OP-P). Through a photoprocess using the eighth mask (MSK8b), a light-emitting aperture (OP-P) exposing at least a portion of the pixel electrode (AE) may be formed on the pixel defining film (PDL).

[0231] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0232] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0233] DP: Display Panel BS: Base Board OLED: Light-emitting element AE: Pixel electrode CE: Counter electrode CAP1, CAP2: Capacitor SL1~SLn, GL1~GLn, HL1~HLn: Injection lines DL1~DLn: Data lines PXij: Pixel T1: First transistor SP1: First semiconductor pattern GE1: First gate electrode CE1: First connection electrode T2: Second transistor SP2: Second semiconductor pattern GE2: Second gate electrode CE2: Second connection electrode ILD1~ILD5: Insulation layer

Claims

Claim 1 A display panel comprising: a first transistor including a first semiconductor pattern comprising either a silicon semiconductor or an oxide semiconductor and a first gate electrode superimposed on a plane with the first semiconductor pattern; a second transistor including a second semiconductor pattern different from the first semiconductor pattern and a second gate electrode superimposed on a plane with the second semiconductor pattern; a first upper electrode superimposed on a plane with the first gate electrode; a first connecting electrode connected to the first semiconductor pattern by penetrating at least one insulating layer; and a light-emitting element disposed on the first connecting electrode, wherein a single insulating layer is disposed between the light-emitting element and the first connecting electrode, and the first connecting electrode and the light-emitting element are connected through a through hole penetrating the single insulating layer, and the first upper electrode is disposed on the same layer as the second gate electrode and is disposed on the second semiconductor pattern, or the first upper electrode is disposed on the same layer as the second semiconductor pattern, or the first gate electrode is disposed on the same layer as the second gate electrode, and each of the first gate electrode and the second gate electrode comprises a first layer and a second layer. Claim 2 In claim 1, the first gate electrode comprises a plurality of layers, and the uppermost layer among the plurality of layers is titanium nitride (TiN x A display panel including ). Claim 3 In claim 1, the display panel comprises at least one insulating layer disposed between the first semiconductor pattern and the first gate electrode; and a second insulating layer disposed on the first gate electrode. Claim 4 In claim 3, the first insulating layer is a display panel disposed between the second semiconductor pattern and the second gate electrode. Claim 5 In claim 3, the at least one insulating layer further comprises a third insulating layer disposed on the second insulating layer, wherein the second insulating layer is disposed below the second semiconductor pattern, and the third insulating layer is disposed between the second semiconductor pattern and the second gate electrode, forming a display panel. Claim 6 delete Claim 7 In claim 1, the second gate electrode is a display panel positioned above the first gate electrode. Claim 8 In claim 1, the first upper electrode is a display panel disposed on the same layer as the first connecting electrode. Claim 9 In claim 1, the first upper electrode is a display panel disposed on the same layer as the second gate electrode. Claim 10 In claim 1, the first upper electrode is a display panel disposed on the same layer as the second semiconductor pattern. Claim 11 A display panel according to claim 1, further comprising a second upper electrode that overlaps the first upper electrode on a plane, wherein the first upper electrode is disposed between the first gate electrode and the second upper electrode, and the second upper electrode is disposed on the same layer as the first connecting electrode. Claim 12 A display panel according to claim 1, further comprising a second connecting electrode connected to the second semiconductor pattern by penetrating the at least one insulating layer, wherein the second connecting electrode is disposed on the same layer as the first connecting electrode. Claim 13 A display panel according to claim 1, further comprising a second connecting electrode connected to the second semiconductor pattern by penetrating the at least one insulating layer, wherein the second connecting electrode is disposed on the same layer as the light-emitting element. Claim 14 A display panel according to claim 1, further comprising a blocking layer disposed on the same layer as the first gate electrode, wherein the blocking layer overlaps the second semiconductor pattern on a plane. Claim 15 In claim 14, the second semiconductor pattern is disposed between the blocking layer and the second gate electrode, and the blocking layer is electrically connected to the second gate electrode. Claim 16 A display panel according to claim 1, further comprising: a first signal line disposed on the same layer as the first gate electrode and comprising the same material as the first gate electrode; and a second signal line disposed on the same layer as the first connecting electrode and comprising the same material as the first connecting electrode. Claim 17 A display panel comprising: a first transistor including a silicon semiconductor pattern and a first gate electrode superimposed on a plane with the silicon semiconductor pattern; a second transistor including an oxide semiconductor pattern and a second gate electrode superimposed on a plane with the oxide semiconductor pattern; a first capacitor including a first electrode integrally connected to the first gate electrode and a second electrode superimposed on the first electrode; a first connecting electrode connected to the silicon semiconductor pattern; a second connecting electrode connected to the oxide semiconductor pattern; a first insulating layer disposed between the oxide semiconductor pattern and the second gate electrode; a second insulating layer disposed between the first electrode and the second electrode; a third insulating layer disposed on the first connecting electrode; and a pixel electrode connected to the first connecting electrode through a first contact hole penetrating the third insulating layer, wherein the second connecting electrode is disposed on the same layer as the pixel electrode and is connected to the oxide semiconductor through a second contact hole penetrating the first to third insulating layers. Claim 18 A display panel comprising: a first transistor including a silicon semiconductor pattern and a first gate electrode overlapping in a plane with the silicon semiconductor pattern; a second transistor including an oxide semiconductor pattern and a second gate electrode overlapping in a plane with the oxide semiconductor pattern; a connecting electrode connected to the silicon semiconductor pattern; a first upper electrode forming a capacitor with the first gate electrode; a second upper electrode forming a capacitor with the first upper electrode; a first insulating layer disposed between the silicon semiconductor pattern and the first gate electrode; a second insulating layer disposed between the first gate electrode and the first upper electrode; a third insulating layer disposed between the oxide semiconductor pattern and the second upper electrode; and a fourth insulating layer disposed between the first upper electrode and the second upper electrode, wherein the connecting electrode is disposed on the same layer as the second upper electrode, and the first upper electrode is disposed on the same layer as the second gate electrode and is disposed on the oxide semiconductor pattern, or the first upper electrode is disposed on the same layer as the oxide semiconductor pattern. Claim 19 In claim 18, the first upper electrode is disposed on the same layer as the second gate electrode, and the third insulating layer overlaps the first upper electrode in a plane, forming a display panel. Claim 20 In claim 18, the first upper electrode is disposed on the same layer as the oxide semiconductor pattern, and the third insulating layer is non-overlapping with the first upper electrode in a plane, forming a display panel.

Images