Processor system and method of operating it

Abstract

The present specification discloses a processor system (1) comprising a plurality of processor cores and a message exchange network, wherein the processor system (1) is configured to execute a neural network having at least a first and a second neural network layer. Among the processor cores, the first processor core is configured to transmit a plurality of activation event data as a packed message, and the packed message includes a common indication for the source of the plurality of activation event data in the first neural network layer. By doing so, the load on the message exchange network can be significantly reduced. Additionally, the number of memory accesses can be reduced.

Description

Technology Field

[0001] The present disclosure relates to a processor system comprising a plurality of processor cores and a message exchange network, wherein the processor system is configured to execute a neural network.

[0002] The present disclosure further relates to a method for operating such a processor system. Background Technology

[0003] In a processor system as disclosed herein, individual processor cores are assigned to individual neural network layers or parts thereof. That is, during execution, a processor core assigned to a neural network layer or part thereof performs computations and operations defined by the neural network elements (further denoted as neurons) within it. The phrase “assigned processor core” of a neuron will be used herein to denote a processor core assigned to a neural network layer or part thereof containing the said neuron.

[0004] In a processor system running a neural network, computation of a processor core is triggered by the arrival of an event containing an output value as a result of the activation of a neuron of the neural network executed by the processor core. Typically, the event is transmitted from the processor core where the activation is computed to all processor cores where the successors of the activated neuron are to be processed. At each of these processor cores, the event is typically processed by accessing and updating the neuron state of all successors of the activated neuron after it is received from an event queue. In the literature of this art, the neuron state is also referred to as a neuron or membrane potential. This known procedure has the following inefficiencies:

[0005] For all activation events, the coordinate values ​​of the event, as well as the identifier for the target neural network layer or part thereof, must be transmitted.

[0006] For every activation event received by a receiving processor core, the receiving processor core must read the neuron state from memory, recompile the neuron state, and write the recompiled neuron state back into the memory for each neuron to update it. Neuron state readings and writings cause a large percentage of energy consumption and consume a large percentage of available memory bandwidth when updating neuron states.

[0007] The goal is to mitigate at least some of these inefficiencies.

[0008] Accordingly, an improved processor system is presented as defined in claim 1.

[0009] Additionally, an improved method for operating a processor system is presented as defined in claim 10.

[0010] An improved processor system as defined in claim 1 comprises a plurality of processor cores and a message exchange network, wherein the processor cores are configured to exchange messages with one another using the message exchange network. In one example, the plurality of processor cores are provided on a single integrated circuit, and the message exchange network is provided as a network on chip (NoC). It is further conceivable that the improved processor system comprises a plurality of such integrated circuits coupled to each other by an additional message exchange network. The processor cores are provided as dedicated hardware configured to perform neural network operations, such as neuron state evaluation, or as programmable processor units having an instruction set including dedicated instructions for such operations.

[0011] The claimed processor system is configured to run a neural network having at least a first and second neural network layer. In reality, a neural network may have tens or hundreds of layers, but for the following description, it is assumed that there are at least two neural network layers.

[0012] The first neural network layer has a corresponding first feature map, and the second neural network layer has a corresponding second feature map. The feature map corresponding to the neural network layer includes multiple feature map data elements, each representing a neural state of an individual neuron in the neural network layer. The feature map data is addressable by a set of two or more coordinates, which includes at least position coordinates representing a position in the feature map, and channel coordinates representing an element of a feature channel at the represented position. A simple example of a feature map is an image having a matrix of image values. Pixels in the image have planar coordinates x,y and may have pixel values ​​for each of the three color channels. The color channels can be considered as feature channels. Accordingly, in this example, the feature map data can be represented by the values ​​of each color channel at each position in the feature map. In another example, the feature map is two-dimensional, where one dimension t represents time and the other dimension specifies sound channels. Likewise, in a convolutional neural network, a neural network layer generates a feature map defined by the values ​​of each feature channel at each position in the feature map. In this regard, it is assumed that the feature map is defined by a pair of channel coordinates specifying the channel and two spatial coordinates (position coordinates). However, other embodiments in which the feature map has more than two spatial coordinates, such as in a 3D image, may be considered.

[0013] The processor system is configured to execute a neural network in such a way that, at operation, it performs all operations associated with the execution of the neural network. In this specification, a first processor core among the processor cores executes at least a portion of a first neural network layer. This includes an option for the first processor core among the processor cores to execute the entire first neural network layer. At operation, it evaluates neuron states in a first feature map or its corresponding portion. The processor core evaluates neuron states, for example, by computation of autonomous state changes, for example, by computation of state changes based on a leakage model, or by performing an integration process. Additionally, the processor core may change the neuron state during evaluation in response to an event message. Based on the evaluation, the processor core generates activation event data to be transmitted to a second processor core among the processor cores that executes at least a portion of a second neural network layer. Typically, the neuron state is considered as a membrane potential. If the processor core determines that, as a result of the evaluation, the neuron's membrane potential exceeds a threshold value, then the activation event data is transmitted. In one embodiment, the processor core is configured to perform these two operations in mutually distinct operation stages. In the first stage, the processor core performs an evaluation of the state of all neurons in a neural network layer or part thereof, and in the subsequent stage, the processor core performs the operations necessary to generate activation event data. In an alternative embodiment, the processor core is configured to perform operations to generate activation event data for a neuron immediately when it determines that an activation condition (e.g., exceeding a threshold level) is met.

[0014] It is assumed that a processor core receiving an activation event message stores the neural states of the neurons executed by it in dedicated state memory. The neural network executed by the processor system may additionally include stateless neurons. A processor core executing a neural network layer containing stateless neurons computes state data from scratch each time. This may vary by layer. That is, some neural network layers may have reserved storage space accessible to the executing processor core to store their feature maps, while other neural network layers may have volatile neural state data.

[0015] When a processor core assigned to the first neural network layer generates activation event data, this is addressed to specific neurons in the second neural network layer. A second processor core executing the second neural network layer or a part thereof containing the specific neurons then updates the neural state of the specific neurons upon receiving the activation event data.

[0016] The improved processor system is characterized in that a first processor core among the processor cores is configured to transmit a plurality of activation event data, which are issued from a plurality of neurons in a first neural network layer and have a common value for at least one of their coordinates, as a packed message, wherein the packed message includes the at least one common coordinate value. In this way, a reduced load on the message exchange network is achieved in that the total amount of source coordinate data to be transmitted is less than in the case where individual source coordinate data is transmitted for each activation event. Additionally, less buffer space needs to be reserved by the receiving processor core to store the packed message than in the case without the claimed measures.

[0017] In some embodiments, a common value for at least one of the coordinates includes an individual common value for each of the position coordinates of the neurons in the first neural network layer where events bundled in the packed message are generated, and the packed message includes, for each of the plurality of activation event data, an individual indication of the channel coordinates of the neurons as well as an individual activation event value. Accordingly, the message is packed such that all activation events originate from neurons in the first neural network layer having the same feature map position coordinate values. Thereby, the values ​​of the feature map position coordinates need to be transmitted only once.

[0018] In one example of this embodiment, for each of the plurality of activation event data Channel coordinates (Z) The indication of ...includes the absolute value of the channel coordinates of the first neuron among the neurons to which the activation event data is transmitted and one or more relative values, and each of the one or more relative values ​​indicates the difference between the absolute value of the channel coordinates of the neuron to which the activation event data is transmitted and the absolute value of the channel coordinates of the preceding neuron to which the activation event data is transmitted.

[0019] The inventors recognized that, in practice, the difference between the channel coordinate values ​​of neurons with common positions in the first neural network layer generating the event is relatively small compared to the available channel coordinate address range. Consequently, relative values ​​can be encoded with significantly fewer bits than required to encode absolute channel coordinate values. Consequently, event messages can be encoded much more compactly in packed messages. For example, only one of each of the four channel coordinate values ​​is provided as an absolute address. The remaining three channel coordinate values ​​are provided as relative addresses (i.e., relative to the preceding address) with fewer bits. For example, relative channel coordinate values ​​are encoded with up to half the number of bits required to encode absolute channel coordinate values.

[0020] In this regard, it is observed that, instead of packing activation event data having common position coordinate values ​​or a common set of position coordinate values ​​in the first neural network layer, packing activation event data having common channel coordinate values ​​can be considered as an alternative. When event data having common channel coordinate values ​​is packed, the packed message includes individual indications of the respective positions of the neurons from which the event data was issued. In addition, in that case, further compactification is possible by encoding the absolute coordinate values ​​of only one of these neurons, and by encoding the relative coordinate values ​​for the other event data in a manner similar to that specified for encoding relative channel coordinate values.

[0021] However, packing activation event data with common source feature map position coordinate values ​​is considered more efficient.

[0022] In some embodiments, the second processor core performs all neuron state updates of the neuron in the second neural network layer or its part containing the neuron before it continues to perform neuron state updates of subsequent neurons in the second neural network layer or its part. Accordingly, the processor core executing the second neural network layer (or its part) containing the neuron only needs to access the storage space for the neural state data once to obtain the current state and once to rewrite the new state after it has performed updates based on multiple event data in the packed message.

[0023] In some embodiments of the processor system, a first processor core among the processor cores is configured to temporarily buffer activation event data generated while evaluating neuron states of a first feature map. This allows the activation event data to be bundled more efficiently into a packed message. For example, in the case of sparse activation, activation event data for a position having specific position coordinate values ​​can be collected in a buffer until a sufficient number of activation events having relatively small channel coordinate value differences can be packed, so that a small number of bit values ​​are sufficient to represent the differences. In one example thereof, the first processor core among the processor cores is configured to transmit a packed message for a predetermined number of buffered activation event data. In this way, the message exchange network load can be controlled. Brief explanation of the drawing

[0024] These and other embodiments are described in more detail with reference to the drawings. In the drawings: FIG. 1 schematically illustrates an embodiment of an improved processor system comprising a plurality of processor cores and a message exchange network. Figure 2 illustrates an example of the allocation of processor cores to two neural network layers of a neural network. Figure 3 schematically illustrates the feature maps of two neural network layers. Figure 4 illustrates the components of an exemplary processor core. FIG. 5 schematically illustrates embodiments of an improved method for operating an improved processor system. FIGS. 6a and 6b illustrate a header pit and a body pit emitted in a first operation mode. FIGS. 7a and 7b illustrate a header fit and a body fit emitted in the second operation mode in the first case. FIG. 8a illustrates a header pit emitted in the second operating mode in the second case. FIG. 8b illustrates a body fit that is emitted every four events in the second operation mode in the second case. FIG. 8c illustrates an additional body fit that is emitted every two events in the second operation mode in the second case. FIG. 9 illustrates the operation steps performed by the receiving processor core. Figure 10 illustrates an exemplary process for updating a single destination neuron based on multiple events in a package. Specific details for implementing the invention

[0025] Similar reference symbols in the various drawings of this application indicate similar elements unless otherwise indicated.

[0026] FIG. 1 schematically illustrates a processor system (1) comprising a plurality of processor cores (100) and a message exchange network (20). In the illustrated embodiment, the message exchange network (20) includes network nodes (21) for each processor core (100), and mutually neighboring network nodes (21) are coupled by network links (22). The processor cores (100) are configured to exchange messages with one another using the message exchange network (20). In the illustrated example, the multiprocessor system includes additional components, such as an arithmetic processor core (200) particularly suitable for arithmetic computations. The processor system (1) is additionally coupled to a host processor (300).

[0027] The processor system is configured to execute a neural network having at least first and second neural network layers. In the example illustrated in FIG. 2, the network has n layers. As an example, subsequent layers L defined herein as at least first and second neural network layers. k , L k+1 A specific reference is made to .

[0028] As schematically illustrated in FIG. 2, the first neural network layer (L k ) is the first feature map (F k It has ), and a second neural network layer (L k+1 ) is the corresponding second feature map (F k+1...has ). The feature map of a neural network layer comprises a plurality of feature map data elements, each representing the neural state of an individual neuron of the neural network layer, and the feature map data is addressable by at least two sets of coordinates, wherein the at least two sets of coordinates include at least a position coordinate, wherein a pair of position coordinates (x,y) for representing a position in the feature map, and a channel coordinate (i,z) for representing an element of a feature channel at the represented position. For example, as illustrated in FIG. 3, neural network layers (L k , L k + 1) Feature maps (F k , F k+1 ) is width D in the x-coordinate direction x and D in the y-coordinate direction y It has a height of. In the illustrated example, the first feature map (F k ) is D i It has channels, and the second feature map (F k+1 ) is D z It has channels. Accordingly, the first feature map (F k The feature map data elements of ) are uniquely addressable using a first coordinate triple, and the second feature map (F k+1 The feature map data elements of ) can be uniquely addressed using a second coordinate triple.

[0029] As schematically illustrated in FIG. 2, the first processor core among the processor cores (100)—specifically denoted as 100_k_1—is the first neural network layer (L k ) executes at least a portion of ). This means that the processor core (100_k_1) executes a first feature map (F) corresponding to at least a portion of the first neural network layer to which it is assigned. kThis means that it is configured to evaluate neuron states in at least a part of ) and, according to said evaluation, generate activation event data. As illustrated in the example of FIG. 2, each of the processor cores (100_k_1, 100_k_2, 100_k_3) is configured to have a first neural network layer (L k Executes a part of ). Partitioning implies that each of the processor cores performs computations on a subset of neurons, for example, a subset of channels, or a subset of spatial regions in a coordinate space defined by position coordinates x,y. Likewise, among the processor cores (100), the second processor core—specifically denoted as 100_k+1_1, 100_k+1_2, and 100_k+1_3—is the second neural network layer (L k+1 Execute the individual parts of ).

[0030] Activation event data generated by a first processor core, e.g., a core (100_k_1), among the processor cores is addressed to specific neurons of a second neural network layer. Upon receipt of activation event data, a second processor core, e.g., 100_k+1_1, executing a second neural network layer or a part thereof containing specific neurons, updates the neural state of these specific neurons.

[0031] In an improved processor system (1), a first processor core among the processor cores, for example, a core (100_k_1), is configured to transmit a plurality of activation event data, which are issued from a plurality of neurons in a first neural network layer and have a common value for at least one of their coordinates, as a packed message, wherein the packed message includes the at least one common coordinate value.

[0032] Figure 4 shows the first neural network layer (L kAn exemplary processor core (100) executing at least a portion of ) is schematically illustrated, for example, a core denoted as 100_k_1. As illustrated herein, the core, a first feature map (F k It includes a processor (110) configured to evaluate neuron states in ) and perform operations to generate activation event data according to said evaluation. The processor (110) provides the generated activation event data to an event queue (120). The processor core (100) further includes an event message generation module (130) configured to transmit a plurality of activation event data as a packed message.

[0033] In the illustrated embodiment, the event message generation module (130) may operate in a selected from a plurality of potential operation modes. The plurality of potential operation modes include a deep neural network operation mode denoted as DNN mode. The DNN mode of the event message generation module (130) is the operation mode most relevant to the purpose of this application, as it utilizes the regularity of the interconnections of neurons in the deep neural network to efficiently use the message exchange network as specified below. However, in the illustrated embodiment, the plurality of potential operation modes also include a data flow graph mode denoted as DFG mode. The DFG mode is particularly suitable for cases where there is no regularity of interconnections. This may apply when a processor core executes a data flow graph, where the computation units exchanging messages are actors rather than neurons. In another exemplary embodiment, the event message generation module (130) always operates in DNN mode. Again in other embodiments, the event message generation module (130) has two or more alternative potential operation modes in addition to the DNN mode.

[0034] Exemplary operations of the event message generation module (130) are further described with reference to FIG. 5. In this section, the amount of data transmitted in a single cycle through a NoC link is referred to as a phit (physical unit). A flow control unit is denoted as a fleet, representing a set of phits that are routed together. A fleet is the smallest routable unit. A single phit does not necessarily contain routing information and, accordingly, can only be routed within the context of the fleet to which it belongs. A fleet may take several cycles (=phits) to traverse the link.

[0035] In procedural block S1, the same initialization procedure is performed for the operation modes of both sides. In the initialization procedure, a message header "HDR" containing routing information for the rest of the fleet is generated, as illustrated in one of FIGS. 6a, 7a, or 8a. The router must set up a connection and (atomically) route all flies belonging to the same fleet through that connection. In this example, the field "Channel" indicates the (physical) channel to which the fleet will be routed, and the values ​​"CLY" and "CLX" encode the relative y and x hops toward the destination core. Furthermore, the field "Queue" specifies which event queue should be used by the receive processor core. Thus, the selection of the receive queue is decoupled from the selection of the physical channel. Consequently, the value of the field "Queue" no longer affects the routing and switching strategy. Following this routing information, the header pit HDR includes a field "L" which specifies the length of the fleet measured by the remaining pits, i.e., the total number of pits minus 1. Since every header pit is always followed by at least one additional pit, the length is encoded as the total number of remaining pits in the fleet minus 1. That is, when the length is zero, exactly one pit will follow the header. Finally, the header pit HDR includes a field "Mode" which serves to indicate one of the operation modes {DFG, DNN}. In DFG mode, the message encodes a single activation event. In DNN mode, the message may contain multiple activation event data. The header pit HDR further includes a content field "Content" which must be populated in additional processing steps, as specified below.

[0036] The header fit HDR is entered as the first item of the list to be included in the message. Therefore, the list "lst" is

[0037] Lst is initialized as [HDR].

[0038] As an additional initial operation in procedural block S1, an activation event is obtained from the event queue (120), which is denoted by the following symbol:

[0039] e = EvtQ.pop()

[0040] Also, the item counter "i" is initialized.

[0041] i = 0

[0042] Subsequently, in procedural block S2, it is determined whether the event message generation module (130) operates in DFG mode or DNN mode. This is indicated in the mode field of the header fit HDR.

[0043] If the event message generation module (130) is in DFG mode, it continues to procedural block S3. In this case, the address of a destination neuron within a destination neural network layer or part thereof executed by the destination core is specified in the content field of the header fit HDR as shown in FIG. 6a. The destination neuron is specified in the event message obtained from the queue (120) as e.nid.

[0044] The list is further extended to body fit B1 as shown in FIG. 6b, where the value field is assigned the value e.value of event e. The abbreviation "RSV" is used in FIG. 6b and other figures to indicate a reserved field. It will be recognized that the reserved field may be used, for example, to specify a value to be conveyed with higher precision in this case, or for other purposes.

[0045] After that, the operation terminates in procedural block S4, where the length of the message is specified in field L of the header fit HDR. As mentioned above, to use the field efficiently, the length is specified as the length of list [HDR, B1] minus 2, i.e., L = 0 here. After that, the list is emitted.

[0046] If it is determined in procedural block S2 that the event message generation module (130) operates in DNN mode, then in procedural block S5 this is indicated in the mode field mode of the header fit HDR in the list (see FIG. 7a) (mode = DNN).

[0047] Subsequently, in procedural block S6, it is determined whether the event queue (120) is empty or not. If it is, the procedure continues to procedural block S7, where body fit B2 as shown in FIG. 7b is added to the list. The value field inside it is assigned the value e.value of the activation event. Also inside it, the channel coordinate value of the neuron to which the event is addressed and, together with it, a mark PID indicating the set of weights to be used by the receiving processor core are specified.

[0048] Following procedural block S7, the operation is completed with procedural block S4 as specified above. That is, list lst [HDR, B2] is transmitted.

[0049] If it is determined in procedural block S6 that the event queue (120) is not empty, it is determined in procedural block S8 whether the value counter i mod 4 is equal to 0 or not. If it is, the next procedural block is S9. Otherwise, the next procedural block is S10. The header HDR, as illustrated in FIG. 8a, indicates the total number of blocks in the list having field L. The value of L is the number of blocks (pits) minus 2.

[0050] In procedural block S9, a body fit B3 as illustrated in FIG. 8b is attached to the list. The field PID is assigned the value B3.PID = e.PID, which is the channel coordinate value of the neuron that is the source of event e. This determines the first set of weights to be used by the receiving processor core. The event message generation module (130) temporarily stores this channel coordinate value as the variable "base", i.e., base = e.PID.

[0051] In procedural block S10, field Δk—in this case, k = 1, 2, or 3—is assigned a value representing the difference between the value of the PID at the current event and the value stored in the variable base. That is, field B3.Δk = e.PID - base, where k = i mod 4.

[0052] After that, the value of the current event's PID is assigned to the variable base, that is, base = e.PID.

[0053] In exceptional cases, the value e.PID-base may exceed the maximum value that can be encoded in field B3.Δk. In that case, other procedural steps may be performed to transmit event data. For example, in that case, event data may be transmitted by using a type B2 fit as shown in FIG. 7b.

[0054] Subsequently, after executing either procedural block S9 or S10, the procedure executes procedural block S11, where the value counter iIt is determined whether or not is a multiple of 2. If so, a new body fit B4, as illustrated in FIG. 8c, is attached to the list in procedural block S12. Procedural block S12 leads to procedural block S13, where the field Valuek (where k = 1 or 2) is assigned the value of the currently active event e, that is, the last event retrieved from the event queue (120). Thus, B4.value_k = e.value, where k = i mod 2.

[0055] Value in procedural block S11 i If it is determined that is not a multiple of 2, then the procedure skips procedural block S12 and instead proceeds directly to procedural block S13.

[0056] Procedural block S13 leads to procedural block S14, which determines whether or not a stopping condition is observed. The stopping condition is observed in any of the following cases:

[0057] a) The event queue is empty

[0058] b) The event counter has a predetermined maximum value, for example, 7.

[0059] If the stop condition is met, the operation terminates with procedural block S4 as specified above.

[0060] If the stop condition is not observed, the operation continues to procedural block S15, where the next event e is popped from the event queue and the event counter i is incremented by 1. Procedural block S15 leads to procedural block S8 as described above.

[0061] Accordingly, in the illustrated embodiment, when operating in DFG mode, the event message generation module (130) will transmit a message containing the header HDR of FIG. 6a and the body fit B1 of FIG. 6b. When operating in DNN mode, if there is only one activation event in the event queue (120), it will transmit a message containing the header HDR of FIG. 7a and the body fit B2 of FIG. 7b. If the event message generation module (130) operates in DNN mode and the event queue (120) contains more than one activation event, it will transmit a packed message containing the header HDR as illustrated in FIG. 8a, followed by body fits of type B3 (Fig. 8b) and B4 (Fig. 8c). Subsequently, the packed message is: HDR [B3, B4, B4] n1 [B3,B4] n2 Includes a list having specific pits as.

[0062] Note that in the example described above, it is assumed that the maximum number of activation events to be packed is 8. In alternative embodiments, fewer or more events are packed. Additionally, other pit types for transmitting packed messages may be considered. For example, a pit of type B3 may be replaced with a pit having more or fewer address fields, or a pit of type B4 may be replaced with a pit having more or fewer value fields. Additionally, pits of a type having both address and value fields may be considered.

[0063] As mentioned above, the processor core (100) includes a processor (110) configured to perform operations to evaluate neuron states in a feature map, e.g., a feature map (Fk), and to generate activation event data based on said evaluation. According to one option, the processor (110) performs the evaluation of neuron states and the generation of activation event data in mutually separate operational phases. According to another option, which is more common in neuromorphic and other event-based AI machines, there are no separate read phases. According to this option, for each update of the neuron's neural state resulting from an event, the allocated processor core evaluates the neuron's activation function, and if the allocated processor core determines that the neuron's state complies with a firing condition, it generates an output event.

[0064] In one example, the processor (110) updates the neural states of the neurons in Z-first order. That is, the processor core updates the neural states to a sequence of feature map elements arranged along the z-axis having predetermined pairs of position coordinate values ​​x,y before proceeding to the next sequence of feature map elements arranged along the z-axis having different pairs of x,y coordinate values. If all updates of the current input event are evaluated in the target Z-first order, then the activation events generated from the updates can be efficiently bundled for transmission as packed messages. Note that activation events can be bundled differently. For example, it can be considered as bundling event messages obtained by evaluating neurons in a region of the XY plane, or even on the entire XY plane, while keeping the Z-coordinate values ​​constant. This approach enables the reuse of some of the state information and weights, but due to sparsity, not all state information can be preserved.

[0065] If the allocated processor core performs neuron state evaluation and the generation of activation event data in mutually distinct operation phases, then it is sufficient to generate the activation events merely in a specific order.

[0066] In the embodiment of FIG. 5, the common display in the packed message includes individual values ​​for each of the first and second position coordinates (X,Y), and for each of the plurality of activation event data, a display of the channel coordinate value (Z) and individual activation event value.

[0067] FIG. 9 illustrates operations performed by a processor core receiving a message as transmitted in the procedure of FIG. 5.

[0068] In procedural block S21, the receiving processor core receives the message header HDR.

[0069] In procedural block S22, the receiving processor core identifies the mode indicated in the header HDR.

[0070] When the mode is indicated as DFG, the receiving processor core proceeds to procedural block S23, where it further receives a body fit of type B1 as shown in FIG. 6b, and subsequently updates a single neuron identified in header HDR based on the transmitted value contained in the body fit B1.

[0071] If the mode is indicated as DNN, the receiving processor core proceeds to procedural block S24, where it determines whether the value L is different from 0 or not.

[0072] If the value L is equal to 0, the receiving processor core proceeds to procedural block S25, where it further receives a body fit of type B2 as shown in FIG. 7b, and subsequently updates a single neuron identified in header HDR (Fig. 7a) and body fit B2 (Fig. 7b) based on the transmitted value contained in body fit B2.

[0073] If the value L is greater than 0, the receiving processor core initializes the data element counter i to 0 and proceeds to procedural block S26, where it additionally receives a body fit of type B3 as illustrated in FIG. 8b. The body fit B3 includes absolute channel coordinate values ​​of a first neuron addressed by an event in the packed message, and relative channel coordinate values ​​of one or more other neurons addressed by other events in the packed message. Each relative channel coordinate value represents the difference between the z-coordinate of the associated source neuron and the z-coordinate of the source neuron associated with the preceding event in the packed message. Relative channel coordinate values ​​are specified by a smaller number of bits than absolute channel coordinate values. For example, the number of bits reserved for each relative channel coordinate value is at most half the number of bits reserved for the absolute channel coordinate value.

[0074] After that, the receiving processor core proceeds to procedural block S27, where it additionally receives a body fit of type B4 as illustrated in FIG. 8c, which contains data value information.

[0075] In the subsequent procedural block S28, the receiving processor core inputs data elements from the data received in procedural blocks S26 and S27. The receiving cluster may immediately perform neural network update operations based on the received data elements, but alternatively, it may buffer the received data elements before performing the update operations.

[0076] In the subsequent procedural block S29, the receiving processor core increments the data element counter by 1.

[0077] If it is determined in procedural block S30 that the counter has reached the maximum value, the procedure stops at procedural block S31. At this point, the receiving processor core will anticipate a new header block.

[0078] If the maximum value has not yet been reached, the receiving processor core checks whether the data element counter is a multiple of 2 or not. If it is not (No), it proceeds to the execution of procedural block S28. If the receiving processor core determines that the data element counter is indeed a multiple of 2 (Yes), the receiving processor core further checks whether the data element counter is a multiple of 4 or not. If it is not (No), it proceeds to the execution of procedural block S27. Otherwise (Yes), it proceeds to the execution of procedural block S26.

[0079] If it is determined in procedural block S30 that a maximum value is reached, then the operation proceeds to procedural block S31. At this point, the receiving core receives a list of event data for updating the state value of a neuron with neuron coordinate values ​​[z][y'][x']. Each item j in the list contains the event value Vj of the source neuron and the corresponding pattern index j of the weight to be used. The event values ​​are elements {Source[j1][y][x], Source[j2][y][x], ..., Source[j N ][y][x]} is.

[0080] Pattern indices j1, j2, ..., j N These can be consecutive values, but this is not essential, especially when activations are sparse. As discussed above, pattern indices are transmitted in an encoded form. That is, the absolute value of the first pattern index is transmitted in the field PID of fit block B3, and the three differences between subsequent pattern index values ​​are transmitted in fields Δ1, Δ2, and Δ3. In procedural block S31, the absolute pattern index values ​​are computed. That is,

[0081] j1= PID, j2= j1+ Δ1, j3= j2+ Δ2, j4= j3+ Δ3

[0082] Likewise, if you use the information from the subsequent pit block B3

[0083] j5= PID, j6= j5+ Δ1, j7= j6+ Δ2, j8= j7+ Δ3

[0084] FIG. 10 illustrates a method for efficiently updating the state value of a neuron having neuron coordinate values ​​[z][y'][x'] using data obtained from a packed message by a receiving processor core.

[0085] In procedural block S41 of the procedure of Fig. 10, the receiving processor core assigns the state value of a neuron with neuron coordinate values ​​[z][y'][x'] to a temporary variable.

[0086] Tmp = Destination[z][y'][x']

[0087] In procedural block S43, it is verified whether counter m has reached its maximum value. The maximum value is displayed in header block HDR.

[0088] If this is not the case, the receiving processor core proceeds to procedural block S43 and updates the value stored in the temporary value as follows:

[0089] Tmp += Source[m] * W[z][j m ][y'-y][x'-x], where

[0090] W[z][j m ][l][k] is the weight value.

[0091] The weight is, index [z][j m It is retrieved from a location in the pattern memory having ][y'-y][x'-x], where z is the Z-coordinate value of the destination neuron, and j m is a pattern index reconstructed from the packed message.

[0092] Subsequently, the receiving processor core increments counter m in procedural block S44 and proceeds to verification in block S42.

[0093] If it is determined in block S42 that counter m has reached its maximum value, the procedure terminates in procedural block S45, where the receiving processor core writes the value of temporary variable tmp to the neuron with neuron coordinate values ​​[z][y'][x']. Otherwise, the procedure continues to block S43.

[0094] Due to the fact that the event message generation module (130) of the transmitting processor core (100) has transmitted multiple activation event data having the same destination neuron as a packed message, the receiving processor core only needs to access the memory location for that neuron only once for the read operation and only once for the write operation to perform all updates.

[0095] In the following claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude the plural. A single component or other unit may perform the functions of some items mentioned in the claims. The mere fact that certain measures are mentioned in mutually different claims does not indicate that a combination of these measures cannot be used to obtain an advantage. Any reference numerals in the claims should not be interpreted as limiting the category.

Claims

Claim 1 A processor system comprising a plurality of processor cores and a message exchange network, wherein the processor cores are configured to exchange messages with one another using the message exchange network, and the processor system is configured to execute a neural network having at least a first neural network layer and a second neural network layer, wherein the first neural network layer has a corresponding first feature map and the second neural network layer has a corresponding second feature map, and the feature map corresponding to the neural network layer of the neural network includes a plurality of feature map data elements each indicating the neural state of an individual neuron of the neural network layer, and the feature map data is addressable by a set of at least two coordinates, wherein the set of at least two coordinates includes one or more position coordinates (X,Y) indicating a position in the feature map and a channel coordinate (Z) indicating an element of a feature channel at the indicated position, and a first processor core among the processor cores that executes at least a part of the first neural network layer evaluates the neuron states in the first feature map, and according to the evaluation, the processor cores The processor core is configured to generate activation event data to be transmitted to a second processor core executing at least a part of the second neural network layer, said activation event data is addressed to specific neurons of the second neural network layer, said processor core is configured to update the neural state of said specific neurons upon receiving said activation event data, and said processor core is configured to transmit a plurality of activation event data issued from a plurality of neurons in the first neural network layer and having a common value for at least one of their coordinates as a packed message, said packed message is characterized by including an indication for said at least one common coordinate value.Processor system., Claim 2 A processor system according to claim 1, wherein the indication in the packed message comprises individual values ​​for each position coordinate (X,Y) of the neurons in the first neural network layer to which activation event data is transmitted, an indication of the channel coordinate (Z) of the neurons for each activation event data among the plurality of activation event data, and individual activation event values ​​for the activation event data. Claim 3 A processor system according to paragraph 2, wherein the indication of the channel coordinate (Z) for each of the plurality of activation event data in the packed message comprises an absolute value of the channel coordinate of a first neuron among the neurons in the first neural network layer to which the activation event data is transmitted and one or more relative values, and each of the one or more relative values ​​indicates the difference between the absolute value of the channel coordinate of a neuron in the first neural network layer to which the activation event data is transmitted and the absolute value of the channel coordinate of a preceding neuron in the first neural network layer to which the activation event data is transmitted. Claim 4 A processor system according to claim 1 or 2, wherein the plurality of activation event data in the packed message are directed to a single neuron in the second neural network layer. Claim 5 A processor system according to claim 1, wherein the first processor core among the processor cores is configured to temporarily buffer activation event data generated while evaluating the neuron states of the first feature map. Claim 6 A processor system according to claim 5, wherein a first processor core among the processor cores is configured to transmit the packed message for a predetermined number of buffered activation event data. Claim 7 A processor system according to claim 5, wherein the first processor core among the processor cores is configured to transmit the packed message for buffered activation event data related to a single position in the first feature map specified by one or more position coordinates (X, Y) in the feature map when proceeding to evaluate the next position in the first feature map. Claim 8 A processor system according to claim 5, wherein a first processor core among the processor cores is configured to transmit the packed message for buffered activation event data related to a range corresponding to a position in the first feature map specified by one or more position coordinates (X,Y) in the feature map when proceeding to evaluate the next position in the first feature map, and the buffered activation event data has a common destination range in the corresponding neurons of the second feature map. Claim 9 A processor system according to claim 1, wherein the second processor core performs all updates of the neuron states of the neurons in the second neural network layer based on each of the activation event data in the packed message to which the neuron is the destination, before proceeding to update the neuron states of other neurons in the second neural network layer upon receipt of the packed message. Claim 10 A method for operating a processor system comprising a plurality of processor cores, comprising the step of configuring the processor system to execute a neural network having at least a first neural network layer and a second neural network layer, wherein the first neural network layer has a corresponding first feature map and the second neural network layer has a corresponding second feature map, and the feature map corresponding to the neural network layer of the neural network comprises a plurality of feature map data elements each representing the neural state of an individual neuron of the neural network layer, and the feature map data is addressable by a set of at least two coordinates, wherein the set of at least two coordinates comprises one or more position coordinates (X,Y) for representing a position in the feature map and a channel coordinate (Z) for representing an element of a feature channel at the represented position, and wherein the first processor core among the processor cores executes at least a part of the first neural network layer and the second processor core among the processor cores executes at least a part of the second neural network layer, and the first processor core among the processor cores A method comprising the steps of evaluating neuron states in a first feature map and, based on the evaluation, generating activation event data, and transmitting the activation event data to a second processor core among the processor cores, wherein the activation event data is addressed to specific neurons of the second neural network layer, the second processor core among the processor cores updates the neural states of the specific neurons based on the activation event data, and the first processor core among the processor cores transmits a plurality of activation event data, which are issued from a plurality of neurons in the first neural network layer and have a common value for at least one of their coordinates, as a packed message, wherein the packed message includes an indication of the common value. Claim 11 A method according to claim 10, wherein the indication in the packed message comprises individual values ​​for each position coordinate (X,Y) of the neurons in the first neural network layer to which activation event data is transmitted, and an indication of the channel coordinate (Z) of the neurons for each activation event data among the plurality of activation event data, and individual activation event values ​​for the activation event data. Claim 12 A method according to claim 11, wherein the indication of the channel coordinate (Z) for each of the plurality of activation event data in the packed message comprises an absolute value of the channel coordinate of a first neuron among the neurons in the first neural network layer to which the activation event data is transmitted and one or more relative values, and each of the one or more relative values ​​indicates the difference between the absolute value of the channel coordinate of a neuron in the first neural network layer to which the activation event data is transmitted and the absolute value of the channel coordinate of a preceding neuron in the first neural network layer to which the activation event data is transmitted. Claim 13 A method according to claim 10, further comprising the step of temporarily buffering activation event data generated while evaluating neuron states of the first feature map by the first processor core among the processor cores. Claim 14 A method according to claim 13, further comprising the step of transmitting the packed message for a predetermined number of buffered activation event data by the first processor core among the processor cores. Claim 15 A method according to claim 10, wherein the second processor core performs all updates of the neuron states of the neurons in the second neural network layer based on each of the activation event data in the packed message to which the neuron is the destination, before proceeding to update the neuron states of other neurons in the second neural network layer upon receiving the packed message.

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