Method for manufacturing high-bandwidth memory

Abstract

The present invention relates to a method for manufacturing High-Bandwidth Memory (HBM). In particular, rather than forming Through Silicon Via (TSV), dished metal pads, and a dielectric on a core die wafer to be stacked on a base wafer in advance and then stacking it on the base wafer through dielectric bonding and metal bonding via annealing processes, the invention is configured such that dielectric bonding is performed sequentially on the base wafer with only the dielectric formed thereon, and TSVs are formed on each dielectric-bonded core die wafer to be electrically connected to an underlying stacking structure, thereby enabling the manufacture of an HBM in which a number of core die wafers set on the base wafer are stacked. This configuration eliminates the need to perform dishing of the metal pads, prevents oxide erosion problems because the metal pads are not formed in advance, prevents warpage problems occurring during the high-temperature annealing process for metal pad bonding, and prevents defects such as cracks and seams caused by dishing depth and uniformity from occurring because dishing of the metal pads is not performed during the CMP process. This relates to a method for manufacturing HBM that can prevent this. The constituent means constituting the HBM manufacturing method of the present invention comprises, in the HBM manufacturing method, a step of preparing a base wafer and core die wafers having dielectrics formed thereon to be sequentially stacked on the base wafer; a basic dielectric bonding step of dielectric bonding a first-stage core die wafer onto the base wafer; a basic connection step of forming a TSV on the first-stage core die wafer and electrically connecting it to the base wafer; a step of forming a connection member on the upper surface of the first-stage core die wafer; an additional dielectric bonding step of dielectric bonding a core die wafer to be additionally bonded onto the uppermost core die wafer among the core die wafers stacked on the base wafer; an additional connection step of forming a TSV on the additionally bonded core die wafer and electrically connecting it to a lower stacking structure; a step of determining whether a set number of core die wafers are stacked on the base wafer; if the determination result indicates that the set number of core die wafers are stacked, an additional process execution step is performed to complete HBM manufacturing, and if it is determined that the set number of core die wafers are not stacked, a step of forming a connection member on the upper surface of the additionally bonded core die wafer is performed, followed by the additional dielectric bonding step. It is characterized by being configured to include a rotating setting, a single stacking step, and an additional process execution step.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing High-Bandwidth Memory (HBM). In particular, rather than forming Through Silicon Via (TSV), dished metal pads, and a dielectric on a core die wafer to be stacked on a base wafer in advance and then stacking it on the base wafer through dielectric bonding and metal bonding via annealing processes, the invention is configured such that dielectric bonding is performed sequentially on the base wafer with only the dielectric formed thereon, and TSVs are formed on each dielectric-bonded core die wafer to be electrically connected to an underlying stacking structure, thereby enabling the manufacture of an HBM in which a number of core die wafers set on the base wafer are stacked. This configuration eliminates the need to perform dishing of the metal pads, prevents oxide erosion problems because the metal pads are not formed in advance, prevents warpage problems occurring during the high-temperature annealing process for metal pad bonding, and prevents defects such as cracks and seams caused by dishing depth and uniformity from occurring because dishing of the metal pads is not performed during the CMP process. This relates to a method for manufacturing HBM that can prevent this. Background Technology

[0003] Semiconductor technology is evolving into a heterogeneous technology trend. Heterogeneous semiconductor technology refers to the technology that integrates various types of semiconductor materials and technologies to form a single system. This enables the achievement of performance, power efficiency, and cost optimization, and plays a crucial role in the field of next-generation AI semiconductors.

[0004] In the packaging domain, heterogeneous semiconductor technologies include chiplet architecture and 2.5D and 3D stacking technologies. Chiplet architecture modularizes individually designed chips to be implemented in the form of a System On Package (SoP) instead of a System On Chip (SoC), and is a technology that efficiently integrates components such as CPUs, GPUs, and memory by manufacturing them using optimized processes.

[0005] 2.5D and 3D stacking refers to stacking into 2.5-dimensional or 3-dimensional structures using technologies such as TSV (Through Silicon Via) and hybrid bonding, and is a technology that efficiently connects chips with different functions (processors, memory, sensors, etc.) to increase network bandwidth and energy efficiency.

[0006] In response to the demand for miniaturization and lightweighting of electronic devices, the semiconductor industry is pursuing the miniaturization, lightweighting, and thinning of semiconductor packages mounted on electronic devices, while simultaneously increasing their speed, multifunctionality, and capacity. Consequently, there is a growing need for packaging technologies capable of storing more data and transmitting data at higher speeds. High Bandwidth Memory (HBM) is a well-known such technology, as it enables high-level bandwidth by stacking more DRAMs on a substrate of the same area.

[0007] HBM is manufactured by stacking multiple memory chips. One of the stacking methods used is hybrid bonding. It is distinguished from TC bonding (Thermo-Compression), which mechanically bonds using heat and pressure, in that it bonds using both mechanical and electrical methods. “Unlike TC bonding, which utilizes heat and pressure, hybrid bonding eliminates the cross-linking between chips and allows them to be directly stacked.” Production using TC bonding requires a cross-linking mechanism called a bumper. Hybrid bonding does not require cross-linking because it directly connects the two chips.

[0008] Conventional general HBM manufacturing methods involve first performing dielectric bonding followed by metal (e.g., copper) bonding in a subsequent heat treatment process. During the heat treatment, mutual diffusion occurs in the copper metal pads; consequently, compressive stress caused by mutual diffusion is generated at the copper-copper interfaces that have widened due to the copper pad dishing phenomenon, thereby facilitating copper bonding.

[0009] In copper pad dishing control technology, the CMP process for copper pads is a core process because the uniformity of copper dishing on the wafer is critical; the degree of copper dishing is determined by the thermal expansion of copper due to temperature during the annealing process after bonding. Since copper readily reacts with oxygen to form copper oxide when exposed to the outside, methods for removing copper oxide and additional oxidation prevention are important.

[0010] In particular, hybrid bonding structurally requires a surface planarization process, and copper dishing control is a critical process. Furthermore, bonding strength may be low, and while unstable native copper oxide present at the copper interface diffuses to fill nano-pores, it also remains at the copper bonding interface, forming crystal defects.

[0011] Regarding conventional HBM manufacturing methods, Korean Patent Publication No. 10-2024-0175915 (hereinafter referred to as the "prior art document") proposes a high-bandwidth memory structure and a method for manufacturing a high-bandwidth memory structure, wherein conductive pads are placed on a buffer die and electrically connected to the connecting members to test for defects that may occur in the connecting members connecting the memory dies during the bonding process between the memory dies.

[0012] The aforementioned prior art documents can detect connection failures early, allowing for prompt action on defects and improving product production yield by reducing losses from defects detected and discarded at the final product stage; however, they do not disclose any methods to improve quality issues (Native oxide, Crack, Seam, Cu Dishing & Oxide erosion, Warpage) that occur in existing hybrid bonding. Prior art literature

[0014] Republic of Korea Published Patent No. 10-2024-0175915 (Publication Date: December 23, 2024, Title of Invention: High-bandwidth memory structure and method for manufacturing the same) The problem to be solved

[0015] The present invention is proposed to solve the aforementioned conventional technology. Instead of forming TSVs (Through Silicon Via), dished metal pads, and dielectrics on core die wafers to be stacked on a base wafer in advance, and then stacking them on the base wafer through dielectric bonding and annealing processes, the invention is configured to sequentially bond dielectrics onto the base wafer with only dielectrics formed on the core die wafers, and then electrically connect TSVs formed on each dielectric-bonded core die wafer to an underlying stacking structure, thereby enabling the manufacture of an HBM in which a number of core die wafers set on the base wafer are stacked. This configuration eliminates the need to perform dishing of metal pads, prevents oxide erosion problems because metal pads are not formed in advance, prevents warpage problems occurring during the high-temperature annealing process for metal pad bonding, and prevents defects such as cracks and seams caused by dishing depth and uniformity because dishing of metal pads is not performed during the CMP process. The purpose is to provide a method for manufacturing HBM. means of solving the problem

[0017] The constituent means constituting the HBM manufacturing method of the present invention, proposed to solve the above-mentioned problem, comprises, in the HBM manufacturing method: a step of preparing a base wafer and core die wafers having dielectrics formed thereon to be sequentially stacked on the base wafer; a basic dielectric bonding step of dielectric bonding a first-stage core die wafer onto the base wafer; a basic connection step of forming a TSV on the first-stage core die wafer and electrically connecting it to the base wafer; a step of forming a connection member on the upper surface of the first-stage core die wafer; an additional dielectric bonding step of dielectric bonding a core die wafer to be additionally bonded onto the top-most core die wafer among the core die wafers stacked on the base wafer; an additional connection step of forming a TSV on the additionally bonded core die wafer and electrically connecting it to a lower stacking structure; a step of determining whether a set number of core die wafers are stacked on the base wafer; and, if the determination result indicates that the set number of core die wafers are stacked, proceeding with an additional process step to complete HBM manufacturing, and if it is determined that the set number of core die wafers are not stacked, forming a connection member on the upper surface of the additionally bonded core die wafer. It is characterized by being configured to include a step of performing an additional process and a step of setting a single stacking and returning to the additional genome bonding step after performing the above.

[0018] Here, the dielectric formed on the core die wafer is formed only on the lower surface of the core die wafer, and the connecting member is characterized by including a dielectric and a metal pad.

[0019] Here, the dielectric formed on the core die wafer is formed on the upper and lower surfaces of the core die wafer, and the connecting member is characterized as being a metal pad. Effects of the invention

[0021] According to the HBM manufacturing method of the present invention having the above-described problem and solution means, instead of forming TSVs (Through Silicon Via), dished metal pads, and dielectrics on core die wafers to be stacked on a base wafer in advance and then stacking them on the base wafer through dielectric bonding and metal bonding via annealing processes, the method is configured such that dielectric bonding is performed sequentially on the base wafer with only dielectrics formed on the core die wafers, and TSVs are formed on each dielectric-bonded core die wafer to be electrically connected to an underlying stacking structure, thereby enabling the manufacturing of an HBM in which a number of core die wafers set on the base wafer are stacked. Consequently, dishing of the metal pads is not required, and since the metal pads are not formed in advance, the problem of oxide erosion can be prevented. Furthermore, the problem of warpage occurring during the high-temperature annealing process for metal pad bonding can be prevented. Additionally, since dishing of the metal pads is not performed during the CMP process, defects such as cracks and seams caused by dishing depth and uniformity can be avoided. The advantage of being able to prevent this arises. Brief explanation of the drawing

[0023] FIG. 1 is a flowchart illustrating a method for manufacturing an HBM according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a laminated structure for explaining a process for manufacturing an HBM according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of an HBM manufactured according to the HBM manufacturing method according to an embodiment of the present invention. Specific details for implementing the invention

[0024] Hereinafter, preferred embodiments of the HBM manufacturing method of the present invention, having the above-mentioned problems, means of solution, and effects, will be described in detail with reference to the attached drawings.

[0025] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0027] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0028] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0029] Where an embodiment can be implemented differently, a specific sequence of operations may be performed differently from the order described. For example, two operations described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0031] FIG. 1 is a flowchart illustrating a method for manufacturing an HBM according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a stacked structure illustrating a process for manufacturing an HBM according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of an HBM manufactured according to the method for manufacturing an HBM according to an embodiment of the present invention.

[0032] The HBM manufacturing method according to an embodiment of the present invention relates to a method for manufacturing a High-Bandwidth Memory (HBM) as illustrated in FIG. 3, and specifically, is a method for manufacturing an HBM formed by stacking core die wafers (30) on a base wafer (10) in a set number of layers.

[0033] Here, the electrical connection between the base wafer (10) and the core die wafers (30) and the electrical connection between the stacked core die wafers (30) are not formed in advance but are formed through a Through Silicon Via (31) formed during the manufacturing process. Meanwhile, the core die wafers (30) stacked on the base wafer (10) are referred to as wafers, but they may be wafers before dicing or core dies after dicing.

[0034] As illustrated in FIG. 1, an HBM manufacturing method comprises the steps of: preparing a base wafer (10) and core die wafers (30) having dielectrics formed thereon to be sequentially stacked on the base wafer (10) (S10); a basic dielectric bonding step (S20) of dielectric bonding a first stage of core die wafers (30) on the base wafer (10); a basic connection step (S30) of forming a TSV (31) on the first stage of core die wafers (30) and electrically connecting it to the base wafer (10); a step of forming a connection member on the upper surface of the first stage of core die wafers (30) (S40); an additional dielectric bonding step (S50) of dielectric bonding a core die wafer (30) to be additionally bonded on the uppermost core die wafer (30) among the core die wafers (30) stacked on the base wafer (10); and an additional connection step of forming a TSV (31) on the additionally bonded core die wafer (30) and electrically connecting it to a lower stacked structure (50). The method comprises a step (S60), a step (S70) for determining whether a set number of core die wafers are stacked on the base wafer (10), and, if the result of the determination is that a set number of core die wafers are stacked, an additional process step (S90) is performed to complete HBM manufacturing, and if it is determined that a set number of core die wafers are not stacked, a step (S80) for forming a connection member (33) on the upper surface of the additionally bonded core die wafer (30) is performed, and then the method returns to the additional dielectric bonding step (S50).

[0035] The step (S10) of preparing the base wafer (10) and the core die wafers (30) having a dielectric formed thereon to be sequentially stacked on the base wafer (10) corresponds to the step of preparing the base wafer (10) having a metal pad and a dielectric formed thereon to be sequentially stacked on the core die wafers (30), and the core die wafers (30) to be sequentially stacked on the base wafer (10) having the metal pad and the dielectric formed thereon.

[0036] Since the HBM manufacturing method according to the embodiment of the present invention is for manufacturing HBM, the base wafer (10) is preferably a Logic Wafer, and the core die wafers (30) to be sequentially stacked on the base wafer (10) are preferably DRAM Wafers to be electrically connected to the Logic Wafer.

[0037] A metal pad and a dielectric are formed on the upper surface of the base wafer (10). The metal pad is preferably a copper (Cu) pad, and the dielectric is preferably an oxide or polymer. The copper pad, metal pad, and dielectric are formed on the upper surface of the base wafer (10) by various methods, such as deposition.

[0038] The upper surface of the base wafer (10) having the metal pad and dielectric formed thereon is subjected to CMP (Chemical Mechanical Polishing). The CMP treatment process according to the present invention is applied only to flatten the metal pad, which is the copper pad, and the dielectric, and unlike conventional methods, is not applied to form dishing on the copper pad.

[0039] That is, the CMP processing process for the upper surface of the base wafer (10) according to the present invention is performed for flattening the upper surface, and the copper pad is not dished by this CMP processing process. Ultimately, the CMP processing process applied in the present invention is simpler and easier than the CMP processing process applied in conventional HBM manufacturing methods, and can reduce the time and effort required for processing.

[0040] As shown in FIG. 2(a), it is preferable that the base wafer (10) be prepared in a state attached to a carrier wafer (10) to stably perform a successive stacking step of core die wafers (30). Meanwhile, unlike the core die wafers (30), the base wafer (10) has a TSV formed in advance as well as a metal pad in order to be electrically connected to the core die wafer (30) to be stacked as well as the dielectric.

[0041] The core die wafers (30) to be sequentially stacked on the base wafer (10) are preferably each subjected to a thinning process and prepared by forming a dielectric on their surface. The dielectric is formed on the surface of the core die wafer (30) by various methods, such as deposition, on each core die wafer (30).

[0042] The dielectric formed on each of the above core die wafers (30) may be formed only on the lower surface of the core die wafer (30), or may be formed on both the lower surface and the upper surface. Here, the lower surface of the core die wafer (30) corresponds to the surface facing the base wafer (10) during the process of stacking on the base wafer (10), and the upper surface of the core die wafer (30) corresponds to the surface opposite to the lower surface.

[0043] As will be described later, depending on whether the dielectric is formed only on the lower surface of the core die wafer (30) or on both the lower and upper surfaces, the connection member in the connection member formation step (S40, S80) performed in the subsequent process may be a dielectric and a metal pad, or only a metal pad.

[0044] If core die wafers (30) with a dielectric formed only on the lower surface are prepared, the time, effort, and cost required for preparation can be reduced compared to the case where core die wafers (30) with a dielectric formed on both the lower and upper surfaces are prepared, but in the connection member formation step (S40, S80) performed in the subsequent process, a dielectric must be additionally formed on the upper surface in addition to the metal pad.

[0045] On the other hand, when preparing core die wafers (30) in which a dielectric is formed on both the lower and upper surfaces, the time, effort, and cost required for preparation increase compared to when preparing core die wafers (30) in which a dielectric is formed only on the lower surface; however, in the connection member formation step (S40, S80) performed in the subsequent process, there is no need to form a dielectric on the upper surface, so only a metal pad needs to be formed.

[0046] Consequently, if HBM is manufactured by continuously performing each step for HBM manufacturing with the core die wafers (30) having the dielectric formed already prepared, it is necessary to reduce the time, effort, and cost required for the connection member formation step (S40, S80) in order to improve the efficiency and productivity of HBM manufacturing. To this end, it is preferable to prepare the core die wafers (30) having the dielectric formed on both the bottom and top surfaces in the wafer preparation step (S10) so that it is sufficient to form only the metal pad in the connection member formation step (S40, S80).

[0047] On the other hand, if the wafer preparation step (S10) is also a series of continuous steps performed for the HBM manufacturing method according to the present invention, more time, effort, and cost than necessary may be required to form a dielectric on the upper surface as well as the lower surface. Therefore, when performing the entire series of steps continuously, it may be more preferable to prepare a core die wafer (30) with a dielectric formed only on the lower surface in the wafer preparation step (S10), then proceed with the subsequent steps continuously, and proceed so as to form a dielectric as well as a metal pad on the upper surface in the connection member formation step (S40, S80).

[0048] When the base wafer (10) and the core die wafers (30) on which the dielectric is formed are prepared in the wafer preparation step (S10), a basic dielectric bonding step (S20) is performed to dielectric bond a single core die wafer (30) onto the base wafer (10), as shown in (b) of FIG. 2.

[0049] That is, the above basic dielectric bonding step (S20) corresponds to a step of performing dielectric bonding primarily by aligning the dielectric formed on the upper surface of the base wafer (10) and the dielectric formed on the lower surface of the first stage core die wafer (30).

[0050] Here, the core die wafer (30) of the first stage refers to the wafer to be stacked first on the base wafer (10) among the core die wafers (30) to be stacked sequentially on the base wafer (10), that is, the core die wafer (30) that is directly bonded and connected to the base wafer (10).

[0051] The above basic dielectric bonding step (S20) is a process of aligning the dielectrics of the base wafer (10) and the core die wafer (30) of the first stage so that they can be accurately bonded together, and applying a constant pressure to the core die wafer (30) to be bonded.

[0052] Then, due to hydrophilicity, van der Waals intermolecular forces are generated on the surfaces of the dielectrics that come into contact with each other, and through this, hydrogen bonds are formed between the dielectrics, allowing them to maintain a bonded state.

[0053] Meanwhile, in order to enable dielectric bonding between the base wafer (10) and the first stage core die wafer (30), it is preferable to perform an activation process on the dielectric surfaces of the base wafer (10) and the first stage core die wafer (30) prior to the basic dielectric bonding step (S20).

[0054] The above activation process corresponds to a plasma activation process performed to bond the base wafer (10) and the core die wafer (30) of the first stage, after activating their dielectric surfaces to be bonded together, using van der Waals forces and hydrolytic bonding by heat. It is preferable to additionally perform a cleaning process after the above activation process to remove contaminants.

[0055] When the above activation and cleaning process is completed, a basic dielectric bonding step (S20) is performed to perform dielectric bonding by aligning and bonding the activated dielectric surfaces of the base wafer (10) and the core die wafer (30) of the first stage.

[0056] When the above basic dielectric bonding step (S20) is completed, a basic connection step (S30) is performed to electrically connect the TSV (31) to the base wafer (10) by forming it on the core die wafer (30) of the first stage, as shown in (c) of FIG. 2.

[0057] The above basic connection step (S30) is a step for electrically connecting the core die wafer (30) of the first stage to the base wafer (10), specifically to a metal pad (Cu pad). The HBM manufacturing step according to the present invention does not form TSVs on each core die wafer (30) in advance and does not form metal pads (copper pads).

[0058] Accordingly, in the basic connection step (S30), a TSV is formed on the core die wafer (30) of the first stage and electrically connected to the base wafer (10). It is preferable that the TSV be formed aligned so as to be electrically connected to a metal pad formed on the upper part of the base wafer (10).

[0059] The above basic connection step (S30) corresponds to the step of forming a TSV to electrically connect the first stage core die wafer (30) to the base wafer (10) by forming via holes in the first stage core die wafer (30) and then depositing or filling a conductive material into the via holes through copper deposition and / or copper plating.

[0060] As such, the HBM manufacturing method according to the embodiment of the present invention adopts a technical feature in which, instead of forming TSVs on each core die wafer (30) in advance and forming a metal pad, which is a copper pad corresponding thereto, on the lower surface, and then performing flattening as well as dishing through a CMP process, and then performing dielectric bonding and then performing electrical connection through the metal bonding of the copper pad through an annealing step, only dielectric is formed on each core die wafer (30) in advance and dielectric bonding is performed, and then TSVs are formed immediately without an annealing process to perform electrical connection.

[0061] As a result, the HBM manufacturing method according to the embodiment of the present invention simplifies the CMP process because there is no need to form a dishing of the copper pad during the planarization process through the CMP process, and because there is no need to form a copper pad and no metal bonding is performed through annealing after dielectric bonding, there is not only no problem of oxide erosion of the copper pad, but also no problem of warpage caused by heat during copper bonding, and the problem of stress on the product caused by the high-temperature annealing process can be eliminated.

[0062] When the above basic connection step (S30) is completed, a basic connection member forming step (S40) is performed to form a connection member (indicated by reference numeral 33 in Fig. 2 (d)) on the upper surface of the core die wafer (30) of the first stage, as shown in Fig. 2 (d).

[0063] The above basic connection member forming step (S40) corresponds to the step of forming a connection member (33) on the upper surface of the first stage core die wafer (30) for bonding and electrical connection with an additional core die wafer (30) to be bonded to be stacked on the upper side of the first stage core die wafer (30).

[0064] As described above, the connecting member (33) may include a dielectric and a metal pad, which is a copper pad, or may be only a metal pad, which is a copper pad. Specifically, the connecting member (33) means including a dielectric and a metal pad when the dielectric formed on the core die wafer (30) prepared in the wafer preparation step (S10) is formed only on the lower surface of the core die wafer (30), and means only a metal pad when the dielectric formed on the core die wafer (30) prepared in the wafer preparation step (S10) is formed on both the lower surface and the upper surface of the core die wafer (30), since the dielectric is already formed on the upper surface.

[0065] When a connection member (33) meaning only a metal pad or a connection member (33) including the dielectric and the metal pad is formed in the above basic connection member formation step (S40), it is desirable to perform a flattening process, i.e., a CMP process, for a smooth subsequent process including bonding. The CMP process performed at this time is only a process for flattening the connection member (33) and does not perform a dishing process for the metal pad corresponding to the copper pad.

[0066] In other words, since electrical connection is performed through TSV without performing metal bonding through annealing, dishing treatment of the metal pads through the CMP process is not required.

[0067] The metal pad formed in the above basic connection member forming step (S40) is formed on the upper surface so as to be electrically connected to the TSV formed on the first stage core die wafer (30). The dielectric formed on the upper surface of the first stage core die wafer (30) is, of course, formed in the part where the metal pad is not formed.

[0068] When the above basic connection member formation step (S40) is completed, an additional dielectric bonding step (S50) and an additional connection step (S60) are subsequently performed in succession as shown in (e) of FIG. 2.

[0069] Specifically, when the basic connection member forming step (S40) is completed, an additional dielectric bonding step (S50) is performed to dielectric bond a core die wafer (30) to be additionally bonded to the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10).

[0070] That is, the additional dielectric bonding step (S50) corresponds to a step of performing additional dielectric bonding by aligning the dielectric formed on the upper surface of the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) with the dielectric formed on the lower surface of the core die wafer (30) to be additionally bonded.

[0071] At the current stage, the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) corresponds to a first layer core die wafer (30), and the additional core die wafer (30) to be bonded corresponds to a second layer core die wafer to be stacked on the first layer core die wafer. That is, the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) and the additional core die wafer (30) to be bonded correspond to core die wafers (30), differing only in stacking position or stacking layer.

[0072] The above additional dielectric bonding step (S50) is a process of aligning the dielectric of the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) and the additional core die wafer (30) to be bonded so that they can be accurately bonded together, and applying a constant pressure to the additional core die wafer (30).

[0073] Then, due to hydrophilicity, van der Waals intermolecular forces are generated on the surfaces of the dielectrics that come into contact with each other, and through this, hydrogen bonds are formed between the dielectrics, allowing them to maintain a bonded state.

[0074] Meanwhile, in order to enable dielectric bonding between the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) and the additional core die wafer (30) to be bonded, it is preferable to perform an activation process on the dielectric surface of the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) and the additional core die wafer (30) to be bonded prior to the additional dielectric bonding step (S50).

[0075] The above activation process corresponds to a plasma activation process performed to bond using van der Waals forces and thermal hydrolysis after activating the dielectric surface of the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) to be bonded together and the additional core die wafer (30) to be bonded. It is preferable to additionally perform a cleaning process after the above activation process to remove contaminants.

[0076] When the above activation and cleaning process is completed, an additional dielectric bonding step (S50) is performed to perform dielectric bonding by aligning and bonding the activated dielectric surface of the top layer core die wafer (30) among the core die wafers (30) stacked on the base wafer (10) to be bonded and the additional core die wafer (30) to be bonded.

[0077] When the above additional dielectric bonding step (S50) is completed, an additional connection step (S60) is performed to form a TSV (31) on the additionally bonded core die wafer (30) and electrically connect it to the lower stacked structure (33), as shown in (e) of FIG. 2.

[0078] At the current stage, the additionally bonded core die wafer (30) refers to a second-stage core die wafer (30) additionally bonded to a first-stage core die wafer, and the stacked structure (33) refers to a stacked structure of a base wafer (10) and a first-stage core die wafer (30) stacked on the base wafer (10). The stacked structure (33) is a structure in which only the number of stacked core die wafers is changed as the core die wafers are stacked sequentially.

[0079] The additional connection step (S60) is a step for electrically connecting the additionally bonded core die wafer (30) to the stacked structure (33). Specifically, the additional connection step (S60) is a step for electrically connecting the additionally bonded core die wafer (30) to the base wafer (10) and / or the core die wafer constituting the stacked structure (33), and most preferably, a step for electrically connecting to the top layer core die wafer (30) constituting the stacked structure (33), specifically to a metal pad (Cu pad).

[0080] The HBM manufacturing step according to the present invention does not form TSVs or metal pads (copper pads) on each core die wafer (30) in advance. Accordingly, in the additional connection step (S60), TSVs (31) are formed on the additionally bonded core die wafer (30) to electrically connect to the lower stacked structure (33), particularly the top layer core die wafer (30). It is preferable that the TSVs be formed aligned so as to be electrically connected to the metal pads formed on the top layer core die wafer (30), which is currently the first layer core die wafer (30).

[0081] The additional connection step (S60) above corresponds to the step of forming a TSV to electrically connect the additionally bonded core die wafer (30) to the top layer core die wafer (30) of the lower stacked structure (33) by forming via holes in the additionally bonded core die wafer (30) and then depositing or filling a conductive material into the via holes through copper deposition and / or copper plating.

[0082] As such, the HBM manufacturing method according to the embodiment of the present invention adopts a technical feature in which, instead of forming TSVs on each core die wafer (30) in advance and forming a metal pad, which is a copper pad corresponding thereto, on the lower surface, and then performing flattening as well as dishing through a CMP process, and then performing dielectric bonding and then performing electrical connection through the metal bonding of the copper pad through an annealing step, only dielectric is formed on each core die wafer (30) in advance and dielectric bonding is performed, and then TSVs are formed immediately without an annealing process to perform electrical connection.

[0083] As a result, the HBM manufacturing method according to the embodiment of the present invention simplifies the CMP process because there is no need to form a dishing of the copper pad during the planarization process through the CMP process, and because there is no need to form a copper pad and no metal bonding is performed through annealing after dielectric bonding, there is not only no problem of oxide erosion of the copper pad, but also no problem of warpage caused by heat during copper bonding, and the problem of stress on the product caused by the high-temperature annealing process can be eliminated.

[0084] When the above additional connection step (S60) is completed, a stacking number determination step (S70) is performed to determine whether a set number of core die wafers (30) are stacked on the base wafer (10). That is, the stacking number determination step (S70) corresponds to a step of determining whether the core die wafers (30) sequentially stacked on the base wafer (10) correspond to a pre-set number.

[0085] Based on the determination result in the stacking number determination step (S70), if the core die wafers (30) sequentially stacked on the base wafer (10) correspond to a predetermined number of stacks, the HBM is manufactured by performing the necessary additional processes because the target core die wafers have been stacked. On the other hand, if the core die wafers (30) sequentially stacked on the base wafer (10) do not correspond to a predetermined number of stacks, the additional connection member forming step (S80) is performed until the set number of core die wafers is stacked, and then the additional dielectric bonding step (S50) and the additional connection step (S60) described above are repeatedly performed.

[0086] That is, if the result of the determination in the stacking number determination step (S70) above indicates that the set number of core die wafers (30) are stacked, the additional process execution step (S90) is performed to complete HBM manufacturing, and if it is determined that the set number of core die wafers (30) are not stacked, the additional connection member formation step (S80) is performed to form a connection member (33) on the upper surface of the additionally bonded core die wafer, and then the set number of stacking and additional process execution step is performed, returning to the additional dielectric bonding step (S50).

[0087] If, as a result of the determination in the stacking number determination step (S70), the set number of core die wafers (30) are stacked, the additional process execution step (S90) is performed to complete the HBM manufacturing. The processes that can be performed in the additional process execution step (S90) may include an epoxy sealing (EMC, Epoxy Molding Compound) process and a wafer test.

[0088] On the other hand, if it is determined that the set number of core die wafers (30) are not stacked based on the result of the determination step (S70) above, an additional connection member forming step (S80) is performed to form a connection member (33) on the upper surface of the additionally bonded core die wafer in order to perform these steps, before repeatedly performing the additional dielectric bonding step (S50) and the additional connection step (S60) described above.

[0089] The step of forming an additional connection member (S80) corresponds to the step of forming a connection member (33) on the upper surface of the additionally bonded core die wafer (30) for bonding and electrical connection with the additionally bonded core die wafer (30) to be stacked on the upper side of the additionally bonded core die wafer (30). In the current state, the additionally bonded core die wafer corresponds to a 2-stage core die wafer, and the additionally bonded core die wafer corresponds to a core die wafer that will become a 3-stage core die wafer.

[0090] As described above, the connecting member (33) may include a dielectric and a metal pad, which is a copper pad, or may be only a metal pad, which is a copper pad. Specifically, the connecting member (33) means including a dielectric and a metal pad when the dielectric formed on the core die wafer (30) prepared in the wafer preparation step (S10) is formed only on the lower surface of the core die wafer (30), and means only a metal pad when the dielectric formed on the core die wafer (30) prepared in the wafer preparation step (S10) is formed on both the lower surface and the upper surface of the core die wafer (30), since the dielectric is already formed on the upper surface.

[0091] When a connection member (33) meaning only a metal pad or a connection member (33) including the dielectric and the metal pad is formed in the additional connection member formation step (S80) above, it is desirable to perform a flattening process, i.e., a CMP process, for a smooth subsequent process including bonding. The CMP process performed at this time is only a process for flattening the connection member (33) and does not perform a dishing process for the metal pad corresponding to the copper pad.

[0092] In other words, since electrical connection is performed through TSV without performing metal bonding through annealing, dishing treatment of the metal pads through the CMP process is not required.

[0093] The metal pad formed in the additional connection member forming step (S80) is formed on the upper surface so as to be electrically connected to the TSV formed on the additionally bonded core die wafer (30). The dielectric formed on the upper surface of the additionally bonded core die wafer (30) is, of course, formed in the portion where the metal pad is not formed.

[0094] When the additional connection member formation step (S80) is completed, the process returns to the additional dielectric bonding step (S50) and sequentially performs the additional dielectric bonding step (S50) and the additional connection step (S60).

[0095] Then, three layers of core die wafers are stacked on the base wafer (10), and the additional connection member forming step (S80), the additional dielectric bonding step (S50), and the additional connection step (S60) are repeatedly performed until the number of core die wafers is set in advance on the base wafer.

[0096] Each time the process is repeated, the stacking number determination step (S70) determines whether the current number of core die wafers is a set number. If the number of core die wafers on the base wafer corresponds to a set number, the additional connection member formation step (S80) is not performed; instead, the subsequent additional process execution step (S90) is performed to complete HBM manufacturing.

[0097] The above additional dielectric bonding step (S50) and additional connection step (S60) differ only in the number of core die wafers to be bonded and connected, but the technical characteristics regarding the bonding and connection of the core die wafers are identical to those of the additional dielectric bonding step (S50) and additional connection step (S60) described above, so their descriptions apply identically.

[0098] According to the HBM manufacturing method of the present invention described above, instead of forming TSVs (Through Silicon Via), dished metal pads, and dielectrics on core die wafers to be stacked on a base wafer in advance and then stacking them on the base wafer through dielectric bonding and metal bonding via annealing processes, the method is configured such that dielectric bonding is performed sequentially on the base wafer with only dielectrics formed on the core die wafers, and TSVs are formed on each dielectric-bonded core die wafer to be electrically connected to an underlying stacking structure, thereby enabling the manufacturing of an HBM in which a number of core die wafers set on the base wafer are stacked. Consequently, the method has the advantages of not requiring dishing of the metal pads, preventing oxide erosion problems because metal pads are not formed in advance, preventing warpage problems that occur during the high-temperature annealing process for metal pad bonding, and preventing defects caused by dishing depth and uniformity, such as cracks and seams, because dishing of the metal pads is not performed during the CMP process. It occurs.

[0099] Although embodiments according to the present invention have been described above, they are merely illustrative and those skilled in the art will understand that various modifications and equivalent embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the following claims. Explanation of the symbols

[0101] 1 : Carrier wafer 10: Base wafer 30: Core die wafer 31 : TSV (Through Silicon Via) 33 : Connection failure 50 : Laminated structure 100 : HBM(High-Bandwidth Memory)

Claims

Claim 1 delete Claim 2 A method for manufacturing an HBM, wherein core die wafers are stacked in a predetermined number on a base wafer, and electrical connections between the base wafer and the core die wafers and between the stacked core die wafers are formed through Through Silicon Via (TSV) formed on the core die wafer during the HBM manufacturing process, comprising: a step of preparing a base wafer having a metal pad and a dielectric formed on its upper surface, and core die wafers to be sequentially stacked on the base wafer, wherein the dielectric is formed only on the lower surface without a metal pad; a basic dielectric bonding step of dielectric bonding a first stage of core die wafers on the base wafer; a basic connection step of forming a TSV on the first stage of core die wafers to electrically connect them to the base wafer; a step of forming a connection member including a dielectric and a metal pad on the upper surface of the first stage of core die wafers; an additional dielectric bonding step of dielectric bonding a core die wafer to be additionally bonded on the uppermost core die wafer among the core die wafers stacked on the base wafer; an additional connection step of forming a TSV on the additionally bonded core die wafers to electrically connect them to a lower stacked structure; and on the base wafer A method for manufacturing an HBM characterized by comprising: a step of determining whether a set number of core die wafers are stacked; a step of performing an additional process to complete HBM manufacturing if, as a result of the determination, the set number of core die wafers are stacked, and if it is determined that the set number of core die wafers are not stacked, a step of forming a connection member on the upper surface of the additionally bonded core die wafer, and then returning to the additional dielectric bonding step. Claim 3 A method for manufacturing an HBM, wherein core die wafers are stacked in a predetermined number on a base wafer, and electrical connections between the base wafer and the core die wafers and between the stacked core die wafers are formed through Through Silicon Via (TSV) formed on the core die wafer during the HBM manufacturing process, comprising: a step of preparing a base wafer having a metal pad and a dielectric formed on its upper surface, and core die wafers to be sequentially stacked on the base wafer, wherein a dielectric is formed on the upper and lower surfaces without a metal pad; a basic dielectric bonding step of dielectric bonding a first stage of core die wafers on the base wafer; a basic connection step of forming a TSV on the first stage of core die wafers to electrically connect them to the base wafer; a step of forming a connecting member, which is a metal pad, on the upper surface of the first stage of core die wafers; an additional dielectric bonding step of dielectric bonding a core die wafer to be additionally bonded to the uppermost core die wafer among the core die wafers stacked on the base wafer; an additional connection step of forming a TSV on the additionally bonded core die wafers to electrically connect them to a lower stacked structure; and a predetermined number of core die wafers on the base wafer. A method for manufacturing an HBM characterized by comprising: a step of determining whether a set number of core die wafers are stacked; a step of performing an additional process to complete HBM manufacturing if, as a result of the determination, a set number of core die wafers are stacked, and if it is determined that a set number of core die wafers are not stacked, a step of forming a connection member on the upper surface of the additionally bonded core die wafer, and then returning to the additional dielectric bonding step.

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