Method of Depositing Thin Film and Method of Manufacturing Semiconductor device Using The Same

Abstract

The present invention relates to a thin film deposition method and a method for manufacturing a semiconductor device using the same. The thin film deposition method of the present embodiment is a thin film deposition method using a substrate processing apparatus comprising a chamber that limits a processing space inside, a substrate support located in the lower region of the chamber on which a substrate is placed, a gas supply unit located in the upper region of the chamber that provides a source gas and a reaction gas to the substrate, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, wherein the method comprises the steps of: placing the substrate, which includes a lower thin film deposited under a process temperature condition of a low-temperature range, on the substrate support; depositing an upper thin film on the lower thin film in a plasma atmosphere under the process temperature condition of the low-temperature range; and, after the step of depositing the upper thin film, treating the surface of the upper thin film in a plasma atmosphere under the process temperature condition of the low-temperature range, wherein the process temperature of the low-temperature range is 100 to 250°C.

Description

Technology Field

[0001] The present invention relates to a thin film deposition method and a method for manufacturing a semiconductor device using the same, and more specifically, to a thin film deposition method for forming a hard mask and a method for manufacturing a semiconductor device using the same. Background Technology

[0002] In manufacturing highly integrated semiconductor devices, pattern miniaturization is essential. To integrate more devices into a small area, it is necessary to reduce the individual patterns constituting the device and the pitch between patterns. Recently, as the design rules of semiconductor devices have decreased rapidly, there are limitations in forming patterns with fine line widths and pitches due to the exposure limits of the current photolithography process.

[0003] Currently, various etching methods are being proposed to limit fine patterns below the exposure limit, and one of these methods is the use of a hard mask.

[0004] The above hard mask is required to have etch resistance for the layers to be etched. In particular, in the case of a 3D NAND device comprising a stacked structure of a plurality of silicon oxide films and a plurality of silicon nitride films, a stacked structure of an amorphous carbon film and a silicon oxynitride film is used as a hard mask to secure a high etch selectivity ratio for the stacked structure.

[0005] A hard mask composed of the above-mentioned amorphous carbon film and the above-mentioned silicon oxynitride film is generally deposited at a high temperature of 450°C to 650°C. However, when fabricating a hard mask film at such a high temperature, there was a problem of degrading the characteristics of the underlying etchable layer and further deforming the device characteristics.

[0006] Accordingly, conventionally, a technique has been proposed to deposit only an amorphous carbon film relatively adjacent to the etching layer at a low temperature of 100 to 250°C. However, since the silicon oxynitride film constituting the hard mask is still deposited at a high temperature in the above method, damage due to high temperature may occur to the underlying amorphous carbon film. This can cause pattern defects in the hard mask pattern. The problem to be solved

[0007] Embodiments of the present invention provide a thin film deposition method capable of reducing damage to a lower thin film while maintaining an etching selectivity ratio with respect to the lower thin film, and a method for manufacturing a semiconductor device using the same. means of solving the problem

[0008] The thin film deposition method of the present embodiment is a thin film deposition method using a substrate processing apparatus comprising a chamber having a processing space defined therein, a substrate support located in the lower region of the chamber on which a substrate is placed, a gas supply unit located in the upper region of the chamber that provides a source gas and a reaction gas to the substrate, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, the method comprising the steps of: placing the substrate, which includes a lower thin film deposited under process temperature conditions of a low-temperature range, on the substrate support; depositing an upper thin film on the lower thin film in a plasma atmosphere under process temperature conditions of a low-temperature range; and, after the step of depositing the upper thin film, treating the surface of the upper thin film in a plasma atmosphere under process temperature conditions of a low-temperature range, wherein the process temperature of the low-temperature range is 100 to 250°C.

[0009] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention comprises the steps of: forming a lower layer on a semiconductor substrate; depositing a lower thin film having an etching selectivity ratio with respect to the lower layer on the lower layer at a process temperature in a low temperature range; depositing an upper thin film having an etching selectivity ratio with respect to the lower thin film on the lower thin film at a process temperature in a low temperature range; plasma treating the upper thin film to form a hard mask; and patterning the lower layer using the hard mask, wherein the process temperature in the low temperature range is in the range of 100 to 250°C, the upper thin film is deposited using a reaction gas and a source gas contained in excess of the reaction gas, and the plasma treatment is performed by supplying the reaction gas. Effects of the invention

[0010] According to an embodiment of the present invention, instead of depositing both the lower thin film and the upper thin film constituting the hard mask at a process temperature in the low-temperature range, the deposition method of the upper thin film is changed to compensate for the etching selectivity of the upper thin film. Accordingly, since the hard mask can be deposited at a low temperature with sufficient compensation for etching selectivity, pattern defects can ultimately be prevented. Brief explanation of the drawing

[0011] FIG. 1 is a flowchart for explaining a method for manufacturing a semiconductor device including a thin film according to one embodiment of the present invention. FIGS. 2 to 4 are cross-sectional views of each process to explain a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a substrate processing apparatus according to one embodiment of the present invention. FIG. 6 is a flowchart for explaining a method for depositing an upper thin film according to one embodiment of the present invention. FIG. 7 is a timing diagram for explaining an upper thin film deposition method according to one embodiment of the present invention. Specific details for implementing the invention

[0012] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of description. Throughout the specification, the same reference numerals refer to the same components.

[0013] FIG. 1 is a flowchart for explaining a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention. FIG. 2 to 4 are cross-sectional views for each process for explaining a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention.

[0014] Referring to FIGS. 1, 2, and 3, a substrate (100) having a lower thin film (120) formed thereon is provided (S1). In this embodiment, a lower layer (110) corresponding to a layer to be etched may be further formed between the substrate (100) and the lower thin film (120). The lower layer (110) may be, for example, a stacked structure in which a silicon oxide film (110a) and a silicon nitride film (110b) are alternately and repeatedly stacked. Additionally, although not shown in detail in the drawings, a separate device layer may be further interposed between the semiconductor substrate (100) and the lower layer (110). In this embodiment, the lower layer (110) is illustrated as an example in which a silicon oxide film (110a) and a silicon nitride film (110b) are alternately stacked, but various layers to be etched may correspond thereto.

[0015] The lower thin film (120) is a material having an etching selectivity ratio with the etchable layer (110), for example, an amorphous carbon layer, a titanium oxide layer, or SOG (Spin on glass) may be used. The lower thin film (120) of the present embodiment may be formed at a process temperature in the low-temperature range, for example, 100 to 250°C. Accordingly, when the lower thin film (120) is deposited, the thermal effect on the lower etchable layer (110) can be reduced.

[0016] Referring to FIGS. 1 and 4, an upper thin film (130) is deposited on the lower thin film (120) as another part of the hard mask film under dual frequencies (e.g., high frequency and low frequency) (S2). The upper thin film (130) may be a material film having an etching selectivity with respect to the lower thin film (120), for example, a silicon oxynitride film (SiON). The upper thin film (130) of the present embodiment may be deposited at a low-temperature process temperature, for example, a low-temperature process temperature (100 to 250°C) that is substantially the same as the deposition temperature of the lower thin film (120). Accordingly, when depositing the upper thin film (130), thermal damage to the lower thin film (120) is not caused. In the drawings, "HM" may refer to the hard mask film.

[0017] The upper film (130) of the present embodiment, composed of the above silicon oxynitride film, can be formed, for example, through a reaction of SiH4 and N2O gas (or NO gas). As an example, the ratio of SiH4 to N2O can be provided in a ratio of 1.2 to 2.5 to 1. By increasing the content of SiH4 gas relative to N2O, the etching selectivity of the silicon oxynitride film can be improved. In addition, the silicon oxynitride film can be formed under a pressure of 1.5 to 4.0 Torr. Furthermore, in the present embodiment, by using N2O or NO instead of NH3 as the reaction gas for forming the silicon oxynitride film, the hydrogen (H) content in the silicon oxynitride film can be reduced. Accordingly, the etching selectivity of the silicon oxynitride film due to low-temperature deposition can be compensated.

[0018] The upper thin film (130) of this embodiment can be deposited, for example, in a substrate processing device shown in FIG. 5.

[0019] FIG. 5 is a schematic cross-sectional view showing a substrate processing apparatus according to one embodiment of the present invention.

[0020] Referring to FIG. 5, the substrate processing device (150) may include a chamber (200), a controller (201), a showerhead (230), a substrate support (240), a driving unit (250), a plasma power supply (260), a matching network (270), and a heater power supply (290).

[0021] The chamber (200) may include a main body (210) with an open top and a top lid (220) installed on the upper outer periphery of the main body (210). The internal space of the top lid (220) may be closed by a shower head (230). An insulating ring (r) may be installed between the shower head (230) and the top lid (220) to electrically insulate the chamber (200) from the shower head (230).

[0022] The upper thin film (130) deposition process can be performed within the chamber (200). A gate (G) for the introduction and removal of a substrate (W) can be provided at a designated location on the side of the main body (210).

[0023] In order to vacuum the inside of the chamber (200), a pump (213) may be connected to an exhaust port (212) located at the bottom of the chamber (200).

[0024] The shower head (230) may be installed on the inside of the top lid (215) so as to face the substrate support (240). The shower head (230) may receive various source gases supplied from the outside through the gas supply line (L) and spray them into the chamber (200). In this embodiment, the shower head (230) may act as a first electrode for generating plasma.

[0025] A source gas supply unit (240a) and a reaction gas supply unit (240b) may be connected to the gas supply line (L) of the shower head (230) of the present embodiment. In the present embodiment, the source gas supply unit (240a) may receive, for example, SiH4 gas, and the reaction gas supply unit (240b) may receive, for example, N2O gas.

[0026] Although only the source gas supply unit (240a) and the reaction gas supply unit (240b) are illustrated in FIG. 5, a purge gas supply unit and / or seasoning gas supply units may be additionally connected to the gas supply line (L). Valves (V1, V2) may be installed between the source gas supply unit (240a) and the gas supply line (L), and between the reaction gas supply unit (240b) and the gas supply line (L), respectively.

[0027] The substrate support portion (240) may include a substrate mounting portion (susceptor, 242) and a support shaft (244). The substrate mounting portion (242) may have an overall flat shape so that at least one substrate (W) is mounted on its upper surface. The support shaft (244) is vertically coupled to the rear surface of the substrate mounting portion (242) and is connected to an external driving unit (250) through a through hole in the bottom of the chamber (200) to raise and / or rotate the substrate mounting portion (242). In this embodiment, the substrate mounting portion (242) may act as a second electrode for generating plasma.

[0028] Additionally, a heater (246) is provided inside the substrate mounting portion (242) to control the temperature of the substrate (100) mounted on the upper portion, and furthermore, the temperature inside the chamber (200). A heater power supply unit (290) is connected to the heater (246) to provide power.

[0029] The controller (201) is configured to control the overall operation of the substrate processing device (150). In one embodiment, the controller (201) controls the operation of each component (200–290, V1, V2) of the substrate processing device (150) and can set control parameters for depositing the upper thin film (130). Although not illustrated, the controller (201) may include a central processing unit, memory, input / output interface, etc.

[0030] The plasma power supply unit (260) may include a first power supply unit (261) and a second power supply unit (263). The first power supply unit (261) may provide a high frequency (HF) power source with a center frequency band of 10 MHz to 40 MHz, e.g., 13.56 MHz, as a plasma power source. Additionally, the second power supply unit (263) may provide a low frequency (LF) power source with a center frequency band of 300 kHz to 500 kHz, e.g., 370 kHz, as a plasma power source. The controller (201) may control the power source supplied from the first power supply unit (261) and / or the second power supply unit (263) according to control parameters.

[0031] The matching network (270) may include a first matching unit (271) connected to a first power supply unit (261) and a second matching unit (273) connected to a second power supply unit (263). The first and second matching units (271, 273) of the matching network (270) may be configured to mutually match the output impedance of the first and second power supply units (261, 263) with the load impedance within the chamber (200), respectively, to eliminate reflection loss caused by the RF power being reflected from the chamber (200).

[0032] FIG. 6 is a flowchart for explaining a top thin film deposition method according to one embodiment of the present invention. FIG. 7 is a timing diagram for explaining a top thin film deposition method according to one embodiment of the present invention.

[0033] Referring to FIGS. 1, 4 to 7, the step (S2) of depositing the upper thin film may include a step (S21) of stabilizing the inside of the chamber (200). The stabilization step (S21) may be a step of creating an atmosphere in which the upper thin film (130) can be deposited at a process temperature in a low-temperature range. In order to deposit the upper thin film (130), the inside of the chamber (200) may be created, for example, at a temperature of 100 to 250°C and a pressure of 1.5 to 4.0 Torr.

[0034] With the inside of the chamber (200) stabilized, an upper thin film (130) is deposited on the lower thin film (120) (S22). As described above, the upper thin film (130) can be formed by supplying the source gas (SiH4) and the reaction gas (N2O) in a ratio of 1.2 to 2.5 to 1 under a temperature of 100 to 250°C and a pressure of 1.5 to 4.0 Torr. By increasing the ratio of the source gas (SiH4) by a predetermined amount compared to the ratio of the reaction gas (N2O), the etching selectivity of the upper thin film (130) relative to the lower thin film (120) can be improved. Consequently, the etching selectivity due to low-temperature deposition of the upper thin film (130) can be compensated for.

[0035] In addition, the upper thin film (130) of the present embodiment is deposited under dual frequencies, namely high frequency (HF) and low frequency (LF). By using the low frequency (LF), ion energy and ion bombardment are promoted, thereby compensating for the thermal energy of the upper thin film (130) due to low-temperature deposition and preventing the occurrence of unstable bonding.

[0036] After that, plasma treatment is performed under the dual frequency (S3). The plasma treatment step (S3) can be performed by stopping the supply of the source gas (SiH4) and supplying only the reaction gas (N2O). The plasma treatment step (S3) using N2O gas can be performed in succession with the upper thin film (130) deposition step at a process temperature in the low-temperature range, for example, 100 to 250°C. The surface of the upper thin film (130) can be modified so that the hardness of the surface of the upper thin film (130) is improved by the plasma treatment. Accordingly, the etching selectivity can be further improved. Although not shown in detail in the drawing, an oxide film may be formed on the surface of the upper thin film (130) by the plasma treatment process.

[0037] Afterwards, although not shown in the drawing, the inside of the process chamber (200) is purged to remove unreacted components and impurities within the chamber (200).

[0038] The upper thin film (130) constituting the hard mask film is generally deposited at a high temperature to secure a high etching selectivity. However, when the upper thin film (130) is deposited at a high temperature, thermal damage may be applied to the lower thin film (120) and even to the underlayer (110).

[0039] Accordingly, in this embodiment, the upper thin film (130) is deposited at a process temperature in a low temperature range that does not affect the material properties of the lower layer (120), such as the lower thin film (120), for example, 100 to 250°C.

[0040] In addition, to compensate for the etching selectivity of the upper thin film (130) deposited at a low temperature, the ratio of the source gas is increased more than the ratio of the reaction gas, and the upper thin film (130) can be deposited under a pressure of 1.5 to 4 Torr. Furthermore, in this embodiment, to compensate for the etching selectivity of the upper thin film (130) deposited at a low temperature, plasma treatment is performed in a low-temperature range by supplying only the reaction gas immediately after the deposition of the upper thin film (130). Accordingly, the surface characteristics of the upper thin film are modified, and the etching selectivity is compensated.

[0041] In addition, by using N2O gas with a low hydrogen content as the reaction gas for depositing the upper thin film, the etching selectivity can be further compensated.

[0042] In addition, in this embodiment, when depositing the upper thin film (130), by using an LF power source together with an HF power source, the thermal energy and ion reaction efficiency are compensated, and the etching selectivity of the upper thin film (130) can be further compensated.

[0043] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical concept of the present invention. Explanation of the symbols

[0044] 100: Semiconductor substrate 110: Underlayer 120: Lower thin film 130: Upper thin film 150 : Substrate processing device

Claims

Claim 1 A thin film deposition method using a substrate processing apparatus comprising a chamber that limits a processing space internally, a substrate support located in a lower region of the chamber on which a substrate is placed, a gas supply unit located in an upper region of the chamber that provides a source gas and a reaction gas to the substrate, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, the method comprising: a step of depositing a lower thin film having an etching selectivity ratio with respect to the etching layer on the substrate including the etching layer under a process temperature condition of a low-temperature range; a step of depositing an upper thin film on the lower thin film in a plasma atmosphere under the process temperature condition of the low-temperature range; and a step of treating the surface of the upper thin film in a plasma atmosphere under the process temperature condition of the low-temperature range after the step of depositing the upper thin film, wherein the process temperature of the low-temperature range is 100 to 250°C, and the content of the source gas is increased more than the reaction gas when depositing the upper thin film. Claim 2 A thin film deposition method according to claim 1, wherein the step of depositing the upper thin film comprises, wherein the source gas comprises silicon and the reaction gas comprises nitrogen and oxygen, and the plasma atmosphere is created by applying the high-frequency and low-frequency power sources inside the chamber. Claim 3 In claim 1, the step of depositing the upper thin film is a thin film deposition method in which the ratio of the source gas to the reaction gas is supplied at a ratio of 1.2 to 2.5 to 1. Claim 4 A thin film deposition method according to claim 1, wherein the source gas comprises SiH4 gas. Claim 5 A thin film deposition method according to claim 1, wherein the reaction gas comprises either N2O or NO. Claim 6 A thin film deposition method according to claim 1, wherein the pressure inside the chamber is 1.5 to 4.0 Torr when depositing the upper thin film. Claim 7 A thin film deposition method according to claim 1, wherein the upper thin film comprises a silicon oxynitride film. Claim 8 A thin film deposition method according to claim 1, wherein the power supply unit is characterized in that the high frequency is HF (High frequency) having a center frequency band of 10 MHz to 40 MHz, and the low frequency is LF (low frequency) having a center frequency band of 300 kHz to 500 kHz. Claim 9 A thin film deposition method according to claim 1, wherein the treatment step is carried out by supplying the reaction gas and applying the high-frequency and low-frequency power sources inside the chamber. Claim 10 A thin film deposition method according to claim 1, wherein the treatment step is carried out continuously with the upper thin film deposition step while the supply of the source gas is stopped. Claim 11 A thin film deposition method according to claim 1, wherein the lower thin film is an amorphous carbon film, a titanium oxide film, or SOG (spin on glass). Claim 12 A method for manufacturing a semiconductor device using a thin film deposition method according to any one of claims 1 to 10, comprising: a step of forming a lower layer on top of a semiconductor substrate; a step of depositing a lower thin film having an etching selectivity ratio with respect to the lower layer on top of the lower layer at a process temperature in a low-temperature range; a step of depositing an upper thin film having an etching selectivity ratio with respect to the lower thin film on top of the lower thin film at a process temperature in a low-temperature range; a step of plasma treating the upper thin film to form a hard mask; and a step of patterning the lower layer using the hard mask, wherein the process temperature in the low-temperature range is in the range of 100 to 250°C, the upper thin film is deposited using a reaction gas and a source gas contained in excess of the reaction gas, and the plasma treatment is performed by supplying the reaction gas.

Images