Ferroelectric heterojunction structure device and its manufacturing method, and transistor , artificial visual system, solar cell, gas sensor, and piezoelectric element using the same

Abstract

A heterojunction structure device is provided. The heterojunction structure device may include a gate electrode disposed on a substrate, a ferroelectric layer disposed on the gate electrode and comprising a material having ferroelectric properties, a channel layer disposed on the ferroelectric layer and comprising a material having ferroelectric and semiconductor properties, and a source electrode and a drain electrode disposed on the channel layer spaced apart from each other.

Description

Technology Field

[0001] The present application relates to a heterojunction structure device and a method for manufacturing the same, and more specifically, to a heterojunction structure device having a structure in which different ferroelectric materials are joined and a method for manufacturing the same.

[0002] The heterojunction structure device and the method for manufacturing the same according to the embodiment of the present application can be applied to field-effect transistors, artificial vision systems, solar cells, gas sensors, and piezoelectric elements. Background Technology

[0003] The most complex biological organ is the human brain. Therefore, to build systems that mimic human capabilities, it is essential to study brain-inspired biological neural networks (BNNs). More than 80% of external sensations are transmitted to the retina via optical stimuli, and these sensations are detected, processed, and stored within the brain via BNNs. Artificial neural networks (ANNs) have recently been receiving more attention than algorithm-based digital logic computing because they closely mimic the structural and functional characteristics of BNNs, such as low power consumption, self-learning, and logical reasoning tasks.

[0004] Conventional CMOS (Complementary Metal-Oxide-Semiconductor) image sensors and CCD (Charge-Coupled Device) cameras, capable of detecting and processing optical signals, are widely used digital image capture devices. However, monolithic CMOS image sensors cannot detect a wide (Vis-NIR) wavelength range. Furthermore, conventional digital image sensors consist of three modules—CMOS photosensors, signal processing units, and electronic memristors—and solve structured problems and process data sets based on CMOS logic operations. However, these devices consume significant power and present problems such as being too large and costly for practical applications. Moreover, as the future Internet of Things (IoT) will have greater performance requirements, artificial intelligence cannot meet the demands for low power consumption and high responsiveness between separate memory and processing units. In contrast, neuromorphic vision systems inspired by BNNs can overcome the shortcomings of existing digital computing systems by integrating a wide range of image detection, learning, reasoning, and memory tasks into a single device through self-learning and self-adaptation.

[0005] Over the past few decades, artificial vision systems have been developed with various device structures, such as diodes, resistive memory, and field-effect transistors (FETs), by integrating various optical sensing and synaptic devices. Many materials, such as transition metal dichalcogenides, carbon nitride, perovskites, and organic materials, have been tested for the development of these artificial vision systems.

[0006] Since the optical response of such systems is mostly handled by inter-band transitions or the trapping of excited electrons, the device has the disadvantage of responding mainly to a single wavelength or operating with a narrow bandwidth and complex device configuration.

[0007] To overcome the aforementioned disadvantages and detect unfiltered polychromatic light in a single device, a different strategy is required. Additionally, to reduce the complexity of the device structure and control the effect of incident light on the gate voltage, a three-terminal structure based on a minimum number of transistors is required, which allows various processing tasks to be performed within a single device.

[0008] Ferroelectrics are receiving significant attention due to the spontaneous electric dipole polarization and domain wall movement under external electric fields, mechanical strain, or light irradiation. Oxide ferroelectrics based on the ABO3 structure are commonly studied due to the spontaneous polarization caused by the distortion of off-center B ions. In addition to these oxide ferroelectrics, van der Waals (vdW) layered ferroelectrics (CIPS, α-In2Se3, SnS, InSe, 1T WTe2) are leading a paradigm shift in fundamental research and technology due to their small size (atomic-scale thin layers), individual dipoles capable of overcoming depolarization fields, and strong ferroic coupling between dipoles.

[0009] Among these 2D ferroelectrics, α-In2Se3 has the characteristic of having both in-plane (IP) and out-of-plane (OOP) polarizations due to its pentabundant structure in which intermediate Se atoms can be easily displaced left and right within the crystal. Therefore, various studies are being conducted on α-In2Se3.

[0010] For example, 'Dutta, D.; Mukherjee, S.; Uzhansky, M.; Koren, E. Cross-field optoelectronic modulation via inter-coupled ferroelectricity in 2D In2Se3. npj 2D Materials and Applications 2021' experimentally demonstrated that these dipoles are locked in both directions within α-In2Se3 controlled by a vertical gate voltage.

[0011] As another example, 'Rubio-Marcos, F.; Ochoa, DA; Del Campo, A.; Garcia, MA; Castro, GR; Fernandandez, JF; Garcia, JE Reversible optical control of macroscopic polarization in ferroelectrics. Nature Photonics 2017' discovered a change in polar order caused by light in ferroelectrics and presented the possibility of switching polarization regions in a non-contact and remote manner.

[0012] As another example, 'Xue, F.; He, X.; Liu, W.; Periyanagounder, D.; Zhang, C.; Chen, M.; Lin, CH; Luo, L.; Yengel, E.; Tung, V.; et al. Optoelectronic Ferroelectric Domain-Wall Memories Made from a Single Van Der Waals Ferroelectric. Advanced Functional Materials 2020' demonstrated a memory effect caused by the movement of a ferroelectric domain wall controlled by external optical illumination of an α-In2Se3 device.

[0013] Accordingly, the present application aims to propose a device capable of performing optical signal detection, processing, and memory within a single device based on an α-In2Se3 ferroelectric having a heterojunction structure to develop an artificial vision system. Prior art literature

[0014] Dutta, D.; Mukherjee, S.; Uzhansky, M.; Koren, E. Cross-field optoelectronic modulation via inter-coupled ferroelectricity in 2D In2Se3. npj 2D Materials and Applications 2021, 5 (1).Rubio-Marcos, F.; Ochoa, D. A.; Del Campo, A.; Garcia, M.A.; Castro, G.R.; Fernαndez, J.F.; Garcia, J.E. Reversible optical control of macroscopic polarization in ferroelectrics. Nature Photonics 2017, 12 (1), 29-32. DOI: 10.1038 / s41566-017-0068-1.Xue, F.; He, X.; Liu, W.; Periyanagounder, D.; Zhang, C.; Chen, M.; Lin, C.H.; Luo, L.; Yengel, E.; Tung, V.; et al. Optoelectronic Ferroelectric Domain-Wall Memories Made from a Single Van Der Waals Ferroelectric. Advanced Functional Materials 2020, 30 (52). The problem to be solved

[0015] One technical problem that the present invention aims to solve is to provide a heterojunction structure device in which layers of different ferroelectric materials are joined, and a method for manufacturing the same.

[0016] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device in which the polarization of a channel layer can be controlled by light irradiated onto the channel layer, and a method for manufacturing the same.

[0017] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device in which the polarization of the ferroelectric layer can be controlled by the voltage applied to the gate electrode, and a method for manufacturing the same.

[0018] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device in which the polarization of the channel layer can be controlled by the voltage applied to the gate electrode, and a method for manufacturing the same.

[0019] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device capable of performing detection, processing, and memory of external signals (optical signals and electrical signals) all within a single device, and a method for manufacturing the same.

[0020] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device capable of detecting optical signals over a wide wavelength range and a method for manufacturing the same.

[0021] Another technical problem that the present invention aims to solve is to provide a heterojunction structure device capable of detecting optical signals of weak intensity and a method for manufacturing the same.

[0022] Another technical problem that the present invention aims to solve is to provide a field-effect transistor to which the above-described heterojunction structure element is applied.

[0023] Another technical problem that the present invention aims to solve is to provide an artificial vision system to which the above-described heterojunction structure element is applied.

[0024] Another technical problem that the present invention aims to solve is to provide a solar cell to which the above-described heterojunction structure element is applied.

[0025] Another technical problem that the present invention aims to solve is to provide a gas sensor to which the above-described heterojunction structure element is applied.

[0026] Another technical problem that the present invention aims to solve is to provide a piezoelectric element to which the above-described heterojunction structure element is applied.

[0027] The technical problems that the present invention aims to solve are not limited to those described above. means of solving the problem

[0028] To solve the technical problems described above, the present invention provides a heterojunction structure element.

[0029] According to one embodiment, the heterojunction structure device may include a gate electrode disposed on a substrate, a ferroelectric layer disposed on the gate electrode and comprising hafnium zirconium oxide (HZO), a channel layer disposed on the ferroelectric layer and comprising alpha-indium selenide (α-In2Se3), and a source electrode and a drain electrode disposed on the channel layer so as to be spaced apart from each other.

[0030] According to one embodiment, the heterojunction structure element may further include an insulating layer disposed between the ferroelectric layer and the channel layer.

[0031] According to one embodiment, the insulating layer may include aluminum oxide (Al2O3).

[0032] According to one embodiment, the heterojunction structure device may include the polarization of the channel layer being controlled by light irradiated onto the channel layer.

[0033] According to one embodiment, the heterojunction structure device may include the polarization of the ferroelectric layer being controlled by a voltage applied to the gate electrode.

[0034] According to another embodiment, the heterojunction structure device may include a gate electrode disposed on a substrate, a ferroelectric layer disposed on the gate electrode and comprising a material having ferroelectric properties, a channel layer disposed on the ferroelectric layer and comprising a material having ferroelectric and semiconductor properties, and a source electrode and a drain electrode disposed on the channel layer so as to be spaced apart from each other.

[0035] According to another embodiment, the ferroelectric layer may include a material having out-of-plane (OOP) polarization characteristics.

[0036] According to another embodiment, the channel layer may include a material having both vertical direction (out-of-plane, OOP) polarization characteristics and horizontal direction (in-plane, IP) polarization characteristics.

[0037] According to another embodiment, the ferroelectric layer comprises hafnium zirconium oxide (HZO), arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), d1T-MoS2, t-MoS2, WS2, WSe2, WTe2, BiN, SbN, BiP, GaN, GaSe, SiC, BN, AIN, ZnO, GeS, GeSe, SnS, SnSe, SiTE, GeTe, SnTE, PbTe, CrN, CrB2, CrBr3, Crl3, GaTeCl, AgBiP2Se6, CuCrP2S6, CuCrP2Se6, CuVP2S6, CuVP2Se6, CuInP2Se6, CuInP2S6(CIPS), Sc2CO2, Bi2O2Se, Bi2O2Te, Bi2O2s, Ba2PbCl4, graphanol, It may include any one of hydroxyl-functionalized graphene, halogen-decorated phosphorene, g-C6N8H, and Bi-CH2OH.

[0038] According to another embodiment, the channel layer may include any one of alpha-indium selenide (α-In2Se3), 1T-MoS2, MoSSe, MoTe, SnS, SnSe, SnTe, GeS, GeSe, and GeTe.

[0039] According to another embodiment, the heterojunction structure device may include the polarization of the channel layer being controlled by light irradiated onto the channel layer.

[0040] According to another embodiment, the heterojunction structure device may include the polarization of the ferroelectric layer being controlled by a voltage applied to the gate electrode.

[0041] According to another embodiment, the heterojunction structure device may include a gate electrode disposed on a substrate, a ferroelectric layer disposed on the gate electrode and comprising a material having ferroelectric properties, an insulating layer disposed on the ferroelectric layer, a channel layer disposed on the insulating layer and comprising a material having ferroelectric and semiconductor properties, and a source electrode and a drain electrode disposed spaced apart from each other on the channel layer.

[0042] According to another embodiment, the insulating layer may include aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and hexagonal boron nitride (h-BN).

[0044] To solve the technical problems described above, the present invention provides a method for manufacturing a heterojunction structure device.

[0045] According to one embodiment, the method for manufacturing the heterojunction structure device may include the steps of preparing a substrate, forming a gate electrode on the substrate, forming a ferroelectric layer comprising a material having ferroelectric properties on the gate electrode, forming an insulating layer on the ferroelectric layer, forming a channel layer comprising a material having ferroelectric and semiconductor properties on the insulating layer, and forming a source electrode and a drain electrode spaced apart from each other on the channel layer. Effects of the invention

[0046] In a heterojunction structure device according to an embodiment of the present invention, the polarization of the channel layer (α-In2Se3) is controlled by light irradiated onto the channel layer, and the polarization of the ferroelectric layer is controlled by a voltage applied to the gate electrode. Accordingly, the heterojunction structure device can perform detection, processing, and memory of external signals (optical signals and electrical signals) all within a single device. As a result, the heterojunction structure device can be easily applied as an artificial visual system.

[0047] In addition, due to the intrinsic polarization characteristics of the channel layer (α-In2Se3) (bidirectional polarization characteristics in which horizontal and vertical polarizations are interconnected), the heterojunction structure device can transmit light over a wide wavelength range (e.g., 405 nm to 850 nm) and light of very low intensity (0.03 mW / cm²). 3 It can detect ).

[0048] In addition, the above heterojunction structure device can implement Paired Pulse Facilitation (PPF), an electrical characteristic that an artificial synapse device must possess, and a transition characteristic from short-term memory (STM) to long-term memory (LTM), and can perform logic operations such as pattern recognition, light adaptation training, and Pavlov's training. Brief explanation of the drawing

[0049] FIG. 1 is a flowchart illustrating a method for manufacturing a heterojunction structure device according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating steps S110 and S120 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating steps S130 and S140 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention. FIG. 4 is a schematic diagram illustrating step S150 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention. FIG. 5 is a schematic diagram illustrating step S160 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention. FIG. 6 is a schematic diagram illustrating step S210 of the manufacturing process of an artificial synapse device according to a first variant of the present invention. FIG. 7 is a schematic diagram illustrating step S220 of the manufacturing process of an artificial synapse device according to a first variant of the present invention. FIG. 8 is a schematic diagram illustrating step S230 of the manufacturing process of an artificial synapse device according to a first variant of the present invention. FIG. 9 is a schematic diagram illustrating step S340 of the manufacturing process of an artificial synapse device according to a second variant of the present invention. FIG. 10 is a schematic diagram illustrating step S350 of the manufacturing process of an artificial synapse device according to a second variant of the present invention. FIG. 11 is a schematic diagram illustrating step S360 of the manufacturing process of an artificial synapse device according to a second variant of the present invention. FIG. 12 is a schematic diagram illustrating step S370 of the manufacturing process of an artificial synapse device according to a second variant of the present invention. FIG. 13 is a schematic cross-sectional view of a ferroelectric field-effect transistor according to a third modified example of the present invention. FIG. 14 is a schematic plan view of a ferroelectric field-effect transistor according to a third modified example of the present invention. FIG. 15 is a schematic diagram illustrating the manufacturing process of an Fe FET device according to an experimental example of the present invention. FIG. 16 is a schematic diagram illustrating an Fe FET device according to an experimental example of the present invention. FIG. 17 is a diagram illustrating the AFM analysis results of the ferroelectric layer of an Fe FET device according to an experimental example of the present invention. FIG. 18 is a diagram illustrating the results of AFM analysis of the insulating layer of an Fe FET device according to an experimental example of the present invention. FIG. 19 is a diagram illustrating the AFM analysis results for the channel layer of an Fe FET device according to an experimental example of the present invention. FIG. 20 is a diagram illustrating the results of Raman analysis of a heterojunction structure of an Fe FET device according to an experimental example of the present invention. FIG. 21 is a diagram showing TEM images and EDS mapping images of a heterojunction structure of an Fe FET device according to an experimental example of the present invention. FIG. 22 is a diagram showing the location where AFM scanning was used to verify the operation of an Fe FET device according to an experimental example of the present invention. Figure 23 is a diagram showing the surface potential measured in the channel layer between the source electrode and the drain electrode when a negative voltage is applied to the gate electrode. Figure 24 is a diagram showing the surface potential measured in the channel layer between the source electrode and the drain electrode when a positive voltage is applied to the gate electrode. Figure 25 is a diagram showing a PFM phase image under dark conditions. Figure 26 is a diagram showing the PFM phase value measured when voltages of opposite polarity are applied to the gate electrode under dark conditions. Figure 27 is a diagram showing a schematic diagram of dipole polarization under dark conditions. Figure 28 is a diagram showing a PFM phase image under bright conditions. Figure 29 is a diagram showing the PFM phase value measured when voltages of opposite polarity are applied to the gate electrode under bright conditions. Figure 30 is a diagram showing a schematic diagram of dipole polarization under bright conditions. FIG. 31 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to an experimental example of the present invention. FIG. 32 is a diagram illustrating the voltage-current characteristics of an Fe-FeT device according to a comparative example of the present invention. FIG. 33 is a diagram illustrating the change in transfer characteristics according to the scanning voltage range of an Fe FET device according to an experimental example of the present invention. FIG. 34 is a diagram illustrating the change in transfer characteristics according to the change in read voltage of an Fe FET device according to an experimental example of the present invention. FIG. 35 is a diagram illustrating the on / off ratio of an Fe FET device according to an experimental example of the present invention. FIG. 36 is a diagram illustrating the memory window of an Fe FET device according to an experimental example of the present invention. FIG. 37 is a diagram illustrating the output characteristics of an Fe FET device according to an experimental example of the present invention. FIG. 38 is a schematic diagram showing the measurement of electrical synapses using an Fe FET device according to an experimental example of the present invention. FIG. 39 is a diagram illustrating the short-term downsizing effect of an Fe FET device according to an experimental example of the present invention. FIG. 40 is a diagram illustrating the short-term strengthening effect of an Fe FET device according to an experimental example of the present invention. Figure 41 is a diagram showing a model of the optical signal detection and information memory process. FIG. 42 is a diagram illustrating the current value according to the number of signals input to an Fe FET device according to an experimental example of the present invention. FIG. 43 is a diagram illustrating the normalized attenuation current value according to the number of signals input to the Fe FET device according to an experimental example of the present invention. FIG. 44 is a diagram illustrating the conversion of short-term memory into long-term memory through an Fe FET device according to an experimental example of the present invention. FIG. 45 is a diagram illustrating the PPF measurement results of an Fe FET device according to an experimental example of the present invention. FIGS. 46 to 49 are drawings for explaining the PPF ratio of an Fe FET device according to an experimental example of the present invention. Figure 50 is a diagram showing the fast relaxation time and slow relaxation time of the damping curve for various wavelengths. Figure 51 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 405 nm is irradiated. Figure 52 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 655 nm is irradiated. Figure 53 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 785 nm is irradiated. Figure 54 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 850 nm is irradiated. FIGS. 55 to 58 are drawings for explaining the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. FIG. 59 is a diagram illustrating the long-term stability of the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention. Figure 60 is a schematic diagram of an ANN for MNIST pattern recognition. Figure 61 is a diagram illustrating pattern recognition accuracy according to Epoch. Figure 62 is a diagram illustrating the results of a light adaptation test when weak light stimulation is applied. Figure 63 is a diagram illustrating the results of a light adaptation test when strong light stimulation is applied. Figure 64 is a diagram illustrating the results of a light adaptation test when both strong light stimulation and electrical stimulation are applied. FIG. 65 is a diagram showing the OR logic operation according to optical signal change and electrical signal change. FIG. 66 is a diagram showing AND logic operation according to optical signal change and electrical signal change. FIG. 67 is a diagram illustrating the multi-state characteristics of an Fe FET device according to an experimental example of the present invention. Figure 68 is a diagram showing the current value when a conditional stimulus is applied. Figure 69 is a diagram showing the current value when unconditional stimulation is applied. Figure 70 is a diagram showing the current value when conditional stimulation and unconditional stimulation are applied simultaneously. Figure 71 is a diagram showing the current values ​​when only conditional stimulation is applied after training. Specific details for implementing the invention

[0050] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the concept of the present invention to those skilled in the art.

[0051] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0052] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0053] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0054] In addition, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0056] Heterojunction structure device and method for manufacturing the same

[0057] FIG. 1 is a flowchart for explaining a method for manufacturing a heterojunction structure device according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining steps S110 and S120 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention, FIG. 3 is a schematic diagram for explaining steps S130 and S140 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention, FIG. 4 is a schematic diagram for explaining step S150 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention, and FIG. 5 is a schematic diagram for explaining step S160 of a method for manufacturing a heterojunction structure device according to an embodiment of the present invention.

[0058] Referring to FIGS. 1 and 2, a substrate (100) may be prepared (S110). According to one embodiment, the substrate (100) may be a silicon semiconductor substrate. More specifically, the substrate (100) may be a substrate on which a silicon oxide (SiO2) layer (120) is formed on a silicon (Si) substrate (110). Alternatively, according to another embodiment, the substrate (100) may be a compound semiconductor substrate. Alternatively, according to yet another embodiment, the substrate (100) may be a glass substrate. Alternatively, according to yet another embodiment, the substrate (100) may be a plastic substrate. The type of the substrate (100) is not limited.

[0059] A gate electrode (200) may be formed on the substrate (100) (S120). According to one embodiment, the gate electrode (200) may include a metal. For example, the gate electrode (200) may include gold (Au). According to one embodiment, the gate electrode (200) may be formed by electron beam lithography and electron beam deposition methods. Additionally, according to one embodiment, the gate electrode (200) may be formed with a thickness of 60 nm. The above-described method of forming the gate electrode (200), material, and thickness are exemplary, and the method of forming the gate electrode (200), material, and thickness are not limited.

[0060] Referring to FIG. 1 and FIG. 3, a ferroelectric layer (300) can be formed on the gate electrode (200) (S130). According to one embodiment, the ferroelectric layer (300) is a material having ferroelectric properties, such as hafnium zirconium oxide (HZO), arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), d1T-MoS2, t-MoS2, WS2, WSe2, WTe2, BiN, SbN, BiP, GaN, GaSe, SiC, BN, AIN, ZnO, GeS, GeSe, SnS, SnSe, SiTE, GeTe, SnTE, PbTe, CrN, CrB2, CrBr3, Crl3, GaTeCl, AgBiP2Se6, CuCrP2S6, CuCrP2Se6, CuVP2S6, CuVP2Se6, CuInP2Se6, CuInP2S6(CIPS), Sc2CO2, Bi2O2Se, Bi2O2Te, Bi2O2s, It may include any one of Ba2PbCl4, graphanol, hydroxyl-functionalized graphene, halogen-decorated phosphorene, g-C6N8H, and Bi-CH2OH.

[0061] According to one embodiment, the ferroelectric layer (300) may be formed by dry transferring a ferroelectric material mechanically peeled from bulk onto the gate electrode (200). The method of forming the ferroelectric layer (300) is not limited.

[0062] An insulating layer (400) may be formed on the ferroelectric layer (300). According to one embodiment, the insulating layer (400) may comprise hexagonal boron nitride (h-BN). In this case, the insulating layer (400) may be formed by dry transferring hexagonal boron nitride (h-BN), mechanically exfoliated from the bulk, onto the ferroelectric layer (300). Alternatively, according to another embodiment, the insulating layer (400) may comprise any one of aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0063] The insulating layer (400) is intended to reduce the gate leakage current between the ferroelectric layer (300) and the channel layer (500) described later, and if the insulating layer (400) is omitted, a problem of device degradation due to gate leakage current may occur.

[0064] Referring to FIGS. 1 and FIGS. 4, a channel layer (500) may be formed on the insulating layer (400) (S150). According to one embodiment, the channel layer (500) may include a material having ferroelectric and semiconductor properties. For example, the channel layer (500) may include any one of alpha-indium selenide (α-In2Se3), 1T-MoS2, MoSSe, MoTe, SnS, SnSe, SnTe, GeS, GeSe, and GeTe.

[0065] According to one embodiment, the channel layer (500) may be formed by dry transferring a channel material mechanically peeled from the bulk onto the insulating layer (400). The method of forming the channel layer (500) is not limited.

[0066] Referring to FIGS. 1 and 5, a source electrode (S) and a drain electrode (D) may be formed on the channel layer (500) so as to be spaced apart from each other (S160). According to one embodiment, the source electrode (S) may comprise titanium (Ti) and gold (Au). More specifically, the source electrode (S) may have a structure in which gold (Au) with a thickness of 60 nm is stacked on titanium (Ti) with a thickness of 10 nm. Additionally, according to one embodiment, the drain electrode (D) may comprise titanium (Ti) and gold (Au). More specifically, the drain electrode (D) may have a structure in which gold (Au) with a thickness of 60 nm is stacked on titanium (Ti) with a thickness of 10 nm. According to one embodiment, the source electrode (S) and the drain electrode (D) may be formed by an electron beam deposition (E-beam deposition) method. The material and method of forming the source electrode (S) and the drain electrode (D) are not limited.

[0067] That is, a heterojunction structure device according to an embodiment of the present invention can be implemented as a ferroelectric field effect transistor (Fe FET), comprising a gate electrode (200) disposed on a substrate (100), a ferroelectric layer (300) disposed on the gate electrode, an insulating layer (400) disposed on the ferroelectric layer, a channel layer (500) disposed on the insulating layer (400), and a source electrode (S) and a drain electrode (D) disposed spaced apart from each other on the channel layer (500).

[0068] In addition, the present invention can be easily applied to an artificial visual system by enabling the detection, processing, and memory of external signals (optical signals and electrical signals) to be performed all within a single ferroelectric field-effect transistor device.

[0069] To this end, the present invention may be configured such that the ferroelectric layer (300) comprises a material having out-of-plane (OOP) polarization characteristics, and the channel layer (500) comprises a material having both out-of-plane (OOP) polarization characteristics and in-plane (IP) polarization characteristics. More specifically, the present invention may be configured such that the ferroelectric layer (300) comprises CuInP2S6 (CIPS) and the channel layer (500) comprises alpha-indium selenide (α-In2Se3). Additionally, the present invention may be configured such that the insulating layer (400) comprises hexagonal boron nitride (h-BN) so that the electrical potential energy generated due to the polarization phenomenon occurring in the ferroelectric layer (300) can maintain its influence on the polarization shape of the channel layer (500).

[0070] In describing the present invention, "polarization" may refer to a phenomenon in which the positions of negative and positive charges are separated within an electric field to form a dipole moment. Additionally, "horizontal polarization" may refer to a phenomenon in which the positions of negative and positive charges are separated along a direction parallel to the straight line from the source electrode (S) to the drain electrode (D) to form a dipole moment. Furthermore, "vertical polarization" may refer to a phenomenon in which the positions of negative and positive charges are separated along a direction perpendicular to the straight line from the source electrode (S) to the drain electrode (D) to form a dipole moment.

[0071] A ferroelectric field-effect transistor having a structure (bottom electrode / CIPS / h-BN / α-In2Se3) as described above can have the polarization of the channel layer (500) controlled by light irradiated on the channel layer (500), and the polarization of the ferroelectric layer (300) controlled by a voltage applied to the gate electrode (200). Accordingly, the ferroelectric field-effect transistor can perform detection, processing, and memory of external signals (optical signals and electrical signals) within a single device. As a result, the ferroelectric field-effect transistor can be easily applied to an artificial visual system.

[0072] In addition, due to the intrinsic polarization characteristics of α-In2Se3 (bidirectional polarization characteristics in which horizontal and vertical polarizations are interconnected), the ferroelectric field-effect transistor can utilize light over a wide wavelength range (e.g., 405 nm to 850 nm) and light of very low intensity (0.03 mW / cm²). 3 It can detect ).

[0073] Furthermore, the above-mentioned ferroelectric field-effect transistor can implement Paired Pulse Facilitation (PPF), an electrical characteristic required of an artificial synapse device, and the characteristic of transitioning from short-term memory (STM) to long-term memory (LTM), and can perform logic operations such as pattern recognition, light adaptation training, and Pavlov's training. The characteristics of the above-mentioned ferroelectric field-effect transistor are explained in detail through experimental examples described later.

[0074] Unlike the above, a ferroelectric field-effect transistor having an α-In2Se3 / h-BN / CIPS / top electrode structure may experience a problem in which light irradiation of the channel layer is not efficiently achieved because the channel layer is obscured by the top electrode. Additionally, while the bottom electrode / CIPS structure forms a Van der Waals metal contact, the CIPS / top electrode structure may form a thermally evaporated metal contact. In the case of a thermally evaporated metal contact, various defects such as interlattice defects, void defects, and antisite defects can be formed more easily compared to a Van der Waals metal contact. That is, in the case of the CIPS / top electrode structure, a problem may arise in which various physical and chemical defects are formed more frequently within the CIPS and the electrode compared to the bottom electrode / CIPS structure.

[0076] For the above, a heterojunction structure device and a method for manufacturing the same according to an embodiment of the present invention have been described. Hereinafter, various application examples of a heterojunction structure (CIPS / h-BN / α-In2Se3) according to an embodiment of the present invention are described.

[0077] According to one embodiment, a heterojunction structure (CIPS / h-BN / α-In2Se3) according to an embodiment of the present invention can be used as a semiconductor layer of a solar cell. More specifically, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a solar cell that converts light energy into electrical energy using the photovoltaic effect.

[0078] In contrast, according to another embodiment, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a gas sensor. More specifically, since the heterojunction structure (CIPS / h-BN / α-In2Se3) has spontaneous polarization characteristics in response to electric force, it can adsorb or release gas molecules (e.g., NH3 gas molecules, NO2 gas molecules) depending on the polarization direction of the surface of the ferroelectric material.

[0079] In contrast, according to another embodiment, the heterojunction structure (CIPS / h-BN / α-In2Se3) can be applied to a piezoelectric sensor. More specifically, since the ferroelectric material has piezoelectric properties, it can be applied to a piezoelectric sensor that utilizes the phenomenon in which dielectric polarization occurs in the heterojunction structure (CIPS / h-BN / α-In2Se3) due to physical deformation applied to the heterojunction structure (CIPS / h-BN / α-In2Se3).

[0081] Various application examples of a heterojunction structure according to an embodiment of the present invention have been described above. Hereinafter, various modification examples of a heterojunction structure element according to an embodiment of the present invention are described.

[0082] First variant example: CIPS / h-BN / α-In 2 Se 3 + Mxene artificial synapse device

[0083] FIG. 6 is a schematic diagram illustrating step S210 of the manufacturing process of an artificial synapse device according to a first modified example of the present invention, FIG. 7 is a schematic diagram illustrating step S220 of the manufacturing process of an artificial synapse device according to a first modified example of the present invention, and FIG. 8 is a schematic diagram illustrating step S230 of the manufacturing process of an artificial synapse device according to a first modified example of the present invention.

[0084] Referring to FIG. 6, a gate electrode (200), a ferroelectric layer (300), an insulating layer (400), and a first channel layer (500) can be sequentially formed on the first region (A1) of a substrate (100) including a first region (A1) and a second region (A2) different from the first region (A1) (S210).

[0085] According to one embodiment, the method of forming the gate electrode (200), the ferroelectric layer (300), the insulating layer (400), and the first channel layer (500) may be the same as the method of forming the gate electrode (200), the ferroelectric layer (300), the insulating layer (400), and the channel layer (500) of the heterojunction structure device described with reference to FIGS. 1 to 4.

[0086] Referring to FIG. 7, a second channel layer (600) may be formed on the second region (A2) of the substrate (100) (S220). According to one embodiment, the second channel layer (600) may include MXene.

[0087] Referring to FIG. 8, a first source electrode (S1), a drain electrode (D), and a second source electrode (S2) may be formed on the first channel layer (500) and the second channel layer (600) (S230). More specifically, the first source electrode (S1) may be formed on one side of the upper surface of the first channel layer (500) and the drain electrode (D) may be formed on the other side. Additionally, the drain electrode (D) may be formed on one side of the upper surface of the second channel layer (600) and the second source electrode (S2) may be formed on the other side. Furthermore, the drain electrode (D) may be formed so that the first channel layer (500) and the second channel layer (600) share it with each other. That is, the drain electrode (D) can be formed to contact the other side of the upper surface of the first channel layer (500) and also to contact one side of the upper surface of the second channel layer (600).

[0088] The first channel layer (500), i.e., α-In2Se3, can be responsible for potentiation in the artificial synapse device, and the second channel layer (600), i.e., Mxene, can be responsible for depression in the artificial synapse device. In addition, in the artificial synapse device having the structure (CIPS / h-BN / α-In2Se3+Mxene) described above, potentiation of the first channel layer (500) and depression of the second channel layer (600) can both be generated by an optical signal. That is, potentiation and depression can be generated by a single signal (optical signal). Accordingly, the burden and complexity of the surrounding circuitry can be reduced, and the processing speed of the system can also be improved.

[0089] In contrast, in the case of an artificial synapse device having a structure (CIPS / h-BN / α-In2Se3) described with reference to FIGS. 1 to 5, potentiation may be generated by an optical signal due to a unidirectional optical response, while depression may be generated by an electrical signal. As such, when two signals (optical and electrical signals) are combined and used, not only is the burden and complexity of the surrounding circuitry increased, but there may also be a limit to the processing speed of the system.

[0090] Example of 2nd variation: CIPS / h-BN / α-In 2 Se 3 + Mxene + Oxide layer artificial synapse device

[0091] FIG. 9 is a schematic diagram illustrating step S340 of the manufacturing process of an artificial synapse device according to a second modified example of the present invention, FIG. 10 is a schematic diagram illustrating step S350 of the manufacturing process of an artificial synapse device according to a second modified example of the present invention, FIG. 11 is a schematic diagram illustrating step S360 of the manufacturing process of an artificial synapse device according to a second modified example of the present invention, and FIG. 12 is a schematic diagram illustrating step S370 of the manufacturing process of an artificial synapse device according to a second modified example of the present invention.

[0092] A method for manufacturing an artificial synapse device according to a second variant of the present invention may include the steps of: sequentially forming a gate electrode (200), a ferroelectric layer (300), an insulating layer (400), and a first channel layer (500) on a first region (A1) of a substrate (100) (S310); forming a second channel layer (600) on a second region (A2) of the substrate (100) (S320); forming a first source electrode (S1), a drain electrode (D), and a second source electrode (S2) on the first channel layer (500) and the second channel layer (600) (S330); forming a mask layer (ML) (S340); etching the mask layer (ML) (S350); forming an oxide layer (700) (S360); and removing the mask layer (ML) (S370).

[0093] The steps S310 to S330 included in the method for manufacturing an artificial synapse device according to the second modified example above may be the same as the steps S210 to S230 included in the method for manufacturing an artificial synapse device according to the first modified example above, as described with reference to FIGS. 6 to 8. Accordingly, a detailed description is omitted.

[0094] Referring to FIG. 9, a mask layer (ML) may be formed on the substrate (100) to cover the first source electrode (S1), the drain electrode (D), the second source electrode (S2), the first channel layer (500), and the second channel layer (600). According to one embodiment, the mask layer (ML) may include a polymer. For example, the polymer may include polymethyl methacrylate (PMMA).

[0095] Referring to FIG. 10, the mask layer (ML) disposed between the second source electrode (S2) and the drain electrode (D) and overlapping with the second channel layer (600) can be etched. According to one embodiment, the etching of the mask layer (ML) can be achieved through oxygen plasma (O2 plasma) treatment and electron beam lithography (E-beam lithography). Accordingly, the upper surface of the second channel layer (600) between the second source electrode (S2) and the drain electrode (D) can be exposed to the outside.

[0096] Referring to FIGS. 11 and 12, after forming an oxide layer (700) on the exposed upper surface of the second channel layer (600) (S360), the mask layer (ML) remaining on the substrate (100) can be removed (S370). According to one embodiment, the oxide layer (700) may include a metal oxide. For example, the oxide layer (700) may include titanium oxide (TiO2).

[0097] In the case of the MXene included in the second channel layer (600), oxidation occurs easily upon contact with air, and the oxidized region acts as a charge trap site, and the charge trap site acts as a scattering center under light illumination, which can reduce electrical conductivity. That is, if the second channel layer (600) is exposed to the outside, a problem may arise in which electrical conductivity is reduced due to oxidation caused by contact with air. However, in the case of the artificial synapse device according to the second modified example, by forming an oxide layer (700) on the exposed upper surface of the second channel layer (600), the problem of reduced conductivity caused by the second channel layer (600) coming into contact with air can be easily resolved.

[0098] Third variant example: Split Gate Ferroelectric Field Effect Transistor (Split Gate Fe FET)

[0099] FIG. 13 is a cross-sectional schematic diagram of a ferroelectric field-effect transistor according to a third modified example of the present invention, and FIG. 14 is a planar schematic diagram of a ferroelectric field-effect transistor according to a third modified example of the present invention.

[0100] Referring to FIG. 13 and FIG. 14, the ferroelectric field-effect transistor according to the third modified example may include a substrate (100), a first gate electrode (210) and a second gate electrode (220) disposed spaced apart from each other on the substrate (100), a ferroelectric layer (300) disposed on the first gate electrode (210) and the second gate electrode (220), an insulating layer (400) disposed on the ferroelectric layer (300), a channel layer (500) disposed on the insulating layer (400), and a source electrode (S) and a drain electrode (D) disposed spaced apart from each other on the channel layer (500).

[0101] According to one embodiment, the substrate (100), the first and second gate electrodes (210, 220), the ferroelectric layer (300), the insulating layer (400), the channel layer (500), the source electrode (S), and the drain electrode (D) included in the ferroelectric field-effect transistor according to the third modified example may be the same as the substrate (100), the gate electrode (200), the ferroelectric layer (300), the insulating layer (400), the channel layer (500), the source electrode (S), and the drain electrode (D) included in the heterojunction structure device described with reference to FIGS. 1 to 5.

[0102] The ferroelectric field-effect transistor according to the third modified example above can form a dynamic change in the memory window by controlling the areas of the first gate electrode (210) and the second gate electrode (220). Additionally, during a write operation, both the first gate electrode (210) and the second gate electrode (220) are used to reduce the subthreshold swing, whereas during a read operation, only one of the gate electrodes, either the first gate electrode (210) or the second gate electrode (220), is used to enhance the memory window. Accordingly, a spiking neural network (SNN) combining an artificial synapse and a spiking neuron can be implemented.

[0104] For the above, various modified examples of heterojunction structure devices according to embodiments of the present invention have been described. Below, specific experimental examples and characteristic evaluation results of heterojunction structure devices according to embodiments of the present invention are described.

[0105] Experimental Example 1: Fe FET Device Fabrication and Structural Characteristics

[0106] FIG. 15 is a schematic diagram for explaining the manufacturing process of an Fe FET device according to an experimental example of the present invention, and FIG. 16 is a schematic diagram for explaining an Fe FET device according to an experimental example of the present invention.

[0107] Referring to FIGS. 15 and 16, a 60 nm thick gold (Au) electrode was deposited as a gate electrode on a SiO2 / Si substrate by electron beam lithography and electron beam deposition. Subsequently, multiple layers of CuInP2S6 (CIPS), h-BN, and α-In2Se3 were obtained through physical exfoliation, and these were sequentially transferred onto the gate electrode by a dry transfer method to form a heterojunction structure in the form of CIPS / h-BN / α-In2Se3 (ferroelectric layer / insulating layer / channel layer). Finally, a source electrode and a drain electrode were deposited on the α-In2Se3 (channel layer) so as to be spaced apart from each other. Specifically, both the source electrode and the drain electrode used a structure in which a 60 nm thick gold (Au) layer was stacked on a 10 nm thick titanium (Ti) layer.

[0108] FIG. 17 is a diagram illustrating the AFM analysis results of the ferroelectric layer of an Fe FET device according to an experimental example of the present invention.

[0109] Referring to Fig. 17, the results of Atomic Force Microscopy (AFM) analysis of the ferroelectric layer (CIPS) of the Fe FET device according to the above experimental example and the thickness of the ferroelectric layer measured through this are shown. As can be seen in Fig. 17, it can be confirmed that the ferroelectric layer (CIPS) has a thickness of approximately 75 nm.

[0110] FIG. 18 is a diagram illustrating the results of AFM analysis of the insulating layer of an Fe FET device according to an experimental example of the present invention.

[0111] Referring to FIG. 18, the results of Atomic Force Microscopy (AFM) analysis of the insulating layer (hBN) of the Fe FET device according to the experimental example above and the thickness of the ferroelectric layer measured through this are shown. As can be seen in FIG. 18, the insulating layer (hBN) has a thickness of approximately 12 nm.

[0112] FIG. 19 is a diagram illustrating the AFM analysis results for the channel layer of an Fe FET device according to an experimental example of the present invention.

[0113] Referring to Fig. 19, the results of Atomic Force Microscopy (AFM) analysis of the channel layer (α-In2Se3) of the Fe FET device according to the above experimental example and the thickness of the channel layer measured through this are shown. As can be seen in Fig. 19, it can be confirmed that the channel layer (α-In2Se3) has a thickness of approximately 45 nm.

[0114] FIG. 20 is a diagram illustrating the results of Raman analysis of a heterojunction structure of an Fe FET device according to an experimental example of the present invention.

[0115] Referring to FIG. 20, the Raman spectra measurement results for the ferroelectric layer (CIPS), channel layer (α-In2Se3), and CIPS / α-In2Se3 junction structure of the Fe FET device according to the experimental example above are shown. Specifically, the black line represents the measurement result for the channel layer (α-In2Se3), the red line represents the measurement result for the ferroelectric layer (CIPS), and the blue line represents the measurement result for the CIPS / α-In2Se3 junction structure. As can be seen in FIG. 20, it can be confirmed through the Raman peaks that general α-In2Se3 and CIPS were utilized.

[0116] FIG. 21 is a diagram showing TEM images and EDS mapping images of a heterojunction structure of an Fe FET device according to an experimental example of the present invention.

[0117] Referring to Fig. 21, the Transmission Electron Microscope (TEM) image and Energy Dispersive X-ray Spectroscopy (EDS) mapping image of the heterojunction structure (CIPS / h-BN / α-In2Se3) of the Fe FET device according to the experimental example above are shown.

[0118] As can be seen in Figure 21, CIPS and α-In2Se3 are formed to be clearly separated by h-BN, and the composition of each layer (ferroelectric layer, insulating layer, channel layer) can also be clearly separated.

[0120] Experimental Example 2: Operation of Fe FET Device

[0121] FIG. 22 is a diagram showing the location where AFM scanning was used to verify the operation of an Fe FET device according to an experimental example of the present invention.

[0122] Referring to FIG. 22, the location where Atomic Force Microscopy (AFM) scanning was used to verify the operation of the Fe FET device according to the above experimental example is indicated. Specifically, the white dotted line area (channel layer area) marked between the source electrode (S) and the drain electrode (D) represents the measurement area using Kelvin probe force microscopy (KPFM) in FIG. 23 and FIG. 24, which will be described later, and the white box area (channel layer area) represents the measurement area using piezoresponse force microscopy (PFM) in FIG. 25 and FIG. 26, which will be described later.

[0123] FIG. 23 shows the surface potential measured in the channel layer between the source electrode and the drain electrode when a negative voltage is applied to the gate electrode, and FIG. 24 shows the surface potential measured in the channel layer between the source electrode and the drain electrode when a positive voltage is applied to the gate electrode.

[0124] Referring to FIGS. 23 and 24, the surface potential (V) is measured using Kelvin probe force microscopy (KPFM) for the white dashed line area as described in FIG. 22. More specifically, FIG. 23 shows the surface potential measured when a negative voltage is applied to the gate electrode, and FIG. 24 shows the surface potential measured when a positive voltage is applied to the gate electrode.

[0125] As can be seen in FIGS. 23 and 24, when a negative voltage is applied to the gate electrode, the slope of the surface potential (increasing from the source electrode to the drain electrode) and when a positive voltage is applied, the slope of the surface potential (decreasing from the source electrode to the drain electrode) show opposite trends. That is, as voltage is applied to the gate electrode, horizontal polarization (in-plane, IP) occurs in the channel layer (α-In2Se3), but depending on the polarity of the applied voltage (positive voltage or negative voltage), the positions of the negative and positive charges of the dipole moment are reversed.

[0126] In addition, it can be seen that out-of-plane (OOP) polarization occurs in the ferroelectric layer (CIPS) due to the voltage applied to the gate electrode, and as a result, out-of-plane (OOP) polarization also occurs in the channel layer (α-In2Se3), and in the channel layer (α-In2Se3), out-of-plane (IP) polarization also occurs in the channel layer (α-In2Se3) in conjunction with the out-of-plane (OOP) polarization in the channel layer (α-In2Se3).

[0127] FIG. 25 is a diagram showing a PFM phase image under dark conditions, FIG. 26 is a diagram showing PFM phase values ​​measured when voltages of opposite polarity are applied to the gate electrode under dark conditions, and FIG. 27 is a diagram showing a schematic diagram of dipole polarization under dark conditions.

[0128] Referring to FIGS. 25 to 27, as described in FIG. 22, PFM phase values ​​were measured for the white box area under dark conditions (conditions where no light is irradiated) using PFM (piezoresponse force microscopy). More specifically, FIG. 26 shows the PFM phase values ​​measured when a gate voltage of -10 V and a gate voltage of +10 V are applied, and FIG. 27 shows the dipole polarization in the ferroelectric layer (CIPS) and channel layer (α-In2Se3) when a gate voltage of -10 V and a gate voltage of +10 V are applied.

[0129] As can be seen in FIGS. 25 to 27, when voltages of opposite polarity (+10 V and -10 V) are applied under dark conditions, spontaneous ferroelectric polarization (180° phase difference) can be observed. Accordingly, it can be seen that under dark conditions, by controlling the polarity of the voltage applied to the gate voltage in reverse, the direction of the dipole caused by the horizontal polarization (IP) of the channel layer can be reversed (the positions of negative and positive charges are reversed by 180°).

[0130] FIG. 28 is a diagram showing a PFM phase image under bright conditions, FIG. 29 is a diagram showing PFM phase values ​​measured when voltages of opposite polarity are applied to the gate electrode under bright conditions, and FIG. 30 is a diagram showing a schematic diagram of dipole polarization under bright conditions.

[0131] Referring to FIGS. 28 to 30, as described in FIG. 22, PFM phase values ​​were measured for the white box area using piezoresponse force microscopy (PFM) under bright conditions (conditions where light of a wavelength of 655 nm is irradiated). More specifically, FIG. 29 shows the PFM phase values ​​measured when a gate voltage of -10 V and a gate voltage of +10 V are applied, and FIG. 30 shows the dipole polarization in the ferroelectric layer (CIPS) and channel layer (α-In2Se3) when a gate voltage of -10 V and a gate voltage of +10 V are applied.

[0132] As can be seen in FIGS. 28 to 30, when voltages of opposite polarity (+10 V and -10 V) are applied under bright conditions (conditions where light is irradiated), it can be observed that weak ferroelectric polarization (< 180°) occurs. Accordingly, it can be seen that under bright conditions, unlike under dark conditions, even if the polarity of the voltage applied to the gate voltage is controlled in reverse, the direction of the dipole caused by the horizontal polarization (IP) of the channel layer cannot be reversed (the positions of negative and positive charges are reversed by 180°). In other words, it can be seen that the horizontal polarization (IP) occurring in the channel layer is more influenced by the light irradiated onto the channel layer than by the voltage applied to the gate electrode.

[0134] Experimental Example 3: The Role of the Insulating Layer in Fe FET Devices

[0135] FIG. 31 is a diagram illustrating the voltage-current characteristics of an Fe FET device according to an experimental example of the present invention, and FIG. 32 is a diagram illustrating the voltage-current characteristics of an Fe FeT device according to a comparative example of the present invention.

[0136] Referring to FIGS. 31 and 32, after preparing an Fe FET device according to the experimental example and an Fe FET device according to the comparative example, for each, the gate electrode-source electrode voltage (VGS Drain electrode-source electrode current (I) according to ) DS ) and gate electrode-source electrode current (I GS ) is measured and expressed. More specifically, as a Fe FET device according to the comparative example, a device was used that is the same as the Fe FET device according to the experimental example above, but has a structure in which the insulating layer (h-BN) is omitted and the ferroelectric layer (CIPS) and the channel layer (α-In2Se3) are in direct contact.

[0137] As can be seen in Fig. 31, the gate leakage current is almost non-existent in the Fe FET device according to the experimental example above, whereas as can be seen in Fig. 32, the gate leakage current is severe in the Fe FET device according to the comparative example above. In other words, it can be seen that the gate leakage current problem can be significantly resolved by placing an insulating layer (h-BN) between the ferroelectric layer (CIPS) and the channel layer (α-In2Se3).

[0139] Experimental Example 4: Ferroelectricity and Electrical Synaptic Characteristics of Fe FET Devices

[0140] FIG. 33 is a diagram illustrating the change in transfer characteristics according to the scanning voltage range of an Fe FET device according to an experimental example of the present invention, and FIG. 34 is a diagram illustrating the change in transfer characteristics according to the change in the read voltage of an Fe FET device according to an experimental example of the present invention.

[0141] Referring to FIG. 33, various gate voltages (V) sweeping for ±5 V, ±8 V, and ±10 V. GS Voltage (V) of the Fe FET device according to the above experimental example under ) conditions GS Current (I) according to , V) DS , A) is measured and represented. As can be seen in Fig. 33, as the gate voltage condition increases (±5 V -> ±10 V), the transfer characteristic curve (ID -V G It can be confirmed that the area of ​​) increases.

[0142] Referring to FIG. 34, the source-drain voltages (V) of 0.2 V and 0.5 V DS Voltage (V) of the Fe FET device according to the above experimental example under ) conditions GS Current (I) according to , V) DS , A) is measured and represented. As can be seen in Fig. 34, the source-drain voltage (V DS As the condition changes, the transfer characteristic curve (I D -V G It can also be confirmed that it appears differently.

[0143] FIG. 35 is a diagram illustrating the on / off ratio of an Fe FET device according to an experimental example of the present invention, FIG. 36 is a diagram illustrating the memory window of an Fe FET device according to an experimental example of the present invention, and FIG. 37 is a diagram illustrating the output characteristics of an Fe FET device according to an experimental example of the present invention.

[0144] Referring to FIG. 35, the voltage (V) of the Fe FET device according to the above experimental example GS On / Off ratio according to , V(On / Off ratio, x 10 5 ) is measured and shown, and referring to FIG. 36, the voltage (V) of the Fe FET device according to the above experimental example is GS Memory windows (V) are measured and shown according to V). As can be seen in FIGS. 35 and 36, it can be observed that the on / off ratio and memory windows of the Fe FET device according to the experimental example increase linearly as the voltage increases. Accordingly, it can be seen that the programmable performance and storage performance of the Fe FET device according to the experimental example can be controlled by controlling the gate voltage.

[0145] Referring to Fig. 37, for a gate voltage change from -10 V to +10 V, I in 5 V increments DS -V DS The curve is shown. As can be seen in Fig. 37, as the gate voltage increases from -10 V to a positive value, the current gradually increases by about twofold, which is consistent with the transfer characteristics.

[0146] FIG. 38 is a schematic diagram showing electrical synapse measurement using an Fe FET device according to an experimental example of the present invention, FIG. 39 is a diagram explaining the short-term downsizing effect of an Fe FET device according to an experimental example of the present invention, and FIG. 40 is a diagram explaining the short-term upsizing effect of an Fe FET device according to an experimental example of the present invention.

[0147] Referring to Fig. 39, the short-term potentiation (STP) effect simulated with a 0.2 V bias and electric pulses (-1 V, -2 V, -3 V, -4 V, -5) to read the Fe FET device according to the above experimental example is shown.

[0148] As can be seen in Fig. 39, it can be observed that the PSC increases rapidly as a negative voltage pulse is applied and decreases rapidly as the pulse is removed. Additionally, it can be observed that the highest PSC value increases as the pulse amplitude increases. This effect can easily mimic the short-term potentiation (STP) behavior of the device.

[0149] Referring to Fig. 40, the short-term depression (STD) effect simulated with -0.2 V bias and electric pulses (+1 V, +2 V, +3 V, +4 V, +5) to read the Fe FET device according to the above experimental example is shown.

[0150] As can be seen in Fig. 40, the PSC value increases due to the action of the voltage pulse, and when the pulse is removed, it decreases to the lowest current level before returning to the initial state. This effect can easily mimic the short-term depression (STD) behavior of the device.

[0152] Experimental Example 5: Optical Signal Detection and Memory Conversion Characteristics of Fe FET Devices

[0153] Figure 41 is a diagram showing a model of the optical signal detection and information memory process.

[0154] Referring to Fig. 41, a model is shown illustrating the conversion from short-term memory (STM) to long-term memory (LTM) when an optical signal stimulus is received from the outside. More specifically, a sensory memory is generated from an external optical stimulus, transferred to short-term memory (STM), and can be converted to long-term memory (LTM) through several rehearsals.

[0155] FIG. 42 is a diagram illustrating the current value according to the number of signals input to an Fe FET device according to an experimental example of the present invention, FIG. 43 is a diagram illustrating the normalized attenuation current value according to the number of signals input to an Fe FET device according to an experimental example of the present invention, and FIG. 44 is a diagram illustrating the conversion of short-term memory into long-term memory through an Fe FET device according to an experimental example of the present invention.

[0156] Referring to Fig. 42, the change in current value is shown when light of a wavelength of 655 nm is repeatedly irradiated onto the channel layer of the Fe FET device according to the experimental example above for each pulse number. Referring to Fig. 43, the normalized decayed current extracted from Fig. 42 is shown. The memory state induced by the light pulse can be determined after analyzing the results of Figs. 42 and 43 using a Kohlrausch stretching exponential function such as <Equation 1> below. <Equation 1> represents a function for modeling spontaneous retention loss.

[0157] <Mathematical Formula 1>

[0158]

[0159] (M t : Normalized current decay, t: time, β: stretch index ranging from 0 to 1, τ: characteristic relaxation time)

[0160] Referring to Fig. 44, a characteristic relaxation time (s) is obtained after fitting the data and expressed as a function of wavelength (nm) and pulse number. As can be seen in Fig. 44, increasing the pulse number from 2 to 10 improves the relaxation time (τ) from 1.08 seconds to 102.2 seconds. Accordingly, it can be seen that information can be converted from short-term memory (STM) to long-term memory (LTM) through rehearsal. Furthermore, it can be seen that this relaxation phenomenon occurs due to strong cohesive interactions between α-In2Se3 dipoles induced by triggering multiple optical pulses.

[0161] FIG. 45 is a diagram illustrating the PPF measurement results of an Fe FET device according to an experimental example of the present invention.

[0162] Referring to FIG. 45, in the channel layer of the Fe FET device according to the experimental example above, a wavelength of 655 nm and 0.33 mW / cm 2 It represents the change in current values ​​measured as a pair of light with an intensity is irradiated at a time interval of 1 second. The ratio of the peak amplitudes of the second (A2) pulse and the first (A1) pulse received by the synapse as two consecutive signals is defined as the PPF ratio (PPF ratio, A2 / A1).

[0163] FIGS. 46 to 49 are drawings for explaining the PPF ratio of an Fe FET device according to an experimental example of the present invention.

[0164] Referring to Fig. 46, the change in the PPF ratio according to the time interval (s) between two input signals under the conditions of Fig. 45 is shown. As can be seen in Fig. 46, it can be confirmed that a high PPF ratio of up to 170% is achieved during a time interval of 1 second. Such a high PPF ratio value means that the Fe FET device according to the above experimental example can transmit residual information from the first signal to the second signal while minimizing information loss.

[0165] Referring to Fig. 47, the change in the PPF ratio according to the time interval (s) between two input signals is shown under conditions similar to those of Fig. 45 but with a wavelength of 405 nm. As can be seen in Fig. 47, it can be confirmed that the PPF ratio is approximately 130% during a time interval of 1 second.

[0166] Referring to Fig. 48, the change in the PPF ratio according to the time interval (s) between two input signals is shown under conditions similar to those of Fig. 45 but with a wavelength of 785 nm. As can be seen in Fig. 48, it can be confirmed that the PPF ratio is approximately 130% during a time interval of 1 second.

[0167] Referring to Fig. 49, the change in the PPF ratio according to the time interval (s) between two input signals is shown under conditions similar to those of Fig. 45 but with a wavelength of 850 nm. As can be seen in Fig. 49, it can be confirmed that the PPF ratio is approximately 112% during a time interval of 1 second.

[0168] In addition, <Equation 2>, which can calculate Paired Pulse Facilitation (PPF), was derived based on the results of Figures 46 to 49. <Equation 2> represents a parameter indicating the degree of change in synaptic weight when two consecutive pulses are applied.

[0169] <Mathematical Formula 2>

[0170]

[0171] (C1: Initial acceleration magnitude of fast decay parameter, C2: Initial acceleration magnitude of slow decay parameter, τ1: Characteristic relaxation time of fast decay parameter, τ2: Characteristic relaxation time of slow decay parameter, Δt: Time interval between the first and second pulses)

[0172] Figure 50 is a diagram showing the fast relaxation time and slow relaxation time of the damping curve for various wavelengths.

[0173] Referring to FIG. 50, the fast relaxation time (τ1) and slow relaxation time (τ2) of the damping curves for different wavelengths (405 nm, 655 nm, 785 nm, and 850 nm) are shown. The fast relaxation time (τ1) and slow relaxation time (τ2) values ​​shown in FIG. 50 were derived through the above-described <Equation 2>.

[0175] Experimental Example 6: Optical Response Characteristics of Fe FET Device According to Electric Field

[0176] Figure 51 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 405 nm is irradiated.

[0177] Referring to FIG. 51, ten optical pulses (405 nm wavelength) with on / off times of 1 second each were irradiated onto the channel layer of the Fe FET device according to the above experimental example, and a voltage in the range of -2 V to +2 V was applied to the gate electrode, and then the normalized conductance for the dark current was measured and shown.

[0178] As can be seen in Fig. 51, it can be observed that the normalized conductance is higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0179] Figure 52 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 655 nm is irradiated.

[0180] Referring to FIG. 52, ten optical pulses (655 nm wavelength) with on / off times of 1 second each were irradiated onto the channel layer of the Fe FET device according to the above experimental example, and a voltage in the range of -2 V to +2 V was applied to the gate electrode, and the normalized conductance for the dark current was measured and shown.

[0181] As can be seen in Fig. 52, it can be observed that the normalized conductance is higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0182] Figure 53 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 785 nm is irradiated.

[0183] Referring to FIG. 53, ten optical pulses (785 nm wavelength) with on / off times of 1 second each were irradiated onto the channel layer of the Fe FET device according to the above experimental example, and a voltage in the range of -2 V to +2 V was applied to the gate electrode, and the normalized conductance for the dark current was measured and shown.

[0184] As can be seen in Fig. 53, it can be observed that the normalized conductance is higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0185] Figure 54 is a diagram illustrating the effect of an electric field on an Fe FET device under conditions where light of a wavelength of 850 nm is irradiated.

[0186] Referring to FIG. 54, ten optical pulses (850 nm wavelength) with on / off times of 1 second each were irradiated onto the channel layer of the Fe FET device according to the above experimental example, and a voltage in the range of -2 V to +2 V was applied to the gate electrode, and then the normalized conductance for the dark current was measured and shown.

[0187] As can be seen in Fig. 54, it can be observed that the normalized conductance is higher when a negative (-) voltage is applied to the gate electrode than when a positive (+) voltage is applied.

[0188] That is, as can be seen in FIGS. 51 to 54, the negative (-) gate voltage exhibits a maximum response for all wavelengths compared to the positive (+) gate voltage.

[0190] Experimental Example 7: Pattern Recognition Using Optical Enhancement and Electrical Depression of Fe FET Devices

[0191] FIGS. 55 to 58 are drawings for explaining the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention.

[0192] Referring to Fig. 55, to update the synapse weights of the Fe FET device according to the experimental example above, the device was potentiated by controlling the polarization of the channel layer (α-In2Se3) through continuous irradiation with an optical pulse (655 nm wavelength) having a pulse width of 1 second. Subsequently, the optical pulse was removed, and the device was depressurized by applying a continuous positive voltage with an amplitude of +2 V to the gate electrode to reposition the dipoles to their initial conditions. A total of 64 optical and electrical pulses were used, and the read voltage (V DS ) was controlled to 0.2 V.

[0193] Referring to Fig. 56, to update the synapse weights of the Fe FET device according to the experimental example above, the device was potentiated by controlling the polarization of the channel layer (α-In2Se3) through continuous irradiation with an optical pulse (405 nm wavelength) having a pulse width of 1 second. Subsequently, the optical pulse was removed, and the device was depressurized by applying a continuous positive voltage with an amplitude of +2 V to the gate electrode to reposition the dipoles to their initial conditions. A total of 64 optical and electrical pulses were used, and the read voltage (V DS ) was controlled to 0.2 V.

[0194] Referring to Fig. 57, to update the synapse weights of the Fe FET device according to the experimental example above, the device was potentiated by controlling the polarization of the channel layer (α-In2Se3) through continuous irradiation with an optical pulse (785 nm wavelength) having a pulse width of 1 second. Subsequently, the optical pulse was removed, and the device was depressurized by applying a continuous positive voltage with an amplitude of +2 V to the gate electrode to reposition the dipoles to their initial conditions. A total of 64 optical and electrical pulses were used, and the read voltage (V DS ) was controlled to 0.2 V.

[0195] Referring to Fig. 58, to update the synapse weights of the Fe FET device according to the experimental example above, the device was potentiated by controlling the polarization of the channel layer (α-In2Se3) through continuous irradiation with an optical pulse (850 nm wavelength) having a pulse width of 1 second. Subsequently, the optical pulse was removed, and the device was depressurized by applying a continuous positive voltage with an amplitude of +2 V to the gate electrode to reposition the dipoles to their initial conditions. A total of 64 optical and electrical pulses were used, and the read voltage (V DS ) was controlled to 0.2 V.

[0196] As can be seen in FIGS. 55 to 58, the Fe FET device according to the experimental example is potentialized by an optical signal, while being depressed by an electrical signal. In addition, it can be seen that the Fe FET device according to the experimental example has synapse weight update characteristics essential for the development of HNN (Human neural networks).

[0197] In addition, synapse weights were updated through the following <Equation 3> and <Equation 4>. More specifically, <Equation 3> is used to calculate nonlinearity in the LTP Curve, and <Equation 4> can be used to calculate nonlinearity in the LTD Curve.

[0198] <Mathematical Formula 3>

[0199]

[0200] (G P : Conductance in reinforced state, G n : Current conductance, G n+1 : Updated conductance, G min : Minimum conductance, A P : Nonlinearity factor for enhancement range, B: Fitting constant for normalizing conductance range, n: Number of applied pulses)

[0201] <Mathematical Formula 4>

[0202]

[0203] (G D : Conductance in the falling state, G n : Current conductance, G n+1 : Updated conductance, G max : Maximum conductance, A D : Nonlinearity factor for the fall range, B: Fitting constant to normalize the conductance range, n: Number of applied pulses, n max : Maximum value of the number of authorized pulses)

[0204] FIG. 59 is a diagram illustrating the long-term stability of the synapse weight update characteristics of an Fe FET device according to an experimental example of the present invention.

[0205] Referring to Fig. 59, the operation of irradiating the Fe FET device according to the above experimental example with light to induce potentialization and then applying a gate voltage to induce depression was set as one cycle, and the change during five consecutive cycles of operation was measured. As can be seen in Fig. 59, stable potentialization and depression are achieved even during five consecutive cycles of operation.

[0206] Figure 60 is a schematic diagram of an ANN for MNIST pattern recognition.

[0207] Referring to Fig. 60, a schematic diagram of a single-layer perceptron-based ANN for MNIST pattern recognition is shown. It consists of 400 input neurons, 100 hidden neurons, and 10 output neurons, and the MNIST dataset is image data consisting of 400 pixels ranging from 0 to 10.

[0208] Figure 61 is a diagram illustrating pattern recognition accuracy according to Epoch.

[0209] Referring to Figure 61, the results of a pattern recognition simulation using a dataset of 10,000 images were obtained after training with 8,000 images randomly selected from 60,000 images. Specifically, the gray line represents the simulation result with an ideal synapse, and the red line represents the simulation result with a Fe FET device according to the experimental example. As can be seen in Figure 61, after 125 epochs, the ideal synapse achieved an accuracy of 94%, while the Fe FET device according to the experimental example achieved an accuracy of 92.5%. Accordingly, it can be seen that the Fe FET device according to the experimental example is similar to the response of an ideal system for forming an Artificial Neural Network (ANN).

[0211] Experimental Example 8: Photo-adaptation test of Fe FET device

[0212] FIG. 62 is a diagram illustrating the results of a light adaptation test when a weak light stimulus is applied, FIG. 63 is a diagram illustrating the results of a light adaptation test when a strong light stimulus is applied, and FIG. 64 is a diagram illustrating the results of a light adaptation test when both a strong light stimulus and an electrical stimulus are applied.

[0213] Referring to Fig. 62, when the light intensity is low (15.3 μW / cm²) 2 It can be confirmed that the measured current value (1 second width, 655 nm wavelength) is lower than the threshold current value (approx. 45 pA). Referring to Fig. 63, when the light intensity is high (0.324 mW / cm²) 2 It can be confirmed that the measured current value is higher than the critical current value. This is similar to a situation where the iris does not function properly and the retina is caught in external light.

[0214] In order to prevent high current from flowing through the device due to such high-intensity optical illumination, as shown in Fig. 64, a positive voltage (+4 V) pulse was applied to the gate electrode to adjust the modulation synapse function, thereby controlling the measured current value to be below a threshold current value. This phenomenon demonstrates a realistic mimicry of the biological eye, and this technique can be applied to develop brain-inspired neural networks.

[0216] Experimental Example 9: Logic Operation of Fe FET Device

[0217] FIG. 65 is a diagram showing OR logic operation according to optical signal change and electrical signal change, and FIG. 66 is a diagram showing AND logic operation according to optical signal change and electrical signal change.

[0218] Referring to FIGS. 65 and 66, logical operations such as "OR" and "AND" functions were implemented through optical signal changes and electrical signal changes. More specifically, light with wavelengths of 655 nm and 850 nm was used as optical spikes for the optical input signals. Simultaneously, +2 V and -2 V electric pulses were applied to the gate electrodes as electrical inputs to perform "OR" and "AND" operations, respectively. V as the read voltage DS = 0.2 V was used, and both operations were performed at the same threshold current value (25 pA). Current magnitudes above and below the threshold level can be considered as the '1' (S=1) and '0' (S=0) states, respectively. Accordingly, the logic functions of "OR" and "AND" were modulated according to the input optical signal and determined by the electrical spikes of the gate electrode. Furthermore, the Fe FET device according to the above experimental example demonstrates optical logic operations, which is another step for performing in-memory calculations in a single device.

[0220] Experimental Example 10: Multi-state of Fe FET devices

[0221] FIG. 67 is a diagram illustrating the multi-state characteristics of an Fe FET device according to an experimental example of the present invention.

[0222] Referring to Fig. 67, the current values ​​measured for each of the four different wavelengths (655 nm, 405 nm, 785 nm, 850 nm) are shown after irradiating the Fe FET device according to the experimental example above with light of four different wavelengths. As can be seen in Fig. 67, it can be confirmed that four different current values ​​appear when light of four different wavelengths (655 nm, 405 nm, 785 nm, 850 nm) is irradiated. Accordingly, it can be seen that the Fe FET device according to the experimental example above has multi-state characteristics. Furthermore, it can be predicted that if light of various wavelengths and electrical signals are used together, more logic functions such as "XOR" and "NAND" as well as "OR" and "AND" can be implemented.

[0224] Experimental Example 11: Pavlov's Dog Experiment with Fe FET Devices

[0225] FIG. 68 is a diagram showing the current value when a conditional stimulus is applied, FIG. 69 is a diagram showing the current value when an unconditional stimulus is applied, FIG. 70 is a diagram showing the current value when both a conditional stimulus and an unconditional stimulus are applied simultaneously, and FIG. 71 is a diagram showing the current value when only a conditional stimulus is applied after training.

[0226] Referring to Fig. 68, the current value is shown when a conditioned stimulus (bell ringing, pulse voltage applied to the gate electrode) is applied. Since the current value is lower than the threshold value, this means that there is no salivary secretion. Referring to Fig. 69, the current value is shown when an unconditioned stimulus (food, light irradiated onto the channel layer) is applied. Since the current value is higher than the threshold value, this means that salivary secretion occurs. Referring to Fig. 70, since the current value is higher than the threshold value, it means that saliva is secreted when both the conditioned stimulus and the unconditioned stimulus are applied simultaneously. Referring to Fig. 71, since the current value is higher than the threshold value, it means that saliva is secreted even when only the conditioned stimulus is applied after training.

[0227] More specifically, among simultaneously occurring events, if one of the conditioned events occurs after successful training, the other event is recalled from memory. Here, optical stimuli, such as food (unconditioned stimulus), were treated as visual information and mimicked using electrical pulses. Thirty electrical pulses with an amplitude of -4 V and a width of 1 s were applied to mimic the bell sound (Fig. 68), demonstrating that conditioned stimuli alone are not effective in inducing salivary secretion with a current below the threshold level (5 pA). In contrast, unconditioned stimulation (wavelength 655 nm, intensity 0.33 mW / cm² 2A light pulse (with a width of 50 s) can induce salivary secretion, which means that a current above a threshold level is passing through the device (Fig. 69). Fig. 70 shows the process in which a conditional event and an unconditional event occur simultaneously. During the training process, the current passing through the device was much higher than the threshold level, indicating that the reflex between the optical stimulus and the electrical stimulus has been established as an associated event. Once this training is complete, a high current (above the threshold level) passing through the device can be induced by the conditional stimulus (electrical pulse) alone, and the sensation is maintained for a long time. Fig. 71 shows the recognition of this event by repeatedly applying an electric pulse every 200 seconds. It can be seen that the Fe FET device according to the above experimental example can retain information for more than 2400 seconds.

[0229] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention. Explanation of the symbols

[0230] 100: Substrate 110: Si substrate 120: SiO2 layer 200: Gate electrode 300: Ferroelectric layer 400: Insulation layer 500: Channel layer (1st channel layer) 600: Second channel layer 700: Oxide layer S, S1, S2: Source electrode, first source electrode, second source electrode D: Drain electrode

Claims

Claim 1 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region and comprising gold (Au); a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; and a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer. An artificial synapse device comprising a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer. Claim 2 An artificial synapse device comprising: a silicon (Si)-based substrate including a first region and a second region different from the first region; a gate electrode disposed on the first region and comprising a metal; a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer; and a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated on the first channel layer. Claim 3 An artificial synapse device according to claim 2, wherein the first channel layer comprises both vertical direction (Out-of-plane, OOP) polarization characteristics and horizontal direction (Inplane, IP) polarization characteristics. Claim 4 An artificial synapse device according to claim 3, wherein the first channel layer has both ferroelectric and semiconductor properties. Claim 5 In claim 4, an artificial synapse device capable of detecting, processing, and remembering optical signals. Claim 6 An artificial synapse device according to claim 5, wherein potentiation is generated by the first channel layer and depression is generated by the second channel layer. Claim 7 In claim 6, an artificial synapse device capable of detecting light in the wavelength range of 405 nm to 850 nm. Claim 8 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region; a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; and a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer. An artificial synapse device comprising a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer, and the gate electrode and the ferroelectric layer form a Van der Waals metal contact. Claim 9 An artificial synapse device according to claim 8, wherein the ferroelectric layer has out-of-plane (OOP) polarization characteristics, and the first channel layer has both out-of-plane (OOP) polarization characteristics and in-plane (IP) polarization characteristics. Claim 10 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region and comprising gold (Au); a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; and a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer. An artificial synapse device comprising a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer, and capable of detecting, processing, and remembering an optical signal. Claim 11 An artificial synapse device capable of detecting, processing, and remembering optical signals as the polarization of the first channel layer is controlled by light irradiated onto the first channel layer in claim 10. Claim 12 An artificial synapse device according to claim 11, wherein potentiation is generated by the first channel layer and depression is generated by the second channel layer. Claim 13 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region and comprising gold (Au); a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; and a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer. An artificial synapse device comprising a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer, and the gate electrode and the ferroelectric layer form a Van der Waals metal contact. Claim 14 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region and comprising gold (Au); a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; and a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer. An artificial synapse device comprising a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer, potentiation is generated by the first channel layer and depression is generated by the second channel layer, and both potentiation and depression are generated solely by the light signal. Claim 15 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region; a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer; and a second source electrode disposed to be in contact with the other side of the second channel layer. An artificial synapse device comprising an oxide layer disposed on the second channel layer and between the drain electrode and the second source electrode, wherein the polarization of the first channel layer is controlled by light irradiated on the first channel layer, and the oxide layer comprises titanium oxide (TiO2). Claim 16 An artificial synapse device comprising: a silicon (Si)-based substrate including a first region and a second region different from the first region; a gate electrode disposed on the first region; a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to be in contact with one side of the first channel layer; a drain electrode disposed to be in contact with the other side of the first channel layer and one side of the second channel layer; and a second source electrode disposed to be in contact with the other side of the second channel layer, wherein the polarization of the first channel layer is controlled by light irradiated on the first channel layer. Claim 17 An artificial synapse device according to claim 16, wherein potentiation is generated by the first channel layer and depression is generated by the second channel layer. Claim 18 An artificial synapse device according to claim 17, comprising that both potentiation and depression occur solely from an optical signal. Claim 19 A silicon (Si)-based substrate comprising a first region and a second region different from the first region; a gate electrode disposed on the first region; a ferroelectric layer disposed on the gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a first channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a second channel layer disposed on the second region and comprising MXene; a first source electrode disposed to contact one side of the first channel layer; a drain electrode disposed to contact the other side of the first channel layer and one side of the second channel layer; and a second source electrode disposed to contact the other side of the second channel layer. An artificial synapse device comprising an oxide layer disposed on the second channel layer and between the drain electrode and the second source electrode, wherein the polarization of the first channel layer is controlled by light irradiated onto the first channel layer. Claim 20 A ferroelectric field-effect transistor comprising: a substrate including silicon (Si); a first gate electrode disposed on the substrate; a second gate electrode disposed on the substrate and spaced apart from the first gate electrode; a ferroelectric layer disposed on the first gate electrode and the second gate electrode so as to be in contact with the first gate electrode and the second gate electrode and comprising CuInP2S6 (CIPS); an insulating layer disposed on the ferroelectric layer and comprising hexagonal boron nitride (h-BN); a channel layer disposed on the insulating layer and comprising alpha-indium selenide (α-In2Se3); a source electrode disposed to be in contact with one side of the channel layer; and a drain electrode disposed to be in contact with the other side of the channel layer, wherein the polarization of the channel layer is controlled by light irradiated onto the channel layer.

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