Display device

Abstract

A display device is provided. The display device comprises a substrate, a plurality of scan stages disposed on the substrate, a first conductive layer disposed on the substrate and including a plurality of scan control lines electrically connected to each of the plurality of scan stages, a first organic insulating layer disposed on the first conductive layer, and a second organic insulating layer disposed on the first organic insulating layer, wherein the first organic insulating layer and the second organic insulating layer overlap with the plurality of scan control lines.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] Various types of display devices are used, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs). Among these, OLEDs display images using organic light-emitting elements that generate light through the recombination of electrons and holes. An OLED includes multiple transistors that provide driving current to the organic light-emitting elements.

[0004] An organic light-emitting display device includes pixels connected to scan lines and data lines, a scan driver that applies scan signals to scan lines, a data driver that applies data voltages to data lines, and a power voltage line that applies power voltage to pixels. The scan driver can generate scan signals according to scan driving signals input through the scan driving lines and output them to the scan lines. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device capable of suppressing or preventing a short circuit between two wires in an area where the power voltage line and the scan driving wire overlap.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to one embodiment for solving the above problem comprises a substrate, a plurality of scan stages disposed on the substrate, a first conductive layer disposed on the substrate and including a plurality of scan control lines each electrically connected to the plurality of scan stages, a first organic insulating layer disposed on the first conductive layer, and a second organic insulating layer disposed on the first organic insulating layer, wherein the first organic insulating layer and the second organic insulating layer overlap with the plurality of scan control lines.

[0008] The device further includes a power voltage line disposed on the second organic insulating layer and overlapping with the plurality of scan stages, wherein the first organic insulating layer and the second organic insulating layer may be disposed between the power voltage line and the plurality of scan stages.

[0009] The first organic insulating layer and the second organic insulating layer disposed between the power supply voltage line and the plurality of scan stages have a first thickness, and the first thickness may be within the range of 0.9 μm to 1.7 μm.

[0010] The apparatus further includes a third organic insulating layer disposed on the second organic insulating layer and an anode electrode disposed on the organic insulating layer, wherein the power supply voltage line may include the same material as the anode electrode.

[0011] It may further include a pixel defining film disposed on the anode electrode while exposing the anode electrode, a light-emitting layer disposed on the anode electrode exposed by the pixel defining film, and a cathode electrode disposed on the light-emitting layer.

[0012] The apparatus further comprises a third organic insulating layer disposed on the second conductive layer, and a power voltage line disposed on the third organic insulating layer and overlapping with the second scan control wiring, wherein the third organic insulating layer overlaps with the second scan control wiring, and the second organic insulating layer and the third organic insulating layer may be disposed between the second scan control wiring and the power voltage line.

[0013] delete

[0014] The second organic insulating layer and the third organic insulating layer disposed between the power supply voltage line and the second scan control wiring have a second thickness, and the second thickness may be within the range of 0.6㎛ to 1.4㎛.

[0015] It may further include an etching prevention pattern disposed on the second organic insulating layer and overlapping with the plurality of scan control wires, a third organic insulating layer disposed on the etching prevention pattern, and a first sub-power voltage line disposed on the third organic insulating layer and overlapping with the plurality of scan control wires.

[0016] The first conductive layer further includes a second sub-power voltage line, and the first sub-power voltage line and the second sub-power voltage line can be electrically connected through the etching prevention pattern.

[0017] The device further includes a display area for displaying a screen and a non-display area disposed around the display area, wherein the plurality of scan stages and the plurality of scan control wires may be disposed in the non-display area.

[0018] The device further includes a driving chip disposed in the above-mentioned non-display area, wherein the driving chip can be electrically connected to the plurality of scan stages through the plurality of scan control wires.

[0019] It may further include a dam structure disposed outside the plurality of scan stages and the plurality of scan control wires, and comprising the first organic insulating layer and the second organic insulating layer.

[0020] It may further include a plurality of light-emitting stages disposed on the substrate, and a plurality of light-emitting control wires electrically connected to each of the plurality of light-emitting stages.

[0021] It may further include a valley portion defined by the first organic insulating layer and the second organic insulating layer, disposed between the plurality of scan stages and the plurality of scan control wires and the plurality of light-emitting stages and the plurality of light-emitting control wires.

[0022] The above valley portion can penetrate the first organic insulating layer and the second organic insulating layer in the thickness direction.

[0023] A display device according to one embodiment for solving the above problem comprises a display area, a scan driving unit disposed outside the display area and including a plurality of scan stages and a plurality of scan control wires electrically connected to each of the plurality of scan stages, a first organic insulating layer disposed on the plurality of scan control wires, a second organic insulating layer disposed on the first organic insulating layer, and a power voltage line disposed on the second organic insulating layer.

[0024] The first organic insulating layer and the second organic insulating layer disposed between the power supply voltage line and the plurality of scan stages have a first thickness, and the first thickness may be within the range of 0.9 μm to 1.7 μm.

[0025] The apparatus further includes a third organic insulating layer disposed on the second organic insulating layer and an anode electrode disposed on the organic insulating layer, wherein the power supply voltage line may include the same material as the anode electrode.

[0026] It may further include a pixel defining film disposed on the anode electrode while exposing the anode electrode, a light-emitting layer disposed on the anode electrode exposed by the pixel defining film, and a cathode electrode disposed on the light-emitting layer.

[0027] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0028] According to a display device of one embodiment, a short circuit between the two wires can be suppressed or prevented in the area where the power voltage line and the scan driving wire overlap.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0030] FIG. 1 is a plan view of a display device according to one embodiment. Figure 2 is a side view of the display device of Figure 1. FIG. 3 is a circuit diagram showing a pixel in detail according to one embodiment. FIG. 4 is a plan view showing the arrangement of a scan driving unit and a light-emitting driving unit of a display device according to one embodiment. Figure 5 is an enlarged view of area A of Figure 4. Figure 6 is a circuit diagram showing an example of the scan drive unit of Figure 5. Figure 7 is a circuit diagram showing an example of the light-emitting driving unit of Figure 5. FIG. 8 is a cross-sectional view of the display area of ​​a display device according to one embodiment. FIG. 9 is a cross-sectional view of a non-display area of ​​a display device according to one embodiment. FIG. 10 is a cross-sectional view of a display device according to another embodiment. FIG. 11 is a cross-sectional view of a display device according to another embodiment. Specific details for implementing the invention

[0031] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] When elements or layers are referred to as being on another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components.

[0033] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a plan view of a display device according to one embodiment. FIG. 2 is a side view of the display device of FIG. 1. FIG. 2 illustrates a side shape of the display device in a state where it is bent in the thickness direction.

[0036] In the drawing, the first direction (DR1) represents the horizontal direction of the planar display device (1), and the second direction (DR2) represents the vertical direction of the planar display device (1). Additionally, the third direction (DR3) represents the thickness direction of the display device (1). The first direction (DR1) and the second direction (DR2) intersect perpendicularly to each other, and the third direction (DR3) intersects perpendicularly to both the first direction (DR1) and the second direction (DR2) in a direction that intersects the plane on which the first direction (DR1) and the second direction (DR2) are placed. However, the directions mentioned in the embodiment should be understood as referring to relative directions, and the embodiment is not limited to the mentioned directions.

[0037] Unless otherwise defined, in this specification, one side of the first direction (DR1) refers to the right direction in the plan view, the other side of the first direction (DR1) refers to the left direction in the plan view, one side of the second direction (DR2) refers to the upper direction in the plan view, and the other side of the second direction (DR2) refers to the lower direction in the plan view. Additionally, “upper” and “upper surface” expressed based on the third direction (DR3) refer to the display surface side based on the display panel (10), and “lower” and “lower surface” refer to the opposite side of the display surface based on the display panel (10).

[0038] Referring to FIGS. 1 and 2, the display device (1) is a device for displaying video or still images, and the display device (1) can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs (Personal Computers), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (Portable Multimedia Players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0039] A display device (1) according to one embodiment may be formed in a substantially rectangular shape on a plane. The display device (1) may be a rectangle with vertical corners on a plane. However, it is not limited thereto, and the display device (1) may be a rectangular shape with rounded corners on a plane.

[0040] If the display device (1) includes a planar rectangular shape, the length of the two sides positioned on one side and the other side of the first direction (DR1) extending into the second direction (DR2) may be longer than the length of the two sides positioned on one side and the other side of the second direction (DR2) extending into the first direction (DR1). In other words, the two sides of the display device (1) positioned on one side and the other side of the first direction (DR1) may be long sides, and the two sides of the display device (1) positioned on one side and the other side of the second direction (DR2) may be short sides.

[0041] The display device (1) may include a display panel (10). The display panel (10) may be a flexible substrate comprising a flexible polymer material such as polyimide. Accordingly, the display panel (10) may be bent, folded, folded, or rolled.

[0042] The display panel (10) may be an organic light-emitting display panel. In the following embodiments, an organic light-emitting display panel is used as the display panel (10), but it is not limited thereto, and other types of display panels such as liquid crystal display panels, quantum dot organic light-emitting display panels, quantum dot liquid crystal displays, quantum nano light-emitting display panels, and micro LEDs may be used.

[0043] The display panel (10) may include a display area (DA) for displaying the screen and a non-display area (NDA) for which no display takes place. The display panel (10) may be divided into a display area (DA) and a non-display area (NDA) in a planar view. The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may form a bezel.

[0044] The display area (DA) may correspond to the planar shape of the display device (1). The display area (DA) may be a rectangular shape with vertical corners or a rectangular shape with rounded corners. However, the planar shape of the display area (DA) is not limited to a rectangle and may have a circular, elliptical, or various other shapes.

[0045] The display area (DA) may include a plurality of pixels. Each pixel may be arranged in a matrix shape. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include wiring, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed by a sealing film. The specific configuration of the pixel will be described later.

[0046] The non-display area (NDA) may surround all sides of the display area (DA) and form the border of the display area (DA). However, it is not limited thereto.

[0047] The display panel (10) may include a main area (MA) and a bending area (BA) connected to one side of the second direction (DR2) of the main area (MA). The display panel (10) may further include a sub-area (SA) connected to the bending area (BA) on one side of the second direction (DR2), bent in the thickness direction, and overlapped with the main area (MA) in the thickness direction.

[0048] A display area (DA) may be located in the main area (MA). A non-display area (NDA) may be located in the surrounding edge portion of the display area (DA) of the main area (MA).

[0049] The main area (MA) may have a shape similar to the planar external shape of the display device (1). The main area (MA) may be a flat area located on a plane. However, it is not limited thereto, and at least one of the remaining edges in the main area (MA), excluding the edge (side) connected to the bending area (BA), may be bent to form a curved surface or bent in a vertical direction.

[0050] In the case where at least one of the remaining edges, excluding the edge (side) connected to the bending area (BA) in the main area (MA), forms a curved surface or is bent, a display area (DA) may also be placed on that edge. However, not limited thereto, a non-display area (NDA) that does not display a screen may be placed on the curved or bent edge, or a display area (DA) and a non-display area (NDA) may be placed together.

[0051] The non-display area (NDA) of the main area (MA) may be placed in the area from the outer boundary of the display area (DA) to the edge of the display panel (10). Signal wiring or driving circuits for applying a signal to the display area (DA) may be placed in the non-display area (NDA) of the main area (MA).

[0052] The bending region (BA) can be connected through one side of the main region (MA). The width of the bending region (BA) (width of the first direction (DR1)) may be smaller than the width of the main region (MA) (width of the side). The connection between the main region (MA) and the bending region (BA) may have a planar L-shaped cutting form to reduce the width of the bezel.

[0053] In the bending area (BA), the display panel (10) can be bent with curvature in the opposite direction of the display surface. As the display panel (10) is bent in the bending area (BA), the surface of the display panel (10) can be reversed. That is, one side of the display panel (10) facing upward can be changed to face outward through the bending area (BA) and then back to face downward.

[0054] The sub-region (SA) extends from the bending area (BA). The sub-region (SA) may extend in a direction parallel to the main area (MA), starting from after the bending is completed. The sub-region (SA) may overlap with the main area (MA) in the thickness direction of the display panel (10). The sub-region (SA) may overlap with the non-display area (NDA) at the edge of the main area (MA), and further overlap with the display area (DA) of the main area (MA). The width of the sub-region (SA) may be the same as the width of the bending area (BA), but is not limited thereto.

[0055] A pad portion (not shown) may be disposed on a sub-region (SA) of a display panel (10). An external device may be mounted (or attached) to the pad portion (not shown). Examples of external devices include a driving chip (20), a driving board (30) made of a flexible printed circuit board or a rigid printed circuit board, and other devices such as a wiring connection film or a connector may also be mounted on the pad portion as external devices. The external device mounted on the sub-region (SA) may be one, but may be multiple. For example, as illustrated in FIGS. 1 and 2, a driving chip (20) may be disposed on a sub-region (SA) of a display panel (10), and a driving board (30) may be attached to an end of the sub-region (SA). In this case, the display panel (10) may include both a pad portion connected to the driving chip (20) and a pad portion connected to the driving board (30). In another embodiment, a driving chip may be mounted on a film, and the film may be attached to a sub-region (SA) of a display panel (10).

[0056] The driving chip (20) is mounted on one side of the display panel (10) which is the same as the display surface, and as the bending region (BA) is bent and inverted as described above, it is mounted on the side of the display panel (10) facing downward in the thickness direction so that the upper surface of the driving chip (20) can face downward.

[0057] The driving chip (20) may be attached to the display panel (10) via an anisotropic conductive film or via ultrasonic bonding. The driving chip (20) may include an integrated circuit that drives the display panel (10).

[0058] FIG. 3 is a circuit diagram showing a pixel in detail according to one embodiment.

[0059] Referring to FIG. 3, the circuit of a pixel (PX) includes a plurality of transistors (T1 to T7), a capacitor (Cst), and a light-emitting element (LE). A data signal (DATA), a first scan signal (GW), a second scan signal (GI), a third scan signal (GB), a light emission control signal (EM), a first power supply voltage (ELVDD), a second power supply voltage (ELVSS), and an initialization voltage (VINT) are applied to the circuit of a pixel (PX).

[0060] The light-emitting element (LE) may be, for example, an organic light-emitting diode comprising a first electrode (or anode electrode), a light-emitting layer, and a second electrode (or cathode electrode), although not limited thereto.

[0061] A plurality of transistors may include first to seventh transistors (T1 to T7). Each transistor (T1 to T7) includes a gate electrode, a first electrode (or, a first source / drain electrode), and a second electrode (or, a second source / drain electrode). Of the first electrode and the second electrode of each transistor (T1 to T7), one becomes the source electrode and the other becomes the drain electrode.

[0062] The first transistor (T1) acts as a driving transistor, and the second to seventh transistors (T2 to T7) can act as switching transistors. Each transistor (T1 to T7) includes a gate electrode, a first electrode, and a second electrode. Of the first electrode and the second electrode of each transistor (T1 to T7), one becomes the source electrode and the other becomes the drain electrode.

[0063] Each transistor (T1 to T7) may be a thin-film transistor. Each transistor (T1 to T7) may be either a PMOS transistor or an NMOS transistor. In one embodiment, the first transistor (T1) which is a driving transistor, the second transistor (T2) which is a data transfer transistor, the third transistor (T3) which is a compensation transistor, the fourth transistor (T4) which is a first initialization transistor, the fifth transistor (T5) which is a first light emission control transistor, the sixth transistor (T6) which is a second light emission control transistor, and the seventh transistor (T7) which is a second initialization transistor are all PMOS transistors.

[0064] However, this is not limited thereto, and for example, the third transistor (T3), which is a compensation transistor, and the fourth transistor (T4), which is a first initialization transistor, may be NMOS transistors, and the first transistor (T1), which is a driving transistor, the second transistor (T2), which is a data transfer transistor, the fifth transistor (T5), which is a first light emission control transistor, the sixth transistor (T6), which is a second light emission control transistor, and the seventh transistor (T7), which is a second initialization transistor, may be PMOS transistors. In this case, the active layer of the third transistor (T3) and the fourth transistor (T4), and the active layer of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may contain different materials. Although not limited thereto, for example, the active layers of the third transistor (T3) and the fourth transistor (T4) may comprise an oxide semiconductor, and the active layers of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6) and the seventh transistor (T7) may comprise polycrystalline silicon.

[0065] Below, each component is described in detail.

[0066] The gate electrode of the first transistor (T1) is connected to the first electrode of the capacitor (Cst). The first electrode of the first transistor (T1) is connected to the first power supply voltage line (ELVDDL) via the fifth transistor (T5). The second electrode of the first transistor (T1) is connected to the anode electrode of the light-emitting element (LE) via the sixth transistor (T6). The first transistor (T1) receives a data signal (DATA) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting element (LE).

[0067] The gate electrode of the second transistor (T2) is connected to a first scan signal line that applies a first scan signal (GW). The first electrode of the second transistor (T2) is connected to a data line that applies a data signal (DATA). The second electrode of the second transistor (T2) is connected to the first electrode of the first transistor (T1). The second transistor (T2) is turned on according to the first scan signal (GW) and performs a switching operation to transmit the data signal (DATA) to the first electrode of the first transistor (T1).

[0068] The third transistor (T3) may be formed as a dual transistor including a first sub-transistor (T3_1) and a second sub-transistor (T3_2). The gate electrode of the first sub-transistor (T3_1) is connected to a first scan signal line that applies a first scan signal (GW), the first electrode is connected to the second electrode of the second sub-transistor (T3_2), and the second electrode is connected together with the first electrode of the capacitor (Cst), the first electrode of the third sub-transistor (T4_1), and the gate electrode of the first transistor (T1). The gate electrode of the second sub-transistor (T3_2) is connected to a first scan signal line that applies a first scan signal (GW), the first electrode is connected to the second electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the first sub-transistor (T3_1).

[0069] The first sub-transistor (T3_1) and the second sub-transistor (T3_2) are turned on by the first scan signal (GW) to connect the gate electrode of the first transistor (T1) and the second electrode, thereby diode-connecting the first transistor (T1). Accordingly, a voltage difference equal to the threshold voltage of the first transistor (T1) is generated between the first electrode and the gate electrode of the first transistor (T1), and the threshold voltage deviation of the first transistor (T1) can be compensated by supplying a data signal (DATA) with the threshold voltage compensated to the gate electrode of the first transistor (T1).

[0070] The fourth transistor (T4) may be formed as a dual transistor comprising a third sub-transistor (T4_1) and a fourth sub-transistor (T4_2). The gate electrode of the third sub-transistor (T4_1) is connected to a second scan signal line that applies a second scan signal (GI), and the first electrode is connected together with the first electrode of the capacitor (Cst), the second electrode of the first sub-transistor (T3_1), and the gate electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the fourth sub-transistor (T4_2). The gate electrode of the fourth sub-transistor (T4_2) is connected to a second scan signal line that applies a second scan signal (GI), the first electrode is connected to the second electrode of the third sub-transistor (T4_1), and the second electrode may be connected to an initialization voltage (VINT). The third sub-transistor (T4_1) and the fourth sub-transistor (T4_2) are turned on by the second scan signal (GI) to transmit an initialization voltage (VINT) to the gate electrode of the first transistor (T1) and perform the operation of initializing the voltage of the gate electrode of the first transistor (T1).

[0071] The gate electrode of the fifth transistor (T5) is connected to a light emission control signal line that applies a light emission control signal (EM), the first electrode is connected to a first power supply voltage line (ELVDDL), and the second electrode is connected to the first electrode of the first transistor (T1). The fifth transistor (T5) is turned on by the light emission control signal (EM) to connect the first electrode of the first transistor (T1) and the first power supply voltage line (ELVDDL).

[0072] The sixth transistor (T6) is connected between the second electrode of the first transistor (T1) and the first electrode of the light-emitting element (LE). The gate electrode of the sixth transistor (T6) is connected to a light-emitting control signal line that applies a light-emitting control signal (EM), the first electrode is connected to the second electrode of the first transistor (T1) and the first electrode of the second sub-transistor (T3_2), and the second electrode is connected to the first electrode of the light-emitting element (LE).

[0073] The fifth transistor (T5) and the sixth transistor (T6) are turned on simultaneously according to the light emission control signal (EM), and accordingly, a driving current flows to the light-emitting element (LE).

[0074] The gate electrode of the seventh transistor (T7) is connected to a third scan signal line that applies a third scan signal (GB). The first electrode of the seventh transistor (T7) is connected to the anode electrode of the light-emitting element (LE). The second electrode of the seventh transistor (T7) is connected to an initialization voltage line that applies an initialization voltage (VINT). The seventh transistor (T7) is turned on according to the third scan signal (GB) to initialize the anode electrode of the organic light-emitting element (OLED).

[0075] In this embodiment, the case where the gate electrode of the seventh transistor (T7) receives the third scan signal (GB) has been exemplified, but in other embodiments, the circuit of the pixel (PX) may be configured so that the gate electrode of the seventh transistor (T7) receives the light emission control signal (EM) or the second scan signal (GI).

[0076] A capacitor (Cst) is formed between the gate electrode of the first transistor (T1) and the first power supply voltage line (ELVDDL) and includes a first electrode and a second electrode. The first electrode of the capacitor (Cst) is connected together to the gate electrode of the first transistor (T1), the second electrode of the third transistor (T3), and the first electrode of the fourth transistor (T4), and the second electrode of the capacitor (Cst) can be connected to the first power supply voltage line (ELVDDL). The capacitor (Cst) can serve to maintain a constant data voltage applied to the gate electrode of the first transistor (T1).

[0077] The cathode electrode of the light-emitting element (LE) is connected to the second power supply voltage line (ELVSSL) and receives the second power supply voltage (ELVSS) from the second power supply voltage line (ELVSSL). The light-emitting element (LE) receives a driving current from the first transistor (T1) and emits light to display an image.

[0078] FIG. 4 is a plan view showing the arrangement of a scan driving unit and a light-emitting driving unit of a display device according to one embodiment. FIG. 5 is an enlarged view of area A of FIG. 4.

[0079] Referring to FIGS. 4 and FIGS. 5, the display device (1) may further include a scan driver (SDU) and a light-emitting driver (EDU).

[0080] The scan driver (SDU) and the light-emitting driver (EDU) may be positioned in the non-display area (NDA). The light-emitting driver (EDU) may be positioned outside the scan driver (SDU). In other words, the scan driver (SDU) may be positioned closer to the display area (DA) than the light-emitting driver (EDU), but is not limited thereto. The scan driver (SDU) and the light-emitting driver (EDU) may be positioned on one side and the other side of the first direction (DR1) of the display area (DA), respectively, but are not limited thereto, and may be positioned on only one side or the other side of the first direction (DR1) of the display area (DA).

[0081] The scan drive unit (SDU) may include a plurality of scan stages (SST) and a plurality of scan control wires (SCL). Each of the plurality of scan stages (SST) may be connected to at least one of the plurality of scan control wires (SCL). Each of the plurality of scan stages (SST) may generate scan signals according to the scan control signal of the scan control wires (SCL) and output them to the scan wires (SLk-1, SLk in FIG. 6).

[0082] Scan control wiring (SCL) extends to a second direction (DR2) and can be positioned between the scan driver (SDU) and the light-emitting driver (EDU) with respect to the first direction (DR1). Scan control wiring (SCL) can be electrically connected to the driver chip (20). Scan control wiring (SCL) can receive scan control signals from the driver chip (20). The scan control signals may include scan clock signals and scan start signals.

[0083] The light-emitting driving unit (EDU) may include a plurality of light-emitting stages (EST) and a plurality of light-emitting control wires (ECL). Each of the plurality of light-emitting stages (EST) may be connected to at least one of the plurality of light-emitting control wires (ECL). Each of the plurality of light-emitting stages (EST) may generate light-emitting signals according to a light-emitting control signal of the light-emitting control wire (ECL) and output them to the light-emitting wires (ELk-1, ELk in FIG. 7).

[0084] The light emission control wires (ECL) can be placed on the outside of the light emission driver (EDU). The light emission control wires (ECL) can be electrically connected to the driver chip (20). The light emission control wires (ECL) can receive light emission control signals from the driver chip (20). The light emission control signals may include light emission clock signals and light emission start signals.

[0085] The second power voltage line (ELVSSL) may be placed in the non-display area (NDA). The second power voltage line (ELVSSL) may be placed on one side and the other side of the first direction (DR1) and on one side of the second direction (DR2) of the display area (DA). In other words, the second power voltage line (ELVSSL) may be placed bypassing the display area (DA). From one side and the other side of the first direction (DR1) of the display area (DA), the second power voltage line (ELVSSL) extends to the second direction (DR2), and from one side of the second direction (DR2), the second power voltage line (ELVSSL) may extend to the first direction (DR1).

[0086] The second power voltage line (ELVSSL) can overlap the scan driver (SDU) and the light-emitting driver (EDU) in the thickness direction (third direction (DR3)) on one side and the other side of the first direction (DR1) of the display area (DA). The second power voltage line (ELVSSL) can be electrically connected to the driver chip (20). The second power voltage line (ELVSSL) can receive a second power voltage (ELVSS, see FIG. 3) from the driver chip (20).

[0087] The second power supply voltage line (ELVSSL) overlaps with the scan control wiring (SCL), and a second organic insulating layer (125, see FIG. 8) is disposed between the second power supply voltage line (ELVSSL) and the scan control wiring (SCL) in the overlapped area, and the second organic insulating layer (125, see FIG. 8) can overlap with all of the multiple scan control wiring (SCL). Accordingly, a short circuit between the second power supply voltage line (ELVSSL) and the scan control wiring (SCL) can be suppressed or prevented. A detailed explanation thereof will be provided later.

[0088] Figure 6 is a circuit diagram showing an example of the scan drive unit of Figure 5.

[0089] Referring to FIG. 6, the scan drive unit (SDU) may include a plurality of scan stages (SST). Although FIG. 6 shows two scan stages (a first sub-scan stage (SST1) and a second sub-scan stage (SST2)), the number of scan stages (SST) may be two or more.

[0090] The first sub-scan stage (SST1) and the second sub-scan stage (SST2) can sequentially output scan signals. For example, the first sub-scan stage (SST1) can be connected to the k-1 scan wiring (SLk-1) to output the k-1 scan signal. The second sub-scan stage (SST2) can be connected to the k scan wiring (SLk) to output the k scan signal.

[0091] The k-th scan signal output by the k-th scan wiring (SLk) is substantially identical to the first scan signal (GW, see FIG. 3) and the third scan signal (GB, see FIG. 3), and the k-1-th scan signal output by the k-1-th scan wiring (SLk-1) may be substantially identical to the second scan signal (GI, see FIG. 3), but is not limited thereto. In other words, the k-th scan wiring (SLk) is connected to the gate electrode of the second transistor (T2, see FIG. 3) and the gate electrode of the third transistor (T3, see FIG. 3) of a pixel (PX, see FIG. 3), and the k-1-th scan wiring (SLk-1) may be connected to the gate electrode of the fourth transistor (T4, see FIG. 3) of a pixel (PX, see FIG. 3).

[0092] The first sub-scan stage (SST1) and the second sub-scan stage (SST2) can be connected to scan control wires (SCL). The scan control wires (SCL) may include a scan start signal wire to which a scan start signal is applied, scan clock wires (SCL1, SCL2) to which scan clock signals are applied, a first gate-on voltage wire (VGHL1), and a first gate-off voltage wire (VGLL1). In FIG. 6, the scan start signal wire has been omitted for convenience of explanation.

[0093] Each of the first sub-scan stage (SST1) and the second sub-scan stage (SST2) includes, as shown in FIG. 6, a first pull-up node (NQ1), a first pull-down node (NQB1), a first pull-up transistor (TU1) that is turned on when the first pull-up node (NQ1) has a first gate-on voltage, a first pull-down transistor (TD1) that is turned on when the first pull-down node (NQB1) has a first gate-on voltage, and a first node control unit (NC1) for controlling the charging and discharging of the first pull-up node (NQ1) and the first pull-down node (NQB1).

[0094] The first node control unit (NC1) includes a first start terminal (ST1), a first reset terminal (RT1), a first gate-on voltage terminal (VGHT1), a first gate-off voltage terminal (VGLT1), a first clock terminal (CT1), and a first output terminal (OT1). The first start terminal (ST1) may be connected to a scan start wiring to which a scan start signal is applied, or to a first front-end carry wiring (PCL1) to which an output signal of a front-end stage is applied. The first reset terminal (RT1) may be connected to a first rear-end carry wiring (RCL1) to which an output signal of a rear-end stage is input. The first gate-on voltage terminal (VGHT1) may be connected to a first gate-on voltage wiring (VGHL1) to which a first gate-on voltage is applied. The first gate-off voltage terminal (VGLT1) may be connected to a first gate-off voltage wiring (VGLL1) to which a gate-off voltage is applied. The first gate-on voltage may be a first-level voltage, and the first gate-off voltage may be a second-level voltage. The first node control unit (NC1) may include a plurality of thin-film transistors.

[0095] The first clock terminal (CT1) may be connected to either the first scan clock wiring (SCL1), to which a scan clock signal is applied, or the second scan clock wiring (SCL2), to which a second scan clock signal is applied. The stages (SST1, SST2) may be alternately connected to the first scan clock wiring (SCL1) and the second scan clock wiring (SCL2). For example, if the first clock terminal (CT1) of the first sub-scan stage (SST1) is connected to the first scan clock wiring (SCL1), the first clock terminal (CT1) of the second sub-scan stage (SST2) may be connected to the second scan clock wiring (SCL2). FIG. 6 illustrates the first sub-scan stage (SST1) and the second sub-scan stage (SST2) being alternately connected to two scan clock wirings (SCL1, SCL2), but is not limited thereto. For example, the first sub-scan stage (SST1) and the second sub-scan stage (SST2) can be alternately connected to three or more scan clock wires.

[0096] The first output terminal (OT1) can be connected to any one of the scan lines (SLk-1, SLk). The stages (SST1, SST2) can be connected sequentially to the scan lines (SLk-1, SLk). For example, the first output terminal (OT1) of the first sub-scan stage (SST1) can be connected to the k-1 scan line (SLk-1), and the first output terminal (OT1) of the second sub-scan stage (SST2) can be connected to the k-1 scan line (SLk).

[0097] Additionally, FIG. 6 illustrates that the first pull-up transistor (TU1), the first pull-down transistor (TD1) of the first sub-scan stage (SST1) and the second sub-scan stage (SST2), and the plurality of transistors of the first node control unit (NC1) are formed as P-type MOSFETs, but the embodiments of the present specification are not limited thereto. That is, the first pull-up transistor (TU1), the first pull-down transistor (TD1) of the first sub-scan stage (SST1) and the second sub-scan stage (SST2), and the plurality of transistors of the first node control unit (NC1) may be formed as N-type MOSFETs.

[0098] Figure 7 is a circuit diagram showing an example of the light-emitting driving unit of Figure 5.

[0099] Referring to FIG. 7, the light-emitting driving unit (EDU) may include a plurality of light-emitting stages (EST). FIG. 7 shows two scan stages (a first sub-light-emitting stage (EST1) and a second sub-light-emitting stage (EST2)), but the number of light-emitting stages (EST) may be two or more.

[0100] The first sub-emitting stage (EST1) and the second sub-emitting stage (EST2) can sequentially output light emission signals. For example, the first sub-emitting stage (EST1) can be connected to the k-1 light emission wiring (ELk-1) to output the k-1 light emission signal. The second sub-emitting stage (EST2) can be connected to the k-1 light emission wiring (ELk) to output the k-1 light emission signal.

[0101] The first sub-luminescent stage (EST1) and the second sub-luminescent stage (EST2) can be connected to light emission control wiring (ECL). The light emission control wiring (ECL) includes a light emission start signal wiring to which a light emission start signal is applied, light emission clock wirings (ECL1, ECL2) to which light emission clock signals are applied, a second gate-on voltage wiring (VGHL2), and a second gate-off voltage wiring (VGLL2). In FIG. 7, the light emission start signal wiring has been omitted for convenience of explanation.

[0102] The k-th light-emitting signal output by the k-th light-emitting wiring (ELk) may be substantially the same as, but not limited to, the light-emitting control signal (EM, see FIG. 3). In other words, the k-th scan wiring (SLk) may be connected to the gate electrode of the fifth transistor (T5, see FIG. 3) and the gate electrode of the sixth transistor (T6, see FIG. 3) of a pixel (PX, see FIG. 3).

[0103] Each of the first sub-emitting stage (EST1) and the second sub-emitting stage (EST2) includes, as shown in FIG. 7, a second pull-up node (NQ2), a second pull-down node (NQB2), a second pull-up transistor (TU2) that is turned on when the second pull-up node (NQ2) has a second gate-on voltage, a second pull-down transistor (TD2) that is turned on when the second pull-down node (NQB2) has a second gate-on voltage, and a second node control unit (NC2) for controlling the charging and discharging of the second pull-up node (NQ2) and the second pull-down node (NQB2).

[0104] The second node control unit (NC2) includes a second start terminal (ST2), a second reset terminal (RT2), a second gate-on voltage terminal (VGHT2), a second gate-off voltage terminal (VGLT2), a second clock terminal (CT2), and a second output terminal (OT2).

[0105] Since the first sub-emitting stage (EST1) and the second sub-emitting stage (EST2) receive a scan start signal and other emission start signals, scan clock signals and other emission clock signals, they differ from the first sub-scan stage (SST1) and the second sub-scan stage (SST2) described in conjunction with FIG. 6 in that they output scan signals and other emission signals, but the rest of the description may be substantially the same. Therefore, the description of the first sub-emitting stage (EST1) and the second sub-emitting stage (EST2) in FIG. 7 is omitted.

[0106] The cross-sectional structure of the display panel is described in detail below.

[0107] First, with reference to FIG. 8, the cross-sectional structure of the display area (DA) will be described.

[0108] FIG. 8 is a cross-sectional view of the display area of ​​a display device according to one embodiment.

[0109] Referring to FIG. 8, a display panel (10) may include a substrate (SUB), a buffer layer (BF), a semiconductor layer (110), a first insulating layer (121, a first inorganic insulating layer), a first conductive layer (130), a second insulating layer (122, a second inorganic insulating layer), a second conductive layer (140), a third insulating layer (123, a third inorganic insulating layer), a third conductive layer (150), a fourth insulating layer (124, a first organic insulating layer), a fourth conductive layer (160), a fifth insulating layer (125, a second organic insulating layer), a fifth conductive layer (170), a sixth insulating layer (126, a third organic insulating layer), an anode electrode (ANO), a pixel defining layer (PDL), an emitting layer (EML), a cathode electrode (CAT), and an encapsulation layer (190). Each layer may be stacked sequentially in the order described above. Additionally, each layer may be composed of a single film, but may also be composed of a stacked film including a plurality of films. Other layers may be placed between each layer.

[0110] The substrate (SUB) supports each layer placed thereon. If the organic light-emitting display is of the back or double-sided emitting type, a transparent substrate may be used. If the organic light-emitting display is of the front emitting type, not only a transparent substrate but also a translucent or opaque substrate may be applied.

[0111] The substrate (SUB) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. Examples of materials that make up a flexible substrate include polyimide (PI), but are not limited thereto.

[0112] A buffer layer (BF) may be disposed on a substrate (SUB). The buffer layer (BF) can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform a surface planarization function. The buffer layer (BF) may include silicon nitride, but is not limited thereto, and may include silicon oxide or silicon oxynitride, etc. The buffer layer (BF) may be omitted depending on the type of substrate (SUB) or process conditions.

[0113] A semiconductor layer (110) is disposed on a buffer layer (BF). The semiconductor layer (110) forms a channel of a pixel thin-film transistor (T1 to T7, see FIG. 3). The semiconductor layer (110) may include polycrystalline silicon. However, it is not limited thereto, and the semiconductor layer (110) may include single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (ABx), a ternary compound (ABxCy), or a quaternary compound (ABxCyDz) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc.

[0114] A first insulating layer (121) is disposed on a semiconductor layer (110). The first insulating layer (121) may be a first gate insulating film having a gate insulating function. The first insulating layer (121) may include an inorganic insulating material. The first insulating layer (121) may include a silicon compound, a metal oxide, etc. For example, the first insulating layer (121) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0115] The first conductive layer (130) is disposed on the first insulating layer (121). The first conductive layer (130) may include the gate electrode (GAT) of the thin-film transistor of the pixel, the scan line connected thereto, and the first electrode (CE1) of the holding capacitor (Cst).

[0116] The first conductive layer (130) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0117] The second insulating layer (122) may be disposed on the first conductive layer (130). The second insulating layer (122) may be an interlayer insulating film or a second gate insulating film. The second insulating layer (122) may include an inorganic insulating material. The second insulating layer (122) may include the same material as the first insulating layer (121), but is not limited thereto.

[0118] The second conductive layer (140) is disposed on the second insulating layer (122). The second conductive layer (140) may include the second electrode (CE2) of the retaining capacitor (Cst). The second conductive layer (140) may be made of the same material as the first conductive layer (130), but is not limited thereto.

[0119] A third insulating layer (123) is disposed on the second conductive layer (140). The third insulating layer (123) may be an interlayer insulating film. The third insulating layer (123) may include an inorganic insulating material. The third insulating layer (123) may include the same material as the first insulating layer (121), but is not limited thereto.

[0120] A third conductive layer (150) is disposed on the third insulating layer (123). The third conductive layer (150) may include the first electrode (SD1) and the second electrode (SD2) of the thin-film transistor of the pixel. The first electrode (SD1) and the second electrode (SD2) of the thin-film transistor may be electrically connected to the source region and the drain region of the semiconductor layer (110) through a contact hole penetrating the third insulating layer (123), the second insulating layer (122), and the first insulating layer (121). The first power supply voltage line (ELVDDL) of the pixel may also be made of the third conductive layer (150). The first power supply voltage line (ELVDDL) may be electrically connected to the second electrode (CE2) of the retaining capacitor (Cst) through a contact hole penetrating the third insulating layer (123).

[0121] The third conductive layer (150) may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer (150) may include a plurality of stacked structures. For example, the third conductive layer (150) may be formed with a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0122] A fourth insulating layer (124) is disposed on the third conductive layer (150). The fourth insulating layer (124) covers the third conductive layer (150). The fourth insulating layer (124) may be a via layer. The fourth insulating layer (124) may include an organic insulating material. For example, the fourth insulating layer (124) may include polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB), etc.

[0123] The fourth conductive layer (160) is disposed on the fourth insulating layer (124). The fourth conductive layer (160) may include a first anode connecting electrode (CNE1). The first anode connecting electrode (CNE1) may be electrically connected to the second electrode (SD2) of the thin-film transistor through a contact hole penetrating the fourth insulating layer (124). Through the first anode connecting electrode (CNE1) and the second anode connecting electrode (CNE2), the anode electrode (ANO) and the second electrode (SD2) of the thin-film transistor may be electrically connected. The fourth conductive layer (160) may include the same material as the third conductive layer (150) or the same stacked structure, but is not limited thereto.

[0124] The fifth insulating layer (125) is disposed on the fourth conductive layer (160). The fifth insulating layer (125) covers the fourth conductive layer (160). The fifth insulating layer (125) may be a via layer. The fifth insulating layer (125) may include an organic insulating material. The fifth insulating layer (125) may include the same material as the fourth insulating layer (124), but is not limited thereto.

[0125] A fifth conductive layer (170) is disposed on the fifth insulating layer (125). The fifth conductive layer (170) may include a second anode connecting electrode (CNE2). The fifth conductive layer (170) may further include a second power supply voltage line (ELVSSL, see FIG. 3). The second anode connecting electrode (CNE2) may be electrically connected to a first anode connecting electrode (CNE1) through a contact hole penetrating the fifth insulating layer (125). The fifth conductive layer (170) may include the same material as the third conductive layer (150) or the same laminated structure, but is not limited thereto.

[0126] A sixth insulating layer (126) is disposed on the fifth conductive layer (170). The sixth insulating layer (126) covers the fifth conductive layer (170). The sixth insulating layer (126) may be a via layer. The sixth insulating layer (126) may include an organic insulating material. The sixth insulating layer (126) may include the same material as the fourth insulating layer (124), but is not limited thereto.

[0127] The sixth conductive layer (180) is disposed on the sixth insulating layer (126). The sixth conductive layer (180) may include an anode electrode (ANO). The anode electrode (ANO) may be a pixel electrode provided for each pixel. The anode electrode (ANO) may be connected to a second anode connecting electrode (CNE2) through a contact hole penetrating the sixth insulating layer (126). The anode electrode (ANO) may overlap at least partially with the light-emitting region (EMA) of the pixel.

[0128] The sixth conductive layer (180) may have a stacked film structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof are stacked. The high work function layer may be positioned above the reflective material layer and positioned close to the light-emitting layer (EML). The sixth conductive layer (180) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0129] A pixel defining film (PDL) may be disposed on the sixth conductive layer (180). The pixel defining film (PDL) may include an opening that exposes an anode electrode (ANO). A light-emitting region (EMA) and a non-light-emitting region (NEM) may be separated by the pixel defining film (PDL) and the opening. The pixel defining film (PDL) may include an organic insulating material such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB). The pixel defining film (PDL) may also include an inorganic material.

[0130] The light-emitting layer (EML) is disposed on the anode electrode (ANO) exposed by the pixel defining layer (PDL). The light-emitting layer (EML) may include an organic material layer. The organic material layer of the light-emitting layer includes an organic light-emitting layer and may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0131] The cathode electrode (CAT) can be placed on the light-emitting layer (EML). The cathode electrode (CAT) may be a common electrode placed across the entire surface without distinguishing pixels. The anode electrode (ANO), the light-emitting layer (EML), and the cathode electrode (CAT) can each constitute an organic light-emitting device.

[0132] The cathode electrode (CAT) may contact not only the light-emitting layer (EML) but also the upper surface of the pixel defining film (PDL). The cathode electrode (CAT) may be formed conformally to the underlying structure to reflect the step difference of the underlying structure.

[0133] The cathode electrode (CAT) may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode electrode (CAT) may further include a transparent metal oxide layer disposed on the layer of material with a low work function.

[0134] The encapsulation layer (190) may be disposed on the cathode electrode (CAT). The encapsulation layer (190) may include a first inorganic encapsulation film (191), an organic encapsulation film (192), and a second inorganic encapsulation film (193). At the ends of the encapsulation layer (190), the first inorganic encapsulation film (191) and the second inorganic encapsulation film (193) may come into contact with each other. The organic encapsulation film (192) may be sealed by the first inorganic encapsulation film (191) and the second inorganic encapsulation film (193).

[0135] The first inorganic sealing film (191) and the second inorganic sealing film (193) may each include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The organic sealing film (192) may include an organic insulating material.

[0136] Next, the cross-sectional structure of the non-display area (NDA) will be described with reference to FIG. 9.

[0137] FIG. 9 is a cross-sectional view of a non-display area of ​​a display device according to one embodiment.

[0138] Referring to FIGS. 8 and 9, the display device (1) may further include a valley section (VAL), a dam structure (DAM), and a groove (TCH).

[0139] The valley portion (VAL) may be positioned between the scan driver (SDU) and the light-emitting driver (EDU). The valley portion (VAL) may be defined by an organic insulating layer. The valley portion (VAL) may be defined by a fourth insulating layer (124), a fifth insulating layer (125), and a sixth insulating layer (126). The valley portion (VAL) may penetrate the fourth insulating layer (124), the fifth insulating layer (125), and the sixth insulating layer (126) in the thickness direction (third direction (DR3)). The valley portion (VAL) may expose the third insulating layer (123).

[0140] The organic insulating layer overlapping the scan driving unit (SDU) and the organic insulating layer overlapping the light-emitting driving unit (EDU) can be separated from each other by the valley portion (VAL). Accordingly, the out-gas generated in the area where the light-emitting driving unit (EDU) is located can be suppressed or prevented from spreading to the area where the scan driving unit (SDU) is located. Furthermore, the out-gas can be suppressed or prevented from spreading to the display area (DA), thereby improving the reliability of the display device (1).

[0141] A dam structure (DAM) may be placed outside the light-emitting driver (EDU). The dam structure (DAM) may include stacked organic insulating layers (124, 125, 126). A groove (TCH) from which the organic insulating layers (124, 125, 126) have been removed may be placed between the dam structure (DAM) and the light-emitting driver (EDU). At least a portion of the encapsulation layer (190) may be placed within the groove (TCH). For example, the organic encapsulation film (192) of the encapsulation layer (190) may be placed only up to the dam structure (DAM) and not beyond the dam structure (DAM). That is, the organic encapsulation film (192) may be prevented from overflowing to the outside of the display device (1) through the dam structure (DAM). The first weapon sealing layer (191) or the second weapon sealing layer (193) of the sealing layer (190) may be placed over the dam structure (DAM).

[0142] The scan driver unit (SDU) may include at least one thin-film transistor (TFT_S). The thin-film transistor (TFT_S) of the scan driver unit (SDU) may be substantially identical to either the first pull-up transistor (TU1, see FIG. 6) and the first pull-down transistor (TD1, see FIG. 6). The thin-film transistor (TFT_S) of the scan driver unit (SDU) includes a gate electrode (GS), a source electrode (SS), and a drain electrode (DS), and the semiconductor layer (100) may include the channel of the thin-film transistor (TFT_S) of the scan driver unit (SDU).

[0143] The scan control wiring (SCL) may be composed of a third conductive layer (150), but is not limited thereto, and at least one of the scan control wiring (SCL) may have a plurality of laminated structures composed of a third conductive layer (150) and a fourth conductive layer (160).

[0144] The light-emitting driver unit (EDU) may include at least one thin-film transistor (TFT_E). The thin-film transistor (TFT_E) of the light-emitting driver unit (EDU) may be substantially identical to either a second pull-up transistor (TU2, see FIG. 7) and a second pull-down transistor (TD2, see FIG. 7). The thin-film transistor (TFT_E) of the light-emitting driver unit (EDU) includes a gate electrode (GE), a source electrode (EE), and a drain electrode (DE), and the semiconductor layer (100) may include the channel of the thin-film transistor (TFT_E) of the light-emitting driver unit (EDU).

[0145] The light-emitting control wiring (ECL) may be composed of a third conductive layer (150), but is not limited thereto, and at least one of the light-emitting control wiring (ECL) may have a plurality of laminated structures composed of a third conductive layer (150) and a fourth conductive layer (160).

[0146] The second power supply voltage line (ELVSSL) may include a first sub-power supply voltage line (ELVSSL1) and a second sub-power supply voltage line (ELVSSL2).

[0147] The first sub-power voltage line (ELVSSL1) is formed of a third conductive layer (150) and may be disposed on a third insulating layer (123). In other words, the third conductive layer (150) may further include the first sub-power voltage line (ELVSSL1). The first sub-power voltage line (ELVSSL1) may be disposed outside the light-emitting driver (EDU), but is not limited thereto. The first sub-power voltage line (ELVSSL1) may be exposed by a groove (TCH). The first sub-power voltage line (ELVSSL1) exposed by the groove (TCH) may be in physical and / or electrical contact with the second sub-power voltage line (ELVSSL2). The first sub-power voltage line (ELVSSL1) may be physically and / or electrically connected to the driver chip (20, see FIG. 4).

[0148] The second sub-power voltage line (ELVSSL2) may be composed of a sixth conductive layer (180). In other words, the sixth conductive layer (180) may further include the second sub-power voltage line (ELVSSL2). The second sub-power voltage line (ELVSSL2) may be in physical and / or electrical contact with the first sub-power voltage line (ELVSSL1) exposed by the groove (TCH). The second sub-power voltage line (ELVSSL2) may be in physical and / or electrical contact with the cathode electrode (CAT). That is, the cathode electrode (CAT) may be electrically connected to the driving chip (20, see FIG. 4) through the first sub-power voltage line (ELVSSL1) and the second sub-power voltage line (ELVSSL2).

[0149] The fourth insulating layer (124) and the fifth insulating layer (125) can overlap with the scan drive unit (SDU) in the thickness direction (third direction (DR3)). The fourth insulating layer (124) and the fifth insulating layer (125) can overlap with a plurality of scan control wires (SCL) in the thickness direction. Accordingly, the fourth insulating layer (124) and the fifth insulating layer (125) are disposed between the scan control wire (SCL) that does not overlap with the sixth insulating layer (126) and the second sub-power voltage line (ELVSSL2), thereby suppressing or preventing a short circuit between the scan control wire (SCL) that does not overlap with the sixth insulating layer (126) and the second sub-power voltage line (ELVSSL2).

[0150] Although not limited thereto, for example, based on the thickness direction (third direction (DR3)), the first thickness (TH1) of the fourth insulating layer (124) and the fifth insulating layer (125) between the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2) may be within the range of 0.9 μm to 1.7 μm or 1.3 μm. The first thickness (TH1) may refer to the average thickness over the entire area, and if the first thickness (TH1) is within the above range, a short between the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2) that does not overlap with the sixth insulating layer (126) can be suppressed or prevented regardless of the deviation of the first thickness (TH1).

[0151] In other words, when the display device (1) includes a sixth conductive layer (180), during the process of patterning the sixth conductive layer (180), the uppermost insulating layer among the plurality of insulating layers in the region that does not overlap with the sixth conductive layer (180) may have its upper portion etched and its thickness reduced. However, when the plurality of scan control wires (SCL) all overlap with the fourth insulating layer (124) and the fifth insulating layer (125), the fourth insulating layer (124) and the fifth insulating layer (125) are disposed between the scan control wires (SCL) and the second sub-power voltage line (ELVSSL2), and even if the thickness of the fifth insulating layer (125) is reduced by being exposed by the sixth insulating layer (126), the thickness of the fourth insulating layer (124) may be maintained. Therefore, a short circuit between the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2) that does not overlap with the sixth insulating layer (126) can be suppressed or prevented. Furthermore, the operation of the display device (1) can proceed more smoothly.

[0152] In addition, while the relationship between the organic insulating film and the scan control wiring (SCL) has been explained above, this explanation can be equally applied to the relationship between the organic insulating film and the light emission control wiring (ECL).

[0153] Other embodiments are described below. In the following embodiments, descriptions of components identical to those already described are omitted or simplified, and the explanation focuses on the differences.

[0154] FIG. 10 is a cross-sectional view of a display device according to another embodiment. FIG. 10 illustrates a cross-section of a non-display area (NDA).

[0155] Referring to FIG. 10, the display device (1_1) according to the present embodiment differs from the embodiment of FIG. 9 in that it further includes a third sub-power voltage line (ELVSSL3_1, or an anti-etching pattern).

[0156] The etch-prevention pattern (ELVSSL3_1) may be formed by the fifth conductive layer (170). In other words, the fifth conductive layer (170) may further include the etch-prevention pattern (ELVSSL3_1). The etch-prevention pattern (ELVSSL3_1) may be placed on the fifth insulating layer (125). The etch-prevention pattern (ELVSSL3_1) may be placed across the scan driver (SDU), valley (VAL), light-emitting driver (EDU), and groove (TCH). The etch-prevention pattern (ELVSSL3_1) may be placed inside the valley (VAL) and groove (TCH).

[0157] The etch prevention pattern (ELVSSL3_1) can overlap with the scan drive unit (SDU). Based on the thickness direction, the etch prevention pattern (ELVSSL3_1) is positioned between the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2), so that it can overlap with the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2). In other words, the etch prevention pattern (ELVSSL3_1) overlaps with the scan control wiring (SCL) in the thickness direction and can overlap with the second sub-power voltage line (ELVSSL2) in the thickness direction from the scan drive unit (SDU).

[0158] The etching prevention pattern (ELVSSL3_1) can cover the exposed fifth insulating layer (125) that is not covered by the sixth insulating layer (126). Accordingly, when the display device (1_1) includes the sixth conductive layer (180), even if the sixth conductive layer (180) is patterned, the etching of the exposed fifth insulating layer (125) that is not covered by the sixth insulating layer (126) can be suppressed or prevented. Furthermore, the reduction in the thickness of the exposed fifth insulating layer (125) that is not covered by the sixth insulating layer (126) can be suppressed or prevented, and a short circuit between the scan control wiring (SCL) and the second sub-power voltage line (ELVSSL2) that does not overlap with the sixth insulating layer (126) can be suppressed or prevented.

[0159] The second power supply voltage line (ELVSSL_1) may further include an etch-prevention pattern (ELVSSL3_1). In other words, when the etch-prevention pattern (ELVSSL3_1) is placed in the groove (TCH), the first sub-power supply voltage line (ELVSSL1) and the second sub-power supply voltage line (ELVSSL2) may be electrically connected by the etch-prevention pattern (ELVSSL3_1). The etch-prevention pattern (ELVSSL3_1) is placed inside the groove (TCH) between the first sub-power supply voltage line (ELVSSL1) and the second sub-power supply voltage line (ELVSSL2) so as to make physical and / or electrical contact with the first sub-power supply voltage line (ELVSSL1) and the second sub-power supply voltage line (ELVSSL2).

[0160] However, this is not limited thereto, and the etch prevention pattern (ELVSSL3_1) is not placed in the area where the groove (TCH) is placed, and the first sub-power voltage line (ELVSSL1) and the second sub-power voltage line (ELVSSL2) may be in direct contact. In this case, the etch prevention pattern (ELVSSL3_1) may be separated from the power voltage line (ELVSSL_1) and may be electrically insulated.

[0161] In this case as well, as the fifth insulating layer (125) overlaps all of the multiple scan control wires (SCL) in the thickness direction, a short circuit between the scan control wires (SCL) and the second sub-power voltage line (ELVSSL2) can be suppressed or prevented.

[0162] FIG. 11 is a cross-sectional view of a display device according to another embodiment. FIG. 11 illustrates a cross-section of a non-display area (NDA) of a display device (1_2).

[0163] Referring to FIG. 11, the present embodiment differs from the embodiment of FIG. 9 in that at least one of the scan control wiring (SCL_2) of the display device (1_2) according to the present embodiment may have a plurality of stacked structures.

[0164] The scan control wiring (SLC_2) may include a first scan control wiring (SCL_S) composed of a third conductive layer (150), and a second scan control wiring (SCL_D) composed of a third conductive layer (150) and a fourth conductive layer (160). The second scan control wiring (SCL_D) may include a first stacked conductive layer (TC1) and a second stacked conductive layer (ST2), wherein the first stacked conductive layer (TC1) is composed of the third conductive layer (150), and the second stacked conductive layer (ST2) is composed of the fourth conductive layer (160). In other words, the third conductive layer (150) may include the first stacked conductive layer (TC1) of the first scan control wiring (SCL_S) and the second scan control wiring (SCL_D), and the fourth conductive layer (160) may include the second stacked conductive layer (TC2) of the second scan control wiring (SCL_D).

[0165] As the second scan control wiring (SCL_D) includes the first stacked conductive layer (TC1) and the second stacked conductive layer (TC2), the electrical resistance of the second scan control wiring (SCL_D) is reduced, and the transmission of the signal can be smoother. For example, if the scan clock wiring (SCL1, SCL2, see FIG. 6) sensitive to electrical resistance is made of the second scan control wiring (SCL_D), the operation of the display device (1_2) can be smoother.

[0166] The sixth insulating layer (126) can overlap with the second scan control wiring (SCL_D) in the thickness direction. The sixth insulating layer (126) can overlap with the second stacked conductive layer (TC2) of the second scan control wiring (SCL_D) in the thickness direction.

[0167] Although not limited thereto, for example, with respect to the thickness direction (third direction (DR3)), the second thickness (TH2) of the fifth insulating layer (125) and the sixth insulating layer (126) between the second scan control wiring (SCL_D) and the second sub-power voltage line (ELVSSL2) may be within the range of 0.6 μm to 1.4 μm. The second thickness (TH2) may refer to the average thickness over the entire area. When the second thickness (TH2) is within the above range, even if the second scan control wiring (SCL_D) includes the first stacked conductive layer (TC1) and the second stacked conductive layer (TC2), a short circuit between the second scan control wiring (SCL_D) and the second sub-power voltage line (ELVSSL2) can be suppressed or prevented regardless of the deviation in the second thickness (TH2).

[0168] In this case as well, as the fifth insulating layer (125) overlaps all of the multiple scan control wires (SCL_2) in the thickness direction, a short circuit between the scan control wires (SCL_2) and the second sub-power voltage line (ELVSSL2) can be suppressed or prevented.

[0169] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0170] 1: Display device 10: Display panel SDU: Scan driver EDU: Light-emitting driver SST: Scan Stage EST: Emitting Stage SCL: Scan control wiring ECL: Light emission control wiring 124: First organic insulating layer 125: Second organic insulating layer 126: Third organic insulating layer ELVSSL: Second power supply voltage wiring

Claims

Claim 1 A display device comprising: a substrate; a plurality of scan stages disposed on the substrate; a first conductive layer disposed on the substrate and including a plurality of scan control wires each electrically connected to the plurality of scan stages; a first organic insulating layer disposed on the first conductive layer; and a second organic insulating layer disposed on the first organic insulating layer, wherein the first organic insulating layer and the second organic insulating layer overlap with the plurality of scan control wires, and further comprising a second conductive layer disposed on the second organic insulating layer, wherein the scan control wires include a first scan control wire formed by the first conductive layer, and a second scan control wire comprising a first stacked conductive layer formed by the first conductive layer and a second stacked conductive layer formed by the second conductive layer. Claim 2 A display device according to claim 1, further comprising a power voltage line disposed on the second organic insulating layer and overlapping with the plurality of scan stages, wherein the first organic insulating layer and the second organic insulating layer are disposed between the power voltage line and the plurality of scan stages. Claim 3 A display device according to claim 2, wherein the first organic insulating layer and the second organic insulating layer disposed between the power supply voltage line and the plurality of scan stages have a first thickness, and the first thickness is within the range of 0.9 μm to 1.7 μm. Claim 4 A display device according to claim 3, further comprising a third organic insulating layer disposed on the second organic insulating layer and an anode electrode disposed on the third organic insulating layer, wherein the power supply voltage line comprises the same material as the anode electrode. Claim 5 A display device according to claim 4, further comprising a pixel defining film disposed on the anode electrode and exposing the anode electrode, a light-emitting layer disposed on the anode electrode exposed by the pixel defining film, and a cathode electrode disposed on the light-emitting layer. Claim 6 delete Claim 7 A display device according to claim 1, further comprising a third organic insulating layer disposed on the second conductive layer, and a power voltage line disposed on the third organic insulating layer and overlapping with the second scan control wiring, wherein the third organic insulating layer overlaps with the second scan control wiring, and the second organic insulating layer and the third organic insulating layer are disposed between the second scan control wiring and the power voltage line. Claim 8 A display device according to claim 7, wherein the second organic insulating layer and the third organic insulating layer disposed between the power supply voltage line and the second scan control wiring have a second thickness, and the second thickness is within the range of 0.6 μm to 1.4 μm. Claim 9 A display device according to claim 1, further comprising an etching prevention pattern disposed on the second organic insulating layer and overlapping with the plurality of scan control lines, a third organic insulating layer disposed on the etching prevention pattern, and a first sub-power voltage line disposed on the third organic insulating layer and overlapping with the plurality of scan control lines. Claim 10 In claim 9, the first conductive layer further comprises a second sub-power voltage line, and the first sub-power voltage line and the second sub-power voltage line are electrically connected through the etching prevention pattern. Claim 11 A display device according to claim 1, further comprising a display area for displaying a screen and a non-display area disposed around the display area, wherein the plurality of scan stages and the plurality of scan control wires are disposed in the non-display area. Claim 12 A display device according to claim 11, further comprising a driving chip disposed in the non-display area, wherein the driving chip is electrically connected to the plurality of scan stages through the plurality of scan control wiring. Claim 13 A display device according to claim 1, further comprising a dam structure disposed outside the plurality of scan stages and the plurality of scan control wires, and including the first organic insulating layer and the second organic insulating layer. Claim 14 A display device according to claim 1, further comprising a plurality of light-emitting stages disposed on the substrate and a plurality of light-emitting control wires electrically connected to each of the plurality of light-emitting stages. Claim 15 A display device according to claim 14, further comprising a valley portion disposed between the plurality of scan stages and the plurality of scan control wires and the plurality of light-emitting stages and the plurality of light-emitting control wires, and defined by the first organic insulating layer and the second organic insulating layer. Claim 16 In claim 15, the valley portion is a display device that penetrates the first organic insulating layer and the second organic insulating layer in the thickness direction. Claim 17 A display device comprising: a display area; a scan driving unit disposed outside the display area and including a plurality of scan stages and a plurality of scan control wires electrically connected to each of the plurality of scan stages; a first organic insulating layer disposed on the plurality of scan control wires; a second organic insulating layer disposed on the first organic insulating layer; and a power voltage line disposed on the second organic insulating layer, and further comprising a second conductive layer disposed between the second organic insulating layer and the power voltage line, wherein the scan control wires include a first scan control wire comprising a first conductive layer, and a second scan control wire comprising a first stacked conductive layer comprising the first conductive layer and a second stacked conductive layer comprising the second conductive layer. Claim 18 A display device according to claim 17, wherein the first organic insulating layer and the second organic insulating layer disposed between the power supply voltage line and the plurality of scan stages have a first thickness, and the first thickness is within the range of 0.9 μm to 1.7 μm. Claim 19 A display device according to claim 18, further comprising a third organic insulating layer disposed on the second organic insulating layer and an anode electrode disposed on the third organic insulating layer, wherein the power supply voltage line comprises the same material as the anode electrode. Claim 20 A display device according to claim 19, further comprising a pixel defining film disposed on the anode electrode and exposing the anode electrode, a light-emitting layer disposed on the anode electrode exposed by the pixel defining film, and a cathode electrode disposed on the light-emitting layer.

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