Die-to-die connectivity monitoring

Abstract

Input / Output (I / O) Sensor for a Multi-IC Module. The I / O sensor includes a delay circuit configured to receive a data signal from an interconnected portion of an IC of the multi-IC module and generate a delayed data signal—the delay circuit includes an adjustable delay line configured to delay the input signal by a set time period—; a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic configured to set the time period of the adjustable delay line and, based on the comparison signal, identify a margin measurement of the data signal to determine an interconnection quality parameter.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 012,457, filed on April 20, 2020, with the title of the invention “Die-to-Die (Tile) Connectivity Degradation Monitoring Based On Eye Measurement”, the contents of which are incorporated herein by reference.

[0003] Technology field

[0004] The present invention relates to the field of integrated circuits. Background Technology

[0005] Semiconductor integrated circuits (ICs) typically contain analog and digital electronic circuits on a flat semiconductor substrate, such as a silicon wafer. Microscopic transistors are printed onto the substrate using photolithography techniques to create complex circuits of billions of transistors in a very small area, achieving both low cost and high performance in modern electronic circuit designs utilizing ICs. ICs are produced on assembly lines in factories referred to as foundries, which have commercialized the production of ICs such as CMOS (complementary metal-oxide-semiconductor) ICs.

[0006] Typically, ICs are manufactured in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductors (e.g., GaAs). The wafer is diced into many pieces, each containing a copy of the circuit. Each of these pieces is referred to as a 'die'.

[0007] Digital ICs are typically packaged within metal, plastic, glass, or ceramic casings. The casing or 'package' is connected to a circuit board, for example, using solder. Types of packages include lead frames (through-hole, surface mount, chip carrier, etc.), pin grid arrays, chip scale packages, ball grid arrays, etc., for connecting IC pads to the circuit board.

[0008] Some modern ICs are, in effect, modules composed of multiple interconnected ICs (sometimes referred to as "chips" or "chiplets") configured to work together. A typical example is a logic IC interconnected with a memory IC, but many other types exist. Additionally, many die-to-die (i.e., IC-to-IC) connectivity technologies exist. One example is wafer-level integration characterized by high-density connectivity, which is based on, for example, the Re-Distribution Layer (RDL) and Through Integrated Fan-Out Vias (TIV) sold by TSMC, Limited (Taiwan Semiconductor Manufacturing Company, Limited). Another example is system-level integration featuring individual chips bonded via microbumps on a silicon interposer, such as Chip on Wafer on Substrate (CoWoS) technology sold by TSMC Limited and Embedded Interconnect Bridge (EMIB) technology sold by Intel Corporation. Both of these enable High Bandwidth Memory (HBM) subsystems. A third example is three-dimensional (3D) chip stacking technology based on through-silicon vias (TSVs), such as Chip on Wafer (CoW) and Wafer on Wafer (WoW) technologies sold by TSMC Limited.

[0009] The foregoing examples of the relevant technology and the limitations associated therewith are intended to be exemplary rather than exclusive. A person skilled in the art will be aware of other limitations of the relevant technology upon reading this specification and examining the drawings. means of solving the problem

[0010] The following embodiments and aspects thereof are described and illustrated in relation to systems, tools, and methods intended to be exemplary and illustrative, rather than limiting in scope.

[0011] In an embodiment, an input / output (I / O) sensor for a multi-IC (integrated circuit) module is provided. The I / O sensor includes a delay circuit configured to receive a data signal from an interconnected portion of an IC of the multi-IC module and generate a delayed data signal—the delay circuit includes an adjustable delay line configured to delay the input signal by a set time period—a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic configured to set the time period of the adjustable delay line and, based on the comparison signal, identify a margin measurement of the data signal to determine an interconnection quality parameter.

[0012] In the embodiments, the processing logic is configured to set an adjustable delay line for each of a plurality of time periods, determine whether a comparison signal for each time period indicates a pass condition or a fail condition, and identify a minimum time period from the plurality of time periods where the comparison signal indicates a fail condition.

[0013] In embodiments, the processing logic is configured to repeat, for each of a plurality of measurement cycles, setting an adjustable delay line for each of a plurality of time periods and identifying a minimum time period, wherein the processing logic is further configured to determine one or more of the following: a minimum minimum time period over a plurality of measurement cycles; a maximum minimum time period over a plurality of measurement cycles; and the sum of the minimum time periods over a plurality of measurement cycles.

[0014] In the embodiments, the interconnection quality parameter comprises one or more of the following: an eye pattern parameter; a microbump resistance parameter; a systematic influence parameter; and a parameter indicating the symmetry of differential signals.

[0015] In the embodiments, the margin measurement comprises one of the following: a data signal setting time to a clock rising edge; a data signal setting time to a clock falling edge; a data signal holding time to a clock rising edge; and a data signal holding time to a clock falling edge.

[0016] In the embodiments, the comparison circuit includes an XOR gate. In the embodiments, the adjustable delay line has a resolution of at least 1 ps and / or at least 16 configurations over a time period.

[0017] In the embodiments, the data signal is provided as an input signal to an adjustable delay line, and the data signal and the delayed data signal are sampled according to the clock signal. In the embodiments, the data signal is sampled according to the clock signal, the clock signal is provided as an input signal to an adjustable delay line to provide a delayed clock signal, and the delayed data signal is the data signal sampled according to the delayed clock signal.

[0018] In embodiments, the delay circuit comprises: a first state element configured to receive a first state-element input signal and provide a first state-element output based on the first state-element input signal and a first clock input; a second state element configured to receive a second state-element input signal and provide a second state-element output based on the second state-element input signal and a second clock input; and further comprises a multiplexing array, wherein the multiplexing array is configured to optionally apply the following: (i) a data signal as an input signal for an adjustable delay line—the output of the adjustable delay line is provided as a first state-element input signal, the data signal is provided as a second state-element input signal, and the clock signal is provided as first and second clock inputs—; or (ii) a clock signal as an input signal for an adjustable delay line - the output of the adjustable delay line is provided as a first clock input, the data signal is provided as first and second state-element input signals, and the clock signal is provided as a second clock input -.

[0019] In embodiments, the multiplexing array is further configured to optionally apply the following as a clock signal: (a) a positive clock signal; or (b) a negative clock signal which is an inverted positive clock signal.

[0020] According to embodiments, an input / output (I / O) block comprising a plurality of I / O sensors is provided, and each I / O sensor is configured to receive a different data signal from an interconnected portion of an IC of a multi-IC module as disclosed herein.

[0021] In the embodiments, the processing logic for each of the plurality of I / O sensors is located in a control block common to all I / O sensors.

[0022] In the embodiments, each I / O sensor is configured to receive a data signal from a different pin of the interconnected portion of the IC of the multi-IC module and to identify a margin measurement for each pin in parallel with other sensors.

[0023] According to embodiments, an input / output (I / O) block for a multi-IC module is provided, wherein the I / O block comprises a receiving buffer configured to receive a voltage signal from an interconnected portion of a semiconductor IC and provide a receiving buffer output; an I / O sensor as disclosed herein, wherein the receiving buffer output is provided as a data signal input to a delay circuit.

[0024] In the embodiments, the I / O sensor is further configured to receive a clock signal input, and the clock signal associated with the received voltage signal is provided as the clock signal input.

[0025] In embodiments, the receiving buffer is a first receiving buffer and is configured to receive a first voltage signal from a first interconnected portion of a semiconductor IC and provide a first receiving buffer output, the I / O sensor is additionally configured to receive a clock signal input, and the I / O block further includes a second receiving buffer configured to receive a second voltage signal from a second interconnected portion of a semiconductor IC and provide a second receiving buffer output; and a second receiving buffer output with a delay applied is provided as a clock signal input.

[0026] In embodiments, the I / O sensor is a first I / O sensor, the clock signal input is a first clock signal input, the I / O block further includes a second I / O sensor as disclosed herein, the second receive buffer output is provided as a data signal input to a delay circuit, and the second I / O sensor is further configured to receive a second clock signal input; and the first receive buffer output with the applied delay is provided as a second clock signal input.

[0027] In embodiments, the I / O block further comprises a multiplexing array, and the multiplexing array is configured to optionally apply: (a) a first receiving buffer output as a data signal input to an I / O sensor and a second receiving buffer output to which a delay is applied as a clock signal input to an I / O sensor; or (b) a second receiving buffer output as a data signal input to an I / O sensor and a first receiving buffer output to which a delay is applied as a clock signal input to an I / O sensor.

[0028] In the embodiments, the first and second interconnected portions of the IC form a differential channel.

[0029] In the embodiments, the I / O block is located on the IC of the multi-IC module and is configured to interface with an external processor to store identified margin measurements and / or determine interconnect quality parameters.

[0030] According to embodiments, an input / output (I / O) monitoring system comprising a plurality of I / O blocks is provided, each of which is as disclosed herein, and all of the plurality of I / O blocks are controlled by a common I / O controller.

[0031] According to embodiments, an IC of a multi-IC module is provided, comprising an input / output (I / O) block as described herein or an input / output (I / O) monitoring system as described herein.

[0032] In some embodiments, when instructions are executed by a processor, a computer-readable medium storing instructions for executing any of the method embodiments disclosed herein may be considered.

[0033] In addition to the exemplary aspects and embodiments described above, additional aspects and embodiments will become apparent by referring to the drawings and reviewing the following detailed description. A person skilled in the art will understand that combinations and sub-combinations of specific features disclosed herein may also be provided, even if not explicitly described. Brief explanation of the drawing

[0034] Exemplary embodiments are illustrated in the referenced drawings. The dimensions of the components and features depicted in the drawings are generally chosen for convenience and clarity of presentation and are not necessarily drawn to scale. The drawings are listed below. FIG. 1 illustrates a schematic block diagram of a die-to-die connectivity monitoring system according to the present disclosure. FIG. 2 illustrates a schematic block diagram of an input / output (I / O) block for use in a die-to-die connectivity monitoring system. Figure 3 shows a schematic circuit diagram of an I / O sensor forming part of an I / O block. FIG. 4 illustrates a waveform timing diagram for monitoring margin parameters by referring to a set time according to the present disclosure. FIG. 5 illustrates a waveform timing diagram for monitoring margin parameters with reference to the holding time according to the present disclosure. Figure 6 illustrates a waveform timing diagram of the operation of a die-to-die connectivity monitoring system over a measurement cycle. FIG. 7 illustrates a waveform timing diagram for activating and resetting an I / O sensor according to FIG. 3. FIG. 8 shows a schematic block diagram of an I / O block controller that forms part of an I / O block. FIG. 9 shows a schematic circuit diagram of a part of the I / O block controller of FIG. 8 configured for automatic test pattern generation (ATPG) mode and sensor reset. FIG. 10 illustrates a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring the degradation of a bidirectional or receive-only interconnect signal channel. FIG. 11 illustrates a schematic circuit diagram of an implementation of an I / O sensor for monitoring the degradation of transmit-only signal interconnection channels. Figure 12 illustrates waveform timing for three scenarios in degradation monitoring of transmit-only signal interconnection channels. FIG. 13 illustrates a schematic circuit diagram of an implementation of an I / O sensor for monitoring the degradation of differential interconnect receiving channels. FIG. 14 illustrates a schematic circuit diagram of an implementation of an I / O sensor for monitoring the degradation of differential interconnect transmission channels. Specific details for implementing the invention

[0035] Devices, systems, and methods for measuring and / or estimating input / output (I / O) margins and / or eye pattern parameters and / or integrity and / or degradation of multi-IC modules (sometimes referred to as “multi-chip modules”), or for optimizing power and / or performance for such multi-IC modules are disclosed herein.

[0036] The term "multi-IC module" describes a group of interconnected ICs integrated and packaged together, as referred to herein, which may be configured to cooperate through such interconnection to achieve specific combined functionality. The ICs within the module may communicate with each other, for example, via an interconnection bus. Their physical integration may be horizontal, vertical, or both.

[0037] The multi-IC module to which the present disclosure relates may be constructed by any known or later-introduced integration technology that provides direct connection between ICs or indirect connection through an intermediary such as a specific interposer, substrate, circuit board, etc. It is also possible for the multi-IC module to utilize both direct and indirect connectivity between various pairs of the integrated ICs. Examples of modern multi-IC module integration technologies include CoWoS (Chip on Wafer on Substrate), WoW (Wafer on Wafer), CoW (Chip on Wafer), and 3D ICs. However, embodiments of the present invention are also clearly beneficial for any other type of multi-IC module featuring die-to-die (IC-to-IC) connectivity.

[0038] The disclosed devices, systems, and methods involve die-to-die connectivity monitoring, in particular, determining the quality of connectivity of high-speed die-to-die interconnects. These interconnects can implement wide buses and / or low power (picojoules / bit). Quality issues may cause open circuits, short circuits, bridge short circuits (signal-to-signal), microbump resistance degradation on the receiver side, and / or microbump resistance degradation on the transmitter side. In this case, the timing of the signal at the receiver is expected to change, and such change can be detected by the monitoring system. The timing and power effects of such monitoring are negligible.

[0039] HBM3 (High Bandwidth Memory 3) is a type of die-to-die connectivity that implements different types of lanes, namely bidirectional lanes, receive-only lanes, transmit-only lanes, and differential lanes. Each of these lane types can be monitored in various ways as discussed herein.

[0040] The margin does not need to be measured by examining the timing difference between signals; instead, it is measured by comparing the received data signal with a delayed data signal using an adjustable delay line set to provide a predetermined time delay. If the comparison results in a pass, the margin is higher than the delay applied to the data signal. The minimum delay applied to the data signal that causes the comparison to fail can be considered as the margin. By using an adjustable delay line in this manner, it is possible to achieve high resolution when measuring the margin. Conventional direct time measurements have relatively poor resolution, such as about a 1-buffer delay, which is technology-dependent and may be in the range of 10 picoseconds (ps). In contrast, using the techniques according to the present disclosure, a resolution of about 2 ps (a fraction of the buffer delay) can be achieved.

[0041] The core application is eye measurement for characterization, specifically measuring failure margins or performance per pin or lane. Input / output (I / O) sensors are positioned at each receiver in each lane. The delay of the adjustable delay line is gradually shifted until failure is detected (adjusted in small increments). The I / O sensors can be configured in four modes to fully characterize the eye opening on the receiver side. For degradation monitoring, the adjustable delay line position can be compared with stored and ongoing life measurements. For eye width characterization, the delay line position can be used to measure the set time to failure.

[0042] In a general concept, an I / O sensor for a semiconductor IC may be considered. The I / O sensor includes a delay circuit configured to receive a data signal from an interconnected portion of the semiconductor IC (e.g., at a pin or lane of one IC within a multi-IC module) and to generate a delayed data signal. The delay circuit includes an adjustable delay line configured to delay an input signal by a set time period (although, as described below, the delayed data signal does not necessarily have to be the output of the adjustable delay line). The I / O sensor further includes a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal. Processing logic is further provided configured to set the time period of the adjustable delay line and, based on the comparison signal, identify a margin measurement of the data signal to determine an interconnection quality parameter. In accordance with this general concept, a method for manufacturing and / or operating the I / O sensor may also be provided, comprising corresponding steps of providing and / or configuring the I / O sensor accordingly.

[0043] The processing logic may be configured to set an adjustable delay line for each of multiple time periods and, for each set time period, determine whether a comparison signal for each time period indicates a pass condition or a fail condition. Then, the processing logic may be configured to identify the minimum value of these time periods from the multiple time periods where the comparison signal indicates a fail condition. This minimum value may correspond to a margin measurement.

[0044] Margin measurements may include one of the following: a data signal setting time to the clock rising edge; a data signal setting time to the clock falling edge; a data signal holding time to the clock rising edge; and a data signal holding time to the clock falling edge. Multiple margin measurements may be determined for the same interconnect (pin or lane), and each may be for different margins of those listed herein.

[0045] Interconnection quality parameters may include, for example, one or more of the following: eye pattern parameters; microbump resistance parameters; systematic influence parameters; and parameters indicating the symmetry of differential signals. These may optionally be determined from margin measurements together with other factors.

[0046] Other specific features will now be discussed. General concepts will be further considered below.

[0047] Refer to Fig. 1, which illustrates a schematic block diagram of a die-to-die connectivity monitoring system, which is not exclusive but particularly applicable to 3D ICs. The same system can be used to monitor die-to-die connectivity of any type, not just 3D ICs. In 2.5D packaging, interconnects (lanes) connect adjacent chips, for example, a DRAM controller located in a system-on-chip (SoC) to a DRAM located in a stacked DRAM (HBM3). In 3D packaging, interconnects (lanes) connect chips stacked together, for example, a DRAM controller located at the bottom of a stack (first chip) to stacked SRAM dies. In other packaging types, connectivity can be described as a transmitter driving a line with a receiver at its end, and a die-to-die connectivity monitoring system can still be used. However, given the area limitations and the fact that the system can use a single I / O sensor to serve multiple receivers, the system is advantageous for 3D ICs.

[0048] The die-to-die connectivity monitoring system detects reliability issues in mission mode per pin and enables margin characterization in four measurement modes per pin. Quality monitoring is based on the (in progress) tracking of the timing of the received signal (Rx signal) at the receiver. Monitoring is performed for each lane with minimal timing and power penalty. Possible quality issues may be related to open pins, short pins, bridge-shorts (signal-to-signal), microbump resistance degradation on the receiver side, and / or microbump resistance degradation on the transmitter side.

[0049] The die-to-die connectivity monitoring system supports a number of [k] I / O blocks, and each block supports a number of [n] I / O lanes. The I / O lanes can be bidirectional (providing transmission and reception), receive-only, transmit-only, and / or differential lanes. The measurement process of each block is managed by a dedicated controller (Prtn_tca_block_controller) located within the block. The block controller controls [n] I / O sensors (one for each lane or pin).

[0050] Configuration data and control signals are transmitted from the block controller to the I / O sensors, and failure indication data is transmitted from each I / O sensor to each block controller. In the measurement cycle, all [n] I / O sensors are activated in parallel to measure the failure margin of each of the [n] pins. At the end of the measurement cycle, the controller maintains the failure margin of each pin, which is represented by a 6-bit digital readout in the embodiment.

[0051] All block controllers are controlled by a central full-chip (FC) controller (prtn_tca_top_ctrl). The FC controller generates a low-frequency clock (Prtn_clk) used to activate the finite state machines (FSMs) within the block controllers. The low-frequency clock (Prtn_clk) signal is generated from the Advanced Peripheral Bus (APB) clock. Frequency division is programmable and related to the APB clock. The FC controller also generates a central active low reset signal (prtn_rst_n) for all block controllers. The FC controller collects data from each of the block controllers (e.g., APB, JTAG, I 2 (Using C) transmit data to an external source via the serial bus.

[0052] At the characterization stage, the offline data analysis system receives margin data through an external source and uses this data to measure or calculate one or more of the following: eye width per pin; eye height per pin; clock duty cycle effects on eye width per pin; eye width and / or eye height jitter amplitude per pin; systematic effects per group of pins; and symmetry of differential signals.

[0053] In mission mode, the offline data analysis system receives margin data via an external source and uses this data to calculate eye width degradation and / or microbump resistance degradation on the receiver side, and / or microbump resistance degradation and / or differential lane microbump degradation on the transmitter side. This may include one or more of the following: anomaly detection; systematic shift detection; warnings; and lane repair.

[0054] Data analysis from a large number of such die-to-die connectivity monitoring systems, each embedded in different ICs, can advantageously be performed in an analysis system. The analysis system may be a computerized system comprising one or more hardware processor(s) (e.g., CPUs), random access memory (RAM), one or more non-transient computer-readable storage device(s), and a network interface controller (NIC). The storage device(s) may store program instructions and / or components configured to operate the hardware processor(s). The program instructions may include one or more software modules, such as a data analysis module, which analyzes margin data received from ICs operating in the field.

[0055] Software components may include an operating system having various software components and / or drivers for controlling and managing general system operations (e.g., memory management, storage device control, power management, network communication, etc.) and facilitating communication between various hardware and software components.

[0056] The analysis system may operate by loading the instructions of the data analysis module into RAM as they are executed by the processor(s). The instructions of the data analysis module may enable the analysis system to receive margin data collected from multiple ICs, for example, through its network interface controller (e.g., via the Internet), process it, and output a statistical analysis of the data. The statistical analysis may indicate, for example, eye pattern parameters (including eye width), degradation rates, lanes and / or pins that typically collapse or degrade faster, etc. Based on the analysis performed by the system, one or more of the ICs may be reconfigured to adjust one or more of the data throughput, clock rate, and processing time. In this regard, the system may transmit a message to be reconfigured to each IC through the system's NIC, through a communication network (e.g., the Internet), and through the communication interfaces of these ICs. The message may include instructions on how to set or change internal IC parameters to affect data flow or clock speed. The instructions may be individual to each IC regarding specific margin data of that IC. Alternatively, the same command can be transmitted to multiple ICs classified as closely related by statistical analysis.

[0057] The analysis system described herein is merely an exemplary embodiment of the invention and may actually be implemented in hardware alone, in software alone, or in a combination of both hardware and software. The analysis system may have more or fewer components and modules than illustrated, may combine two or more of the components, or may have different configurations or arrangements of the components. The analysis system may include any additional components that enable it to function as an operable computer system, such as a motherboard, data buses, power, display, input device (e.g., keyboard, pointing device, touch-sensitive display), etc. Additionally, the components of the analysis system may be located together or distributed, or the analysis system may be executed as one or more cloud computing "instances," "containers," and / or "virtual machines" as is known in the art.

[0058] Referring to FIG. 2, a schematic block diagram of the I / O block is shown. This illustrates the connectivity of the block controller to the I / O sensors (the I / O sensor pin names are identical to the signal names). The signals will be discussed in more detail below.

[0059] The block controller (Prtn_tca_block_controller) is clocked by a phase-locked loop (PLL) split clock (in one embodiment, equivalent to 1 GHz and 10 splits for a 10 GHz PLL clock) and by a low-frequency clock (Prtn_clk) generated by the FC controller. The PLL clock is provided by the PLL block. Thus, the split clock is a derivative of the main clock used for data transmission. The two clocks are distinct.

[0060] The divided PLL clock synchronizes the sensor failure indication signal and is used for internal FSMs. The low-frequency clock (Prtn_clk) interfaces with the FC controller and is used to acquire commands and measurement readings. As described below, each I / O sensor is clocked by the PLL clock (10 GHz, as discussed above). Failure margin data is associated with the rising edge of this clock.

[0061] Referring to FIG. 3, a schematic circuit diagram of an I / O sensor forming part of an I / O block is illustrated. As discussed above, the key input to the I / O sensor is a clock signal, which is an undivided clock provided from the PLL block. In practice, the clock signal can be provided in two forms: a positive clock signal (clkp); and a negative clock signal, which is the inverted form of the positive clock signal (clkn). The other input is a data signal (d_in) from the pin or lane being measured. Configuration signals (ptrn_io_sensor_cfg) are also provided to the I / O sensor as inputs. An enable signal (ptrn_io_sensor_en) is an additional input to the I / O sensor.

[0062] The core components of the I / O sensor are as follows: an adjustable delay line (10); and an XOR comparison logic gate providing an output comparison signal (X0). The adjustable delay line provides an output signal (x_in_d) which is a version of its input delayed by a set configurable time period. A plurality of state elements or sampling elements or flip-flops (FF) are also provided, with a first state element (FF1) and a second state element (FF2) being most relevant, as the outputs of these two state elements are two inputs to the XOR comparison logic gate. The I / O sensor also includes a signal multiplexing array (20) that constitutes the inputs for the adjustable delay line, the first state element (FF1), and the second state element (FF2). Each state element has two inputs: a respective data signal (i4nput); and a respective clock signal input. If the outputs of the first and second state elements are the same, the output comparison signal (X0) will be a logic low value, indicating a pass result where the margin is smaller than the set delay time period. If the outputs of the first and second state elements are different, the output comparison signal (X0) will be a logic low value, indicating a failure result where the margin is less than or equal to the set delay time period.

[0063] The input signals are processed to define additional signals. The data signal (d_in) and the activation signal (ptrn_io_sensor_en) are provided as inputs to a first AND gate to define the processed data signal (d_in_i). The positive clock signal (clkp) and the activation signal (ptrn_io_sensor_en) are provided as inputs to a second AND gate to define the processed positive clock signal (clk_p_i). The negative clock signal (clkn) and the activation signal (ptrn_io_sensor_en) are provided as inputs to a third AND gate to define the processed negative clock signal (clk_n_i).

[0064] The signal multiplexing array (20) includes a first multiplexer (Mux1); a second multiplexer (Mux2); a third multiplexer (Mux3); a fourth multiplexer (Mux4); a fifth multiplexer (Mux5); a sixth multiplexer (Mux6); and a seventh multiplexer (Mux7). Of course, the use of seven multiplexers is merely an exemplary example, and any number of multiplexers may be used as required for a particular implementation while adhering to the principles described herein. The first multiplexer (Mux1) is controlled by a first 3-bit multiplexer control signal (S1) and provides a first multiplexer output by selecting among the following inputs: a processed data signal (d_in_i); a processed positive clock signal (clk_p_i); and a processed negative clock signal (clk_n_i). The first multiplexer output is an input to an adjustable delay line.

[0065] The second multiplexer (Mux2) is controlled by the second 3-bit multiplexer control signal (S2) and provides the second multiplexer output by selecting among the following inputs: a constant logic low signal (1'b0); a processed positive clock signal (clk_p_i); and a processed negative clock signal (clk_n_i). The third multiplexer (Mux3) is controlled by the third 3-bit multiplexer control signal (S3) and provides the third multiplexer output by selecting among the following inputs: a processed data signal (d_in_i); a constant logic low signal (1'b0); a constant logic low signal (1'b0).

[0066] The fourth multiplexer (Mux4), the fifth multiplexer (Mux5), the sixth multiplexer (Mux6), and the seventh multiplexer (Mux7) are all controlled by a 1-bit common control signal (C0). For each of these multiplexers, the enumerated first input is provided as an output when the common control signal is at a high logic level, and the enumerated second input is provided as an output when the common control signal is at a low logic level. The fourth multiplexer (Mux4) provides a fourth multiplexer output by selecting among the following inputs: a third multiplexer output; and an adjustable delay line output signal (x_in_d). The fourth multiplexer output is a data input for the first state element (FF1). The fifth multiplexer (Mux5) provides a fifth multiplexer output by selecting among the following inputs: an adjustable delay line output signal (x_in_d); and a second multiplexer output. The fifth multiplexer output is a clock input for the first state element (FF1). The sixth multiplexer (Mux6) provides a sixth multiplexer output by selecting from the following inputs: the third multiplexer output; and the first multiplexer output. The sixth multiplexer output is a data input for the second state element (FF2). The seventh multiplexer (Mux6) provides a seventh multiplexer output by selecting from the following inputs: the first multiplexer output; and the second multiplexer output. The seventh multiplexer output is a clock input for the second state element (FF2).

[0067] The I / O sensor can measure the relative timing characteristics of data and clock signals by a suitable configuration of the signal multiplexing array, and the following measurements are possible: the data signal setting time to the clock rising edge; the data signal setting time to the clock falling edge; the data signal holding time to the clock rising edge; and the data signal holding time to the clock falling edge. These configurations will be discussed further below.

[0068] The I / O sensor is configured by setting the configuration signal (values ​​of the configuration bits in prtn_io_sensor_cfg[10:0]). The 11 configuration bits are responsible for three types of functionality: 4 configuration bits (prtn_io_sensor_cfg[3:0]) configure an adjustable delay line value that changes dynamically during margin testing; 5 configuration bits (prtn_io_sensor_cfg[8:4]) configure the operating frequency (equivalent to half the data rate) and remain unchanged during margin testing; 2 configuration bits (prtn_io_sensor_cfg[10:9]) configure the measurement mode.

[0069] An example of how the five configuration bits (prtn_io_sensor_cfg[8:4]) can be configured according to the operating frequency is provided in Table 1 below.

[0070]

[0071] During the measurement cycle (described in more detail below), the block controller configures the internal adjustable delay lines of each I / O sensor using four configurations (prtn_io_sensor_cfg[3:0]) reserved for that purpose. This allows up to 16 different delay periods to be set for margin measurements. The minimum delay line value is configured by prtn_io_sensor_cfg[3:0] =

[0000] , and the maximum delay line value is configured by prtn_io_sensor_cfg[3:0] =

[11111] .

[0072] Four different margin measurement modes will now be discussed in more detail. The first mode to be considered is the measurement of the data signal setting time up to the clock rising edge. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), the second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed positive clock signal (clk_p_i), and the common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and, therefore, can be set to a constant logic low signal (1'b0). Consequently, the first state element is configured to sample the delayed data signal by the positive clock signal, and the second state element is configured to sample the data signal by the positive clock signal (i.e., without delay). Thus, an XOR comparison logic gate tests whether the data signal and the delayed data signal are identical when both are sampled by the same clock rising edge.

[0073] The measurement of the data signal setting time up to the clock falling edge is achieved as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), the second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed negative clock signal (clk_n_i), and the common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and, therefore, can be set to a constant logic low signal (1'b0). Consequently, the first state-element is configured to sample the delayed data signal by the negative clock signal, and the second state-element is configured to sample the data signal by the negative clock signal (i.e., without delay). Thus, an XOR comparison logic gate tests whether the data signal and the delayed data signal are the same when both are sampled by the same clock negative clock rising edge.

[0074] Now, refer to Fig. 4, which illustrates a waveform timing diagram for monitoring margin parameters with reference to the set time. The top waveform shows a clock signal (clk) displaying a UI (unit interval) that defines the minimum data width. For example, a system using dual data rate (DDR) generates data at the rising edge and falling edge of the clock; therefore, the UI is equal to the time interval between the rising and falling edges of the clock. The second waveform is the data signal (d_in). From this, the set time to the rising edge of the clock (△T_S_r) and the set time to the falling edge of the clock (△T_S_f) can be seen. A delayed data signal (x_in_d), which is the output from the adjustable delay line, is also illustrated, representing a range of different delays depending on the delay time period set for the adjustable delay line. Also, an output comparison signal (X0) for a specific delayed data signal (x_in_d) is shown, indicating a logic low in the illustrated case and thus indicating that the margin is at least a set delay time period. The sensor output signal (SO) corresponds to a sensor failure indicator signal (ptrn_io_sensor_fail). This is a sticky bit that remains at a logic low level from the first failure until a reset, and will be discussed further below.

[0075] The measurement of the data signal hold time up to the clock rising edge is achieved as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as a processed positive clock signal (clk_p_i), the third multiplexer (Mux3) is controlled to provide the third multiplexer output as a processed data signal (d_in_i), and the common control signal (C0) is set to a logic low value. The second multiplexer output is irrelevant and, therefore, can be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is a delayed positive clock signal. The data signal is not provided as an input to the adjustable delay line. Consequently, the first state-element is configured to sample the data signal by the delayed positive clock signal. Thus, the output of the first state-element is a delayed data signal, and the delay is introduced by sampling. The second state element is configured to sample the data signal by a positive clock signal (i.e., no delay). Thus, the XOR comparison logic gate tests whether the data signal sampled by the clock rising edge and the data signal sampled by the delayed clock rising edge (i.e., the delayed data signal) are the same.

[0076] The measurement of the data signal hold time up to the clock falling edge is achieved as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as a processed negative clock signal (clk_n_i), the third multiplexer (Mux3) is controlled to provide the third multiplexer output as a processed data signal (d_in_i), and the common control signal (C0) is set to a logic low value. The second multiplexer output is irrelevant and, therefore, can be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is the delayed negative clock signal. The data signal is again not provided as an input to the adjustable delay line. Consequently, the first state-element is configured to sample the data signal by the delayed negative clock signal. The output of the first state-element is again the data signal delayed by this, and the delay is introduced by sampling. The second state element is configured to sample the data signal by the negative clock signal (i.e., without delay). Thus, the XOR comparison logic gate tests whether the data signal sampled by the negative clock rising edge and the data signal sampled by the delayed negative clock rising edge (i.e., the delayed data signal) are the same.

[0077] Now, refer to FIG. 5, which illustrates a waveform timing diagram for monitoring margin parameters with reference to the hold time. The top waveform shows the clock signal (clk), and the second waveform is the data signal (d_in). From this, the hold time (△T_H_f) to the clock falling edge and the set time (△T_H_r) to the clock rising edge can be seen. A delayed clock signal (x_in_d), which is the output from the adjustable delay line, is also illustrated, representing a range of different delays depending on the delay time period set for the adjustable delay line. Additionally, an output comparison signal (X0) for a specific delayed clock signal (x_in_d) is illustrated, representing a logic low in the illustrated case and thus indicating that the margin is at least the set delay time period. The sensor output signal (SO) is as discussed above with reference to FIG. 4, and an example for its generation will be described in detail below.

[0078] As discussed above, two bits of the configuration signal (prtn_io_sensor_cfg) are used to configure the I / O sensor into one of four measurement modes. The first bit of these bits (prtn_io_sensor_cfg[9]) is a common control signal (C0) that configures the I / O sensor to set or hold a measurement. When the common control signal (C0, prtn_io_sensor_cfg[9]) is a logic low value ([0]), the I / O sensor is configured in the set measurement mode, and when the common control signal (C0, prtn_io_sensor_cfg[9]) is a logic low value ([1]), the I / O sensor is configured in the hold measurement mode. The second bit of these bits (C1, prtn_io_sensor_cfg

[10] ) determines whether the clock rising edge or the clock falling edge is used for reference. If this second bit (C1, prtn_io_sensor_cfg

[10] ) is a logic low value ([0]), then the I / O sensor is configured in clock-fall (negative) measurement mode, and if the second bit (C1, prtn_io_sensor_cfg

[10] ) is a logic low value ([1]), then the I / O sensor is configured to clock in clock-rise (positive) measurement mode.

[0079] The I / O sensor can configure a signal multiplexing array using these two configuration bits by the following logic mathematical expressions in Table 2:

[0080]

[0081] Returning to the general concept discussed above, additional features may be considered. For example, the comparison circuit may include an XOR gate. Then, the comparison signal may be based on the output of the XOR gate. One input to the XOR gate may be a data signal, and the other input may be a delayed data signal. The adjustable delay line may have a resolution of at least 1 ps. Additionally, or alternatively, the adjustable delay line may have at least 16 configurations over a time period.

[0082] In certain configurations, a data signal may be provided as an input signal to an adjustable delay line, and the data signal and the delayed data signal are sampled according to a clock signal. In other configurations, the data signal is sampled according to a clock signal, and the clock signal is provided to an adjustable delay line as an input signal to provide a delayed clock signal. Next, the delayed data signal may be a data signal sampled according to a delayed clock signal.

[0083] The delay circuit may further include: a first state element (e.g., a flip-flop) configured to receive a first state-element input signal and provide a first state-element output based on the first state-element input signal and a first clock input; a second state element (e.g., a flip-flop) configured to receive a second state-element input signal and provide a second state-element output based on the second state-element input signal and a second clock input; and a multiplexing array. The multiplexing array is advantageously configured to selectively apply one of two configurations. In the first configuration, a data signal is applied to an adjustable delay line as an input signal, the output of the adjustable delay line is provided as a first state-element input signal, the data signal is provided as a second state-element input signal, and a clock signal is provided as first and second clock inputs. In the second configuration, a clock signal is applied as an input signal to an adjustable delay line, the output of the adjustable delay line is provided as a first clock input, a data signal is provided as first and second state-element input signals, and a clock signal is provided as a second clock input. The multiplexing array may be further configured to optionally apply the following as a clock signal: (a) a positive clock signal; or (b) a negative clock signal which is an inverted positive clock signal.

[0084] In other general concepts (which may be combined with any other embodiments disclosed herein), an I / O block comprising a plurality of I / O sensors may be considered, each I / O sensor being as disclosed herein and configured to receive a different data signal from an interconnected portion of a semiconductor IC. The processing logic for each of the plurality of I / O sensors may be located in a common control block. Each I / O sensor may be configured to receive a different data signal from a different pin of an interconnected portion of a semiconductor IC and to identify a margin measurement for each pin in parallel with other sensors.

[0085] The I / O block may be located on a semiconductor IC. Next, the I / O block may be configured to interface with an external processor to store identified margin measurements and / or determine interconnection quality parameters.

[0086] According to other general concepts (which may also be combined with any other disclosures of this specification), an I / O monitoring system comprising a plurality of I / O blocks may be provided, each of which is as disclosed in this specification. Subsequently, each of the plurality of I / O blocks may be controlled by a common I / O controller.

[0087] Some general concepts may be considered as semiconductor ICs comprising an I / O block as described herein or an I / O monitoring system as described herein. As discussed above, a method for manufacturing and / or operating an I / O block, an I / O monitoring system, and / or semiconductor IC may also be provided, comprising corresponding steps of providing and / or configuring an I / O sensor accordingly.

[0088] The I / O sensor also includes a test verification section, and the test verification section includes a third state element (FF3); a fourth state element (FF4); an OR gate (OR1); and a fifth state element (FF5). An output comparison signal (X0) is provided to the OR gate (OR1) as a first input, and the output of the OR gate (OR1) is a data input for the fifth state element (FF5). The clock input for the fifth state element (FF5) is the seventh multiplexer output (as mentioned above, it is a positive clock signal when a rising edge measurement is being performed, and a negative clock signal when a falling edge measurement is being performed). The output of the fifth state element (FF5) is provided to the OR gate (OR1) as a second input. This output (provided through a buffer) indicates a sensor failure signal (ptrn_io_sensor_fail), which is maintained as a logic low value as soon as the output comparison signal (X0) becomes high. This corresponds to the sensor output signal (SO) discussed above.

[0089] The sensor failure indicator signal (ptrn_io_sensor_fail) is a 1-bit signal from each I / O sensor, which indicates that the delay line configuration adjustable by it is equal to or greater than the pin margin, which is the time difference between the data rise and the clock rise. As mentioned above, the failure indicator is generated by the I / O sensor using a sticky mechanism; that is, when the failure indicator rises, it will remain at a logic low level until the next I / O sensor reset (as described below). The sensor indicator is always related to the active or current configuration mode of the I / O sensor.

[0090] The third state element (FF3) and the fourth state element (FF4) form a two-stage synchronizer used to reset the fifth state element (FF5) and thereby reset the test failure signal (ptrn_io_sensor_fail). (As discussed above) the clock input for both the third state element (FF3) and the fourth state element (FF4) is the seventh multiplexer output. The data input for the third state element (FF3) is a constant logic low signal (1'b0), and the data input for the fourth state element (FF4) is the output of the third state element (FF3). The input of the active-low asynchronous reset signal (ptrn_io_sensor_rst_n) is also provided as a set signal input for both the third state element (FF3) and the fourth state element (FF4). The output of the fourth state element (FF4) is provided to the fifth state element (FF5) as a reset signal. Thus, the fifth state element (FF5) is used to synchronize the sensor failure indication signal with a high-speed clock. The serial structure of the third state element (FF3) and the fourth state element (FF4) is used to avoid meta-stability.

[0091] The block controller (prtn_tca_block_ctrl) generates a reset signal (prtn_io_sensor_rst_n) that is distributed to all I / O sensors within the block. The reset signal is associated with the PLL split clock domain used to clock the block controller (prtn_tca_block_ctrl). To this end, the block controller may use the block reset signal (prtn_rst_n) generated by the FC controller (prtn_tca_top_ctrl) synchronized with the PLL split clock.

[0092] The reset signal is generated by a block controller that is not synchronized with the I / O sensor operation clock (10 GHz clock in this exemplary example) and is used as an asynchronous reset in the I / O sensor. Therefore, the I / O sensor reset assertion is not synchronized with the 10 GHz clock. The reset must be asserted prior to any change in the adjustable delay line configuration. The I / O sensor reset assertion is synchronized with the I / O sensor operation clock (10 GHz) within the I / O sensor. Synchronization is performed using a 2-stage synchronizer located within each I / O sensor. The reset assertion time is equal to two 10 GHz clock cycles.

[0093] The I / O sensor is enabled by setting the enable signal (prtn_io_sensor_en) to a high logic level ([1]). This is performed for one clock cycle (PLL divided clock cycle) before the reset assertion. When the I / O sensor is disabled, after the reset assertion, the enable signal (prtn_io_sensor_en) is set to a low logic level ([0]) after one clock cycle (PLL divided clock cycle).

[0094] Generally, an input / output (I / O) sensor for a semiconductor three-dimensional (3D) integrated circuit (IC) may be considered. The I / O sensor includes a delay circuit configured to receive a data signal from an interconnected portion of the semiconductor 3D IC (which may be a bidirectional interface) and generate a delayed data signal; and a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal. The delay circuit includes an adjustable delay line configured to delay the input signal by a set time period. The I / O sensor further includes processing logic configured to set the time period of the adjustable delay line and, based on the comparison signal, identify a margin measurement of the data signal to determine an eye pattern parameter. Part or all of the processing logic may be located together with the remainder of the I / O sensor, and part or all of the processing logic may be located remotely from the I / O sensor. Part or all of the processing logic may be shared among two or more I / O sensors. A method for measuring an I / O margin, comprising steps for providing and / or operating the features of an I / O sensor described in this specification, may also be understood.

[0095] Additionally, an input / output (I / O) block including multiple I / O sensors may be considered. In this case, each I / O sensor may be configured to receive a different data signal from a different interconnected portion of a semiconductor 3D IC, for example, a different lane or pin. Each I / O sensor may be configured to receive a different data signal from a different pin of an interconnected portion of the semiconductor 3D IC, and each I / O sensor may be configured to identify a margin measurement for each pin in parallel with other sensors. Part or all of the processing logic for each of the multiple I / O sensors of the I / O block is advantageously located in a common control block. The I / O sensors and / or the I / O block may be located on the semiconductor 3D IC. Then, the I / O sensors and / or the I / O block may be configured to interface with an external processor to store the identified margin measurement and / or determine eye pattern parameters.

[0096] In an additional embodiment, an input / output (I / O) monitoring system comprising a plurality of I / O blocks may also be considered. Each of the plurality of I / O blocks may be controlled by a common I / O controller.

[0097] Another aspect may be found in a semiconductor three-dimensional (3D) integrated circuit (IC) comprising an input / output (I / O) sensor and / or an I / O block and / or an I / O monitoring system as described in this specification.

[0098] If we refer again to the I / O sensor (optionally within the I / O block, I / O monitoring system, or 3D IC), additional optional, desirable, and / or advantageous features may be considered.

[0099] Margin measurements may include, for example, one of the following: a data signal setting time to the clock rising edge; a data signal setting time to the clock falling edge; a data signal holding time to the clock rising edge; and a data signal holding time to the clock falling edge.

[0100] For each of the multiple time periods, the processing logic may set an adjustable delay line to each time period and determine whether a comparison signal for each time period indicates a pass or fail condition. Then, the processing logic may identify a minimum time period from the multiple time periods where the comparison signal indicates a failure condition. Optionally, for each of the multiple measurement cycles, the processing logic may repeat the following: the step of setting an adjustable delay line to each of the multiple time periods; and the step of identifying a minimum time period. Next, the processing logic may further determine one or more of the following: a minimum time period across the multiple measurement cycles; a maximum minimum time period across the multiple measurement cycles; and the sum of the minimum time periods across the multiple measurement cycles.

[0101] Optionally, the adjustable delay line has a resolution of at least 1 ps and / or at least 16 (optional, 32) configurations at the maximum frequency of operation during a time period (optional, 2 ps or for the operating frequency).

[0102] In the embodiments, the comparison circuit includes an XOR gate. A first input to the XOR gate may be provided by a data signal (advantageous, sampled), and a second input to the XOR gate may be provided by a delayed data signal.

[0103] In certain operation modes, the data signal is provided as an input signal to an adjustable delay line, and the data signal and the delayed data signal are sampled according to the clock signal. In other operation modes, the data signal is sampled according to the clock signal, and the clock signal is provided as an input signal to an adjustable delay line to provide a delayed clock signal. Next, the delayed data signal may be the data signal sampled according to the delayed clock signal.

[0104] The operation modes may be controlled by a multiplexing array. For example, the delay circuit comprises: a first state element configured to receive a first state-element input signal and provide a first state-element output based on the first state-element input signal and a first clock input; a second state element configured to receive a second state-element input signal and provide a second state-element output based on the second state-element input signal and a second clock input; and further comprises a multiplexing array, wherein the multiplexing array is configured to optionally apply the following: (i) a data signal as an input signal for an adjustable delay line—the output of the adjustable delay line is provided as a first state-element input signal, the data signal is provided as a second state-element input signal, and the clock signal is provided as first and second clock inputs—; or (ii) a clock signal as an input signal for an adjustable delay line—the output of the adjustable delay line is provided as a first clock input, the data signal is provided as first and second state-element input signals, and the clock signal is provided as a second clock input—. The multiplexing array may be further configured to optionally apply the following as a clock signal: (a) a positive clock signal; or (b) a negative clock signal which is an inverted positive clock signal.

[0105] Although the present disclosure has now been discussed in general terms, additional specific details will be considered again below.

[0106] Referring to FIG. 6, a waveform timing diagram for the operation of a die-to-die connectivity monitoring system over a measurement cycle is illustrated. A measurement cycle defines the activity of a block controller during a measurement time interval. Each measurement cycle includes a plurality of [K] delay line cycles. Each delay line cycle includes a plurality of (16 in the example) measurements, each having a different position of an adjustable delay line. The number of measurements per each delay line cycle may be 2 to 100 in a more general sense, or more specifically 2-10, 2-20, 2-30, 2-40, 2-50, 5-10, 5-20, 5-30, 5-40, 5-50, 10-20, 10-20, 10-30, 10-40, 10-50, 20-30, 20-40, 20-50, 30-40, 30-50, 40-50, or any other sub-range of 2 to 100. In other embodiments, the number of measurements per each delay line cycle may exceed 100.

[0107] The measurement cycle starts when a measurement command is sent to the block controller (prtn_tca_block_ctrl) and stops when a read cycle is executed. To perform a new measurement cycle, a new measurement command is sent. When the block controller receives the read command, the block controller will first disable the I / O sensor by setting the enable signal (ptrn_io_sensor_en) to a logic low level.

[0108] During each of the adjustable delay line cycles, the I / O sensor adjustable delay line is configured with each of its 16 positions, that is, the I / O sensor adjustable delay line changes from its minimum delay value to its maximum delay value. The time interval for staying at each position is defined by the "WIN" parameter. The WIN parameter can be configured as one of 8, 16, 32, and 64, and the time interval is equal to the WIN configuration multiplied by the PLL output time interval divided by the clock cycle time.

[0109] Referring to FIG. 7, a waveform timing diagram for the activation and reset of the I / O sensor according to FIG. 3 is illustrated. The time for setting the new delay line value is the sum of the following: the time taken for the block controller (prtn_tca_block_ctrl) to reset the fifth state element (FF5) controlling the sensor failure indicator signal (ptrn_io_sensor_fail); the time for setting the new delay line value (position of the adjustable delay line); and the guard band time. This is calculated as 8 cycles of the PLL split clock (1 GHz in this example) according to the following sequence: the first cycle [2] for setting the active-low asynchronous reset signal (ptrn_io_sensor_rst_n); and the 2 cycles to wait for the sensor failure indicator signal (ptrn_io_sensor_fail) to reset [4]. The delay line cycle length is as follows: [16 x WIN] + [32 x time for setting the new adjustable delay line value].

[0110] Referring to FIG. 8, a schematic block diagram of an I / O block controller forming part of an I / O block is shown. It includes a synchronizer; a first logic; a memory block; and a second logic. The third logic generates four configuration bits that constitute an enable signal (ptrn_io_sensor_en), an active-low asynchronous reset signal (ptrn_io_sensor_rst_n), and an adjustable delay line value (prtn_io_sensor_cfg[3:0]).

[0111] The synchronizer receives a 1-bit sensor failure indication signal (ptrn_io_sensor_fail) for each of the multiple (in this case, 44, [43:0]) different sensors, the PLL (1 GHz) clock signal, and the active-low asynchronous reset signal (ptrn_io_sensor_rst_n), and provides the synchronized sensor failure signal for each sensor (sensor_fail_sync[43:0]) to the first logic. Next, the first logic determines the minimum delay line position that causes the sensor failure and provides it to the memory block. The memory block must store the minimum delay line position that causes the sensor failure for each pin during the entire delay line cycle (16 delay line positions exercised by 16 WIN intervals). The second logic can be used to read from the memory block to the FC controller.

[0112] When the third logic (prtn_tca_block_ctrl) within the block controller receives the start_measure command, it first enables the I / O sensor by setting the enable signal (ptrn_io_sensor_en) to a logic high value. Then, it enables the measurement cycle.

[0113] Four data types are generated by the block controller for each I / O sensor (pin) to provide a total of 33 bits (or 31 bits depending on the count_length configuration). The first type is the lower minimum delay line position that causes sensor failure during the entire measurement cycle ([N] x delay line cycles), which requires 5 bits per I / O sensor (memory [4:0]). The second type is the upper minimum delay line position that causes sensor failure during the entire measurement cycle ([N] x delay line cycles), which requires 5 bits per IO sensor (memory [4:0]). The third type is a validity bit indicating that the lower minimum delay line position reading (Type 1) and the upper minimum delay line position reading (Type 2) correspond to an actual failure indication. Specifically, this bit indicates that the I / O-sensor output, i.e., the sensor failure indication signal (prtn_io_sensor_fail), was a logic low-level at least once during the measurement cycle.

[0114] Type 4 is the sum of the minimum delay line positions that cause sensor failure during each delay line cycle (one measurement cycle). This requires 14 bits (5+9) per I / O sensor when Count_length = 512, and 13 bits (5+8) per I / O sensor when Count_length = 256. Type 5 is the number of effective delay line cycles used in the sum of the minimum delay line values ​​(Count), which requires 9 bits per I / O sensor (maximum 512 counts). Types 4 and 5 are optional and depend on the Readout_mode, which can be configured as the following modes: a normal mode that reads 11 bits per I / O sensor (a total of 44 x 11 = 484 bits, approximately 61 bytes); Debug mode for Count_length = 512 to read 33 bits per I / O sensor (a total of 44 x 33 = 1452, approximately 181 bytes) or Count_length = 256 to read 31 bits per I / O sensor (a total of 44 x 31 = 1364, approximately 171 bytes).

[0115] During operation in WIN intervals, the block controller checks the sensor failure indicator signal (prtn_io_sensor_fail[43:0]) for each sensor. The signal is synchronized to the PLL split clock inside the block controller using a synchronizer. When the sensor failure indicator signal (prtn_io_sensor_fail) is a logic low value, the block controller stores the value of the delay line position executed during the WIN interval in Memory[x], but only if the delay line position is smaller than that stored in Memory[x].

[0116] The first 5 bits ([4:0]) of Memory[x] store the delay line position, and the 6th bit ([5]) of Memory[x] is the validity bit. The validity bit is set to a logic low value when the sensor failure indicator signal (prtn_io_sensor_fail) for the sensor ([x]) is detected as a logic low value for the first time. At the end of the delay line cycle, the memory for the sensor ([x]) will store the minimum delay line value corresponding to the margin of each pin.

[0117] The block controller (prtn_tca_block_controller) stores the minimum value of the adjustable delay line that causes failure in all delay line measurement cycles, as well as the maximum value between all minimum values ​​of the adjustable delay line that cause failure measured across all delay line measurement cycles. It will also store up to 512 delay line cycles, the sum of the measured minimum delay line values, and a count of how many measurement cycles were summed.

[0118] Communication between the block controller (prtn_tca_block_controller) and the I / O sensors within the block implements high fan-out (FO) connectivity. The propagation delay of these signals is defined to advantageously optimize test efficiency, that is, to optimize the active time of the test relative to the total test time.

[0119] To ensure optimal operation of the I / O sensor, the signals driving the I / O sensor must reach the I / O sensor input with a well-defined slope. Table 3 below defines the propagation time of each signal (between the block controller and the I / O sensor, optionally in both directions) and the signal slope (at the I / O sensor input).

[0120]

[0121] Referring further to the general concepts discussed above, the processing logic may be configured to repeatedly set an adjustable delay line for each of the multiple time periods and identify the minimum time period for each of the multiple measurement cycles. Then, the processing logic may be further configured to determine one or more of the following: the lowest minimum time period across the multiple measurement cycles; the highest minimum time period across the multiple measurement cycles; and the sum of the minimum time periods across the multiple measurement cycles.

[0122] Referring to FIG. 9, a schematic circuit diagram of a portion of the I / O block controller of FIG. 8 configured for Automatic Test Pattern Generation (ATPG) mode is shown. In particular, it includes two serial state elements (D flip-flops), both of which are clocked by a PLL clock (1 GHz), and the first state element has a constant logic high value (1'b1) as a data input and provides its output (Q) as a data input to the second state element. Both state elements have a central active low reset signal (prtn_rst_n) from the FC controller as a reset input, and this signal is also provided as a first input (for a logic low value) to the multiplexer. The output (Q) of the second state element is provided as a second input (for a logic low value) to the multiplexer.

[0123] Referring to FIG. 10, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring the degradation of a bidirectional or receive-only signal interconnection channel (lane) is illustrated. This implementation is used particularly in high bandwidth memory 3 (HBM3) semiconductor 3D IC packages. The interconnection signal channel has a near-end (NE) bump (connection, e.g., a soldered pin) and a far-end (FE) bump. The pads in the NE and FE have capacitance (schematically illustrated by a capacitor labeled as a C-pad). In the FE in the dynamic random access memory (DRAM) portion of the 3D IC in this example, a physical layer (Phy) transmit buffer receives an input (DQ[n]), which is received by an NE (pseudo) differential receive buffer (differential Rx buffer), which compares the received signal with a threshold voltage (VREF). The output of the NE differential receive buffer is provided as a data input to an I / O sensor that also receives a clock (clk). In a bidirectional channel, the main chip (MC) physical layer (Phy) transmitter also includes a transmit buffer (Tx buffer). The degradation of the transition gradient for the transmit signal (from gradient-input to gradient-output) is illustrated, which determines the margin. The receive buffer can alternatively be implemented as a CMOS receiver (or another type of receive buffer), in which case it is not necessary to receive the threshold voltage (VREF) or perform a comparison with it. This is applicable to other differential receive buffers disclosed below.

[0124] Referring to FIG. 11, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring the degradation of transmit-only signal interconnect channels (lanes) is shown, which is also particularly suitable for HBM3 3D IC packages. Features common to the features of FIG. 10 will not be described again for the sake of brevity. Two signal interconnect channels are shown, and each of the channels has a respective I / O sensor to which the output of the respective NE differential receive buffer for the channel is provided as a data input. In this mode of operation, there is no reference signal, such as a clock signal, that can be used as a comparison to measure a set or hold time. Accordingly, the output of the NE differential receive buffer for the other channel is provided to the respective I / O sensor as a clock input. This means that each I / O sensor measures the set or hold time between signals from adjacent pins or lanes. In other words, each pin is used as a reference signal for an adjacent pin.

[0125] For example, the reference for the first lane receiver output (Rx[0]) is a delayed version of the second lane receiver output (Rx[1]). The delay is given by △T. In this case, the data signal for the first lane I / O sensor is Rx[0] and the clock signal is Rx[1] + △T. The set time is measured by the I / O sensor as the time difference (delta) between Rx[1] + △T and Rx[0]. Degradation of either of the signals (Rx[0] or Rx[1]) will cause a change in the set time to be detected by the sensor. Therefore, this is sensitive to changes in transmit buffer strength and NE bump resistance. △T is set to ensure that at least one of the following conditions is maintained, taking into account the total skew of Rx[0] to Rx[1]: I / O sensor intrinsic delay (IO_Sensor int_Delay) ≤ Setup_time[0] ≤ IO sensor maximum setting window; and I / O sensor inherent delay ≤ Setup_time[1] ≤ I / O sensor maximum setting window.

[0126] Referring to Fig. 12, waveform timings for three scenarios in the degradation monitoring of transmit-only signal interconnection channels are illustrated. In each case, △T is 1.5 x IO_Sensor int_Delay It is set as such. The initial timing relationship is determined by random variation of the receivers and by data alignment (D[0] to D[1]). Timing scenarios are used to determine △T for appropriate operation under timing skew from the first lane to the second lane. In the first scenario (a), the timing for the first lane is the same as for the second lane (i.e., Rx[0] = Rx[1]), in the second scenario (b), the timing for the first lane is before the second lane (e.g., Rx[0] - Rx[1] ≥ -20 ps), and in the third scenario (c), the timing for the first lane is after the second lane (i.e., Rx[0] - Rx[1] ≤ 20 ps).

[0127] Referring to FIG. 13, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring the degradation of differential interconnect receiving channels (lanes) is shown, which is also particularly suitable for HBM3 3D IC packages. Features common to those of FIG. 10 and FIG. 11 will not be described again for the sake of brevity. With respect to the transmit-only lanes, there is no reference signal such as a clock, and therefore, two single-ended signals (Rx_c & Rx_t) are used as references to each other after being delayed by △T (in the same manner as in the transmit-only case). The first single-ended signal (Rx_c) is generated by comparing a signal received from one side of the differential channel with a threshold voltage (VREF), and the second single-ended signal (Rx_t) is generated by comparing a signal received from the other side of the differential channel with a threshold voltage (VREF). Degradation of one of the signals will be detected by the I / O sensor (assuming that degradation does not occur simultaneously for both signals). This can be used for continuous measurements of clock or strobe symmetry (Rx_c-rise to Rx_t-rise).

[0128] Referring to FIG. 14, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring the degradation of differential interconnect transmission channels (lanes) is shown, which is also particularly suitable for HBM3 3D IC packages. It shows a transmitting strobe using a differential transmit buffer that receives a data input (D_in) and provides differential transmit outputs (cn, cp). The differential transmit outputs are each provided to respective (pseudo)_ differential receive buffers (which, as previously mentioned, can be implemented with alternative types of receive buffers) that provide data outputs (Rx_c, Rx_t), respectively. The figure also shows how a single I / O sensor and multiplex array for the Rx_c and Rx_t signals can be used instead of two I / O sensors. This can also be used to monitor the degradation of differential interconnect receiving channels instead of the arrangement of FIG. 13, or to monitor the degradation of multiple transmit-only signal interconnect channels (lanes) instead of the arrangement shown in FIG. 11.

[0129] Returning to the general concept discussed above, an I / O block for a semiconductor IC may be considered (and may be combined with any other embodiments disclosed herein). The I / O block includes a receiving buffer configured to receive a voltage signal from an interconnected portion of the semiconductor IC and provide a receiving buffer output; and an I / O sensor as disclosed herein. The receiving buffer output (which may indicate a logic level) may be provided as a data signal input to a delay circuit of the I / O sensor. The receiving buffer may be a differential (or pseudo-differential) receiving buffer and may be further configured to compare the received voltage signal with a voltage threshold input and provide a receiving buffer output based on the comparison.

[0130] The I / O sensor is advantageously further configured to receive a clock signal input (which may be used in various ways as discussed elsewhere in this specification). In some embodiments, a clock signal associated with a received voltage signal may be provided as a clock signal input. This may be used for bidirectional measurement and / or monitoring, or may receive only pins or lanes.

[0131] In some implementations, the (differential) receive buffer is a first (differential) receive buffer and is configured to receive a first voltage signal from a first interconnected portion of the semiconductor IC and provide a first receive buffer output. Then, the I / O block may further include a second (differential) receive buffer configured to receive a second voltage signal from a second interconnected portion of the semiconductor IC, optionally compare the received second voltage signal with a voltage threshold input, and, if appropriate based on the comparison, provide a second receive buffer output. In this case, a second receive buffer output with a (fixed or adjustable) delay applied may be provided as a clock signal input. This may be used for transmit-only or for measuring and / or monitoring differential pins or lanes. For example, the first and second interconnected portions of the semiconductor IC may form a differential channel (however, in other embodiments, they may simply be physically and / or logically adjacent).

[0132] In certain embodiments, the I / O sensor is a first I / O sensor, and the clock signal input is a first clock signal input. Then, the I / O block further includes a second I / O sensor as disclosed herein, and a second receive buffer output is provided as a data signal input to a delay circuit. The second I / O sensor may be further configured to receive a second clock signal input. Then, a first receive buffer output with a (fixed or adjustable) delay applied may be provided as a second clock signal input.

[0133] In other embodiments, a single I / O sensor may be used to measure the margin. Then, the I / O block further comprises a multiplexing array, and the multiplexing array is configured to optionally apply: (a) a first receive buffer output as a data signal input to the I / O sensor and a second receive buffer output to which a delay is applied as a clock signal input to the I / O sensor; or (b) a second receive buffer output as a data signal input to the I / O sensor and a first receive buffer output to which a delay is applied as a clock signal input to the I / O sensor.

[0134] Optionally, a mechanism for maintaining the output of the fifth state element (FF5), which indicates a sensor failure signal (ptrn_io_sensor_fail), may be masked. This option may be used to avoid locking the sensor failure signal in situations where the data and / or clock are unstable (the time interval for instability may be defined by the protocol). This may be accomplished by adding a control signal to enable sampling by the fifth state element (FF5), for example, by controlling the reset or data input of the fifth state element (FF5).

[0135] In a general sense, an I / O sensor or die-to-die connectivity monitoring system physically residing (embedded) within a single IC of a multi-IC module is provided herein; or multiple such sensors / systems may be physically residing within multiple ICs of a multi-IC module, one for each IC, or even multiple for each IC. Such sensors / systems may be beneficial to any interconnected portion of any IC within the multi-IC module.

[0136] Throughout the present disclosure, various embodiments may be presented in the form of ranges. It should be understood that descriptions in the form of ranges are for convenience and brevity only and should not be interpreted as inflexible limitations on the scope of the invention. Accordingly, descriptions of ranges should be considered as specifically disclosing individual numerical values ​​within the range as well as all possible sub-ranges. For example, a description of a range such as 1 to 6 should be considered as having specifically disclosed sub-ranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numerical values ​​within the range, e.g., 1, 2, 3, 4, 5, and 6. This applies regardless of the width of the range.

[0137] Whenever a numerical range is indicated in this specification, it is intended to include any cited number (fraction or integer) within the indicated range. The phrases “range / ranges” between the first indicated number and the second indicated number, and the phrase “range / ranges” of the first indicated number “to” the second indicated number, are used interchangeably in this specification and are intended to include the first and second indicated numbers and all fractions and integers between them.

[0138] In the description and claims of this disclosure, the words “comprise,” “include,” and “have,” and their forms, are not necessarily limited to the members in the list to which these words may be associated. Additionally, in the event of any discrepancy between this application and any document incorporated by reference, this application is intended to take precedence.

[0139] To clarify the references in this disclosure, it should be noted that the use of nouns as common nouns, appropriate nouns, named nouns, etc., is not intended to imply that the embodiments of the invention are limited to a single embodiment, and that while many configurations of the disclosed components may be used to describe some embodiments of the invention, other configurations may be derived from these embodiments in different configurations.

[0140] For clarity, not all routine features of the implementations described herein are illustrated or described. Of course, it should be understood that in the development of any such actual implementation, a number of implementation-specific decisions must be made to achieve specific developer goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from implementation to implementation and from developer to developer. Furthermore, it will be understood that while such development efforts may be complex and time-consuming, they will nevertheless be routine engineering work for those skilled in the art who benefit from this disclosure.

[0141] Based on the teachings of the present disclosure, it is expected that a person skilled in the art will be able to easily practice the present invention. The descriptions of the various embodiments provided herein are considered to provide sufficient insight and details of the invention to enable a person skilled in the art to practice the invention. Furthermore, the various features and embodiments of the invention described above are specifically considered to be used not only alone but also in various combinations.

[0142] Conventional and / or modern circuit design and layout tools may be used to implement the present invention. The specific embodiments described herein, in particular the various circuit arrangements, measurements, and data flows, are illustrative of exemplary embodiments and should not be considered to limit the present invention to these specific implementation choices. Accordingly, multiple instances may be provided as a single instance for the components described herein. The determination of margins and / or other parameters may be made, for example, at different parts of the configuration. Eye parameters of types other than eye width may be determined using margin measurements. In practice, in some cases, eye parameters do not need to be calculated at all. Optionally, the IO-sensor may be extended to simultaneously measure two aspects of the data eye by implementing a second delay line for the clock signal.

[0143] While circuits and physical structures are generally assumed, it is well known that in modern semiconductor design and manufacturing, physical structures and circuits can be implemented in computer-readable technical forms suitable for use in subsequent design, test, or manufacturing stages as well as in the resulting manufactured semiconductor integrated circuits. Accordingly, claims relating to traditional circuits or structures, in accordance with their particular language, may read computer-readable encodings (which may be referred to as programs) and their representations, whether implemented in a medium or combined with suitable reader facilities, to allow for the manufacturing, testing, or design improvement of the corresponding circuits and / or structures. Structures and functions presented as distinct components in exemplary configurations may be implemented as combined structures or components. The present invention is considered to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all of which are described herein and defined in the appended claims. As used in this specification, a computer-readable medium includes at least a disk, tape, or other non-transient magnetic, optical, or semiconductor (e.g., flash memory card, ROM) medium.

[0144] The foregoing detailed description describes only some of the many possible embodiments of the present invention. For this reason, such detailed description is intended as an example rather than a limitation. Variations and modifications of the embodiments disclosed herein may be made based on the description provided herein without departing from the scope and spirit of the invention. The following claims, which include all equivalents, are intended to define the scope of the invention. In particular, although the principal embodiments are described in the context of 3D ICs, the teachings of the present invention are considered advantageous for use with other types of semiconductor ICs utilizing I / O circuits. Furthermore, the techniques described herein may also be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may be within the scope of the present invention as defined in the following claims.

[0145] Embodiments of the present invention may be used to manufacture, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0146] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks within the flowcharts and / or block diagrams, may be implemented by computer-readable program instructions.

[0147] The flowcharts and block diagrams in the drawings illustrate the architecture, function, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions comprising one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions mentioned in the blocks may occur differently from the order mentioned in the drawings. For example, two blocks depicted consecutively may, in fact, be executed substantially simultaneously depending on the accompanying function, or the blocks may sometimes be executed in reverse order. It should also be noted that each exemplary block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts examples, may be implemented by special-purpose hardware-based systems that perform the specified functions or operations or perform combinations of special-purpose hardware and computer instructions.

[0148] The descriptions of various embodiments of the present invention are provided for illustrative purposes but are not intended to be comprehensive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best describe the principles of the embodiments, actual applications, or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

Claim 1 A multi-IC (integrated circuit) module comprising: a first IC including a transmitter; and a second IC interconnected to the first IC via an interconnect lane, wherein the second IC comprises a receiver, a delay circuit including an adjustable delay line—the adjustable delay line being configured to receive a data signal transmitted by the transmitter of the second IC via the interconnect lane from the receiver—and processing logic, wherein the processing logic is configured to delay the data signal until a failure condition is detected by setting the adjustable delay line to a plurality of time periods, and to determine the reliability of connectivity between the first IC and the second IC based on the detection of the failure condition. Claim 2 A multi-IC module according to claim 1, wherein the processing logic is additionally configured to repair the interconnection lane in response to the reliability of the determined connectivity. Claim 3 A multi-IC module according to claim 1, wherein the processing logic is further configured to adjust at least one of the data throughput and clock rate of the multi-IC module in response to the reliability of the determined connectivity. Claim 4 A multi-IC module according to claim 1, wherein the first IC and the second IC are interconnected using at least one of (a) bumps; (b) micro-bumps; (c) pins; (d) through-silicon vias (TSVs) (e) through-integrated fan-out vias (RDL) and TIVs; and (f) pads. Claim 5 A multi-IC module according to claim 4, wherein the determination of the reliability of the connectivity comprises determining at least one resistance parameter among (a) to (f). Claim 6 In paragraph 4, a multi-IC module in which the reliability of the connectivity is affected by at least one of (a) to (f). Claim 7 A multi-IC module according to claim 1, wherein the determination of the reliability of the connectivity includes determining a systemic influence parameter. Claim 8 A multi-IC module according to claim 1, wherein the determination of the reliability of the connectivity includes determining a parameter representing the symmetry of differential signals. Claim 9 A multi-IC module according to claim 1, wherein the determination of the reliability of the connectivity includes determining the clock duty cycle effects on the eye width. Claim 10 A multi-IC module according to claim 1, wherein the reliability of the connectivity is affected by an open circuit. Claim 11 A multi-IC module in which the reliability of the connectivity is affected by a short circuit in claim 1. Claim 12 In claim 1, a multi-IC module in which the reliability of the connectivity is affected by a bridge short circuit. Claim 13 A multi-IC module according to claim 1, wherein the processing logic is further configured to measure a margin based on the minimum delay that caused the failure condition. Claim 14 A multi-IC module according to claim 1, wherein the processing logic is additionally configured to determine the sum of the minimum time periods that caused the failure condition. Claim 15 A multi-IC module according to claim 1, wherein the processing logic is further configured to measure the margin of the data signal based on the detection of the failure condition. Claim 16 A multi-IC module according to claim 15, wherein the margin measurement comprises at least one of a data signal setting time to a clock rising edge; a data signal setting time to a clock falling edge; a data signal holding time to a clock rising edge; and a data signal holding time to a clock falling edge. Claim 17 In claim 1, the delay circuit comprises: a first state element configured to receive a first state element input signal and provide a first state element output based on the first state element input signal and a first clock input; a second state element configured to receive a second state element input signal and provide a second state element output based on the second state element input signal and a second clock input; and further comprises a multiplexing array, wherein the multiplexing array comprises a data signal as an input signal for the adjustable delay line—the output of the adjustable delay line is provided as the first state element input signal, the data signal is provided as the second state element input signal, and the clock signal is provided as the first and second clock inputs—; A multi-IC module configured to selectively apply one of the following: a clock signal as an input signal for the adjustable delay line—the output of the adjustable delay line is provided as the first clock input, the data signal is provided as the first and second state-element input signals, and the clock signal is provided as the second clock input. Claim 18 In claim 17, the multiplexing array is further configured to selectively apply a positive clock signal; or a negative clock signal which is an inverted positive clock signal as the clock signal, a multi-IC module. Claim 19 A multi-IC module according to any one of claims 1 to 18, wherein the first IC and the second IC are different dies integrated and packaged together and configured to cooperate to achieve combined functionality. Claim 20 A computer-readable storage medium comprising a computer-readable encoding of a multi-IC module according to any one of claims 1 to 18. Claim 21 delete

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