3D packaging using a silicon die as a heat sink for high-power, low-thermal-conductivity dies

Abstract

The present disclosure relates to a three-dimensional (3D) package having a die-on-die configuration and comprising a first die and at least one second die disposed below the first die. The first die comprises a back-end-of-line (BEOL) portion, a device region above the BEOL portion, a substrate above the device region, and a substrate tie structure extending through the device region and at least into the substrate. The substrate and the substrate tie structure each have a thermal conductivity greater than 50 W / mK. At least one second die is configured to be coupled to the BEOL portion of the first die so that heat generated by the second die can propagate through the BEOL portion and the substrate tie structure and be released outside the first substrate.

Description

Technology Field

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 124,450 filed on December 11, 2021, the entire disclosure of which is incorporated herein by reference.

[0003] Technology field

[0004] The present disclosure relates to a three-dimensional (3D) package, and more specifically, to a 3D package having a die-on-die configuration, wherein a silicon die is used as one or more high-power, low-thermal-conductivity die heat sinks. Background Technology

[0005] Many radio frequency (RF) applications, such as base stations or mobile terminals with mmWave front-ends, involve very large power dissipation that requires special heat extraction elements. Typically, this large power dissipation is primarily generated by single-channel or multi-channel power amplifier dies implemented with low thermal conductivity materials. Metal heat sinks are frequently used when there is significant volume and height (e.g., several millimeters) that can be allocated to the heat extraction element. However, a relatively large vertical distance between the metal heat sink and the power amplifier die can still result in relatively high die temperatures.

[0006] Meanwhile, due to the popularity of portable electronic devices such as smartphones and tablet computers, the height and thickness of these devices have become important. In many cases, the height requirements of portable electronic devices will not allow for the use of metal heat sinks.

[0007] Accordingly, the object of the present disclosure is to provide an improved package design having enhanced thermal performance and reduced package size / height without expensive and complex processes to accommodate low-profile requirements for portable products and to create an efficient (relatively short) low thermal resistance path for high-power, low-thermal-conductivity dies.

[0008] The present disclosure describes a three-dimensional (3D) package having a silicon die as a heat sink for one or more high-power, low-thermal-conductivity dies. The disclosed 3D package comprises a first die and at least one second die disposed below the first die. The first die comprises a back-end-of-line (BEOL) portion, a first device region above the BEOL portion, a first substrate above the first device region, and a substrate tie structure extending through the first device region and extending at least into the first substrate. Herein, the first substrate has a thermal conductivity higher than 100 W / mK, and the substrate tie structure has a thermal conductivity higher than 50 W / mK. The second die comprises a second device region and a second substrate disposed below the second device region, having a thermal conductivity lower than that of the first substrate. The second device region is configured to be coupled to the BEOL portion of the first die, so that heat generated by the second device region can propagate through the BEOL portion and the substrate tie structure and is released out of the first substrate.

[0009] In one embodiment of the 3D package, the first device region includes one or more active sections configured to provide one or more electrical device components. A substrate tie structure is laterally offset from one or more active sections.

[0010] In one embodiment of the 3D package, the first die further includes a dielectric layer between the first device region and the first substrate. The substrate tie structure extends through the first device region and the dielectric layer, and extends at least into the first substrate.

[0011] In one embodiment of the 3D package, the dielectric layer of the first die is formed of silicon oxide or silicon nitride.

[0012] In one embodiment of the 3D package, the first substrate is in contact with a first device region that has no dielectric layer between them.

[0013] In one embodiment of the 3D package, the substrate tie structure is positioned vertically aligned with the second die.

[0014] In one embodiment of the 3D package, the first substrate is formed of silicon.

[0015] In one embodiment of the 3D package, the second device region is configured to provide one or more electrical device components comprising one or more of gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), gallium phosphide (GaP), gallium carbon (GaC), gallium, indium gallium arsenide (InGaAs), indium gallium nitride (InGaN), indium gallium phosphide (InGaP), and indium gallium carbide (InGaC). The second substrate is formed of GaAs, GaN, GaP, or GaC.

[0016] In one embodiment of the 3D package, the second device region is configured to provide one or more heterojunction bipolar transistors (HBT), one or more amorphous high-electron mobility transistors (pHEMT), and / or one or more field-effect transistors (FET).

[0017] In one embodiment of the 3D package, the substrate tie structure has one of a grid array configuration, a multi-ring configuration, and a fish-bone configuration.

[0018] In one embodiment of the 3D package, the substrate tie structure comprises at least one of a doped semiconductor, a metal powder, a plated metal, and a metal compound.

[0019] According to one embodiment, the 3D package further includes a plurality of bump structures. The bump structures are formed on the bottom of the BEOL portion of the first die and surround the second die. Each bump structure has the same height and is higher than the second die. The BEOL portion of the first die includes a plurality of connection structures, wherein a specific structure among the bump structures is connected to a second device area of ​​the second die through the corresponding structure among the connection structures.

[0020] In one embodiment of the 3D package, the bump structure is a plurality of copper pillars or a plurality of solder balls.

[0021] In one embodiment of the 3D package, a specific structure among the connection structures is coupled to a second device region of the second die and extends through the BEOL portion of the first die, wherein a specific structure among the connection structures contacts a substrate tie structure within the first die.

[0022] In one embodiment of the 3D package, a specific structure among the connection structures is shaped to fit the configuration of the substrate tie structure.

[0023] According to one embodiment, the 3D package further includes an antenna module that is placed under the second die and connected to a bump structure.

[0024] According to one embodiment, the 3D package further comprises a mold compound and a heat sink. The mold compound covers the side of the first die and extends vertically past the upper surface of the first die. The heat sink is deposited on the upper surface of the first die and embedded in the mold compound.

[0025] According to one embodiment, the 3D package further includes a mold compound that fills the gap between the first die and the antenna module, and the second die and the bump structure are encapsulated by the mold compound.

[0026] In one embodiment of the 3D package, the outer edge of the substrate tie structure covers at least substantially the horizontal area of ​​the second die.

[0027] In one embodiment of the 3D package, the first substrate further includes a doped substrate region. Here, the substrate tie structure is located immediately below the doped substrate region or extends into the doped substrate region. The doped substrate region has higher thermal conductivity than other parts of the first substrate.

[0028] In one embodiment of the 3D package, the doped substrate region has a thickness of tens of micrometers to 500 micrometers and is sized to substantially cover the outer edge of the substrate tie structure in a horizontal plane.

[0029] In one embodiment of the 3D package, the substrate tie structure within the first die extends through the first device region and through the first substrate.

[0030] In one embodiment of the 3D package, the substrate tie structure is hollow.

[0031] According to one embodiment, the 3D package further includes a plurality of dies disposed below a first die. Herein, the second die is one of the plurality of dies, and the plurality of dies are configured in such a way that heat generated by these dies can be released outside the first substrate.

[0032] In one embodiment of the 3D package, the first die includes a plurality of substrate tie structures, each substrate tie structure being vertically aligned with a corresponding one of the plurality of dies.

[0033] According to one embodiment, the 3D package further includes a plurality of bump structures. Here, the bump structures are formed at the bottom of the BEOL portion of the first die and surround the plurality of dies. Each bump structure has the same height and is higher than each of the plurality of dies. A specific structure among the bump structures is connected to a specific die among the plurality of dies.

[0034] According to one embodiment, the 3D package further includes an antenna module that is placed under a plurality of dies and connected to a bump structure.

[0035] According to one embodiment, the 3D package further includes a mold compound that fills the gap between the first die and the antenna module, and a plurality of dies and bump structures are encapsulated by the mold compound.

[0036] According to one embodiment, the 3D package further includes a printed circuit board (PCB) module placed on a first die. Herein, the first die further includes a plurality of devices through a structure configured to connect the PCB module to a specific die among a plurality of dies through a connection structure of the BEOL portion of the first die, and configured to connect the PCB module to an antenna module through a specific structure among the bump structures.

[0037] In other embodiments, any one of the aforementioned embodiments, and / or various separate embodiments and features as described herein, may be combined individually or together for additional advantage. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements unless otherwise indicated herein.

[0038] Those skilled in the art will understand the scope of this disclosure and will realize additional aspects thereof after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Brief explanation of the drawing

[0039] The accompanying drawings included in and forming part of this specification illustrate various aspects of the present disclosure and serve to explain the principles of the present disclosure together with this description. FIG. 1 illustrates an exemplary three-dimensional (3D) assembly including a high-power low-thermal-conductivity die and a heat sink die according to one embodiment of the present disclosure. FIGS. 2a to 2c illustrate exemplary configurations of a substrate tie structure configured to improve the thermal conductivity of a heat dissipation path from a high-power, low-thermal-conductivity die to a heat sink die. FIGS. 3 to 5 illustrate an alternative die-on-die 3D assembly according to one embodiment of the present disclosure. FIGS. 6A and 6B illustrate in 3D an exemplary 3D package including the die-on-die 3D assembly illustrated in FIG. 1. FIG. 7 illustrates an alternative exemplary 3D package including the alternative die-on-die 3D assembly shown in FIG. 2. FIG. 8 illustrates a top view of an alternative 3D package comprising a plurality of high-power low-thermal-conductivity dies and one heat sink die according to one embodiment of the present disclosure. FIGS. 9a to 9c illustrate cross-sectional views of the 3D package shown in FIG. 8. For the sake of clarity, it will be understood that Figures 1 through 9c may not be drawn to scale. Specific details for implementing the invention

[0040] The embodiments described below provide information necessary to enable a person skilled in the art to perform the embodiments and to exemplify the best mode of carrying out the embodiments. By reading the following description in light of the accompanying drawings, a person skilled in the art will understand the concepts of the present disclosure and recognize the applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0041] Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements are not to be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0042] If an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it will be understood that this may be directly on or extending directly onto another element, or that intervening elements may also exist. In contrast, if an element is referred to as extending "directly" on or "directly onto" another element, no intervening elements exist. Likewise, if an element such as a layer, region, or substrate is referred to as being "on" or extending "up" another element, it will be understood that this may be directly on or extending directly onto another element, or that intervening elements may also exist. In contrast, if an element is referred to as extending "directly" on or "directly up" another element, no intervening elements exist. Furthermore, if an element is referred to as being "connected" or "joined" to another element, it will be understood that it may be directly connected or joined to another element, or that intervening elements exist. In contrast, if an element is referred to as being "directly connected" or "directly joined" to another element, no intervening elements exist.

[0043] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. These terms and those discussed above are to be understood as intended to include different orientations of the device in addition to the orientations shown in the drawings.

[0044] The terms used herein are merely for describing specific embodiments and are not intended to limit the disclosure. As used herein, the singular forms “one,” “one,” and “a specific one” are intended to also include the plural forms unless otherwise indicated in the context. As used herein, the terms “include,” “include,” “include,” and / or “included” specify the presence of the mentioned feature, integer, step, operation, element, and / or component, but it will also be understood that they do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. Terms used herein should be interpreted as having meanings consistent with their meanings in the context of this specification and related technology, and should be further understood that they should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0046] Examples are described herein with reference to schematic drawings of the examples of the present disclosure. As such, the actual dimensions of layers and elements may vary, and variations from the shapes in the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, areas illustrated or described as square or rectangular may have rounded or curved features, and areas depicted as straight may have some irregularities. Accordingly, the areas shown in the drawings are schematic, and their shapes are not intended to illustrate the exact shapes of the areas of the device, nor are they intended to limit the scope of the present disclosure. Furthermore, the size of a structure or area may be exaggerated relative to another structure or area for illustrative purposes and is provided to illustrate the general structure of the subject matter; it may or may not be drawn to scale. Common elements between drawings may be indicated herein by common element numbers and may not be described again subsequently.

[0047] The present disclosure relates to a three-dimensional (3D) package having enhanced heat dissipation performance and complying with low profile requirements. FIG. 1 illustrates an exemplary 3D die-on-die assembly (10) that can be stacked in a 3D package (more details of the 3D package described below) according to one embodiment of the present disclosure. For the purposes of this example, the 3D die-on-die assembly (10) comprises a first die (12) having a first substrate (14) having relatively high thermal conductivity, and a second die (16) disposed below the first die (12), wherein the first die (12) is configured to provide electrical functions and is also configured as a heat sink for the second die (16). In other applications, the 3D die-on-die assembly (10) may comprise a plurality of second dies (16) disposed below the first die (12), and the first die (12) may be utilized as a heat sink.

[0048] In detail, the first die (12) comprises a back-end-of-line (BEOL) portion (18) on which a second die (16) is formed, a first device region (20) on the BEOL portion (18), a dielectric layer (22) on the first device region (20), a first substrate (14) on the dielectric layer (22), and a substrate tie structure (24) extending through the first device region (20) and the dielectric layer (22) and extending into the first substrate (14). The BEOL portion (18), configured to connect the first device region (20) to an external component (e.g., configured to accommodate the second die (16)), comprises a plurality of connection structures (26) (only two connection structures (26) are shown herein for simplification) and an interlayer dielectric (28). The connection structures (26) may be formed of a metal / alloy material such as copper. A portion of the connection structure (26) (for internal connection) is completely encapsulated by an interlayer dielectric (28) (not shown), while a portion of the connection structure (26) has a bottom portion not covered by the interlayer dielectric (28) for external connection.

[0049] The first device region (20) may be a front-end-of-line (FEOL) portion and may include one or more active sections (21) configured to provide one or more electrical device components such as a switched field-effect transistor (FET), a diode, a capacitor, a resistor, and / or an inductor (not shown). The dielectric layer (22) on the first device region (20) may be formed of silicon oxide, silicon nitride, or other compounds having a relatively low thermal conductivity of 10 W / mK or less (typical silicon dioxide has a thermal conductivity of about 0.03 W / mK). The first substrate (14) on the dielectric layer (22) may be formed of silicon or other semiconductor materials having good thermal conductivity higher than 100 W / mK, close to the thermal conductivity of many metals (e.g., zinc = 123 W / mK). The metals with the best thermal conductivity are copper (about 400 W / mK) and gold (about 300 W / mK). For example, the first die (12) can be formed from a silicon-on-insulator (SOI) wafer or a silicon-on-sapphire (SOS) wafer.

[0050] The first substrate (14) (e.g., a silicon substrate) provides heat dissipation capabilities, but the first substrate (14) is isolated from the device region (20) (which generates heat) and the BEOL portion (18) (which propagates heat from the second die (16), details to be described later) by a dielectric layer (22) which may have low thermal conductivity (less than 10 W / mK and, in most cases, less than a few W / mK). In this way, the dielectric layer (22) can limit heat dissipation through the first substrate (14). A substrate tie structure (24) extending from the upper surface of the BEOL portion (18) into the first substrate (14) through the first device region (20) and the dielectric layer (22) is introduced to improve the heat dissipation efficiency of the heat path from the BEOL portion (18) to the first substrate (14). In one embodiment, if the dielectric layer (22) is a very thin layer, it may provide good electrical insulation, but may not in terms of equivalent thermal resistance.

[0051] In some applications, the dielectric layer (22) may not exist on the first die (12) so that the first substrate (14) is directly above the first device region (20) (not shown). For example, the first die (12) may be formed by a bulk semiconductor process. Here, the substrate tie structure (24) may still exist and may extend into the first substrate (14) (not shown) through the first device region (20) from the upper surface of the BEOL portion (18).

[0052] The BEOL portion (18) has a thickness of several micrometers when the connection structure (26) is distributed in a small number of metal layers (e.g., 2, 3, 4 metal layers) or several tens of micrometers when the connection structure (26) is distributed in a large number of metal layers (e.g., 8, 10, 13, 16 metal layers). The first device region (20) has a thickness of several tens or hundreds of nanometers to several micrometers depending on the manufacturing process. The dielectric layer (22), if present, has a thickness of 100 nanometers (or even lower) to 1 or several micrometers. The first substrate has a thickness of 20 micrometers to 450 micrometers. To penetrate the first device region (20) and the dielectric layer (22), the substrate tie structure (24) needs to have a height greater than, for example, a combination of thicknesses of several hundred micrometers to several micrometers or several tens of micrometers of the first device region (20) and the dielectric layer (22). In the case where the dielectric layer (22) is omitted, the substrate tie structure (24) needs to have a height greater than the thickness of the first device region (20).

[0053] The substrate tie structure (24) may comprise a high thermal conductivity material, such as doped silicon or metal powder or compound, having a thermal conductivity of more than 50 W / mK (e.g., a typical value is about 100 W / mK). It is noted that since the first device region (20) includes one or more active sections (21) configured to provide an electrical device component and the substrate tie structure (24) penetrates the first device region (20), it is preferable that the substrate tie structure (24) be laterally offset from the active section (21).

[0054] The second die (16) includes a second substrate (30), a second device region (32) on the second substrate (30), and a plurality of die contacts (34) on the upper part of the second device region (32) (only two die contacts (34) are shown here for simplification). Typically, the second die (16) has a much smaller size (at least in the horizontal plane) compared to the first die (12). However, the second die (16), particularly the second device region (32), will generate a much higher thermal volume than the first die (12).

[0055] The second device region (32) may be configured to provide one or more high-power device components, such as a heterojunction bipolar transistor (HBT), an amorphous high-electron mobility transistor (pHEMT), and / or one or more field-effect transistors (FETs). These high-power device components may be realized in a III to V process using, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), gallium phosphide (GaP), gallium carbon (GaC), gallium, indium gallium arsenide (InGaAs), indium gallium nitride (InGaN), indium gallium phosphide (InGaP), indium gallium carbide (InGaC), etc. Meanwhile, the second substrate (30) for the high-power second device region (32) is typically formed of a low thermal conductivity material (e.g., GaAs, GaN, InN, or GaC) having a thermal conductivity of 70 W / mK or less (e.g., GaAs 32 W / mK, InN 45 W / mK, InP 68 W / mK at 300K, thermal conductivity varies with temperature). Typically, the thermal conductivity of the second substrate (30) is several times lower than that of the first substrate (14) in the first die (12) (e.g., silicon or doped silicon with much higher thermal conductivity, closer to metal). Therefore, heat generated by the second device region (32) may not be effectively dissipated through the second substrate (30).

[0056] Here, the second die (16) is deposited under the first die (12) via an attachment material (36) (e.g., solder or other compounds, or alternatively any metal bonding technique), and the die contact (34) above the second device region (32) is thermally and electrically connected to the exposed bottom portion of the connection structure (26) in the BEOL portion (18) of the first die (12) via the attachment material (36). Consequently, heat generated by the second device region (32) can be propagated through the BEOL portion (18) (e.g., mainly through the connection structure (26)) and the substrate tie structure (24), and can finally be released from the first substrate (14). For superior thermal performance, it is preferable that the substrate tie structure (24) be positioned vertically aligned with the second die (16) to provide the shortest thermal path from the second device area (32) to the first substrate (14) (through the BEOL portion (18) and the substrate tie structure (24). Typically, the outer edge of the substrate tie structure (24) covers at least substantially the horizontal area of ​​the second die (16).

[0057] Additionally, the 3D die-on-die assembly (10) may further include a plurality of bump structures (38) formed on the bottom of the first die (12) (i.e., the bottom of the BEOL portion (18)) and surrounding the second die (16). The bump structures (38) may be electrically connected to the second device region (32) of the second die (16) through a connection structure (26) within the BEOL portion (18) of the first die (12), and may be electrically connected to the first device region (20) of the first die (12) through some other connection structure (not shown). The bump structures (38) may be copper pillars or solder balls (see FIG. 2).

[0058] In the second die (16), the second substrate (30) has a thickness of several / tens of micrometers (in extreme cases) to 150 to 200 micrometers, or even up to the natural thickness of the wafer (hundreds of micrometers). The second device region (32) has a thickness of several tens or hundreds of nanometers to several micrometers, depending on the manufacturing process. Since the second die may have low thermal conductivity, its thickness is determined solely by the mechanical strength for the assembly. In many cases, the second die (16) (i.e., the second substrate (30)) is thinned to fit together with the bump structure (38) of the 3D die-on-die assembly (10). Here, each bump structure (38) has the same height and is taller than the second die (16) to meet additional packaging requirements (more details are described below).

[0059] FIGS. 2a through 2c illustrate top views of exemplary configurations of a substrate tie structure (24). The substrate tie structure (24) may have a grid array configuration (illustrated in FIG. 2a), a multi-ring configuration (illustrated in FIG. 2b), and a fish-bone configuration (illustrated in FIG. 2c). However, the configuration of the substrate tie structure (24) is not limited to these exemplary configurations.

[0060] In some applications, to further increase the thermal conductivity of the thermal path between the high-power second die (16) and the first substrate (14) of the first die (12), as illustrated in FIG. 3, a specific structure of the connection structure (26) coupled to the second die (16) (i.e., the second device region (32)) may be extended through the BEOL portion (18) of the first die (12) (i.e., through the interlayer dielectric (28) of the BEOL portion (18). Here, the connection structure (26) is connected to the die contact (34) of the second die (16) through an attachment material (36) and is directly connected to the substrate tie structure (24) within the first die (12). The connection structure (26) may be shaped to conform to the configuration of the substrate tie structure (24). Since the connection structure (26) is formed of a metal / alloy material and the substrate tie structure (24) is directly connected to the second die (16), the thermal conductivity of the thermal path between the second die (16) and the first substrate (14) is further improved. In FIG. 3, the bump structure (38) is shown as a BGA, which is still higher than the second die (16).

[0061] In some applications, as illustrated in FIG. 4, the first substrate (14) of the first die (12) may include a doped substrate region (40) on the substrate tie structure (24). The doped substrate region (40) may include one or more doper materials, e.g., boron, indium, gallium, aluminum for P-type, and phosphorus, arsenic, antimony, bismuth, or lithium for N-type. The doping concentration may be 1e+13 cm-3 for low doping and 1e+18 cm-3 for high doping. A doping concentration greater than 1e+18 cm-3 may result in degenerated silicon having metal-like properties. The doped substrate region (40) may have a thermal conductivity higher than the rest of the first substrate (14) (e.g., higher than 100 W / mK) and a thickness of up to several hundred micrometers (e.g., several tens of micrometers to 500 micrometers) as needed. The thicker the silicon substrate, the better it will function as a heat sink for the second die, which has high power loss. The doped substrate region (40) may have a size that substantially covers the outer edge of the substrate tie structure (24) in a horizontal plane (e.g., nearly equal to or larger than the outer edge of the substrate tie structure (24). In one embodiment, the substrate tie structure (24) is located directly below the doped substrate region (40) or extends into the doped substrate region (40) (not shown). Because the doped substrate region (40) has lower thermal resistance than the rest of the first substrate, the doped substrate region (40) further improves the dissipation of heat propagated from the substrate tie structure (24).

[0062] As described above, the first die (12) includes a substrate tie structure (24) that extends through the first device region (20) and the dielectric layer (22) and extends into the first substrate (14), thereby improving the heat dissipation efficiency of the thermal path from the BEOL portion (18) to the first substrate (14). In some applications, as illustrated in FIG. 5, the substrate tie structure (24) may extend through the first device region (20), through the dielectric layer (22), and further through the first substrate (14), and may come into contact with a connection structure (26). In this case, the substrate tie structure (24) may have a height of several hundred micrometers. The substrate tie structure (24) may be hollow or filled with a high thermal material (e.g., silver and / or metal compounds) and has a thermal conductivity of more than 100 W / mK, in many cases several hundred W / mK. The substrate tie structure (24) may include a silicon through-via (TSV).

[0063] FIGS. 6A and 6B illustrate in 3D an exemplary 3D package (50) comprising the die-on-die 3D assembly (10) illustrated in FIG. 1. In addition to the die-on-die 3D assembly (10), as illustrated in FIG. 6A, the 3D package (50) may further comprise a mold compound (52) and an antenna module (54). For the purposes of this example, the mold compound (52) covers the side of the first die (12) and has a top surface and a bottom surface that are coplanar with the top surface and bottom surface of the first die (12), respectively. In some applications, a portion of the mold compound (52) may exist on the first die (12) and / or underfill the first die (12) to encapsulate a second die (16) and a bump structure (38) (not shown). In some applications, the mold compound (52) may be omitted (see FIG. 9A illustrated below). In some applications, the mold compound (52) may underfill the first die (12) to encapsulate the second die (16) and the bump structure (38), but not cover the side and top surfaces of the first die (12) (see FIG. 9b shown below).

[0064] An antenna module (54) is positioned below the second die (16) and connected to a bump structure (38). Since the bump structure (38) can be electrically connected to the first die (12) and the second die (16) (as described above), a signal received from the antenna module (54) can be transmitted to the first die (12) and / or the second die (16). In this embodiment, heat generated by the second die (16) (i.e., the second device region (32)) can still propagate through the BEOL portion (18) and the substrate tie structure (24) and be emitted from the first substrate (14). Additionally, heat generated by the second die (16) can also propagate toward the antenna module (54) through the connection structure (26) within the BEOL portion (18) and the bump structure (38). Here, since the bump structure (38) is higher than the second die (16), the second die (16) will not come into contact with the antenna module (54).

[0065] The mold compound (52) may be formed from a thermoplastic or thermosetting polymer material, such as polyphenylene sulfide (PPS), overmolded epoxy doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives. The antenna module (54) may provide a patch antenna (see FIG. 9c) and may include ceramic, FR4, etc.

[0066] In some applications, as illustrated in FIG. 6b, the 3D package (50) may further include a heat sink (56) over the first die (12). For the purposes of this example, the mold compound (52) covers the side of the first die (12) and extends vertically past the top surface of the first die (12). The heat sink (56) contacts the top surface of the first substrate (14) (i.e., the top surface of the first die (12)) and is embedded in the mold compound (52). The top surface of the heat sink (56) and the top surface of the mold compound (52) may be coplanar. The heat sink (56) may be formed of a metal / alloy material such as copper or nickel in the case of a plated metal shield. The metal shield may also be sprayed.

[0067] Note that in FIGS. 6a and 6b, the 3D package (50) includes the 3D die-on-die assembly (10) shown in FIG. 1. In other applications, the 3D package (50) may include the 3D die-on-die assembly (10) shown in any one of FIGS. 3 to 5, or any other suitable 3D die-on-die assembly. For example, FIG. 7 shows that the 3D package (50) includes the 3D die-on-die assembly (10) shown in FIG. 2. Here, the antenna module (54) is still placed below the second die (16) and connected to the bump structure (38) (i.e., BGA). A signal received from the antenna module (54) can be transmitted to the first die (12) and / or the second die (16) through the bump structure (38) and the connection structure (26). Most of the heat generated by the second die (16) will still be dissipated through the first substrate (14) due to the through-BEOL connection structure (26). Some of the heat generated by the second die (16) may also be propagated toward the antenna module (54) through the bump structure (38).

[0068] FIG. 8 illustrates a top view of a 3D package comprising a plurality of high-power low-thermal-conductivity dies and a silicon die as a heat sink for the plurality of high-power low-thermal-conductivity dies according to one embodiment of the present disclosure.

[0069] In some applications, there may be multiple high-power, low-thermal-conductivity dies placed under a single heat sink die. FIG. 8 illustrates a top view of an alternative 3D package (60) comprising multiple high-power second dies (16) under one first die (12) (for clarification, only one second die is labeled with a reference number). For the purposes of this example, the alternative 3D package (60) comprises 12 second dies (16) under the first die (12) arranged in a 3x4 array. For other applications, the alternative 3D package (60) may comprise a smaller number of second dies (16) having different array configurations.

[0070] FIGS. 9a through 9c illustrate a cross-sectional view (along the dotted line A-A') of an alternative 3D package (60) illustrated in FIG. 8. Compared to the 3D package (50) illustrated in FIGS. 6a through 6b, as illustrated in FIG. 9a, the alternative 3D package (60) comprises a plurality of second dies (16) positioned below the first die (12) and surrounded by a bump structure (38) (for clarity, only one element within the second die (16) is labeled with a reference number), and a plurality of substrate tie structures (24) extending through the first device region (20) and the dielectric layer (22) of the first die (12) and extending into the first substrate (14) of the first die (12). For the purposes of this example, each second die (16) has the same size and the same height, each substrate tie structure (24) corresponds to one second die (16), and each substrate tie structure (24) has the same shape with the same outline. For other applications, these multiple second dies (16) may provide different high-power device components and may have different sizes and / or different heights. One large substrate tie structure (24) may provide more than one second die (16). Additionally, multiple substrate tie structures (24) may have different shapes and / or different outlines. It is noted that since the first device region (20) includes one or more active sections (21) configured to provide electrical device components and each substrate tie structure (24) penetrates the first device region (20), it is preferable that each substrate tie structure (24) be laterally offset from the active section (21).

[0071] Here, at least some of the second dies (16) are electrically connected to a specific bump structure (38) by a corresponding connection structure (26) within the BEOL portion (18) of the first die (12) (for simplification, only two connection structures (26) are shown here). These multiple second dies (16) may be electrically connected to each other by other connection structures (26) within the BEOL portion (18) (not shown) and / or electrically connected to the first die (12). Each bump structure (38) still extends from the bottom surface of the first die (12) to the top surface of the antenna module (54) and electrically connects the first die (12) / second die(s) (16) (i.e., the first device area (22) / second device area (32)) to the antenna module (54). The bump structures (38) may have the same height and are higher than each of the second dies (16).

[0072] In this embodiment, heat generated by each second die (16) can be propagated through the BEOL portion (18) and the substrate tie structure (24) and can be emitted from the first substrate (14) of the first die (12). When a specific second die (16) is connected to a bump structure (38), heat generated by this second die (16) can also be propagated toward the antenna module (54) through the connection structure (26) within the BEOL portion (18) and the bump structure (38).

[0073] In one embodiment, an alternative 3D package (60) may further include a mold compound (52) as illustrated in FIG. 9b. For the purposes of this example, the mold compound (52) underfills the first die (12) to encapsulate each of the second die (16) and each of the bump structures (38), but does not cover the side and top surfaces of the first die (12). In some applications, the mold compound (52) may additionally cover the side of the first die (12) or completely encapsulate the first die (12) (not shown). If the mold compound (52) has high thermal conductivity (e.g., >30 W / m·K), heat generated by the second die (16) may also be dissipated through the mold compound (52).

[0074] In one embodiment, an alternative 3D package (60) may further include a printed circuit board (PCB) module (62) on the first die (12) as illustrated in FIG. 9c. Here, the first die (12) further includes a device through a structure (64) configured to connect the PCB module (62) to a corresponding bump structure (38). The device through the structure (64) may penetrate vertically through the first die (12) and may include a conductive material such as copper. The device through the structure (64) may be a TSV. The antenna module (54), the PCB module (62), and a specific second die (16) may be electrically and / or thermally connected through the corresponding bump structure (38), the corresponding device through the structure (64), and the corresponding connection structure (26) within the BEOL portion (18). Consequently, the heat generated by the second die (16) can be dissipated through the die structure (24) and the first substrate (14), through the bump structure (38) and the antenna module (54), and / or through the device through the structure (64) and the PCB module (62).

[0075] In this embodiment, the antenna module (54) provides a patch antenna comprising a plurality of metal patches (66) on the bottom of the antenna module (54). Additionally, the antenna module (54) may include a ground plane structure (68) capable of providing an electrical ground level to some of the second die (16) through a bump structure (38).

[0076] It is considered that any one of the aforementioned embodiments and / or various separate embodiments and features as described herein may be combined for additional benefit. Any of the various embodiments as disclosed herein may be combined with one or more other embodiments unless otherwise indicated herein.

[0077] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims

Claim 1 A three-dimensional (3D) package comprising: a back-end-of-line (BEOL) portion; a first die comprising a first device region above the BEOL portion; a first substrate above the first device region; and a substrate tie structure extending through the first device region and extending into the first substrate without extending through the first substrate; wherein the first substrate has a thermal conductivity greater than 100 W / mK and the substrate tie structure has a thermal conductivity greater than 50 W / mK. A 3D package comprising: a second die disposed below the first die, wherein the second die comprises a second device region and a second substrate below the second device region; wherein the second substrate has a thermal conductivity lower than that of the first substrate; and wherein the second device region is electrically and thermally coupled to the BEOL portion of the first die, so that heat generated by the second device region can propagate through the BEOL portion and the substrate tie structure and be released outside the first substrate. Claim 2 In claim 1, the first device region comprises one or more active sections configured to provide one or more electrical device components; and the substrate tie structure is laterally offset from the one or more active sections, forming a 3D package. Claim 3 In claim 1, the first die further comprises a dielectric layer between the first device region and the first substrate; and the substrate tie structure extends through the first device region and the dielectric layer, and extends into the first substrate without extending through the first substrate, 3D package. Claim 4 In paragraph 3, the dielectric layer of the first die is formed of silicon oxide or silicon nitride, in a 3D package. Claim 5 A 3D package according to claim 1, wherein the first substrate contacts the first device region without sandwiching a dielectric layer. Claim 6 In claim 1, the substrate tie structure is positioned vertically aligned with the second die, forming a 3D package. Claim 7 In claim 1, the 3D package, wherein the first substrate is formed of silicon. Claim 8 In claim 1, the second device region is configured to provide one or more electrical device components comprising one or more of gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), gallium phosphide (GaP), gallium carbon (GaC), gallium, indium gallium arsenide (InGaAs), indium gallium nitride (InGaN), indium gallium phosphide (InGaP), and indium gallium carbide (InGaC); and the second substrate is a 3D package formed of GaAs, GaN, GaP, or GaC. Claim 9 In claim 8, the 3D package wherein the second device region is configured to provide one or more heterojunction bipolar transistors (HBT), one or more amorphous high-electron mobility transistors (pHEMT), and / or one or more field-effect transistors (FET). Claim 10 In claim 1, the substrate tie structure is a 3D package having one of a grid array configuration, a multi-ring configuration, and a fish-bone configuration. Claim 11 The 3D package according to claim 1, wherein the substrate tie structure comprises at least one of a doped semiconductor, a metal powder, a plated metal, and a metal compound. Claim 12 A 3D package according to claim 1, further comprising a plurality of bump structures, wherein the plurality of bump structures are formed at the bottom of the BEOL portion of the first die and surround the second die; each of the plurality of bump structures has the same height and is higher than the second die; and the BEOL portion of the first die includes a plurality of connection structures, and a specific structure among the plurality of bump structures is connected to a second device area of ​​the second die through a corresponding structure among the plurality of connection structures. Claim 13 In claim 12, the plurality of bump structures are a plurality of copper pillars or a plurality of solder balls, a 3D package. Claim 14 A 3D package according to claim 12, wherein a specific structure among the plurality of connection structures is coupled to a second device region of the second die and extends through a BEOL portion of the first die, and a specific structure among the plurality of connection structures contacts the substrate tie structure within the first die. Claim 15 A 3D package according to claim 14, wherein a specific structure among the plurality of connection structures is shaped to conform to the configuration of the substrate tie structure. Claim 16 A 3D package according to claim 12, further comprising an antenna module disposed below the second die and connected to the plurality of bump structures. Claim 17 A 3D package according to claim 16, further comprising a mold compound and a heat sink, wherein the mold compound covers the side of the first die and extends vertically over the upper surface of the first die; and the heat sink is positioned over the upper surface of the first die and embedded within the mold compound. Claim 18 A 3D package according to claim 16, further comprising the mold compound that fills the gap between the first die and the antenna module such that the second die and the plurality of bump structures are encapsulated by the mold compound. Claim 19 A 3D package according to claim 1, wherein the outer edge of the substrate tie structure covers at least substantially the horizontal region of the second die. Claim 20 The 3D package according to claim 1, wherein the first substrate further comprises a doped substrate region, and the substrate tie structure is located immediately below the doped substrate region or extends into the doped substrate region; and the doped substrate region has higher thermal conductivity than other parts of the first substrate. Claim 21 In claim 20, the doped substrate region has a thickness of several tens of micrometers to 500 micrometers and is sized to substantially cover the outer edge of the substrate tie structure in a horizontal plane, forming a 3D package. Claim 22 delete Claim 23 A 3D package according to claim 1, further comprising a plurality of dies disposed below the first die, wherein the second die is one of the plurality of dies; and each of the plurality of dies is electrically and thermally coupled to the BEOL portion of the first die so that heat generated by the plurality of dies can be released outside the first substrate. Claim 24 In claim 23, the first die comprises a plurality of substrate tie structures including the substrate tie structure, and each of the plurality of substrate tie structures is vertically aligned with a corresponding one of the plurality of dies, a 3D package. Claim 25 A 3D package according to claim 23, further comprising a plurality of bump structures, wherein the plurality of bump structures are formed at the bottom of the BEOL portion of the first die and surround the plurality of dies; each of the plurality of bump structures has the same height and is higher than each of the plurality of dies; and a specific structure among the plurality of bump structures is connected to a specific die among the plurality of dies. Claim 26 A 3D package according to claim 25, further comprising an antenna module disposed below the plurality of dies and connected to the plurality of bump structures. Claim 27 A 3D package according to claim 26, further comprising the mold compound that fills the gap between the first die and the antenna module such that the plurality of dies and the plurality of bump structures are encapsulated by the mold compound. Claim 28 A 3D package according to claim 26, further comprising a printed circuit board (PCB) module disposed on the first die, wherein the first die is configured to connect the PCB module to a specific die among the plurality of dies through a connection structure within the BEOL portion of the first die, and the PCB module is configured to connect to the antenna module through a specific structure among the plurality of bump structures.

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