Semiconductor device and method for fabricating the same

Abstract

A method for manufacturing a semiconductor device according to the present invention may include the steps of: forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of sacrificial semiconductor layers on a lower structure; etching the stack body to form an opening; etching the semiconductor layers and the sacrificial semiconductor layers through the opening to form a plurality of active layers and a plurality of horizontal recesses; partially filling the horizontal recesses while forming sacrificial insulating layers in contact with the active layers; and replacing the sacrificial insulating layers with word lines.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device with a three-dimensional structure and a method for manufacturing the same. Background Technology

[0003] To increase the net die of a memory device, the size of memory cells is being continuously reduced. As the size of memory cells becomes finer, parasitic capacitance (Cb) should decrease and capacitance should increase; however, it is difficult to increase the net die due to the structural limitations of memory cells.

[0004] Recently, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions have been proposed. The problem to be solved

[0006] Embodiments of the present invention provide a semiconductor device having a highly integrated memory cell and a method for manufacturing the same. means of solving the problem

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of sacrificial semiconductor layers on a lower structure; etching the stack body to form an opening; etching the semiconductor layers and the sacrificial semiconductor layers through the opening to form a plurality of active layers and a plurality of horizontal recesses; partially filling the horizontal recesses while forming sacrificial insulating layers in contact with the active layers; and replacing the sacrificial insulating layers with word lines.

[0009] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a seed silicon layer on a lower structure; repeatedly forming a substack stacked in the order of a first single-crystal silicon germanium layer, a first single-crystal silicon layer, a second single-crystal silicon germanium layer, and a second single-crystal silicon layer on the seed silicon layer; etching the substacks and the seed silicon layer to form an opening; removing the first and second single-crystal silicon germanium layers through the opening to form initial horizontal recesses; thinning the second single-crystal silicon layers while removing the first single-crystal silicon layers to form horizontal recesses that are wider than the initial horizontal recesses and thin-body active layers between the horizontal recesses; forming sacrificial insulating layers that partially fill the horizontal recesses and contact the thin-body active layers; and replacing the sacrificial insulating layers with word lines.

[0010] A semiconductor device according to an embodiment of the present invention may include: a lower structure; cell separation insulating layers vertically stacked on the upper part of the lower structure and parallel to the lower structure; single-crystal silicon active layers located between the cell separation insulating layers and horizontally oriented parallel to the lower structure; word lines horizontally oriented to cross each of the single-crystal silicon active layers between the cell separation insulating layers; a bit line commonly connected to one side of the single-crystal silicon active layers and extended along a direction perpendicular to the lower structure; and capacitors connected to the other side of the single-crystal silicon active layers. Effects of the invention

[0012] This technology can improve the reliability of semiconductor devices by forming a thin-body active layer using single-crystal silicon.

[0013] This technology can improve the margin of metal contact etching and also prevent punching of the metal contact. Brief explanation of the drawing

[0015] FIG. 1 shows a schematic perspective view of a memory cell of a semiconductor device according to embodiments. Figure 2 shows a cross-sectional view of the memory cell of Figure 1. FIG. 3 is a schematic perspective view of a semiconductor device according to one embodiment. FIG. 4 is a schematic cross-sectional view of a memory cell array of a semiconductor device according to another embodiment. FIG. 5 is a schematic plan view for illustrating a semiconductor device according to another embodiment. FIGS. 6a and FIGS. 6b are schematic perspective views of a semiconductor device according to other embodiments. FIGS. 7 to 21 are drawings for explaining a method of manufacturing a semiconductor device according to one embodiment. Specific details for implementing the invention

[0016] The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block drawings, which are ideal schematic diagrams of the invention. Accordingly, the shapes of the exemplary drawings may be modified due to manufacturing techniques and / or tolerances, etc. Therefore, the embodiments of the invention are not limited to the specific shapes depicted but include variations in shape resulting from the manufacturing process. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of the regions of the device and are not intended to limit the scope of the invention.

[0017] The embodiments described below can increase memory cell density and reduce parasitic capacitance by vertically stacking memory cells.

[0018] FIG. 1 shows a schematic perspective view of a memory cell of a semiconductor device according to embodiments. FIG. 2 shows a cross-sectional view of the memory cell of FIG. 1.

[0019] Referring to FIGS. 1 and 2, a memory cell (MC) of a three-dimensional semiconductor device according to embodiments may include a bit line (BL), a transistor (TR), and a capacitor (CAP). The transistor (TR) may include an active layer (ACT) and a double word line (DWL), and the double word line (DWL) may include first and second word lines (WL1, WL2) facing each other with the active layer (ACT) in between. The capacitor (CAP) may include a storage node (SN), a dielectric layer (DE), and a plate node (PN).

[0020] The bit line (BL) may have a pillar shape extending along the first direction (D1). The active layer (ACT) may have a bar shape extending along the second direction (D2) intersecting the first direction (D1). The double word line (DWL) may have a line shape extending along the third direction (D3) intersecting the first and second directions (D1, D2). The plate node (PN) of the capacitor (CAP) may be connected to the plate line (PL).

[0021] The bit line (BL) may be vertically oriented along a first direction (D1). The bit line (BL) may be referred to as a vertically oriented bit line or a pillar-type bit line. The bit line (BL) may include a conductive material. The bit line (BL) may include a silicon-base material, a metal-base material, or a combination thereof. The bit line (BL) may include silicon, metal, metal nitride, metal silicide, or a combination thereof. The bit line (BL) may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line (BL) may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line (BL) may include a TiN / W stack comprising titanium nitride and tungsten on titanium nitride.

[0022] The double word line (DWL) may be extended along the third direction (D3), and the active layer (ACT) may be extended along the second direction (D2). The active layer (ACT) may be arranged horizontally along the second direction (D2) from the bit line (BL). The double word line (DWL) may include a pair of word lines, namely a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) may face each other in the first direction (D1) with the active layer (ACT) in between. A gate insulating layer (GD) may be formed on the upper surface and the lower surface of the active layer (ACT).

[0023] The active layer (ACT) may comprise a semiconductor material or an oxide semiconductor material. For example, the active layer (ACT) may comprise single-crystal silicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide). The active layer (ACT) may comprise polysilicon or single-crystal silicon. The active layer (ACT) may comprise a channel (CH), a first source / drain region (SR) between the channel (CH) and a bit line (BL), and a second source / drain region (DR) between the channel (CH) and a capacitor (CAP). The channel (CH) may be defined between the first source / drain region (SR) and the second source / drain region (DR). In the present embodiment, the active layer (ACT) may be single-crystal silicon.

[0024] The first source / drain region (SR) and the second source / drain region (DR) may be doped with impurities of the same conductivity type. The first source / drain region (SR) and the second source / drain region (DR) may be doped with N-type impurities or P-type impurities. The first source / drain region (SR) and the second source / drain region (DR) may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first side of the first source / drain region (SR) may be in contact with the bit line (BL), and the second side of the first source / drain region (SR) may be in contact with the channel (CH). The first side of the second source / drain area (DR) may contact the storage node (SN), and the second side of the second source / drain area (DR) may contact the channel (CH). The second side of the first source / drain area (SR) and the second side of the second source / drain area (DR) may partially overlap with the sides of the first and second word lines (WL1, WL2), respectively. The horizontal length of the channel (CH) along the second direction (D2) may be smaller than the horizontal length of the first and second source / drain areas (SR, DR) along the second direction (D2). In another embodiment, the horizontal length of the channel (CH) along the second direction (D2) may be larger than the horizontal length of the first and second source / drain areas (SR, DR) along the second direction (D2).

[0025] The transistor (TR) is a cell transistor and may have a double word line (DWL). In the double word line (DWL), the first word line (WL1) and the second word line (WL2) may have the same potential. For example, the first word line (WL1) and the second word line (WL2) may form a pair, and the same word line driving voltage may be applied to the first word line (WL1) and the second word line (WL2). In this way, the memory cell (MC) according to the present embodiment may have a double word line (DWL) in which two first and second word lines (WL1, WL2) are adjacent in one channel (CH).

[0026] In another embodiment, the first word line (WL1) and the second word line (WL2) may have different potentials. For example, a word line driving voltage may be applied to the first word line (WL1), and a ground voltage may be applied to the second word line (WL2). The second word line (WL2) may be referred to as a back word line or a shield word line. In another embodiment, a ground voltage may be applied to the first word line (WL1), and a word line driving voltage may be applied to the second word line (WL2).

[0027] The active layer (ACT) may have a thickness thinner than the first and second word lines (WL1, WL2). In addition, the vertical thickness of the active layer (ACT) along the first direction (D1) may be thinner than the vertical thickness of each of the first and second word lines (WL1, WL2) along the first direction (D1). Thus, the thin active layer (ACT) may be referred to as a thin-body active layer. The thin active layer (ACT) may include a thin-body channel (CH), and the thickness of the thin-body channel (CH) may be 10 nm or less. In another embodiment, the channel (CH) may have the same vertical thickness as the first and second word lines (WL1, WL2).

[0028] The gate insulating layer (GD) may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The gate insulating layer (GD) may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or HfZrO.

[0029] The double word line (DWL) may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The double word line (DWL) may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the double word line (DWL) may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The double word line (DWL) may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less, and the P-type work function material may have a high work function of 4.5 eV or more.

[0030] A capacitor (CAP) may be horizontally positioned along a second direction (D2) from a transistor (TR). The capacitor (CAP) may include a storage node (SN) that extends horizontally from an active layer (ACT) along the second direction (D2). The capacitor (CAP) may further include a dielectric layer (DE) and a plate node (PN) on the storage node (SN). The storage node (SN), the dielectric layer (DE), and the plate node (PN) may be horizontally arranged along the second direction (D2). The storage node (SN) may be a horizontally oriented cylinder shape. The dielectric layer (DE) may conformally cover the inner wall and outer wall of the cylinder of the storage node (SN). The plate node (PN) may be a shape that extends from the dielectric layer (DE) to the inner wall and outer wall of the cylinder of the storage node (SN). A plate node (PN) can be connected to a plate line (PL). A storage node (SN) can be electrically connected to a second source / drain area (DR).

[0031] The storage node (SN) has a three-dimensional structure, and the storage node (SN) of the three-dimensional structure may be a horizontal three-dimensional structure oriented along the second direction (D2). As an example of the three-dimensional structure, the storage node (SN) may have a cylinder shape. In another embodiment, the storage node (SN) may have a pillar shape or a cylinder shape. A cylinder shape may refer to a structure in which a pillar shape and a cylinder shape are merged.

[0032] A plate node (PN) may include an internal node (N1) and external nodes (N2, N3, N4). The internal node (N1) and the external nodes (N2, N3, N4) may be interconnected. The internal node (N1) may be located inside the cylinder of the storage node (SN). The external nodes (N2, N3) may be located outside the cylinder of the storage node (SN) with a dielectric layer (DE) in between. The external node (N4) may interconnect the internal node (N1) and the external nodes (N2, N3). The external nodes (N2, N3) may be positioned to surround the outer wall of the cylinder of the storage node (SN). The external node (N4) may serve as a plate line (PL).

[0033] The storage node (SN) and the plate node (PN) may comprise metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the storage node (SN) and the plate node (PN) may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, and tungsten nitride / tungsten (WN / W) stacks. The plate node (PN) may also comprise a combination of metal-based materials and silicon-based materials. For example, the plate node (PN) may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-fill material that fills the inside of the cylinder of the storage node (SN) on the titanium nitride, titanium nitride (TiN) may serve as the plate node (PN) of the capacitor (CAP), and tungsten nitride may be a low-resistance material.

[0034] The dielectric layer (DE) may comprise silicon oxide, silicon nitride, a high dielectric constant material, or a combination thereof. The high dielectric constant material may have a dielectric constant higher than that of silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer (DE) may comprise a high dielectric constant material having a dielectric constant of 4 or higher. The high dielectric constant material may have a dielectric constant of about 20 or higher. The high dielectric constant material may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer (DE) may be composed of a composite layer comprising two or more layers of the aforementioned high dielectric constant material.

[0035] The dielectric layer (DE) may be formed of zirconium-base oxide (Zr-base oxide). The dielectric layer (DE) may be a stack structure comprising at least zirconium oxide (ZrO2). The stack structure comprising zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack may be a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). A ZAZ stack may be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. ZA stacks and ZAZ stacks may be referred to as zirconium oxide-base layers (ZrO2-base layer). In another embodiment, the dielectric layer (DE) may be formed of hafnium-base oxide (Hf-base oxide). The dielectric layer (DE) may be a stack structure comprising at least hafnium oxide (HfO2). The stack structure comprising hafnium oxide (HfO2) may include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. An HA stack may be a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). An HAH stack may be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. An HA stack and an HAH stack may be referred to as a hafnium oxide-base layer (HfO2-base layer). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) may have a higher band gap energy (hereinafter abbreviated as band gap) than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2).Accordingly, the dielectric layer (DE) may include a stack of a high dielectric constant material and a high band gap material having a larger band gap than the high dielectric constant material. The dielectric layer (DE) may include silicon oxide (SiO2) as a high band gap material other than aluminum oxide (Al2O3). Leakage current can be suppressed by including the high band gap material in the dielectric layer (DE). The high band gap material may be thinner than the high dielectric constant material. In another embodiment, the dielectric layer (DE) may include a laminated structure in which the high dielectric constant material and the high band gap material are alternately stacked. For example, it may include a ZAZA(ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ(ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA(HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH(HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In such a laminate structure, the aluminum oxide (Al2O3) may be thinner than the zirconium oxide (ZrO2) and the hafnium oxide (HfO2).

[0036] In another embodiment, the dielectric layer (DE) may include a stack structure, a laminate structure, or a mutual mixing structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0037] In another embodiment, the dielectric layer (DE) may include a ferroelectric material or an antiferroelectric material.

[0038] In another embodiment, an interface control layer (not shown) for improving leakage current may be further formed between the storage node (SN) and the dielectric layer (DE). The interface control layer may include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the plate node (PN) and the dielectric layer (DE).

[0039] The capacitor (CAP) may include a Metal-Insulator-Metal (MIM) capacitor. The storage node (SN) and the plate node (PN) may include a metal-base material.

[0040] The capacitor (CAP) may be replaced with other data storage materials. For example, the data storage material may be a phase change material, a Magnetic Tunnel Junction (MTJ), or a variable resistor material.

[0041] FIG. 3 is a schematic perspective view of a semiconductor device according to one embodiment. FIG. 4 is a cross-sectional view of the vertical memory cell array (MCA_C) of FIG. 3.

[0042] Referring to FIGS. 3 and 4, a semiconductor device (100) may include a substructure (LS) and a memory cell array (MCA). A plurality of memory cells (MC) of FIG. 1 may be arranged along first to third directions (D1, D2, D3) to form the memory cell array (MCA) of FIG. 3. The memory cell array (MCA) may include a three-dimensional array of memory cells (MC), and the three-dimensional memory cell array may include a vertical memory cell array (MCA_C) and a horizontal memory cell array (MCA_R). The vertical memory cell array (MCA_C) may refer to an array of memory cells (MC) arranged vertically along the first direction (D1). The horizontal memory cell array (MCA_R) may refer to an array of memory cells (MC) arranged horizontally along the third direction (D3). A vertical memory cell array (MCA_C) can be referred to as a column array of memory cells (MC), and a horizontal memory cell array (MCA_R) can be referred to as a row array of memory cells (MC). Bit lines (BL) can be oriented vertically so as to be connected to the vertical memory cell array (MCA_C), and double word lines (DWL) can be oriented horizontally so as to be connected to the horizontal memory cell array (MCA_R). Bit lines (BL) connected to the vertical memory cell array (MCA_C) can be referred to as common bit lines (Common BL), and adjacent vertical memory cell arrays (MCA_C) along the third direction (D3) can be connected to different common bit lines. A double word line (DWL) connected to a horizontal memory cell array (MCA_R) can be referred to as a common double word line (Common DWL), and adjacent horizontal memory cell arrays (MCA_R) along a first direction (D1) can be connected to different common double word lines.

[0043] A memory cell array (MCA) may include a plurality of memory cells (MC), and an individual memory cell (MC) may include a vertically oriented bit line (BL), a horizontally oriented active layer (ACT), a double word line (DWL), and a horizontally oriented capacitor (CAP). For example, FIG. 3 illustrates a three-dimensional DRAM memory cell array composed of four memory cells (MC).

[0044] In one bit line (BL), adjacent active layers (ACTs) may be in contact along the first direction (D1). Adjacent active layers (ACTs) along the third direction (D3) may share a double word line (DWL). Capacitors (CAPs) may be connected to each of the active layers (ACTs). Capacitors (CAPs) may share a single plate line (PL). An individual active layer (ACT) may be thinner than the first and second word lines (WL1, WL2) of the double word line (DWL).

[0045] A memory cell array (MCA) may have a plurality of double word lines (DWL) stacked vertically along a first direction (D1). Each double word line (DWL) may include a pair of a first word line (WL1) and a second word line (WL2). Between the first word line (WL1) and the second word line (WL2), a plurality of active layers (ACT) may be arranged horizontally spaced apart from each other along a third direction (D3). A channel (CH) of the active layer (ACT) may be located between the first word line (WL1) and the second word line (WL2).

[0046] The double word line (DWL) may be a notched structure including protrusions (PWL). In another embodiment, it may be a linear shape without protrusions (PWL). That is, the double word line (DWL) may have the same shape as the double word line (DWL) of FIG. 1.

[0047] FIG. 5 is a schematic plan view for illustrating a semiconductor device according to another embodiment. The semiconductor device (100M) of FIG. 5 may be similar to the semiconductor device of FIG. 1 to FIG. 4. Hereinafter, detailed descriptions of overlapping components will be omitted.

[0048] Referring to FIG. 5, the semiconductor device (100M) may include a memory cell array (MCA), and the memory cell array (MCA) may include a plurality of memory cells (MC). The memory cell array (MCA) may include a plurality of bit lines (BL), a plurality of transistors (TR), and a plurality of capacitors (CAP). The transistors (TR) may share a single double word line (DWL). The bit lines (BL) may extend vertically along a first direction, and the double word lines (DWL) may extend along a third direction (D3). Each of the transistors (TR) may include an active layer (ACT), and the active layers (ACT) may extend along a second direction (D2). Each of the capacitors (CAP) may include a storage node (SN), a dielectric layer (DE), and a plate node (PN). The plate nodes (PN) may be connected to a plate line (PL). One end of the active layer (ACT) can be connected to the bit line (BL), and the other end of the active layer (ACT) can be connected to the capacitor (CAP).

[0049] Each active layer (ACT) may include a channel that overlaps the double word line (DWL), and the channel may include a channel protrusion (CHP). The active layers (ACT) may be rhombus-shaped. The channel protrusions (CHP) may overlap perpendicularly to the double word line (DWL).

[0050] A double word line (DWL) may include two opposing notch-type sidewalls. For example, it may include a first notch-type sidewall (NS1) and a second notch-type sidewall (NS2) opposing each other along a second direction (D2). The first and second notch-type sidewalls (NS1, NS2) may include a plurality of flat surfaces (WLF) and a plurality of recessed surfaces (WLR). The flat surfaces (WLF) may be adjacent to a bit line (BL) and a storage node (SN). Along a third direction (D3), the flat surfaces (WLF) and recessed surfaces (WLR) may be formed alternately. When viewed from the top, the recessed surfaces (WLR) may have a round shape.

[0051] A double word line (DWL) having first and second notched sidewalls (NS1, NS2) can be referred to as a notched double word line (DWL). By forming a notched double word line (DWL), bridges between adjacent memory cells (MCs) can be prevented. Additionally, by forming a notched double word line (DWL), the capacitance between double word lines (DWL) can be reduced.

[0052] The double word line (DWL) in Fig. 3 may also be a notched double word line, and the top view shape of the active layer (ACT) in Fig. 3 may be rectangular. The active layer (ACT) in Fig. 3 may be rhombus-shaped, just like the active layer (ACT) in Fig. 5.

[0053] FIGS. 6a and 6b are schematic perspective views of semiconductor devices according to different embodiments. FIG. 6a illustrates a semiconductor device (110) with a COP structure, and FIG. 6b illustrates a semiconductor device (120) with a POC structure. Detailed descriptions of components in FIGS. 6a and 6b that overlap with FIGS. 1 through 5 are omitted.

[0054] Referring to FIG. 6a, the semiconductor device (110) may include a peripheral circuit portion (PERI), and the peripheral circuit portion (PERI) may be located at a lower level than the memory cell array (MCA). This may be referred to as a COP (Cell over PERI) structure. The bit line (BL) of the memory cell array (MCA) may be oriented perpendicularly along a first direction (D1) with respect to the surface of the peripheral circuit portion (PERI), and the double word line (DWL) may be oriented parallel to the surface of the peripheral circuit portion (PERI) with respect to a third direction (D3).

[0055] Referring to FIG. 6b, the semiconductor device (120) may include a memory cell array (MCA) and a peripheral circuit (PERI). The peripheral circuit (PERI) may be located at a higher level than the memory cell array (MCA). This may be referred to as a POC (PERI over Cell) structure.

[0056] The memory cell array (MCA) and peripheral circuit (PERI) of the semiconductor device (120) can be interconnected by wafer bonding. For example, a first multilayer level metal wiring connected to bit lines (BL) may be formed at the top level of the memory cell array (MCA), and the peripheral circuit (PERI) may include a second multilayer level metal wiring. After adjusting the orientation of the peripheral circuit (PERI) so that the second multilayer level metal wiring is located at the bottom, the first multilayer level metal wiring of the memory cell array (MCA) and the second multilayer level metal wiring of the peripheral circuit (PERI) can be wafer bonded through bonding pads.

[0057] In FIG. 6a and 6b, the peripheral circuit (PERI) may include at least one control circuit for driving a memory cell array (MCA). At least one control circuit of the peripheral circuit (PERI) may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit (PERI) may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit (PERI) may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0058] For example, the peripheral circuitry (PERI) may include a subword line driver (SWD) and a sense amplifier (SA). The double word line (DWL) may be connected to the subword line driver (SWD) via a multi-level metal interconnection (MLM). The bit lines (BL) may be connected to the sense amplifier (SA). Although not shown, the bit lines (BL) and the sense amplifier (SA) may be interconnected via additional multi-level metal interconnection.

[0059] FIGS. 7 to 21 are drawings for explaining a method of manufacturing a semiconductor device according to one embodiment.

[0060] As illustrated in FIG. 7, a seed layer (12) may be formed on top of a substructure (11). The substructure (11) may include a semiconductor substructure. The seed layer (12) may include a semiconductor material. The seed layer (12) may be a silicon-based material, for example, silicon (Si). The seed layer (12) may be formed by epitaxial growth. The seed layer (12) may be epitaxial silicon with a thickness of 7 to 10 nm. The seed layer (12) may be a single-crystal seed layer, for example, single-crystal silicon.

[0061] A stack body (SBD) including a plurality of sacrificial semiconductor layers (13, 15) and a plurality of semiconductor layers (14, 16) may be formed on the upper portion of a seed layer (12). In the stack body (SBD), the plurality of sacrificial semiconductor layers (13, 15) and the plurality of semiconductor layers (14, 16) may have a structure in which they are stacked alternately one by one. The stack body (SBD) may further include an uppermost sacrificial semiconductor layer (17).

[0062] A plurality of semiconductor layers (14, 16) may include first semiconductor layers (14) and second semiconductor layers (16). The first semiconductor layers (14) may be thinner than the second semiconductor layers (16). The second semiconductor layers (16) may be about 2 to 3 times thicker than the first semiconductor layers (14). For example, the first semiconductor layers (14) may be about 20 nm thick, and the second semiconductor layers (16) may be about 40 nm thick.

[0063] A plurality of sacrificial semiconductor layers (13, 15) may include first sacrificial semiconductor layers (13) and second sacrificial semiconductor layers (15). The first sacrificial semiconductor layers (13) and the second sacrificial semiconductor layers (15) may have the same thickness. The first sacrificial semiconductor layers (13) and the second sacrificial semiconductor layers (15) may be thinner than the first and second semiconductor layers (14, 16). The first sacrificial semiconductor layers (13) and the second sacrificial semiconductor layers (15) may be thinner than the first semiconductor layers (14). For example, the first sacrificial semiconductor layers (13) and the second sacrificial semiconductor layers (15) may have a thickness of 7 to 10 nm.

[0064] The top sacrificial semiconductor layer (17) may be located on the top second semiconductor layer (16) among the first and second semiconductor layers (14, 16). The top sacrificial semiconductor layer (17) may have the same thickness as the first and second sacrificial semiconductor layers (13, 15). For example, the top sacrificial semiconductor layer (17) may have a thickness of 7 to 10 nm.

[0065] In another embodiment, the top sacrificial semiconductor layer (17) may be omitted.

[0066] In another embodiment, a plurality of semiconductor layers (14, 16) may be formed by changing the order of the first semiconductor layers (14) and the second semiconductor layers (16). That is, the first semiconductor layers (14) may be thicker than the second semiconductor layers (16). The first semiconductor layers (14) may be about 2 to 3 times thicker than the second semiconductor layers (16). For example, the first semiconductor layers (14) may be about 40 nm thick, and the second semiconductor layers (16) may be about 20 nm thick.

[0067] The first and second semiconductor layers (14, 16), the first and second sacrificial semiconductor layers (13, 15), and the top sacrificial semiconductor layer (17) constituting the stack body (SBD) can each be formed by an epitaxial growth process. For example, the first semiconductor layers (14), the second semiconductor layers (16), the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the top sacrificial semiconductor layer (17) may be made of a single-crystal semiconductor or a single-crystal semiconductor compound. In exemplary embodiments, the first and second semiconductor layers (14, 16) may include a first semiconductor material selected from single-crystal silicon and single-crystal silicon germanium, and the first and second sacrificial semiconductor layers (13, 15) may include a second semiconductor material different from the first semiconductor material. The top sacrificial semiconductor layer (17) may include the same material as the first and second sacrificial semiconductor layers (13, 15), for example, the second semiconductor material. For example, the first and second semiconductor layers (14, 16) may each be a single-crystal silicon layer, and the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the top sacrificial semiconductor layer (17) may each be a single-crystal silicon germanium layer.

[0068] As described above, epitaxial growth can be used to form a stack body (SBD) on top of a seed layer (12), and the stack body (SBD) can be formed by repeating a plurality of sub-stacks. For example, individual sub-stacks can be stacked in the order of a first sacrificial semiconductor layer (13), a first semiconductor layer (14), a second sacrificial semiconductor layer (15), and a second semiconductor layer (16).

[0069] Next, an insulating layer (18) may be formed on the upper part of the stack body (SBD). The insulating layer (18) may include silicon oxide. The insulating layer (18) may be omitted as a hard mask.

[0070] A mask layer (19) may be formed on top of an insulating layer (18). The mask layer (19) may include at least one opening (19M), and the insulating layer (18) may be exposed through the opening (19M). The mask layer (19) may be a material having an etching selectivity ratio with respect to the insulating layer (18) and the stack body (SBD). The mask layer (19) may include photoresist, silicon nitride, silicon oxynitride, amorphous silicon, amorphous carbon, ARC (anti-reflective coating) material, or a combination thereof.

[0071] As illustrated in FIG. 8, at least one first opening (20) may be formed in the stack body (SBD). To form the first opening (20), the insulating layer (18), the stack body (SBD), and the seed layer (12) may be etched sequentially. For example, the insulating layer (18) may be etched using a mask layer (19) as an etching mask, and then the stack body (SBD) and the seed layer (12) may be etched. The first opening (20) may extend vertically through the insulating layer (18), the stack body (SBD), and the seed layer (12). The first opening (20) may expose the surface of the lower structure (11).

[0072] As illustrated in FIG. 9, a plurality of initial horizontal recesses (AG') can be formed between the first semiconductor layers (14) and the second semiconductor layers (16). While forming the plurality of initial horizontal recesses (AG'), an initial horizontal recess (AG') can also be formed between the insulating layer (18) and the uppermost second semiconductor layer (16). To form the plurality of initial horizontal recesses (AG'), the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the uppermost sacrificial semiconductor layer (17) can be selectively removed. The initial horizontal recesses (AG') can have the same size, for example, the same height.

[0073] To selectively remove the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the top sacrificial semiconductor layer (17), the difference in etching selectivity between the first and second semiconductor layers (14, 16) and the first and second sacrificial semiconductor layers (13, 15) may be utilized. Wet etching or dry etching may be used to selectively remove the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the top sacrificial semiconductor layer (17). For example, when the first sacrificial semiconductor layers (13), the second sacrificial semiconductor layers (15), and the top sacrificial semiconductor layer (17) contain silicon germanium and the first and second semiconductor layers (14, 16) contain silicon, the silicon germanium may be etched using an etching solution or etching gas having selectivity for the silicon layers.

[0074] As illustrated in FIG. 10, the first and second semiconductor layers (14, 16) can be recessed through initial horizontal recesses (AG'). To recess the first and second semiconductor layers (14, 16), the first and second semiconductor layers (14, 16) can be etched using wet etching or dry etching. In this embodiment, the second semiconductor layers (16) can be partially etched until the first semiconductor layers (14) are removed. Accordingly, the thin first semiconductor layers (14) can be completely removed, and the thick second semiconductor layers (16) can be thinned to the level indicated by the reference numeral '16S'. The recessing process of the first and second semiconductor layers (14, 16) may be referred to as a thinning process of the second semiconductor layers (16). The thinned second semiconductor layers (16S) may be abbreviated as thin-body active layer (16S). The thin-body active layer (16S) may include single-crystal silicon. While removing the first semiconductor layers (14), the seed layer (12) may also be completely removed, and the surface of the substructure (11) may be recessed to a certain depth.

[0075] After etching the first and second semiconductor layers (14, 16), the initial horizontal recesses (AG') may be expanded in the vertical direction. For example, a plurality of horizontal recesses (AG) may be formed between the thin-body active layers (16S), and the plurality of horizontal recesses (AG) may be larger in size than the initial horizontal recesses (AG'). Among the plurality of horizontal recesses (AG), the uppermost horizontal recess (AG) may be located between the insulating layer (18) and the uppermost thin-body active layer (16S). The uppermost horizontal recess (AG) may be lower in height than other levels of horizontal recesses (AG).

[0076] As illustrated in FIG. 11, horizontal recesses (AG) can be filled with insulating materials (21, 22). The insulating materials (21, 22) may include sacrificial insulating layers (21) and cell isolation insulating layers (22). First, a plurality of sacrificial insulating layers (21) may be formed to cover thin-body active layers (16S), and subsequently, a plurality of cell isolation insulating layers (22) may be formed on the sacrificial insulating layers (21). The thin-body active layers (16S) and the sacrificial insulating layers (21) may be in direct contact. The sacrificial insulating layers (21) and the cell isolation insulating layers (22) may be different materials. The sacrificial insulating layers (21) may include silicon nitride, and the cell isolation insulating layers (22) may include silicon oxide. The cell isolation insulating layers (22) and the insulating layer (18) may be the same material. Hereinafter, the insulating layer (18) is illustrated by the reference numeral '22' and is abbreviated as the cell separation insulating layer.

[0077] As described above, a cell body (CBD) can be formed on the upper part of the lower structure (11) by forming sacrificial insulating layers (21) and cell separation insulating layers (22). The cell body (CBD) may include a plurality of thin-body active layers (16S), a plurality of sacrificial insulating layers (21), and a plurality of cell separation insulating layers (22). The cell body (CBD) may include a plurality of sub-stacks located between the cell separation insulating layers (22). Here, the sub-stack may be a structure in which one thin-body active layer (16S) is located between two sacrificial insulating layers (21). Since the plurality of cell separation insulating layers (22), the plurality of sacrificial insulating layers (21), and the plurality of thin-body active layers (16S) each include silicon oxide, silicon nitride, and a single-crystal silicon layer, the cell body (CBD) may include a structure in which an ONSN (Oxide-Nitride-Silicon-Nitride) stack is stacked multiple times.

[0078] As illustrated in FIG. 12, word line recesses (23) may be formed in the cell body (CBD). To form the word line recesses (23), portions of a plurality of sacrificial insulating layers (21) may be selectively etched. A dummy word line recess (23D) may be formed between the lower structure (11) and the lowest level cell isolation insulating layer (22).

[0079] A portion of the thin-body active layers (16S) may be exposed by the word line recesses (23).

[0080] As illustrated in FIG. 13, a gate insulating layer (GD) can be formed on the exposed portion of the thin-body active layer (16S). The gate insulating layer (GD) can be optionally formed on the surfaces of the thin-body active layer (16S) by an oxidation process. In another embodiment, the gate insulating layer (GD) can be formed by a deposition process, in which case the gate insulating layer (GD) can be formed on the surface of the word line recesses (23) and the surface of the thin-body active layers (16S).

[0081] Next, a double word line (DWL) can be formed by filling each of the word line recesses (23) with a conductive material. The double word line (DWL) may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the step of forming the double word line (DWL) may include conformally depositing titanium nitride, depositing tungsten on the titanium nitride to fill the word line recesses (23), and etching back the titanium nitride and tungsten. The double word line (DWL) may partially fill the word line recesses (23), thereby exposing a portion of the gate insulating layer (GD). Each double word line (DWL) may include a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) may face each other perpendicularly with the thin-body active layers (16S) in between. The double word line (DWL), the first word line (WL1), and the second word line (WL2) of FIG. 13 may correspond to the double word line (DWL), the first word line (WL1), and the second word line (WL2) of FIG. 1 to FIG. 5.

[0082] While forming the double word line (DWL), a dummy word line (DMWL) that fills the dummy word line recess (23D) may be formed. The dummy word line (DMWL) may be formed from the same material as the double word line (DWL).

[0083] As illustrated in FIG. 14, bit line-side capping layers (BC) can be formed in contact with one side of a double word line (DWL). The bit line-side capping layers (BC) may be located within word line recesses (23). The bit line-side capping layers (BC) may comprise silicon oxide, silicon nitride, or a combination thereof. The bit line-side capping layers (BC) may be in contact with the first and second word lines (WL1, WL2).

[0084] The first end (E1) of the thin-body active layer (16S) can be exposed by the bit line-side capping layers (BC).

[0085] As illustrated in FIG. 15, a first source / drain region (SR) may be formed at the first end (E1) of the thin-body active layer (16S). To form the first source / drain region (SR), deposition and annealing of a conductive layer containing impurities may be performed. In another embodiment, the first source / drain region (SR) may be formed by an impurity doping process.

[0086] As illustrated in FIG. 16, a bit line (BL) may be formed. The bit line (BL) may be a pillar shape that fills the first opening (20). The bit line (BL) may include titanium nitride, tungsten, or a combination thereof.

[0087] As illustrated in FIG. 17, a second opening (24) can be formed by etching another part of the cell body (CBD). The second opening (24) may be vertically extended. The second opening (24) may be a hole shape that penetrates another part of the cell body (CBD).

[0088] As illustrated in FIG. 18, the sacrificial insulating layers (21) and thin-body active layers (16S) can be selectively recessed through the second opening (24). Accordingly, a capacitor opening (25) can be formed between the cell isolation insulating layers (22). After performing the processes for forming the second opening (24) and the capacitor opening (25), the remaining thin-body active layer (16S) may remain as indicated by the reference numeral 'ACT'. First and second word lines (WL1, WL2) may be formed with the thin-body active layer (ACT) in between, and a gate insulating layer (GD) may be located between the thin-body active layer (ACT) and the first and second word lines (WL1, WL2). The thin-body active layer (ACT) may be referred to as a single-crystal silicon active layer.

[0089] Next, the sacrificial insulating layers (21) can be further recessed. Accordingly, a void (or horizontal recess) may be provided on one side of the sacrificial insulating layers (21), and the second end (E2) of the thin-body active layer (ACT) may be exposed by the void. The remaining sacrificial insulating layers may become a storage node-side capping layer (21'). The storage node-side capping layer (21') may cover the upper and lower surfaces of the thin-body active layer (ACT).

[0090] As illustrated in FIG. 19, a second source / drain region (DR) may be formed within the thin-body active layer (ACT). Accordingly, a first source / drain region (SR) and a second source / drain region (DR) may be formed horizontally spaced apart within the thin-body active layer (ACT), and a channel (CH) may be defined between the first source / drain region (SR) and the second source / drain region (DR).

[0091] Next, a storage node (SN) can be formed on the second source / drain region (DR). To form the storage node (SN), a deposition and etch-back process of a conductive material can be performed. The storage node (SN) may include titanium nitride. The storage node (SN) may have a horizontally oriented cylindrical shape. Individual storage nodes (SN) may be connected to individual second source / drain regions (DR).

[0092] As shown in FIG. 20, the cell separation insulating layers (22) can be recessed (see reference numeral 26) to expose the outer wall of the storage node (SN).

[0093] As shown in FIG. 21, a dielectric layer (DE) and a plate node (PN) can be sequentially formed on a storage node (SN).

[0094] According to FIGS. 7 to 21, when thin-body active layers (ACT) include a single-crystal active layer, the semiconductor device may include a lower structure (11), cell isolation insulating layers (22) vertically stacked on top of the lower structure (11) and parallel to the lower structure (11), single-crystal silicon active layers (ACT) located between the cell isolation insulating layers (22) and horizontally oriented to be parallel to the lower structure (11), word lines (WL1, WL2) horizontally oriented to cross each of the single-crystal silicon active layers (ACT) between the cell isolation insulating layers (22), a bit line (BL) commonly connected to one side of the single-crystal silicon active layers (ACT) and extended along a direction perpendicular to the lower structure (LS), and capacitors (CAP) connected to the other side of the single-crystal silicon active layers (ACT). It may further include a dummy word line (DMWL) located between the lowest word line (WL2) among the word lines (WL1, WL2) and the substructure (11). A cell separation insulating layer (22) may be located between the lowest word line (WL2) and the dummy word line (DMWL). Plate nodes (PN) may be spaced apart from the substructure (11).

[0095] A semiconductor device in which the above dummy word line and the lowest word line are separated from each other by the lowest cell separation insulating layer of the above cell separation insulating layers.

[0096] It will be obvious to those skilled in the art that the present invention is not limited by the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0098] DWL: Double Word Line ACT: Active Layer GD: Gate insulation layer CH: Channel SR: 1st Source / Drain Area DR: 2nd Source / Drain Area BL : Bit line TR : Transistor CAP: Capacitor SN: Storage Node DE: Dielectric layer PN: Plate node PL: Plate line WL1: 1st word line WL2: Second word line MCA: Memory cell array MC: Memory Cell

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a step of forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of sacrificial semiconductor layers on a lower structure; a step of etching the stack body to form an opening; a step of etching the semiconductor layers and the sacrificial semiconductor layers through the opening to form a plurality of active layers and a plurality of horizontal recesses; a step of partially filling the horizontal recesses while forming sacrificial insulating layers in contact with the active layers; and a step of replacing the sacrificial insulating layers with word lines, wherein the semiconductor layers are formed thicker than the sacrificial semiconductor layers. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein each of the plurality of semiconductor layers comprises a single-crystal silicon layer, and each of the sacrificial semiconductor layers comprises a single-crystal silicon germanium layer. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial insulating layers comprise silicon nitride. Claim 4 delete Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the stack body includes the step of repeatedly forming a plurality of sub-stacks on the upper part of the lower structure using epitaxial growth, wherein the individual sub-stacks are stacked in the order of a first sacrificial semiconductor layer, a first semiconductor layer, a second sacrificial semiconductor layer, and a second semiconductor layer thicker than the first semiconductor layer. Claim 6 A method for manufacturing a semiconductor device according to claim 5, wherein the second semiconductor layer is formed to be 2 to 3 times thicker than the first semiconductor layer, the first semiconductor layer is formed to be thicker than the first and second sacrificial semiconductor layers, and the first sacrificial semiconductor layer and the second sacrificial semiconductor layer are formed to be of the same thickness. Claim 7 In claim 5, the lowest material and the highest material in the plurality of sub-stacks are a semiconductor device manufacturing method comprising the first sacrificial semiconductor layer. Claim 8 A method for manufacturing a semiconductor device according to claim 5, wherein the lowest material in the plurality of sub-stacks comprises the first sacrificial semiconductor layer and the highest material comprises the second semiconductor layer. Claim 9 A method for manufacturing a semiconductor device according to claim 5, wherein the first and second semiconductor layers each comprise a single-crystal silicon layer, and the first and second sacrificial semiconductor layers each comprise a single-crystal silicon germanium layer. Claim 10 A method for manufacturing a semiconductor device according to claim 5, further comprising the step of forming a single crystal seed layer between the substructure and a plurality of substacks, wherein the single crystal seed layer has a thickness thinner than the first and second semiconductor layers and has the same thickness as the first and second sacrificial semiconductor layers. Claim 11 A method for manufacturing a semiconductor device according to claim 10, wherein the single crystal seed layer, the first semiconductor layer, and the second semiconductor layer each comprise a single crystal silicon layer, and the first and second sacrificial semiconductor layers each comprise a single crystal silicon germanium layer. Claim 12 A method for manufacturing a semiconductor device according to claim 10, wherein the single crystal seed layer and the lowest first sacrificial semiconductor layer are replaced with dummy word lines. Claim 13 A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layers include first semiconductor layers and second semiconductor layers thicker than the first semiconductor layers, and the step of etching the semiconductor layers and sacrificial semiconductor layers through the opening to form a plurality of active layers and a plurality of horizontal recesses comprises: a step of removing the sacrificial semiconductor layers to form an initial horizontal recess; and a step of thinning the second semiconductor layers while removing the first semiconductor layers to form the horizontal recesses and the active layers between the horizontal recesses that are wider than the initial horizontal recess. Claim 14 A method for manufacturing a semiconductor device according to claim 1, further comprising, after the step of forming sacrificial insulating layers in contact with the active layers, the step of forming cell separation insulating layers that fill between the sacrificial insulating layers, wherein the sacrificial insulating layers and the cell separation insulating layers comprise different materials. Claim 15 A method for manufacturing a semiconductor device according to claim 1, further comprising: forming a bit line that is commonly connected to the first end of the active layers and oriented perpendicularly to the surface of the substructure; and forming a capacitor comprising a storage node that is respectively connected to the second end of the active layers. Claim 16 A method for manufacturing a semiconductor device comprising: forming a seed silicon layer on top of a substructure; repeatedly forming a substack stacked in the order of a first single-crystal silicon germanium layer, a first single-crystal silicon layer, a second single-crystal silicon germanium layer, and a second single-crystal silicon layer on the seed silicon layer; etching the substacks and the seed silicon layer to form an opening; removing the first and second single-crystal silicon germanium layers through the opening to form initial horizontal recesses; thinning the second single-crystal silicon layers while removing the first single-crystal silicon layers to form horizontal recesses that are wider than the initial horizontal recesses and thin-body active layers between the horizontal recesses; forming sacrificial insulating layers that partially fill the horizontal recesses and contact the thin-body active layers; and replacing the sacrificial insulating layers with word lines. Claim 17 A method for manufacturing a semiconductor device according to claim 16, wherein the second single-crystal silicon layers are formed thicker than the first single-crystal silicon layers, and the first and second single-crystal silicon germanium layers are formed thinner than the first single-crystal silicon layers. Claim 18 A method for manufacturing a semiconductor device according to claim 16, wherein the second single-crystal silicon layers are formed to be 2 to 3 times thicker than the first single-crystal silicon layers. Claim 19 In claim 16, a method for manufacturing a semiconductor device wherein the seed silicon layer, the first single-crystal silicon germanium layer, the first single-crystal silicon layer, the second single-crystal silicon germanium layer, and the second single-crystal silicon layer are each formed by epitaxial growth. Claim 20 A method for manufacturing a semiconductor device according to claim 16, wherein the seed silicon layer and the lowest first single-crystal silicon germanium layer are replaced with the lowest sacrificial insulating layer among the sacrificial insulating layers, and the lowest sacrificial insulating layer is replaced with a dummy word line. Claim 21 A method for manufacturing a semiconductor device according to claim 16, further comprising, after the step of forming the word lines, the step of forming a bit line that is commonly connected to one end of the thin-body active layers and extends along a direction perpendicular to the surface of the substructure; and the step of forming a capacitor connected to each of the other ends of the thin-body active layers. Claim 22 A semiconductor device comprising: a substructure; cell isolation insulating layers vertically stacked on top of the substructure and parallel to the substructure; single-crystal silicon active layers located between the cell isolation insulating layers and horizontally oriented parallel to the substructure; word lines horizontally oriented to cross each of the single-crystal silicon active layers between the cell isolation insulating layers; a bit line commonly connected to one side of the single-crystal silicon active layers and extended along a direction perpendicular to the substructure; capacitors connected to the other side of the single-crystal silicon active layers; and a dummy word line located between the lowest word line among the word lines and the substructure. Claim 23 A semiconductor device according to claim 22, wherein each of the above word lines comprises a double word line crossing the upper and lower surfaces of each of the above single-crystal silicon active layers. Claim 24 A semiconductor device according to claim 22, wherein each of the capacitors comprises: a storage node electrically connected to the other side of each of the single-crystal silicon active layers; a plate node on the storage node; and a dielectric layer between the storage node and the plate node. Claim 25 A semiconductor device according to claim 22, wherein the dummy word line and the lowest word line are separated from each other by the lowest cell separation insulating layer of the cell separation insulating layers.

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