Method for generating and verifying logical circuits using artificial intelligence

Abstract

A logic circuit diagram generation and verification device may include: a data acquisition unit that acquires a system diagram and control information regarding the system diagram from a user; a data preprocessing unit that parses the control information to extract a plurality of text sets; a main part extraction unit that extracts a plurality of main parts from the acquired system diagram; and an artificial intelligence model unit that analyzes the extracted plurality of main parts and text sets to generate logic circuit diagram information and an input / output list for the logic circuit diagram.

Description

Technology Field

[0001] The present invention relates to a method and system for generating and verifying schematic diagrams and logic circuits using artificial intelligence. More specifically, the invention relates to a technology that automatically extracts key parts from a schematic diagram, parses natural language information of control items to generate a text set, automatically generates logic circuit diagrams and input / output (I / O) lists using an artificial intelligence model, detects defects in the generated circuit diagrams through scenario-based virtual operation, and iteratively improves the circuit diagrams by reflecting the findings in retraining. Background Technology

[0002] In general, in the fields of industrial control systems or building automation, it is essential to create a logic circuit diagram based on the equipment's operating conditions and control sequence, and then verify the validity of the diagram.

[0003] Traditionally, users manually created circuit diagrams by directly analyzing system diagrams and control conditions, and error detection often relied on the engineer's experience. Consequently, problems such as omissions, duplication, and conflicting conditions during the design process, or unexpected malfunctions in actual operating environments, were frequent.

[0004] A related background technology is Korean Patent Publication No. 10-1759215 (July 12, 2017).

[0005] While the aforementioned publication presents technology that supports the creation and simulation of control logic, it fails to provide functions for extracting key components based on system diagrams or analyzing control conditions based on natural language. Furthermore, it does not present a configuration for automatically detecting defects in generated logic circuit diagrams using artificial intelligence or for redesigning the circuit diagrams based on detected defects. Relying solely on such background technology, there are limitations to automatically generating and verifying highly reliable logic circuit diagrams in complex equipment control environments. The problem to be solved

[0006] The objective of the present invention to solve the above-mentioned problems is to provide a method and system for generating and verifying logic circuit diagrams using artificial intelligence. means of solving the problem

[0007] An apparatus for generating and verifying a logic circuit diagram according to embodiments (hereinafter referred to as "an apparatus according to embodiments") is disclosed. The apparatus according to embodiments may include: a data acquisition unit that acquires a system diagram and control information regarding the system diagram from a user; a data preprocessing unit that parses the control information and extracts a plurality of text sets; a main part extraction unit that extracts a plurality of main parts from the acquired system diagram; and an artificial intelligence model unit that analyzes the extracted plurality of main parts and text sets to generate logic circuit diagram information and an input / output list regarding the logic circuit diagram.

[0008] Additionally, the artificial intelligence model unit according to the embodiments may be characterized by including: a first artificial intelligence model unit that maps text data corresponding to each extracted main unit; and a second artificial intelligence model unit that receives the result mapped by the first artificial intelligence model unit and the system diagram as input, and generates the logic circuit diagram and the input / output list.

[0009] Furthermore, the device according to the embodiments may further include a defect detection unit that verifies the generated logic circuit diagram to detect one or more defects.

[0010] Furthermore, the defect detection unit according to the embodiments can detect one or more defects by generating a plurality of scenarios based on a combination of input signals input or imputed to the input / output list and virtually driving the logic circuit diagram based on the generated plurality of scenarios.

[0011] Meanwhile, the artificial intelligence model unit according to the embodiments further includes a learning unit that optimizes the first artificial intelligence model unit and the second artificial intelligence model unit; and the learning unit may perform: a step of obtaining a plurality of similar diagrams from the database; a step of generating a script for optimizing the first artificial intelligence model based on the obtained similar diagrams; a step of injecting the generated script into the first artificial intelligence model to extract a plurality of major parts; and a step of injecting a prompt into the second artificial intelligence model to command the output of detailed information regarding the extracted plurality of major parts, the similar diagrams, and each major part. Effects of the invention

[0012] The present invention according to the embodiments automatically generates and verifies a logic circuit diagram using an artificial intelligence model based on system diagrams and control information input by a user.

[0013] The present invention according to the embodiments can significantly reduce the problems of omission, duplication, and misinterpretation that occurred in the conventional manual circuit diagram creation process by automatically recognizing key parts from a schematic diagram through a first artificial intelligence model unit and mapping control conditions or semantic information corresponding to each key part based on natural language. In particular, as the recognition of key parts and text mapping are automated, even non-experts can perform reliable circuit design.

[0014] In addition, the present invention according to the embodiments provides the effect of improving the speed and accuracy of circuit diagram generation by eliminating the need for a person to directly interpret complex equipment control logic and convert it into a circuit by utilizing a second artificial intelligence model unit.

[0015] In addition, the present invention according to the embodiments can detect both primary defects (structural errors in the logic itself) and secondary defects (discrepancies with user intent) by repeatedly driving a logic circuit diagram generated by a defect detection unit based on a virtual scenario, providing much more robust safety and reliability, and can prevent equipment malfunction or unexpected control errors in advance. Brief explanation of the drawing

[0016] FIG. 1 is a drawing showing a logic circuit generation and verification system according to embodiments (hereinafter referred to as the 'system according to embodiments'). FIG. 2 is a configuration diagram showing the detailed configuration of a logic circuit generation and verification device according to embodiments (hereinafter referred to as the 'device according to embodiments'). FIG. 3 illustrates the process in which a first artificial intelligence model unit (203a) according to embodiments detects a main part and maps text data for each main part. FIG. 4 illustrates a method for training and optimizing an artificial intelligence model according to embodiments. FIG. 5 illustrates a method for a system or device according to embodiments to detect and verify defects in a logic circuit diagram. FIG. 6 is an example of a configuration diagram of a system or server according to embodiments. Specific details for implementing the invention

[0017] The present invention is susceptible to various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0018] Terms such as first, second, A, B, etc., may be used to describe various components, but the components should not be limited by these terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of multiple related described items or any of the multiple related described items.

[0019] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0020] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0021] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0022] FIG. 1 is a drawing showing a logic circuit generation and verification system according to embodiments (hereinafter referred to as the 'system according to embodiments').

[0023] Referring to FIG. 1, the system according to the embodiments generates a logic circuit diagram file using a processor (10), a database (11), and / or one or more artificial intelligence models (13) provided in the system when a user (12) provides a design schematic (12b) including a control design diagram and a control item (12a) showing a detailed description thereof.

[0024] First, according to the embodiments, the user (12) transmits to the system control matters (12a) that describe the operating conditions, state changes, control sequences, etc. of a specific facility or equipment (e.g., a control device for an air conditioning system, air conditioning and pumps, etc. in a sentence form) and a design diagram (12b) that shows the sensor placement, mechanical structure, and signal flow of the equipment.

[0025] Subsequently, the processor (10) according to the embodiments receives the control item (12a) and the design schematic (12b) through a network and can check the standardized control rule information stored in the database (11). Here, the standardized control rule information may include past reference schematics, sequence representation rules, etc.

[0026] Next, the processor (10) according to the embodiments can use an artificial intelligence model (13) to generate a logic circuit diagram of a system intended by the user (12) based on natural languages ​​included in the control item (12a) and / or a design diagram (12b), and convert it into a logic circuit diagram file.

[0027] The artificial intelligence model (13) according to the embodiments receives natural language and / or design schematic (12b) information included in control items (12a) obtained from the user (12). Based on the input information, the artificial intelligence model (13) generates and outputs a logic circuit diagram of the system intended by the user (12).

[0028] The artificial intelligence model (13) according to the embodiments can parse conditions, actuating actions, exceptions, timing sets, etc. included in the control items (12a) and automatically convert them into logic gates, comparators, timers, and state transition configurations to configure a signal flow. The artificial intelligence model (13) according to the embodiments can extract the connection relationships of physical components such as sensors, valves, and / or pumps listed in the design schematic (12b) and design a logic circuit diagram to combine with the signal flow, and derive a final logic circuit structure that does not conflict with the actual equipment structure.

[0029] Here, the logic circuit diagram output by the artificial intelligence model (13) may be source code representing a voltage application unit, a plurality of circuit modules, a plurality of gates, a plurality of function modules and the connection relationship of each gate.

[0030] A processor (10) according to the embodiments can further verify whether the input / output relationship between the sentence-unit instructions of the control item (12a) and the hardware components included in the design diagram (12b) conflicts with each other based on the logic circuit diagram information (i.e., the result) output from the artificial intelligence model (13). Here, the processor (10) according to the embodiments can query and receive a response to verification rules stored in the database (11) (e.g., mapping rules for sensors and actuators, interlock rules, safety condition rules, etc.) to verify the validity of the generated logic circuit diagram.

[0031] Specifically, the processor (10) according to the embodiments runs a plurality of simulations (e.g., sequence execution, conditional branching, exception handling flow) on the generated logic circuit diagram to primarily verify the validity of the logic circuit diagram. At this time, the processor (10) according to the embodiments may design one or more simulations including a plurality of instructions that are executed sequentially and the execution timing of each instruction by utilizing an artificial intelligence model (13) to run different simulations. Based on the one or more designed simulations, the processor (10) can verify whether the logic circuit diagram is executed appropriately.

[0032] If the above-mentioned generated logic circuit diagram does not operate effectively in a specific simulation, the processor (10) according to the embodiments can identify the corresponding simulation log and the point of error occurrence, and provide this information back to the artificial intelligence model (13) to perform a correction procedure. At this time, the artificial intelligence model (13) reinterprets the conditional branch, timer setting, gate combination, or interlock configuration where the error occurred, and automatically generates a replaceable circuit block or a modified signal path by referring to standard circuit templates and safety rules stored in the database (11). The generated modification is transmitted back to the processor (10), and the processor (10) can derive an improved logic circuit diagram by replacing or patching the error section within the existing circuit diagram. According to the embodiments, the processor (10) can repeat this error correction and replacement process multiple times to continuously perform the automatic correction function until the structural stability and operational validity of the logic circuit diagram are secured.

[0033] Subsequently, the processor (10) according to the embodiments can run a simulation on the generated logic circuit diagram multiple times to secondarily verify whether it is designed to meet the user's (12) intentions. Specifically, the processor (10) takes the conditions, actions, exceptions, and / or safety requirements specified by the user (12) in the control item (12a) as reference values ​​and compares and analyzes whether the generated logic circuit diagram satisfies the requirements. For example, if the user (12) requests that forced ventilation be performed above a certain temperature, the processor (10) changes the sensor values ​​stepwise in the simulation and verifies whether the ventilation signal occurs at the correct time. In addition, it checks whether the timer delay, operation priority, stepwise interlock conditions specified by the user (12) exactly match the operation flow of the generated circuit diagram.

[0034] The above secondary verification process is a procedure that goes beyond the logical validity of the circuit diagram itself to ensure compatibility with the control logic intended by the user, and if necessary, can request the artificial intelligence model (13) to redesign each item to automatically adjust sections that operate differently from the user requirements.

[0035] In a preferred embodiment, the processor (10) can repeatedly perform operation simulations of the circuit diagram by repeatedly calling the artificial intelligence model (13) and analyze whether there is a possibility of system malfunction under specific conditions. Subsequently, the artificial intelligence model (13) according to the embodiments can detect errors such as unexpected state transitions, operation timing conflicts, and failure to receive safety signals during the simulation process and suggest a warning message or an improved circuit block for the corresponding section to the user (12).

[0036] The database (11) according to the embodiments provides various existing accumulated circuit templates, equipment-specific standard sequences, safety regulations, industrial control rules, etc., to help the artificial intelligence model (13) generate more accurate circuit patterns. The processor (10) compares the reference circuit patterns stored in the database (11) with the circuits generated by the AI ​​to detect missing conditions, duplicate conditions and / or unnecessary loops, and automatically corrects the circuit blocks if necessary.

[0037] The system according to the embodiments generates a completed logic circuit diagram file based on the control details (12a) and design schematic (12b) provided by the user (12). The final generated logic circuit diagram file is transmitted to the user's (12) terminal device, allowing the user (12) to review it or upload it to an actual field control device to apply control logic.

[0038] According to the embodiments, the logic circuit diagram information and I / O information finally generated by the artificial intelligence model (13) and the processor (10) can be expressed in the form of code based on a specific programming language. For example, the logic circuit diagram can be output in the form of a structured script language, a functional control language, a text-based PLC instruction set, etc., and can also be converted and provided to conform to commercial tool specifications used in industrial automatic control systems, such as ladder diagrams, function blocks, and structured text. In addition, the generated I / O information can also be output in a file format that is automatically aligned according to the input / output mapping rules of the commercial tool, so that the user can upload the generated result to a control device or use it immediately for field engineering work without separate post-processing.

[0039] The system according to the embodiments enables the user to automate the generation and verification of stable logic circuit diagrams using only natural language-based control descriptions and simple design schematics, without the need to design complex control logic directly at the circuit level.

[0040] Below, a device configuration diagram of a system according to embodiments is specifically presented.

[0041] FIG. 2 is a configuration diagram showing the detailed configuration of a logic circuit generation and verification device according to embodiments (hereinafter referred to as the 'device according to embodiments').

[0042] Referring to FIG. 2, the device according to the embodiments may include a data acquisition unit (200), a data preprocessing unit (201), a key part extraction unit (202), an artificial intelligence model unit (203), a defect detection unit (204), and a database unit (11).

[0043] The data acquisition unit (200) receives control items (12a) and a system diagram (12b) from the user (12). Here, the control items (12a) may include control conditions, control steps, exception handling, time conditions, etc., described in a natural language format, and the system diagram (12b) may be an image or other file containing structural information such as the placement of sensors, wiring diagrams, and placement of pumps and / or valves of equipment and / or devices. The data acquisition unit (200) receives the two pieces of information and transmits them to a subsequent processing step.

[0044] The data preprocessing unit (201) can parse the control items (12a) input from the data acquisition unit (200) to generate and extract multiple text sets. According to embodiments, the data preprocessing unit (201) can break down conditions, actuating actions, exception situations, timing sets, etc. included in the control items (12a) into sentence units and convert them into a structured text set. Additionally, the data preprocessing unit (201) converts the system diagram (12b) into an analyzable form (e.g., image preprocessing, vector form for object recognition, string list, etc.) and prepares it to be input into the artificial intelligence model unit (203).

[0045] The key part extraction unit (202) identifies and extracts a plurality of key parts from the system diagram (12b). For example, the key part extraction unit (202) can recognize key components such as sensors, motors, valves, power units and / or pumps within the system diagram, and generate information on the relative positions, connections, and input / output ports of each component in JSON format. The generated JSON data is provided as input to the artificial intelligence model unit (203), and the artificial intelligence model unit (203) can infer a structural analysis for each key functional unit.

[0046] The artificial intelligence model unit (203) receives text sets provided by the data preprocessing unit (201) and main part JSON data provided by the main part extraction unit (202) and generates logic circuit diagram information and an input / output (I / O) list.

[0047] The artificial intelligence model unit (203) may include a first artificial intelligence model unit (203a), a second artificial intelligence model unit (203b), and a learning unit (203c).

[0048] The first artificial intelligence model unit (203a) maps text data corresponding to each main part extracted by the main part extraction unit (202). For example, it extracts control conditions corresponding to a specific pump (PUMP-A) (e.g., operation when temperature exceeds 70 degrees) and performs a primary semantic mapping between the main part and natural language text.

[0049] The second artificial intelligence model unit (203b) receives the results mapped by the first artificial intelligence model unit (203a) and the structural information of the system diagram (12b) together, and generates a logic circuit diagram and an input / output (I / O) list that reflect the actual operation of the equipment. The second artificial intelligence model unit (203b) designs a circuit structure including signal flow, condition gates, timers, comparators, interlock conditions, etc., and finally provides the circuit diagram information and the input / output list to the output unit (205).

[0050] The artificial intelligence learning unit (203c) performs learning to optimize the first artificial intelligence model unit (203a) and the second artificial intelligence model unit (203b).

[0051] The learning unit (203c) can obtain multiple similar schematic diagrams from the database unit (11), generate a script based on them, and inject it into the first artificial intelligence model unit (203a) to train it to automatically extract key parts. Additionally, the learning unit (203c) improves model precision by configuring a prompt that causes the second artificial intelligence model unit (203b) to output detailed circuit diagrams and / or input / output information based on the key parts and schematic diagram information.

[0052] The defect detection unit (204) detects one or more defects by verifying the logic circuit diagram generated by the artificial intelligence model unit (203). According to embodiments, the defect detection unit (204) can detect defects such as malfunction, non-operation, interlock error, and timing conflict by generating multiple scenarios (e.g., test cases by input combination) based on an input / output list and virtually simulating the logic circuit diagram based on the generated scenarios. Additionally, the defect detection unit (204) can transmit the discovered defect information to the user (12) or provide feedback to the artificial intelligence model unit (203) to enable automatic redesign.

[0053] The output unit (205) provides circuit diagram information and an input / output list generated by the artificial intelligence model unit (203) to the terminal device of the user (12). The user (12) can verify and review this information and, if necessary, perform re-verification or iterative improvement through the defect detection unit (204).

[0054] As described above, the device according to the embodiments illustrated in FIG. 2 enables stable and reliable logic circuit generation and verification by including control item and schematic-based natural language-structure information combination analysis, key part recognition and mapping, AI-based circuit diagram generation, automatic defect verification and learning-based redesign.

[0055] FIG. 3 illustrates the process in which a first artificial intelligence model unit (203a) according to embodiments detects a main part and maps text data for each main part.

[0056] Specifically, FIG. 3(A) illustrates a method in which a first artificial intelligence model unit (203a) according to embodiments extracts a main part from a system diagram (12b). FIG. 3(B) illustrates a method in which the first artificial intelligence model unit (203a) extracts the main part in detail. FIG. 3(C) illustrates a process in which the first artificial intelligence model unit (203a) maps text data (302) corresponding to each main part.

[0057] First, FIG. 3(A) illustrates the process of the first artificial intelligence model unit (203a) primarily identifying candidate areas that are likely to contain a main part among the entire area included in the system diagram (12b). According to the embodiments, the first artificial intelligence model unit (203a) receives image data of the system diagram (12b) and classifies objects having functional meanings within the image, such as sensors, power supply units, valves, and actuators, according to pre-learned feature values, thereby initially detecting the area (300) where the main part exists.

[0058] FIG. 3(B) illustrates the process in which the first artificial intelligence model unit (203a) extracts a main part (301) in detail according to detailed criteria within a candidate area (300). At this time, the first artificial intelligence model unit (203a) according to the embodiments comprehensively analyzes symbols, text and / or thickness, color and / or relative arrangement of electrical signal lines on the system diagram, as proposed in PPT, and can accurately separate and recognize individual main parts even when components of the same type appear redundantly. In addition, the first artificial intelligence model unit (203a) determines the boundaries and roles of the main parts by considering the connection line structure around each main part or the signal flow pattern of the same system, thereby extracting components in functional units beyond simple object detection.

[0059] FIG. 3(C) illustrates the process of a first artificial intelligence model unit (203a) according to embodiments mapping text data (302) corresponding to each extracted main unit (301). According to embodiments, the first artificial intelligence model unit (203a) infers the semantic role of the main unit based on the type, location, and surrounding signal flow of the main unit, and forms a semantic connection relationship between the main unit and the text data by selecting a sentence or control condition that is highly related to the main unit from the text set provided by the data preprocessing unit (201). For example, when a CO₂ sensor component is extracted, the first artificial intelligence model unit (203a) can automatically map text such as 'operate ventilation fan when CO₂ concentration rises'.

[0060] Furthermore, the first artificial intelligence model unit (203a) according to the embodiments may readjust the mapping accuracy based on feedback information provided from the second artificial intelligence model unit (203b) or the defect detection unit (204) when the mapping result for the main part is insufficient or when there are multiple text candidates for the same main part.

[0061] Due to this configuration, if the user (12) enters a separate requirement or comment regarding a specific main part, the first artificial intelligence model part (203a) can be configured to connect the comment (302) with the main part and consider it preferentially.

[0062] FIG. 4 illustrates a method for training and optimizing an artificial intelligence model according to embodiments.

[0063] Specifically, FIG. 4 illustrates the process of training and optimizing a first artificial intelligence model and a second artificial intelligence model according to embodiments (S100~S103), and the process of generating logic circuit diagram information and an input / output (I / O) list using the trained models (S200~S203).

[0064] That is, steps S100 to S103 shown in Fig. 4 are preliminary learning steps for enhancing the performance of the artificial intelligence model, and steps S200 to S203 are actual operation steps for applying the learned model to a real-world usage scenario to generate a logic circuit diagram and an input / output list.

[0065] First, referring to FIG. 4, steps S100 to S103 on the left represent the operation of training and optimizing the first artificial intelligence model unit (203a) and the second artificial intelligence model unit (203b).

[0066] According to the embodiments, in step S100, the learning unit (203c) obtains a plurality of similar diagrams from the database unit (11). The learning unit (203c) according to the embodiments obtains the obtained diagrams, and the diagrams obtained therefrom include learning data having a structure similar to actual user input.

[0067] In step S101, the learning unit (203c) generates a script for optimizing the first artificial intelligence model unit (203a) based on the similar diagrams. The script may include information such as prompt engineering to improve the performance of recognizing key parts, strengthening of key part extraction criteria, and rules for inferring relationships between key parts.

[0068] In step S102, the learning unit (203c) injects the script generated in S101 into the first artificial intelligence model unit (203a) to train it to automatically extract key parts from multiple similar diagrams. This step may refer to a fine-tuning process that enables the first artificial intelligence model to reliably identify objects, symbols, and / or signal line patterns within the diagram.

[0069] In step S103, the learning unit (203c) according to the embodiments can train the second artificial intelligence model unit (203b). The learning unit (203c) injects a prompt into the second artificial intelligence model unit (203b) that commands it to output the main parts extracted in S102, the entire structure of the similar system diagram, and detailed semantic information for each main part. With this configuration, the learning unit (203c) enables the second artificial intelligence model unit (203b) to learn circuit diagram structure generation rules, component connection relationships, and methods for reflecting equipment operation scenarios, and enables the generation of logic circuit diagrams and input / output lists with high precision.

[0070] Meanwhile, steps S200 to S203 shown on the right side of Fig. 4 represent the procedure for generating an actual logic circuit diagram and outputting an I / O list using a learned model.

[0071] In step S200, the data acquisition unit receives a system diagram and control information regarding the system diagram from the user. In step S201, the data preprocessing unit parses the control information to extract multiple text sets. In step S202, the main part extraction unit extracts the main parts again from the user's system diagram. Due to this operation, the system according to the embodiments supports the learned first artificial intelligence model unit (203a) to identify the main parts more accurately.

[0072] In step S203, the learned first artificial intelligence model unit (203a) and the second artificial intelligence model unit (203b) operate together, and the system according to the embodiments analyzes the text sets generated in S201 and the main parts extracted in S202, and then generates logic circuit diagram information and an input / output list of the corresponding logic circuit diagram.

[0073] Due to this configuration, the device according to the embodiments can adapt to various schematic diagram formats and control conditions, enabling the generation of stable and consistent logic circuit diagrams.

[0074] FIG. 5 illustrates a method for a system or device according to embodiments to detect and verify defects in a logic circuit diagram.

[0075] Specifically, FIG. 5 illustrates the operation of a logic circuit generation and verification device according to embodiments, which detects defects by virtually running various scenarios based on the generated logic circuit diagram, and improves the logic circuit diagram and input / output list by reinjecting the detected defect information into an artificial intelligence model.

[0076] Some or all of the operations shown in FIG. 5 can be performed in the defect detection unit (204) shown in FIG. 2.

[0077] Referring to FIG. 5, first, in step S300, the device according to the embodiments obtains an input / output list (I / O List) generated by the second artificial intelligence model unit (203b).

[0078] Subsequently, in step S301, the device according to the embodiments can generate a plurality of scenarios based on one or more inputs included in the input / output list. The scenarios can be configured by defining input values ​​that may occur in an actual control environment, such as combinations of input signals, state changes, conditional branching, and time delays, in JSON format (50), based on the generated input / output list.

[0079] Subsequently, in step S302, the device according to the embodiments virtually simulates the corresponding logic circuit diagram using each generated scenario as input and outputs the simulation result value. According to the embodiments, step S302 can be implemented as an iterative structure and sequentially executes the same simulation for all scenarios.

[0080] In step S303, it is determined whether a defect has been detected during the simulation process. The defect detection according to the embodiments includes (i) a primary defect detection (validity error of the logic itself) which determines structural errors in the logic circuit itself, such as signal collisions, interlock failures, non-fulfillment of conditions, and loop errors, and / or (ii) a secondary defect detection (verification of discrepancy with user intent) which detects sections that do not match user requirements by comparing whether conditions, actions, and exceptions described in the control item (12a) match the actual circuit operation result.

[0081] If no defect is detected (N) in step S303, the system continues to evaluate the next scenario. On the other hand, if a defect is “detected (Y)” in step S303, in step S304, the device according to the embodiments generates a feedback script containing the identifier (ID) of the scenario in which the defect occurred and simulation log information (e.g., input combination, output change over time, time of error occurrence, etc.). This feedback script may be composed of a natural language-based prompt or a structured command unit (JSON Script) so that it can be provided to the second artificial intelligence model unit (203b).

[0082] In step S305, the device according to the embodiments injects the generated feedback script into the second artificial intelligence model unit (203b). According to the embodiments, the second artificial intelligence model unit (203b) can reanalyze the error occurrence section of the logic circuit diagram based on the script and infer on itself the parts that need to be supplemented in the connection structure between key parts, conditional branching, timer operation, etc.

[0083] Finally, in step S306, the second artificial intelligence model unit (203b) improves the logic circuit diagram and input / output list by reflecting the feedback information. During this process, circuit modification plans to resolve defects such as incorrect conditional branching, non-implementation of interlocks, and timing errors may be automatically generated, and if necessary, the main part text mapping or control condition analysis may be performed again to rearrange the entire structure.

[0084] As described above, through the scenario-based virtual driving and defect detection procedure illustrated in FIG. 5, the device according to the embodiments can repeatedly verify the stability, safety, and suitability of the user's intent of the generated logic circuit diagram, and can provide a high-precision circuit diagram through automatic redesign.

[0085] Furthermore, the system according to the embodiments can automatically generate a feedback script based on the scenario in which a defect is detected and related log information, and inject it into a second AI model to continuously improve the logic circuit diagram and the I / O list. Due to such a fine-tuning loop structure, the system according to the embodiments enables the AI ​​model to improve its precision as it adapts to the actual facility environment, and provides the effect of allowing the user to perform advanced circuit design without separate professional operation.

[0086] FIG. 6 is an example of a configuration diagram of a system or server according to embodiments.

[0087] Referring to FIG. 6, the server (600) includes an input unit (610), an output unit (620), a control unit (630), a storage unit (640), and a communication unit (650).

[0088] The input unit (610) receives commands or information from the manager. The input unit (710) may include one or more of a microphone and a key input unit for receiving audio signals.

[0089] The output unit (620) outputs command processing results or various information to the administrator. For example, the output unit (620) outputs result information of the logic circuit generation and verification device (1). To this end, the output unit (620) may include a display, a speaker, a haptic output unit (620), and a light output unit (620), although these are not shown in the drawings. The display may be provided in a flat panel display, a flexible display, an opaque display, a transparent display, electronic paper (E-paper), or any form well known in the technical field to which the present invention belongs. A touch pad may be laminated on the display to form a touch screen, and a touch key may be implemented through such a touch screen. In addition to the display and speaker, the output unit (620) may be configured to include any form of output means well known in the technical field to which the present invention belongs.

[0090] The control unit (630) connects and controls the components within the server (600). For example, it controls each component so that the result of the logic circuit generation and verification device (1) (e.g., a logic circuit diagram and / or a schematic diagram as a final result) can be output through the output unit (620). For another example, when judgment information is input by a manager, the control unit (630) generates a response signal containing the judgment information. The control unit (630) may be configured to include a CPU (Central Processing Unit), MPU (Micro Processor Unit), MCU (Micro Controller Unit), GPU (Graphic Processing Unit), or any type of processor well known in the art of the present invention.

[0091] The storage unit (640) stores data, programs, and applications necessary for the server (600) to operate. This storage unit (640) may include non-volatile memory, volatile memory, a hard disk, an optical disk, a magneto-optical disk, or any type of computer-readable recording medium well known in the art to which the present invention belongs.

[0092] The communication unit (650) communicates with a logic circuit generation / verification system or another system through a wired / wireless network.

[0093] The embodiments of the present invention disclosed in this specification and drawings are provided merely as specific examples to facilitate the explanation of the technical content of the present invention and to aid in understanding the present invention, and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other variations based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein.

[0094] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A device for generating and verifying a logic circuit diagram, comprising: a data acquisition unit that acquires a system diagram and control information regarding the system diagram from a user; a data preprocessing unit that parses the control information to extract a plurality of text sets; a main part extraction unit that extracts a plurality of main parts from the acquired system diagram; and an artificial intelligence model unit that analyzes the extracted plurality of main parts and text sets to generate logic circuit diagram information and an input / output list for the logic circuit diagram; wherein the artificial intelligence model unit comprises: a first artificial intelligence model unit that maps text data corresponding to each extracted main part; a second artificial intelligence model unit that receives the result mapped by the first artificial intelligence model unit and the system diagram as input to generate the logic circuit diagram and the input / output list; and a learning unit that optimizes the first artificial intelligence model unit and the second artificial intelligence model unit. A logic circuit diagram generation and verification device further comprising, wherein the learning unit performs: a step of obtaining a plurality of similar diagrams from a database unit; a step of generating a script for optimizing a first artificial intelligence model unit based on the obtained similar diagrams; a step of injecting the generated script into the first artificial intelligence model unit to extract a plurality of key units; and a step of injecting a prompt into the second artificial intelligence model unit to command the output of the extracted plurality of key units, the similar diagrams, and detailed information regarding each key unit. Claim 2 delete Claim 3 The logic circuit generation and verification device according to claim 1 further comprises a defect detection unit that verifies the generated logic circuit and detects one or more defects. Claim 4 A logic circuit generation and verification device according to claim 3, wherein the defect detection unit generates a plurality of scenarios based on a combination of input signals input to the input / output list, and detects one or more defects by virtually driving the logic circuit based on the generated plurality of scenarios. Claim 5 delete

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