Automatic defect detection in micromachining

Abstract

The method comprises the steps of: collecting first process processing tool machine data from a first process processing tool while processing a semiconductor substrate, wherein the first process processing tool machine data includes process data and operation codes associated with one or more discrete time intervals during processing; training a first neural network with the first process processing tool machine data from the first process processing tool; and generating a first output from the first neural network indicating a defect of the first process processing tool based on applying subsequent machine data from at least one process processing tool, at least partially.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 180,907 filed on April 28, 2021, the entire contents of which are incorporated herein by reference.

[0003] The present invention generally relates to micro-machining technology, and specifically, in an embodiment, to automatic defect detection in micro-machining. Background Technology

[0004] Semiconductor device manufacturers face the ongoing challenge of producing semiconductor devices in the shortest possible time at the lowest possible production cost. One method to reduce device production time and costs is to minimize errors and defects in semiconductor process tools. Defects in semiconductor tools, such as reactive ion etching chambers or robotic wafer tracking systems, can result in semiconductor wafer(s) being processed incorrectly and subsequently discarded. This leads to increased material costs and, consequently, higher overall production costs. Furthermore, if semiconductor tools fail or are in a defective state, wafer operations may be halted. This results in a temporary, unscheduled suspension of semiconductor process processing, which can lead to increased processing time. means of solving the problem

[0005] According to an embodiment of the present invention, the method comprises: collecting first process processing tool machine data from a first process processing tool while processing a semiconductor substrate, wherein the first process processing tool machine data includes process data and operation codes associated with one or more discrete time intervals during processing; training a first neural network with the first process processing tool machine data from the first process processing tool; and generating a first output from the first neural network indicating a defect of the first process processing tool based on applying subsequent machine data from at least one process processing tool, at least partially.

[0006] According to another embodiment of the present invention, a tool system comprises: a processor; a non-transient memory coupled to the processor and having a program executed on the processor, wherein the program comprises: collecting first process processing tool machine data from a first process processing tool while processing a semiconductor substrate, the first process processing tool machine data including process data and operation codes associated with one or more discrete time intervals during processing; training a first neural network with the first process processing tool machine data; and, at least partially, an instruction for generating a first output indicating a defect from the first neural network based on applying subsequent machine data from at least one process processing tool.

[0007] According to another embodiment of the present invention, the method comprises the steps of: initializing a neural network in a processor of a first machine learning system coupled to a first semiconductor process processing tool for process processing a wafer; training the neural network to predict failures of the first semiconductor process processing tool; storing the neural network in the memory of the first machine learning system after training the neural network; and implementing the first machine learning system in a second semiconductor process processing tool. Brief explanation of the drawing

[0008] For a more complete understanding of the present invention and its advantages, the following description, together with the accompanying drawings, will now be referred to. FIG. 1 illustrates a block diagram showing a micro-processing defect prediction system according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a machine learning system according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an exemplary neural network implemented in a machine learning system according to an embodiment of the present invention. FIGS. 4a through 4e illustrate intermediate steps of acquiring, accumulating, and formatting machine data for input to a neural network according to an embodiment of the present invention, FIG. 4a illustrates the collected and accumulated machine data and optional code, FIG. 4b illustrates the first formatted machine data for use in a learning phase, FIG. 4c illustrates the second formatted machine data for use in a learning phase, FIG. 4d illustrates the first additional formatted machine data for use in a usage phase, and FIG. 4e illustrates the second additional formatted machine data for use in a usage phase. FIG. 5 is a flowchart illustrating an exemplary process flow used to learn and utilize a neural network for micro-machining tool defects according to an embodiment of the present invention. FIG. 6 is a flowchart illustrating an exemplary process flow used to implement a neural network learned in an additional micro-machining tool used to predict the defect state of the additional micro-machining tool according to an embodiment of the present invention. FIG. 7 illustrates a block diagram showing a defect prediction system according to an embodiment of the present invention. FIG. 8 illustrates a block diagram showing a micro-processing defect prediction system according to an embodiment of the present invention. Specific details for implementing the invention

[0009] The configuration and use of embodiments of the present disclosure are described in detail below. However, it should be understood that the concepts disclosed herein may be embodied in a wide variety of specific details, and that the specific embodiments described herein are merely illustrative and do not limit the scope of the claims. It should also be understood that various modifications, substitutions, and changes may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims. Although the present disclosure is described in the context of semiconductor process processing, the embodiments of the present disclosure generally apply to all microfabrication technologies for any manufacturing line for processing small structures at a sub-micrometer scale. Examples of such microfabrication technologies include integrated circuit fabrication, microelectromechanical systems (MEMS), microfluidic / lab-on-a-chip, optical MEMS, RF MEMS, Power MEMS, BioMEMS, nanoelectromechanical systems, etc.

[0010] Increased material costs for semiconductor materials due to wafer scrap caused by defects in semiconductor process tools are a common problem associated with semiconductor processing. Semiconductor tool process defects can lead to situations where improperly processed wafer(s) must be discarded, thereby increasing production costs.

[0011] The inventors of the present invention have discovered that one method for preventing wafer scrap is to use artificial intelligence algorithms to predict wafer processing defects and to stop / modify the wafer processing tool from the wafer operation before an error occurs. Generally, during microfabrication, semiconductor processing tools continuously generate a large amount of complex data related to tool performance, such as temperature, pressure, various currents and voltages, and the ratio of specific materials. Machine data, such as tool performance data and measured in-situ tool data, is continuously collected during processing. Even slight changes in machine data variables can lead to tool defects. Due to the large amount of data related to the performance of processing tools and the accuracy required in microfabrication, there exist interrelationships between machine data variables that can lead to failure. However, the interrelationships between machine data variables may not be clear relationships that can be mathematically modeled to predict potential failures.

[0012] The embodiments described herein relate to a method and system for predicting micro-machining tool defects using an artificial intelligence (AI)-based algorithm. The AI-based algorithm is trained to understand the interrelationships between machine data variables and potential failures. Based on this trained AI-based algorithm, tool failures can be predicted and corrected before the tool incorrectly processes the wafer.

[0013] FIG. 1 illustrates a block diagram showing a micro-processing defect prediction system (100) according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor prediction system (100) may include a semiconductor process processing tool (120) coupled to an AI-based tool such as a machine learning (ML) system (130), and the AI-based tool may additionally be coupled to a semiconductor process processing tool controller (110).

[0014] The semiconductor process processing tool (120) may include any tool used in a microfabrication process, such as an annealing tool, a deposition tool, a coating / developing tool, an etching tool, a surface preparation tool, a lithography tool, an ion implantation tool including a gas cluster ion beam tool, a wafer tracking system, various chambers, a robotic wafer handler, testing equipment particularly an on-site testing tool, or any other semiconductor process processing tool known in the art. Additionally, as used herein, a semiconductor process processing defect is defined as a state in which the normal operation of the semiconductor process processing tool is temporarily interrupted and / or, as a result, the wafer(s) are processed incorrectly.

[0015] In various embodiments, the semiconductor process processing tool controller (110) may include a microcontroller, a computer, a microprocessor, or other process processing circuit elements.

[0016] In various embodiments, the machine learning (ML) system (130) may include any machine learning system including a deep learning algorithm. In one example, the machine learning system may include a neural network-based deep learning algorithm.

[0017] In several embodiments, the ML system (130) may include at least one neural network implemented in software, which may also include different software modules. In one or more embodiments, the machine learning (ML) system (130) may further include software modules such as a data processor (135) and a defect detector (150), all of which are coupled to the neural network (140). In several embodiments, the data processor (135), the neural network (140), and the defect detector (150) may be implemented as further described in FIG. 2.

[0018] In various embodiments, the semiconductor process processing tool (120) may be further coupled to a sensor (122) and a state detector (124). Both the sensor (122) and the state detector (124) may be included in or coupled to the semiconductor process processing tool (120).

[0019] In one or more embodiments, the sensor (122) may include a plurality of sensors configured to measure field-in-the-ground tool data and output it to the data processor (135). Examples of the sensor (122) may include a temperature sensor, a pressure sensor, a flow meter spectroscopic analysis tool, a current / voltage sensor, etc. These will be described in more detail below.

[0020] In one or more embodiments, the state detector (124) may be equipment configured to determine the state of the semiconductor tool (120) and output a corresponding operation code to the data processor (135). Furthermore, this will be explained in more detail below.

[0021] Before being coupled to a semiconductor process controller (110) and used to predict tool defects, the neural network (140) may be trained. In one or more embodiments, during training, the neural network (140) learns on its own how to predict tool defects while the semiconductor process tool (120) processes the wafer.

[0022] As illustrated in FIG. 1, machine data and operation codes can be collected and accumulated by a data processor (135). In several embodiments, machine data may include process data generated by a semiconductor process processing tool (120). Process data may refer to values ​​of process parameters that can be controlled by a semiconductor process processing tool user from the time wafer process processing begins until the present time. Examples of process data may include all process recipes, such as temperature, pressure, and flux of various gases introduced into the process tool, but are not limited thereto.

[0023] In some embodiments, machine data may further include measured in-situ tool data output by the sensor (122). The measured in-situ tool data may refer to data measured by the sensor (122) that occurs as a result of process data. In one or more embodiments, the measured in-situ tool data may refer to any measured process parameter from the time wafer process processing started in the semiconductor process processing tool (120) up to the present time. Accordingly, the measured in-situ tool data may include values ​​of process data and / or wafer measurement data that are measured and monitored, such as wafer temperature, wafer position, stator voltage, current / voltage at different nodes within the circuit elements of the process processing tool (120), and other characteristics that are continuously or periodically monitored.

[0024] In some embodiments, machine data may additionally include ex-situ data acquired by sensors outside the tool. For example, ex-situ data may include measurements from a bulk transfer system, a vacuum system, a relaxation system, and / or process processing time-window conditions for a substrate transferred between tools as part of a manufacturing process. An operation code may be generated by a state detector (124). The operation code may indicate whether the semiconductor process processing tool (120) has reached a fault state for a time or condition, and / or may include a code and / or message indicating the state of the semiconductor process processing tool (120). For example, the operation code may include an error code / message when the semiconductor process processing tool has reached a fault state, or a code / message indicating that the tool is in normal operation or that the tool has exceeded a threshold value indicating the state or condition of the tool. In one or more embodiments, process data, measured in-situ data, measured ex-situ data, and operation code may be generated on the same time scale.

[0025] The way the data processor (135) collects and accumulates data depends on whether the neural network (140) is in the learning phase or the usage phase. During the learning phase, the neural network (140) is trained, while during the usage phase, the neural network (140) predicts, for example, the state of the semiconductor process processing tool (120) regarding an impending defect.

[0026] In several embodiments, the neural network (140) may be trained to predict the state of the semiconductor process tool (120) using supervised learning before a defect actually occurs. During supervised learning, the neural network (140) estimates or constructs a function from training data containing a dataset of training examples. Each example typically includes an input object and a desired output value. The supervised learning algorithm analyzes the training data and generates an estimation function that can be used to map new examples. An optimal scenario would allow the algorithm to accurately determine class labels for unseen cases. This requires a learning algorithm to generate new situations from the training data. The learning steps include determining the type of training example, collecting data for the training example, determining the structure of the learning function, determining how to represent the input to the learning function, running the learning algorithm to develop an initial learning function, and evaluating the accuracy of the learning function and retraining or optimizing the learning function to improve the accuracy of the prediction. Each of these steps will be described in more detail below.

[0027] In supervised learning, the neural network (140) can learn how to predict an output by receiving an input mapped to (or labeled as an expected output) the expected output. Subsequently, based on the difference between the output predicted by the neural network (140) and the mapped input, the neural network (140) can update itself. Thus, in one or more embodiments, during learning, the data processor (135) may be configured to continuously acquire and accumulate machine data and to map the machine data to a future operation code (i.e., an expected output). In other words, during learning, when the semiconductor process processing tool is operated, the data processor (135) continuously acquires and accumulates machine data and operation codes. Subsequently, as the data processor (135) acquires and accumulates machine data and operation codes, the data processor formats the machine data into each formatted machine data containing machine data collected over each multiple period, determines the operation code existing in the next period for each formatted machine data, maps each determined operation code to each individual formatted machine data, and can use the mapped machine data as a learning input. This process will be described in more detail below.

[0028] Advantageously, the machine learning (ML) system (130) generates "self-labeled" mapped machine data for training the neural network (140). One advantage of this is that, generally, labeling training data is done manually, which can be time-consuming and costly, or using a database with a finite amount of data. The self-labeled training data enables the neural network (140) to be trained continuously while the semiconductor process processing tool (120) processes the wafer.

[0029] Advantageously, by self-labeling of the data, embodiments of the present invention can overcome the need for a large dataset typically required for training a neural network. For example, in several embodiments, during the regular operation of the process processing tool (120), training data (e.g., machine data and operation codes) is continuously collected and can grow sufficiently large over a period of time to provide a meaningful starting point for training the neural network.

[0030] Referring again to FIG. 1, in one or more embodiments, a first neural network (140) configured to predict the defect state of a semiconductor process processing tool (120) is created after sufficient learning. Accordingly, the ML system (130) can be additionally coupled to a semiconductor process processing controller (110). The semiconductor process processing controller (110) can be coupled to or included in the semiconductor process processing tool (120).

[0031] In various embodiments, during the usage phase, a plurality of unmapped machine data formatted by the data processor (135) may be continuously supplied to the neural network (140). Each unmapped machine data, i.e., machine data output by the process processing tool after sufficient learning, may correspond to a period in which each period is equal in length to the period used in learning. The neural network (140) generates an output supplied to the defect detector (150) based on the learning. The defect detector (150) determines whether a defect will occur in the immediately adjacent period for each machine data based on the output of the neural network (140). Subsequently, the output of the defect detector (150) may be supplied to the semiconductor process processing tool controller (110) and may notify the user of the future state of the tool. If the output of the defect detector (150) indicates a possible defect, the semiconductor process processing tool controller (110) can generate a control signal to stop the operation of the wafer prior to the defect, notify the person in charge, or take a series of pre-programmed measures to avoid the possible defect. Advantageously, this prevents wafer scrap before it occurs and allows corrective measures, such as adjusting process processing parameters, to be taken before the defect occurs.

[0032] In several embodiments, the semiconductor process processing tool controller (110) and the machine learning (ML) system (130) may be integrated into one system, and in some embodiments, they may be integrated into one system together with the semiconductor process processing tool (120).

[0033] FIG. 2 illustrates a block diagram of an exemplary ML system (130) for carrying out the method described herein according to an embodiment of the present invention.

[0034] As illustrated, the machine learning (ML) system (130) includes a memory (210), a processor (220), and an interface (230) that may or may not be placed as illustrated in FIG. 2.

[0035] The processor (220) may be any component or set of components configured to perform operations and calculations of the ML system (130). In one or more embodiments, to increase the throughput of the ML system, the processor (220) may be implemented with multiple large-scale graphics processing units (GPUs). For example, each individual calculation of the neural network may be performed independently by multiple parallel GPUs, thereby reducing the overall process processing time. In another embodiment, the processor (220) may be implemented as an AI supercomputer including a GPU multicluster.

[0036] In various embodiments, to increase the processing speed of the ML learning system (130), the processor (220) may also be implemented as a plurality of FPGAs (flexible programmable logic arrays) or ASICs (application-specific integrated circuits).

[0037] In various embodiments, the processor (220) may be implemented as a central AI supercomputer comprising a GPU multicluster that can be connected to a plurality of semiconductor process processing tools. In other words, the processor (220) may be a central processor implemented to support a plurality of ML systems (130). For example, machine data collected by a plurality of ML systems (130) implemented on different semiconductor process processing tools may be transmitted to a central GPU multicluster supercomputer.

[0038] The memory (210) may be any component or set of components configured to store instructions executed by a neural network, programming, and / or processor (220). In one or more embodiments, the memory (210) comprises a non-transient computer-readable medium. In several embodiments, the computer-readable medium memory may comprise a non-transient mechanism for storing machine-readable information, including ROM (read-only memory), RAM (random access memory), magnetic disk storage medium, optical storage medium, flash-memory device, solid-state storage medium, etc.

[0039] In various embodiments, the data processor (135), neural network (140), and defect detector (150) may be implemented as a program stored in memory (210), which is then executed in the processor (220).

[0040] Advantageously, in one or more embodiments, after the neural network (140) is trained for the semiconductor process processing tool (120), the neural network (140) may be stored in the memory (210) of the ML system (130). One advantage of this is that the trained neural network may be implemented in an additional ML system that can be coupled to an additional process processing tool. In one or more embodiments, the additional ML system may be coupled to an additional process processing tool that is of the same type as the semiconductor process processing tool (120) without additional training. In one or more embodiments, the trained neural network may be implemented in an additional semiconductor process processing tool located in the same manufacturing facility or a different manufacturing facility.

[0041] In another embodiment, the additional semiconductor process processing tool may be a different type of process processing tool that shares some features with the semiconductor process processing tool (120). When the additional semiconductor process processing tool is one of different types, the neural network may be additionally trained during the operation of the additional process processing tool. In this way, the neural network may be additionally trained for the additional semiconductor process processing tool.

[0042] The interface (230) may be any component or set of components that enable the ML algorithm (130) to communicate with other devices / components, such as a semiconductor process processing tool controller (120). For example, in one or more embodiments, the interface (230) may be configured so that the ML system (130) can communicate with the semiconductor process processing tool controller (110) to instruct the semiconductor process processing tool controller (110) to stop the operation of the wafer prior to failure of the semiconductor process processing tool (120). In another embodiment, the interface (230) may be additionally configured to communicate with a display to notify the user of the predicted state of the tool. The ML system (130) may include additional components not shown in FIG. 2, such as a long-term storage unit (e.g., non-volatile memory, etc.).

[0043] FIG. 3 is a diagram illustrating an exemplary neural network implemented in a machine learning system according to an embodiment of the present invention.

[0044] FIG. 3 illustrates a simplified diagram of a feed-forward multi-layer neural network (300) that can be implemented in a machine learning (ML) system (130). The neural network (300) includes an input layer (310) comprising an input node (320), at least one hidden layer (330) comprising a hidden node (340), and an output layer (350) comprising an output node (360). There is no limit to the number of input nodes (320), hidden layers (330), hidden nodes (340), and output nodes (360). Accordingly, any suitable number of input nodes (310), output nodes (350), and hidden layers (330) may be used. Although FIG. 3 illustrates a single neural network, the ML system (130) may include multiple neural networks.

[0045] The neural network (300) operates as a feed-forward neural network, which means that data always travels through the neural network (300) in one direction (e.g., forward). In other words, the neural network (300) operates by receiving input (i.e., machine data) at an input node and outputting a prediction (i.e., future state of the process processing tool) in relation to the probability of a result at an output node. In one or more embodiments, the neural network (300) may include output nodes for all possible operation codes of the semiconductor process processing tool (120). In another embodiment, there may be two output nodes, one node may output the probability that a defect will occur and the other output node may output the probability that a defect will not occur. The number of input nodes and output nodes is not limited by this disclosure.

[0046] Although a feedforward neural network is described herein, the neural network (300) may be any type of suitable neural network. For example, the neural network (300) may include other types of neural networks such as a recurrent neural network (RNN) or a convolutional neural network (CNN). The type of neural network used is not limited by this disclosure.

[0047] As illustrated in FIG. 3, the input nodes (320) and each successive layer are connected using weighted connections (315). Each weighted connection (315) includes a unique weight that determines how the input relatively affects the output. The weight value corresponding to each weighted connection (315) is the knowledge structure of the neural network (300). Here, learning and / or learning is defined as any self-directed change of the knowledge structure of the neural network (300) that improves performance.

[0048] Each hidden node (340) implements a non-linear mathematical activation function that generates a learning function by applying a set of weights to the input. In one or more embodiments, each of the hidden nodes (340) may apply the same non-linear activation function. In other embodiments, the hidden nodes (340) may apply different non-linear activation functions. For example, the non-linear activation function may be a sigmoid function, a ReLU function, or any other known non-linear activation function known in the art.

[0049] As described above, the neural network (300) can be trained using labeled training data (i.e., machine data mapped to subsequent action codes). This is known as supervised learning. A supervised learning algorithm requires determining the format of the training data before labeling the training data. In various embodiments, the format of the training data may be based on the structure of the training function. In other words, the training data must be compatible with the training function. Examples of training functions may include, without limitation, support vector-based training functions and decision tree-based training functions.

[0050] For example, in several embodiments, where the learning function is a support vector-based learning function, machine data (e.g., training data) may be formatted as an n-dimensional vector of numerical features to represent machine data known as feature vectors. In one or more embodiments, the machine data may be formatted as a feature vector containing raw values ​​of machine data or as an image having feature vector values ​​containing pixel values ​​of an image.

[0051] Next, in several embodiments, after determining the format of the learning data and the learning function, random weights may be assigned to each weighted connection (315), and the learning function may be initialized. In one or more embodiments, after the initialization of the learning function, during the operation of the semiconductor process processing tool (120), mapped ("self-labeled") machine data formatted by the data processor (135) may be supplied to the neural network and used to update the learning function. In other words, based on the relationship between the learning data and each of its mappings, the neural network learns, self-updates the learning function, and, after sufficient learning, creates a model for predicting the output based on the input without the mapping.

[0052] Semiconductor process processing tools continuously generate a large amount of complex data. This can result in unrecognizable relationships between tool process processing performance variables. Even very minute changes within machine data values ​​can lead to process failure. Therefore, in one or more embodiments, a neural network (300) can be trained using a group of learning / learning techniques that utilize pattern association, such as back propagation. The purpose of pattern association learning is to map output patterns to input patterns. Pattern association learning techniques provide the neural network (300) with a set of rules and instructions to self-adjust the learning function in response to outputs generated from mapped inputs. In other words, the neural network (300) has the ability to autonomously update itself as it receives mapped inputs and improves its performance.

[0053] Advantageously, pattern association learning enables the neural network (300) to detect patterns between relationships of machine data values. One advantage of this is that the neural network (300) can learn and recognize patterns between machine data input values ​​that an expert might not be able to perceive.

[0054] FIGS. 4a through 4e illustrate intermediate steps of acquiring, accumulating, and formatting machine data to be input into a neural network according to an embodiment of the present invention, FIG. 4a illustrates the collected and accumulated machine data and operation code, FIG. 4b illustrates the first formatted machine data to be used in the learning step, FIG. 4c illustrates the second formatted machine data to be used in the learning step, FIG. 4d illustrates the first additional formatted machine data to be used in the usage step, and FIG. 4e illustrates the second additional formatted machine data to be used in the usage step. FIG. 5 is a flowchart illustrating an exemplary process flow used to train and utilize a neural network to predict semiconductor process processing tool defects according to an embodiment of the present invention.

[0055] FIG. 4a illustrates an example of the output of a semiconductor process processing tool (400) that may be similar to the semiconductor process processing tool (120) described above. As illustrated in FIG. 4a, in one or more embodiments, the output of the semiconductor process processing tool (400) may include machine data (404) and operation code (402). As described above, the machine data (404) may include process processing data generated by the process processing tool (120) and / or in-site tool data measured by the sensor (122). The machine data (404) is d0 to d nIt can be defined as a plurality of machine data values ​​indicated by. The operation code (402) may include the state of the semiconductor process processing tool (120) (e.g., whether it is in a defective state) along with a corresponding code / message indicating the state of the tool. For example, the corresponding code / message may indicate substrate position, pressure, robot speed, stator voltage, temperature, or others. As illustrated in FIG. 4a, the output of the semiconductor process processing tool (400) is continuously output with a time interval (406). For example, the output of the semiconductor process processing tool (400) may be output continuously or after periodic intervals.

[0056] In various embodiments, as also described in connection with FIGS. 4a and 4b, machine data may be generated over a plurality of periods during the operation of the first semiconductor process processing tool (120) (block (502)), and each of the plurality of machine data includes process data of the process processing tool during operation over each of the plurality of periods.

[0057] Next, an operation code may be determined for each period immediately following each machine data (block (504)). Specifically, a plurality of operation codes are determined, and each of the plurality of operation codes follows an associated period among the plurality of periods for each of the plurality of machine data. Each of the plurality of operation codes is temporally separated from an adjacent operation code among the plurality of operation codes by at least one period. For example, refer to the description of the relationship between the first period (412) and the second period (414) and the operation code (410), which is further described below using FIG. 4b.

[0058] FIG. 4b illustrates an example of first machine data (408) formatted for input to a neural network (140) when the machine learning (ML) system (130) is in the learning phase. As illustrated in FIG. 4b, the data processor (135) collects and accumulates the output of the semiconductor process processing tool (400) during operation. In one or more embodiments, when the output of the semiconductor process processing tool (400) is collected and accumulated, the data may be divided by period. In the example illustrated in FIG. 4b, the output of the semiconductor process processing tool (400) may be divided into a first period (412) and a second period (414). In several embodiments, the second period (414) may begin immediately after the end of the first period (412). The lengths of the first period (412) and the second period (414) may range from a few minutes (e.g., 10 minutes) to a few days (e.g., 2 days). The durations of the first period (412) and the second period (414) may be the same duration or different durations.

[0059] In several embodiments, as described above, the method of formatting machine data is based on the structure of the learning function. In one or more embodiments, as described above, if the learning function is a support vector-based learning function, the machine data may be formatted as a feature vector. For example, in one or more embodiments, the machine data may be converted into an image. Subsequently, the image may be formatted as a feature vector.

[0060] Referring again to the exemplary example of FIG. 4b, in one or more embodiments, machine data collected over a first period (412) can be converted into a first machine data image. The size of the first machine data image can be defined by multiplying its length (l) within a pixel by its width (w). The length (l) within a pixel of the machine data image may be equal to the number of time intervals included in the first period. The width (w) within a pixel of the first machine data image is the machine data value (d n It may be equal to the number (n) of ). Subsequently, the first data machine image may be formatted as a feature vector of size lxw that is filled with values ​​corresponding to the pixel values ​​of each machine data variable within the first period (412).

[0061] In another embodiment, the first machine data (408) can be formatted as a feature vector filled with raw machine data values.

[0062] After formatting the first machine data (408), operation code(s) (410) existing within the second period (414) can be determined (block (504)). When using the first machine data (408) as input and each operation code (410) as output, the operation code (410) can be mapped to the first machine data (408). This results in the first "self-labeled" machine data input to the neural network (140) for learning (block (506)).

[0063] Next, after inputting the first machine data (408) mapped to the first operation code (410) into the neural network (140), the first period (412) and the second period (414) can be time-shifted by an equal amount of time. Additional machine data can be mapped to each operation code corresponding to the time-shifted period and can be used to train the neural network (140) using the aforementioned process.

[0064] FIG. 4c illustrates an example of second machine data (416) formatted for input to a neural network (140) when the machine learning (ML) system (130) is in the learning phase.

[0065] Next, as described more specifically with respect to FIG. 4c, the neural network can be trained using machine data as inputs mapped to each operation code as outputs to generate a neural network trained for a process processing tool (block (506)), and each of the multiple inputs is mapped to multiple outputs based on multiple periods.

[0066] Referring to FIG. 4c, the second machine data (416) is formatted by the data processor (135) and mapped to each operation code (418) (e.g., labeled). The second machine data (416) can be formatted by time-shifting the first period (412) and the second period (414) by an equal amount of time. After time-shifting the first period (412) and the second period (414), the second machine data (416) is formatted by filling the second feature vector with machine data contained in the time-shifted first period (420) using the same process as described in FIG. 4b.

[0067] After generating the second machine data (416), the data processor (135) can determine the operation code (418) present in the time-shifted second period (422). Subsequently, when using the second machine data (416) as input and each operation code (418) as output, the operation code (418) can be mapped to the second machine data (416) and supplied to the neural network (140). This process can be repeated using a predetermined number of machine data until the neural network (140) is sufficiently trained. This can form a first trained neural network for the semiconductor process processing tool (120).

[0068] In several embodiments, after creating a first neural network with a predetermined number of machine data mapped to corresponding operation codes, the performance of the first neural network can be tested to determine whether the first neural network has been sufficiently trained. In one or more embodiments, the first neural network can be tested by inputting a series of machine data not mapped into the first neural network and comparing the output of the defect detector (150) with a known operation code. As described above, the first neural network can output a set of probabilities corresponding to each operation code. Subsequently, based on the probabilities output by the first neural network, the defect detector (150) can predict future operation codes of the semiconductor process processing tool (120). Accordingly, the output with the highest probability is considered to be the prediction of the first neural network. In one or more embodiments, when the output of the neural network for the unmapped machine data used during testing predicts an appropriate output having a minimum threshold probability, the first neural network is sufficiently trained for the semiconductor process processing tool (120). The minimum threshold probability can be set by the user and, for example, can be within the range of 90% to 98%.

[0069] If the output during testing does not satisfy the required threshold probability, the first neural network may be further trained using the process described in FIGS. 4a through 4c on another predetermined number of mapped machine data. For example, during retraining, the neural network (140) and / or duration, e.g., the first duration (412) and the second duration (414), may be modified. In some embodiments, a number of neural networks may be generated in parallel (or sequentially) to save time until a satisfactorily trained neural network having the desired threshold probability is obtained.

[0070] In several embodiments, a first neural network trained for a semiconductor process processing tool (120) may be stored in the memory (210) of an ML system (130). The ML system (130) may then be implemented in an additional semiconductor process processing tool. In one or more embodiments, if the additional semiconductor process processing tool is a tool of the same type as the semiconductor process processing tool (120), significant additional training may not be required. In other embodiments, if the additional semiconductor process processing tool is a different type of process processing tool, the neural network may be additionally trained using the process described in FIGS. 4a through 4c. This may result in an additional neural network trained for the additional semiconductor process processing tool.

[0071] Referring to FIG. 4d, after generating a first neural network for a semiconductor process processing tool (120), the first neural network can be coupled to a semiconductor process processing tool controller (110) and used to generate an output indicating a defect in the tool (block (508)). As described above, during operation, the data processor (135) can continuously collect and accumulate additional machine data and format the additional machine data. In several embodiments, the additional machine data may not be mapped and may correspond to machine data collected over a plurality of additional periods. In several embodiments, the additional periods may have the same duration as the first period.

[0072] Referring again to FIG. 4d, first additional machine data (424), including machine data accumulated over a first additional period (426), may be supplied to the first neural network. The first neural network may output a probability of the future state of the tool to the defect detector (150) based on its learning. Based on the output of the first neural network, the defect detector (150) may notify the semiconductor process processing tool controller (110) and the user that the semiconductor process processing tool (120) is reaching a defective state. If the defect detector (150) determines that the semiconductor process processing tool (120) is reaching a defective state, the defect detector transmits a signal to the semiconductor process processing tool controller (110) and the user and stops the wafer operation. Advantageously, this allows the user to adjust the process parameters that cause the defect and prevents wafer scrap.

[0073] Referring to FIG. 4e, a first additional period (426) may be shifted, and a second additional machine data (430) corresponding to the machine data accumulated over the time-shifted first additional period (432) may be formatted and used to predict semiconductor process processing tool defects. This process may be repeated until process processing is completed.

[0074] In several embodiments, the machine learning (ML) system (130) may include a plurality of neural networks trained in parallel. When a plurality of neural networks are used, each neural network is trained with mapped machine data generated over periods of different sizes. For example, when two neural networks are used, one neural network may be trained with machine data generated over a shorter period than the other neural network. Advantageously, this allows a plurality of neural networks to be trained to determine the optimal machine data dimensions for the semiconductor process processing tool (120).

[0075] FIG. 6 is a flowchart illustrating an exemplary process flow used to implement a neural network learned in an additional semiconductor process processing tool used to predict the defect state of an additional semiconductor process processing tool according to an embodiment of the present invention.

[0076] As illustrated in block (602) and described with reference to FIG. 1, the neural network (140) is initialized in the processor of the ML system (130) coupled to the semiconductor process processing tool (120).

[0077] Next, as illustrated in block (604) and described with reference to FIG. 1, after the neural network (140) is initialized, the neural network (140) can be trained to predict whether the first semiconductor process processing tool (120) will reach a defect state. The neural network (140) can be trained in the same manner as described in FIG. 4a through 4c.

[0078] Next, as illustrated in block (606) and described with reference to FIGS. 1 and FIGS. 2, after the neural network (140) has been sufficiently trained, the neural network (140) can be stored in the memory (210) of the ML system (130).

[0079] Next, as illustrated in block (608), after the neural network is stored in the memory (210) of the ML system (130), the ML system (130) can be implemented on an additional semiconductor process tool. In several embodiments, the additional semiconductor process tool may be a tool of the same type as the semiconductor process tool (120). In one or more embodiments, both the first and second semiconductor process tools may be located within the same manufacturing facility (fab). In other embodiments, the first and second semiconductor process tools may be located within different fabs having different geographical locations. Advantageously, since the semiconductor process tools are of the same type, there is no need to retrain the neural network (140). Advantageously, although the trained neural network may be implemented at a second location different from the first location where the neural network was trained, there is no need to transfer machine data containing process parameters / recipes to the second location. This prevents issues related to data leakage and confidentiality.

[0080] In various embodiments, operation defects can be predicted across multiple semiconductor process tools of a semiconductor process facility line using a single artificial intelligence (AI) algorithm.

[0081] FIG. 7 illustrates a block diagram showing a defect prediction system according to an embodiment of the present invention.

[0082] Several embodiments may be applied to include multiple process processing tools having a common machine learning system.

[0083] Referring to FIG. 7, a first semiconductor process processing tool (702), a second semiconductor process processing tool (704), a third semiconductor process processing tool (706), and a fourth semiconductor process processing tool (708) can be coupled to a machine learning (ML) system (130). The first semiconductor process processing tool (702), the second semiconductor process processing tool (704), the third semiconductor process processing tool (706), and the fourth semiconductor process processing tool (708) are similar to the semiconductor process processing tool (120) described in FIG. 1, and the description is included by reference and is not repeated.

[0084] Although FIG. 7 shows four semiconductor process processing tools, this does not represent the number of semiconductor process processing tools that can be coupled to the ML system (130).

[0085] In one or more embodiments, the ML system (130) can collect machine data and operation codes from each semiconductor process processing tool, self-learn how to predict defects across the facility line, and can be used to predict operation defects across the facility line.

[0086] Advantageously, using a single ML system (130) allows the ML system (130) to learn and evaluate the interrelationships between multiple semiconductor tools. For example, all robot handlers capable of moving wafers between multiple chambers and / or multiple chamber equipment can be coupled to the ML system (130). For example, the ML system can detect defects caused by an annealing chamber after the wafer has exited the deposition chamber, or defects caused by a robot handler during wafer transfer but determined after a subsequent process, for example, after the wafer has passed through the annealing chamber, or defects caused by an alignment tool that can only be known after the wafer has been developed following a lithography process. One advantage of this is that the interrelationships between process parameters of multiple semiconductor processing tools can be evaluated individually and collectively by a single ML system (130), and this single ML system can stop the processing of the wafer and prevent wafer scrap when predicting potential failures.

[0087] In various embodiments, the semiconductor process processing facility line may be divided into compartments and coupled to a number of AI algorithms used to predict semiconductor process processing tool defects.

[0088] FIG. 8 illustrates a block diagram showing a semiconductor process defect prediction system according to an embodiment of the present invention.

[0089] Referring to FIG. 8, the first semiconductor process processing tool (702) and the second semiconductor process processing tool (704) may be coupled to the first machine learning (ML) system (802), the third semiconductor process processing tool (706) may be coupled to the second ML system (804), and the fourth semiconductor process processing tool (708) may be coupled to the third ML system (806). The first ML system (802), the second ML system (804), and the third ML system (806) are similar to the ML system (130) described in FIG. 1, and the description thereof is included by reference and is not repeated.

[0090] This may represent a production line in which a wafer sequentially passes through a semiconductor process processing tool (702), a second semiconductor process processing tool (704), a third semiconductor process processing tool (706), and a fourth semiconductor process processing tool (708). Accordingly, the process processing tools are grouped into separate modules, and each module has its own machine learning system. Thus, multiple machine learning systems may be set up and designed to prevent failures that may occur in each module.

[0091] Although the illustrated example illustrates four semiconductor process processing tools, the number of semiconductor process processing tools and the number of tools coupled to the ML system are not limited by this disclosure.

[0092] In another embodiment, as described above, the ML system (130) may be implemented in an additional semiconductor process processing tool that may be a different type of tool from the semiconductor process processing tool (120). In this case, the neural network (140) may be further trained to operate in the additional semiconductor process processing tool.

[0093] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims set forth herein.

[0094] Example 1. A method comprising: collecting first process processing tool machine data from a first process processing tool while processing a semiconductor substrate, wherein the first process processing tool machine data includes process data mapped to an operation code associated with one or more discrete time intervals during processing; training a first neural network with the first process processing tool machine data from the first process processing tool; and generating a first output from the first neural network indicating a defect of the first process processing tool based on at least partially applying unmapped machine data from at least one process processing tool.

[0095] Example 2. The method of Example 1, further comprising the step of stopping the processing of a semiconductor substrate in at least one process processing tool based on a first output.

[0096] Example 3. In either Example 1 or Example 2, the method further comprises the step of collecting second process processing tool machine data from the second process processing tool while processing another semiconductor substrate, wherein the second process processing tool machine data is mapped to each operation code associated with one or more discrete time intervals, and the step of training the first neural network comprises the step of training the first neural network with the second process processing tool machine data.

[0097] Example 4. A method in any one of Examples 1 to 3, wherein process data represents process conditions during semiconductor substrate processing, and operation code represents one or more conditions of a first process processing tool during semiconductor substrate processing.

[0098] Example 5. A method in any one of Examples 1 to 4, wherein the process data includes in-situ measurement data during semiconductor substrate processing.

[0099] Example 6. A method in any one of Examples 1 to 5, wherein the operation code includes an alarm / warning condition, tool status information, or tool usage information.

[0100] Example 7. A method in any one of Examples 1 to 6, wherein the step of collecting first process processing tool machine data from a first process processing tool is performed at a first location, and the step of collecting second process processing tool machine data from a second process processing tool is performed at a second location different from the first location.

[0101] Example 8. A method comprising, in any one of Examples 1 to 7, further comprising the step of generating a second output from a first neural network representing a defect of a second process processing tool based on applying, at least partially, unmapped machine data from at least one process processing tool.

[0102] Example 9. A method further comprising, in any one of Examples 1 to 8, a step of collecting second process processing tool machine data while processing another semiconductor substrate, wherein the second process processing tool machine data is mapped to each operation code associated with one or more discrete time intervals; a step of training a second neural network using the second process processing tool machine data; and a step of generating a second output indicating a defect from the second neural network based on applying subsequent machine data from at least one process processing tool, at least partially.

[0103] Example 10. A tool system comprising: a processor; a non-transient memory coupled to the processor and having a program executed on the processor, wherein the program collects first process processing tool machine data including process data mapped to an operation code associated with one or more discrete time intervals during processing from a first process processing tool while processing a semiconductor substrate; trains a first neural network with the first process processing tool machine data; and includes instructions for generating a first output indicating a defect from the first neural network based on at least partially applying unmapped machine data from at least one process processing tool.

[0104] Example 11. The tool system of Example 10, wherein the program further comprises a command for stopping the processing of a semiconductor substrate in at least one process processing tool based on a first output.

[0105] Example 12. A tool system comprising, in either Example 10 or Example 11, a first process processing tool.

[0106] Example 13. A tool system in any one of Examples 10 to 12, wherein the program further comprises instructions for storing the first neural network in non-transient memory.

[0107] Example 14. A tool system in any one of Examples 10 to 13, wherein the program further comprises instructions for converting process data of a first process processing tool machine data into a plurality of images for training a first neural network.

[0108] Example 15. A tool system in any one of Examples 10 to 14, wherein process data represents process conditions during semiconductor substrate processing and operation code represents one or more conditions of a first process processing tool during semiconductor substrate processing.

[0109] Example 16. A tool system in any one of Examples 10 to 15, wherein the operation code includes an alarm / warning condition, tool status information, or tool usage information.

[0110] Example 17. A method comprising: initializing a neural network in a processor of a first machine learning system coupled to a first semiconductor process processing tool for process processing a wafer; training the neural network to predict failure of the first semiconductor process processing tool; storing the neural network in the memory of the first machine learning system after training the neural network; and implementing the first machine learning system in a second semiconductor process processing tool.

[0111] Example 18. Method in Example 17, wherein the first semiconductor process processing tool and the second semiconductor process processing tool are tools of the same type.

[0112] Example 19. A method in which, in either Example 17 or Example 18, the first semiconductor process processing tool and the second semiconductor process processing tool are tools of different types.

[0113] Example 20. A method in any one of Examples 17 to 19, wherein the step of implementing the first machine learning system in the second semiconductor process processing tool further includes the step of training a neural network to predict failures of the second semiconductor process processing tool.

[0114] Example 21. A method in which, in either Example 17 or Example 20, the first semiconductor process processing tool and the second semiconductor process processing tool are located within different manufacturing facilities.

[0115] Example 22. A method in which, in either Example 17 or Example 21, the first semiconductor process processing tool and the second semiconductor process processing tool are located within the same manufacturing facilities.

[0116] Although the present invention has been described with reference to exemplary embodiments, such description should not be interpreted in a limiting sense. By referring to this description, various modifications and combinations of the exemplary embodiments as well as other embodiments of the present invention will be apparent to those skilled in the art. Accordingly, the appended claims are intended to include all such modifications or embodiments.

Claims

Claim 1 A method comprising: a step of collecting first process processing tool machine data from a first process processing tool while processing a semiconductor substrate, wherein the first process processing tool machine data includes process data mapped to an operation code associated with one or more discrete time intervals during the processing, wherein the operation code includes data generated by a state detector coupled to the first process processing tool during the processing that indicates the operation state of the first process processing tool, and wherein the operation state includes information indicating a defect state of the first process processing tool and a normal operation of the first process processing tool; and a step of training a first neural network with the first process processing tool machine data from the first process processing tool, wherein the training is performed by including the information indicating the defect state of the first process processing tool and the normal operation of the first process processing tool. A method comprising the step of generating a first output from the first neural network representing a defect of the first process processing tool, based on applying at least partially unmapped machine data from at least one process processing tool. Claim 2 A method according to claim 1, further comprising the step of stopping the processing of a semiconductor substrate within the at least one process processing tool based on the first output. Claim 3 A method according to claim 1, further comprising the step of collecting second process processing tool machine data from a second process processing tool while processing another semiconductor substrate, wherein the second process processing tool machine data is mapped to each operation code associated with one or more discrete time intervals, and the step of training the first neural network comprises the step of training the first neural network with the second process processing tool machine data. Claim 4 A method according to claim 1, wherein the process data represents the process conditions during the semiconductor substrate processing. Claim 5 A method according to claim 1, wherein the process data includes in-situ measurement data during the processing of the semiconductor substrate. Claim 6 A method according to claim 1, wherein the operation code includes alarm / warning conditions, tool status information, or tool usage information. Claim 7 A method according to paragraph 3, wherein the step of collecting first process processing tool machine data from a first process processing tool is performed at a first location, and the step of collecting second process processing tool machine data from a second process processing tool is performed at a second location different from the first location. Claim 8 A method according to claim 3, further comprising the step of generating a second output from the first neural network representing a defect of the second process processing tool, based on applying at least partially unmapped machine data from at least one process processing tool. Claim 9 A method according to claim 1, further comprising: a step of collecting second process processing tool machine data while processing another semiconductor substrate, wherein the second process processing tool machine data is mapped to each operation code associated with one or more discrete time intervals; a step of training a second neural network using the second process processing tool machine data; and a step of generating a second output from the second neural network indicating a defect of the second process processing tool, at least partially based on applying subsequent machine data from at least one process processing tool. Claim 10 As a tool system, the processor comprises a non-transient memory coupled to the processor and having a program executed on the processor, wherein the program collects first process processing tool machine data, which includes process data mapped to an operation code associated with one or more discrete time intervals during processing, from a first process processing tool while processing a semiconductor substrate - the operation code includes data generated by a state detector coupled to the first process processing tool during processing, which indicates an operating state of the first process processing tool, and the operating state includes information indicating a fault state of the first process processing tool and a normal operation of the first process processing tool -; trains a first neural network with the first process processing tool machine data - the training is performed by including information indicating the normal operation of the first process processing tool and the fault state of the first process processing tool during processing -; and, at least partially, an instruction for generating a first output from the first neural network indicating a fault of the first process processing tool based on applying unmapped machine data from at least one process processing tool. A tool system including. Claim 11 In claim 10, the tool system further comprises a program for stopping the processing of a semiconductor substrate within at least one process processing tool based on the first output. Claim 12 A tool system comprising, in addition to the above-mentioned first process processing tool, the 10th item. Claim 13 In paragraph 10, the tool system further comprises a program for storing the first neural network in the non-transient memory. Claim 14 In claim 10, the tool system further comprises a command for converting process data of the first process processing tool machine data into a plurality of images for training the first neural network, wherein each of the plurality of images is formatted as a feature vector filled with values ​​corresponding to the pixel values ​​of each machine data variable within a single period. Claim 15 In item 10, the tool system, wherein the process data represents the process conditions during the processing of the semiconductor substrate. Claim 16 In paragraph 15, the above-mentioned operation code is a tool system comprising alarm / warning conditions, tool status information, or tool usage information. Claim 17 A method comprising: initializing a neural network in a processor of a first machine learning system coupled to a first process processing tool; collecting first process processing tool machine data from the first process processing tool while processing a semiconductor substrate, wherein the first process processing tool machine data includes process data mapped to an operation code associated with one or more discrete time intervals during the processing, and the operation code includes information indicating a defect state of the first process processing tool and a normal operation of the first process processing tool; training the neural network using the first process processing tool machine data, wherein the training is performed by including information indicating the defect state of the first process processing tool and the normal operation of the first process processing tool; storing the neural network in the memory of the first machine learning system; and implementing the first machine learning system in a second process processing tool, wherein the method comprises generating an output from the neural network indicating a defect of the second process processing tool based at least partially on applying unmapped machine data from at least one process processing tool. Claim 18 In claim 17, the above process data represents process conditions during semiconductor substrate processing. Claim 19 In claim 17, the method comprises process data including in-situ measurement data during the processing of the semiconductor substrate. Claim 20 In paragraph 17, the above-mentioned operation code includes alarm / warning conditions, tool status information, or tool usage information, in a method. Claim 21 delete

Images