Peak current measurement of class-d amplifier driver utilizing charge accumulation and operation method thereof

Abstract

A Class D amplifier includes an output driver stage configured to output an output signal at an output node. The Class D amplifier further includes a current sensing circuit connected to the output node of the output driver stage, wherein the current sensing circuit may include a peak detector connected to the output node of the output driver stage and configured to capture a peak value of the output signal; and a current sensor connected to the peak detector, configured to receive the peak value of the output signal and generate a sensing current based on the peak value of the output signal.

Description

Technology Field

[0001] The present disclosure relates to the field of electronic circuits in audio systems, and in particular, the present disclosure relates to the measurement of peak current of a Class D amplifier driver. Background Technology

[0003] A Class-D amplifier (also known as a switching amplifier) ​​is an electronic amplifier in which transistors act as binary switches, turning completely On or completely Off during operation. Class-D amplifiers employ rail-to-rail output switching, and preferably, the output transistors of these amplifiers deliver near-zero current or zero voltage. Consequently, these Class-D amplifiers consume very little power and provide high efficiency over a wide range of power levels. Thanks to their excellent high efficiency, Class-D amplifiers have been widely adopted in various audio applications, ranging from cellular phones to flat-screen televisions and home theater receivers. Class-D audio power amplifiers have higher efficiency than Class-AB audio power amplifiers. Due to their higher efficiency, Class-D amplifiers require smaller power supplies and do not require heat sinks, significantly reducing overall system cost, size, and weight. The problem to be solved

[0005] A general embodiment provides a Class D amplifier. Another general embodiment provides a method for operating a Class D amplifier. means of solving the problem

[0007] A general embodiment includes a Class D amplifier. The Class D amplifier may include an output driver stage, and the output driver stage is configured to output an output signal at an output node. The Class D amplifier may further include a current sensing circuit, wherein the current sensing circuit is connected to the output node of the output driver stage and the current sensing circuit is connected to the output node of the output driver stage and the peak detector is configured to capture a peak value of the output signal; and a current sensor connected to the peak detector, configured to receive the peak value of the output signal and generate a sensing current based on the peak value of the output signal.

[0008] Another general embodiment includes a method for operating a Class D amplifier. The method includes the step of outputting an output signal at an output node of an output driver stage. The method further includes the step of a peak detector capturing a peak value of the output signal. The method further includes the step of a current sensor generating a sensed current based on the peak value of the output signal. Brief explanation of the drawing

[0010] The embodiments of the present invention will be described in detail below in combination with the attached drawings to best facilitate understanding. However, it should be noted that, in accordance with standard practices in the field, the various features are not depicted in proportion. In practice, the size of the various features may be arbitrarily increased or decreased to ensure clarity of explanation. FIG. 1A is a simple schematic diagram illustrating a Class D amplifier. The Class D amplifier is a conventional Class D amplifier having a feedback loop. FIG. 1B is a waveform diagram illustrating the signal modulation of the Class D amplifier (100) of FIG. 1A. FIG. 2A is a diagram illustrating an exemplary conventional configuration regarding current sensing of a Class D amplifier. FIG. 2B is a diagram illustrating, exemplarily, the waveform of the voltage drop across the first sensing resistor. FIG. 2C is a diagram exemplarily illustrating the output signal of a low-pass filter amplifier corresponding to the voltage drop across the first sensing resistor. FIG. 2D is a diagram illustrating another conventional configuration for current sensing of a Class D amplifier. FIG. 3A is a block diagram illustrating a current sensing circuit for a Class D amplifier according to some embodiments. FIG. 3B is a drawing illustrating an example of a sensing circuit for a Class D amplifier according to some embodiments. FIG. 4A is a drawing illustrating a conversion circuit as an example according to some embodiments. FIG. 4B is a drawing illustrating a conversion circuit as another example according to some embodiments. FIG. 5 is a flowchart illustrating an exemplary method of operating a Class D amplifier according to some embodiments. Specific details for implementing the invention

[0011] The present disclosure provides many different embodiments or examples for implementing various features of the gist of the invention presented. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely illustrative and are not intended to be restrictive. Meanwhile, reference numerals and / or letters may be duplicated in various examples of the present disclosure. Such duplication is for simplicity and clarity and does not imply, in itself, a relationship between the various embodiments and / or configurations described.

[0012] Meanwhile, the source / drain ("S / D") region may refer to a source or a drain individually or collectively depending on the context. For example, the device may include a first source / drain region and a second source / drain region and other components. The first source / drain region may be a source region, the second source / drain region may be a drain region, or vice versa. Various variations, modifications, and substitutions are obvious to those skilled in the art.

[0013] Some embodiments of the present disclosure are described. Additional operations may be provided prior to, during, and / or after the steps described in these embodiments. In various embodiments, some of the described steps may be substituted or omitted. In various embodiments, some of the features described below may be substituted or omitted, and additional features may be added. Although some embodiments describe a combination of operations performed in a specific order, these operations may be performed in a different logical order.

[0014] Class D audio power amplifiers convert audio input signals into high-frequency pulses that switch output transistors according to the audio input signal. Some Class D amplifiers use Pulse Width Modulators (PWM) to generate a series of modulating pulses whose width varies according to the amplitude of the audio input signal. These width-varying pulses switch the output transistors via a fixed frequency. Other Class D amplifiers may follow other types of pulse modulators. While the following description primarily focuses on Pulse Width Modulators, those with ordinary knowledge in the field will understand that Class D amplifiers can be configured with other types of modulators.

[0015] FIG. 1A is a simplified schematic diagram illustrating a Class D amplifier (100), which is a conventional Class D amplifier. As shown in FIG. 1A, the Class D amplifier (100) is a differential amplifier. A pair of differential audio input signals (INP and INM) (i.e., a first audio input signal (INP) and a second audio input signal (INM)) are input to a first comparator (101) and a second comparator (102), respectively. Each of the pair of differential audio input signals (INP and INM) is compared with a triangular wave signal (VREF) (i.e., a signal having a triangular waveform; triangular signal) generated by an oscillator (103) to generate a first PWM signal (106) and a second PWM signal (107), respectively. The first audio input signal (INP) and the second audio input signal (INM) are differential signals, and since the same triangular wave signal (VREF) is used as a reference signal, the first PWM signal (106) and the second PWM signal (107) also correspond to differential signals. For example, if the first PWM signal has a duty cycle of 60%, the second PWM signal has a duty cycle of 40%; if the first PWM signal has a duty cycle of 70%, the second PWM signal has a duty cycle of 30%.

[0016] The first PWM signal (106) is connected to the gates of output transistors (191 and 192) that are electrically connected together. Thus, the first PWM signal (106) controls the On and Off of the output transistors (191 and 192). The second PWM signal (107) is connected to the gates of output transistors (193 and 194) that are electrically connected together. Thus, the second PWM signal (107) controls the On / Off of the output transistors (193, 194). Thus, the first output signal (OUTM) and the second output signal (OUTP) of the Class D amplifier (100) are also differential output signals. As shown in FIG. 1A, the first output signal (OUTM) and the second output signal (OUTP) are applied to both ends of a speaker load (110), which is represented in FIG. 1A as an inductor (L1) and a resistor (R1).

[0017] FIG. 1B is a waveform diagram illustrating the signal modulation of the Class D amplifier (100) of FIG. 1A. As shown in FIG. 1B, the first audio input signal (INP) and the second audio input signal (INM) are compared with a triangular wave signal (VREF), as described above with FIG. 1A. The output signals of the first comparator (101) and the second comparator (102) are pulse signals of a fixed frequency (i.e., a fixed cycle), and the pulse width of these pulse signals is proportional to the corresponding audio input signals. Thus, the first output signal (OUTM) and the second output signal (OUTP) are two PWM signals, as shown in FIG. 1B.

[0018] FIG. 2A is a diagram illustrating an exemplary conventional configuration for current sensing of a Class D amplifier. Similar to the example illustrated in FIG. 1A, the output driver stage (290) includes p-type output transistors (291 and 293) and n-type output transistors (292 and 294) connected in the manner illustrated in FIG. 2A. Specifically, the source of the p-type output transistor (291) is a higher power rail (e.g., V DDIt is connected to ), and the drain of the p-type output transistor (291) is connected to the first output terminal (T OUTM The drain of the n-type output transistor (292) is connected to the lower power rail (e.g., V) and the source of the n-type output transistor (292) is connected to the drain of the n-type output transistor (292). SS The source of the p-type output transistor (293) is connected to a higher power rail (e.g., V). DD It is connected to ), and the drain of the p-type output transistor (293) is connected to the second output terminal (T OUTP The drain of the n-type output transistor (294) is connected to the lower power rail (e.g., V) and the source of the p-type output transistor (293) is connected to the drain of the n-type output transistor (294) and the source of the p-type output transistor (293) is connected to the lower power rail (e.g., V SS or ground) is connected. A speaker load (110) including an inductor (L1) and a resistor (R1) is connected to a first output terminal (T OUTM ) and the second output terminal (T OUTP It is connected between ).

[0019] First sensing resistor (R S1 ) is the lower power rail (e.g., V SS It is connected between the source of the n-type output transistor (292) and the ground (or ground). The second sensing resistor (R S2 ) is the lower power rail (e.g., V SS It is connected between the source of the n-type output transistor (294) and the ground. The first sensing resistor (R S1 ) and the second sensing resistor (R S2 ) acts as a current sensor, and the voltage drop across it (V S Converts ) to a current value. The output current (I_out) is I_out=V s / R S1 It can be calculated according to.

[0020] FIG. 2B shows the first sensing resistor (R S1 ) Voltage drop across the ends (V S This is a diagram illustrating the waveform of ). FIG. 2C is a first sensing resistor (R S1 ) Voltage drop across the ends (V SThis is a diagram illustrating, by way of example, the output signal of a low-pass filter amplifier corresponding to ). As shown in FIG. 2B, the first sensing resistor (R S1 ) Voltage drop across the ends (V S The waveform is similar to the PWM signal shown in FIG. 1B, provided that the envelope of the waveform is a sinusoidal wave. Voltage drop (V S The signal is input to a low-pass filter amplifier. Typically, the low-pass filter amplifier has a resistor-capacitor (RC) circuit that has a relatively large gain and occupies a significantly large chip area. The low-pass filter amplifier can filter out high-frequency components of the signal, thereby smoothing the signal and providing a certain gain. The output signal of the low-pass filter amplifier is supplied to an analog-to-digital converter (ADC), which samples the analog signal and converts it into a digital signal. As illustrated in FIG. 2C, the sampled output signal (Vout) is fed to a first sensing resistor (R S1 ) Voltage drop across the ends (V S It corresponds to the waveform of ). FIG. 2C illustrates the peak value (Vpeak) of the sampled output signal (Vout). Therefore, the peak current (Ipeak) is Ipeak = Vpeak / (g * R S It can be calculated according to ), where g is the gain of the low-pass filter amplifier and RS is the first sensing resistor (R S1 It is the resistance of ).

[0021] However, this existing configuration has several drawbacks. RC circuits and ADCs occupy a significantly large chip area. Removing the RC circuits and ADCs drastically reduces the chip area used for current sensing, thereby lowering costs.

[0022] FIG. 2D is a diagram illustrating another conventional configuration for current sensing of a Class D amplifier. Similar to the example illustrated in FIG. 1A, the output driver stage (290) includes p-type output transistors (291 and 293) and n-type output transistors (292 and 294) connected in the manner illustrated in FIG. 2A. Specifically, the source of the p-type output transistor (291) is a higher power rail (e.g., V DD It is connected to ), and the drain of the p-type output transistor (291) is connected to the first output terminal (T OUTM The drain of the n-type output transistor (292) is connected to the lower power rail (e.g., V) and the source of the n-type output transistor (292) is connected to the drain of the n-type output transistor (292). SS The source of the p-type output transistor (293) is connected to a higher power rail (e.g., V). DD It is connected to ), and the drain of the p-type output transistor (293) is connected to the second output terminal (T OUTP The drain of the n-type output transistor (294) is connected to the lower power rail (e.g., V) and the source of the p-type output transistor (293) is connected to the drain of the n-type output transistor (294) and the source of the p-type output transistor (293) is connected to the lower power rail (e.g., V SS or ground) is connected. A speaker load (110) including an inductor (L1) and a resistor (R1) is connected to a first output terminal (T OUTM ) and the second output terminal (T OUTP It is connected between ).

[0023] First sensing resistor (R S1 Unlike the configuration shown in FIG. 2A, where ) is used for current sensing, a sensing transistor (295) is used instead for current sensing in the configuration shown in FIG. 2D. The sensing transistor (295) is connected to another branch parallel to the branch consisting of the p-type output transistor (291) and the n-type output transistor (292). The gate of the sensing transistor (295) is connected to the gate of the n-type output transistor (292). The source of the sensing transistor (295) is a lower power rail (e.g., V SSIt is connected to (or ground). Therefore, the source of the sensing transistor (295) and the source of the n-type output transistor (292) are connected to the same voltage level. Therefore, the gate-source voltage (V) of the sensing transistor (295) GS ) is equal to the gate-source voltage of the n-type output transistor (292).

[0024] When the transistor operates in the linear region, the drain current passing through the transistor is calculated according to the following equation.

[0025]

[0026] At this time, ID is the drain current, and ε is the effective mobility of charge carriers, COX is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, and V DS ε is the voltage drop across the drain and source, and Vth is the threshold voltage. As presented in the equation above, if the sensing transistor (295) and the n-type output transistor (292) are manufactured in the same process corner, some of these parameters ( , COX, Vth) are the same. As previously mentioned, the gate-source voltage (V) of the sensing transistor (295) is the same. GS ) is equal to the gate-source voltage of the n-type output transistor (292). Therefore, the voltage drop (V) across the drain and source is DSWhen ) are the same, they vary according to their respective W / L ratios, and the drain current of the sensing transistor (295) is proportional to the drain current of the n-type output transistor (292). In other words, the current ratio between these two transistors can be controlled by controlling the W / L ratio of the n-type output transistor (292) and the W / L ratio of the sensing transistor (295). In the example illustrated in FIG. 2D, the W / L ratio of the n-type output transistor (292) is M times the W / L ratio of the sensing transistor (295). Therefore, the voltage drop (V) across the drain and source DS Assuming that ) is the same, the drain current of the sensing transistor (295) is 1 / M of the drain current of the n-type output transistor (292). Naturally, M can be selected from various available values ​​(e.g., 10, 100, 1000, 10000, etc.) depending on the situation.

[0027] However, the voltage drop (V) across the drain and source DS The assumption that ) is identical is not always valid. Therefore, the sensing current (i.e., the drain current of the sensing transistor (295)) is not exactly 1 / M of the drain current of the n-type output transistor (292), and this may cause an error during the current sensing process.

[0028] To address these defects described according to FIGS. 2A to 2D, a novel current sensing configuration and circuit are provided. FIG. 3A is a block diagram illustrating a current sensing circuit for a Class D amplifier according to some embodiments. FIG. 3B is a drawing illustrating an example of a sensing circuit for a Class D amplifier according to some embodiments.

[0029] As shown in FIG. 3A, the current sensing circuit (300) is connected to the output driver stage (390; output driver stage (290) shown in FIG. 2A) of a Class D amplifier (Class D amplifier (100) shown in FIG. 1A). The current sensing circuit (300) includes a peak detector (310), a current sensor (350), and other components. The peak detector (310) is connected to the output driver stage (390) and the peak value of the first output signal (OUTM) (V shown in FIG. 2A). S It is configured to capture and fix the peak. An embodiment of the peak detector (310) is illustrated in FIG. 3B. Naturally, this embodiment illustrated in FIG. 3B is exemplary and is not limited thereto, and other embodiments may be used. A current sensor (350) is connected to the peak detector (310). The current sensor (350) is configured to receive the peak value of the output voltage captured by the peak detector (310) and to generate a sensed current based on the peak value of the output voltage. An embodiment of the current sensor (350) is illustrated in FIG. 3B. Naturally, this embodiment illustrated in FIG. 3B is exemplary and is not limited thereto, and other embodiments may be used.

[0030] In the example illustrated in FIG. 3B, the peak detector (310) includes an operational amplifier (312; also referred to as the "first operational amplifier"), a first n-type transistor (314), a second n-type transistor (318), a third n-type transistor (322), a first capacitor (316), a second capacitor (320), and other components. As an input node of the peak detector (310), the positive input terminal of the operational amplifier (312) is the first output terminal (T OUTM It is connected to ), and the negative input terminal of the operational amplifier (312) is connected to the output node (A) of the peak detector (310). The drain of the first n-type transistor (314) is connected to a higher power rail (e.g., V DDIt is connected to ), the source of the first n-type transistor (314) is connected to the output node (A), and the gate of the first n-type transistor (314) is connected to the output terminal of the operational amplifier (312).

[0031] The first capacitor (316) is connected to the output node (A) and a lower power rail (e.g., V SS It is connected between (or ground). The drain of the second n-type transistor (318) is connected to the output node (A), the source of the second n-type transistor (318) is connected to the node (B), and the gate of the second n-type transistor (318) is connected to the clock signal (labeled "CK" in FIG. 3B). The second capacitor (320) is connected between the node (B) and the lower power rail (e.g., V SS It is connected between (or ground). The drain of the third n-type transistor (322) is connected to node (B), and the source of the third n-type transistor (322) is connected to a lower power rail (e.g., V). SS It is connected to ground or ground, and the gate of the third n-type transistor (322) is connected to a clock signal (labeled "CKB" in FIG. 3B) that is complementary to the clock signal (labeled "CK" in FIG. 3B).

[0032] When the first output signal (OUTM) increases, the voltage level of the first input terminal of the operational amplifier (312) increases. Accordingly, the voltage level of the output terminal of the operational amplifier (312) also increases correspondingly. The output terminal of the operational amplifier (312) is connected to the gate of the first n-type transistor (314), and thus the first n-type transistor (314) is turned on. Accordingly, the voltage level at the output node (A) increases to a higher power rail (e.g., V DD Pulled up by ) (removing the voltage drop across the source and drain of the first n-type transistor (314).

[0033] When the first output signal (OUTM) decreases, the voltage level of the first input terminal of the operational amplifier (312) decreases. Accordingly, the voltage level of the output terminal of the operational amplifier (312) also decreases correspondingly. The output terminal of the operational amplifier (312) is connected to the gate of the first n-type transistor (314), and thus the first n-type transistor (314) is turned off. However, because the first capacitor (316) is present, there is no pull-down path to reduce the voltage level at the output node (A). In other words, the voltage level at the output node (A) can only be changed in one direction (i.e., increase rather than decrease). When the first output signal decreases, the voltage level at the output node (A) is maintained without change. Therefore, the first output terminal (T OUTM The peak value of the first output signal (OUTM) in ) is captured and fixed at the output node (A) of the peak detector (310).

[0034] However, the peak voltage of OUTM exhibits variability, with different peak values ​​corresponding to different sinusoidal waves. To effectively capture subsequent peak values, a compact discharge path must be implemented, and traditionally, such a compact discharge path is implemented using larger resistors. However, the disadvantages associated with using larger resistors—namely, increased space requirements and increased costs—need to urge the search for alternatives to address these issues. The present disclosure facilitates optimized discharge and enhanced peak value capture by presenting a novel method using a switching capacitor (the second capacitor (320) in FIG. 3B, described later) as a more space-efficient and cost-effective alternative to conventional resistors.

[0035] Hereinafter, the second capacitor (320), the second n-type transistor (318), and the third n-type transistor (322) will be described. The capacitance of the second capacitor (320) is smaller than the capacitance of the first capacitor (316). In one example, the capacitance of the second capacitor (320) is 0.1%, 1%, 5%, or 10% of the capacitance of the first capacitor (316). When the clock signal (indicated as "CK" in FIG. 3B) is at a logic high level, the second n-type transistor (318) is turned on. At the same time, the complementary clock signal (indicated as "CKB" in FIG. 3B) is at a logic low level accordingly, and the third n-type transistor (322) is turned off. Accordingly, the second capacitor (320) is connected in parallel with the first capacitor (316), and some of the charge stored in the first capacitor (316) is transferred to the second capacitor (320). From another perspective, the total capacitance increases due to the parallel connection, and the voltage level at the output node (A) decreases as the total amount of charge remains unchanged.

[0036] When the clock signal (labeled "CK" in FIG. 3B) is at a logic low level, the second n-type transistor (318) is turned off. At the same time, the complementary clock signal (labeled "CKB" in FIG. 3B) is accordingly at a logic high level, and the third n-type transistor (322) is turned on. Therefore, the second capacitor (320) is no longer connected in parallel with the first capacitor (316), and both sides of the second capacitor (320) are connected to a lower power rail (e.g., V SS It is connected to (or ground). Therefore, since the voltage drop becomes zero, the charge transferred to the second capacitor (320) is discharged.

[0037] In the example illustrated in FIG. 3B, the current sensor (350) includes another operational amplifier (352; also referred to as the "second operational amplifier"), a sensing transistor (395), a first p-type transistor (354), a second p-type transistor (356), a third p-type transistor (358), and other components. The negative terminal of the operational amplifier (352) is connected to the output node (A) of the peak detector (310), and the positive terminal of the operational amplifier (352) is connected to node (C). The output terminal of the operational amplifier (352) is connected to the gate of the first p-type transistor (354). The drain of the sensing transistor (395) is connected to node (C), and the source of the sensing transistor (395) is connected to a lower power rail (e.g., V SS It is connected to (or ground). The gate of the sensing transistor (395) is connected to the gate of the n-type output transistor (392).

[0038] Since the positive and negative input terminals of the operational amplifier (352) are assumed to be short-circuited, the voltage level of the positive input terminal (the corresponding voltage level at node (C)) is the same as the voltage level at the output node (A) of the peak detector (310). In other words, the voltage level at the output node (A) of the peak detector (310) is replicated at node (C). Therefore, V of the sensing transistor (395) DS and V of the n-type output transistor (392) DS has the same peak value. As described above with reference to FIG. 2D, the drain current of the sensing transistor (395) is proportional to the drain current of the n-type output transistor (392), which is V of the sensing transistor (395). DS V of the n-type output transistor (392) DSThis is because it is clamped to the peak value. In the example illustrated in FIG. 3B, the W / L ratio of the n-type output transistor (392) is M times the W / L ratio of the sensing transistor (395). Therefore, the drain current of the sensing transistor (395) is 1 / M of the drain current of the n-type output transistor (392).

[0039] The source of the first p-type transistor (354) is connected to the drain and gate of the second p-type transistor (356), and the drain of the first p-type transistor (354) is connected to node (C). When the voltage level of the output terminal is low and the first p-type transistor (354) is turned on, the sensing transistor (395) is connected to a current mirror (360) composed of the second p-type transistor (356) and the third p-type transistor (358). The source of the second p-type transistor (356) and the source of the third p-type transistor (358) are connected to a higher power rail (e.g., V DD It is connected to ). The drain of the second p-type transistor (356) is connected to the gate of the second p-type transistor (356) and the third p-type transistor (358). In the example shown in FIG. 3B, the drain current of the third p-type transistor (358) is 1 / N of the drain current of the second p-type transistor (356). Thus, the sense current (Isense) can be calculated according to Isense = I_out_peak / (M*N), where I_out_peak is the peak value of the output current (I_out) flowing through the n-type output transistor (392). In one example, M is 10. In another example, M is 100. In yet another example, M is 1000. In yet another example, M is 10000. In one example, N is 10. In another example, N is 100. In yet another example, N is 1000. Naturally, these examples are not intended to limit the present disclosure, and other values ​​may be used in other embodiments.

[0040] In some embodiments, the sense current (Isense) may be further converted into a digital signal for additional processing, such as digital signal processing (DSP). FIG. 4A is a drawing illustrating a conversion circuit (410) as an example according to some embodiments. FIG. 4B is a drawing illustrating a conversion circuit (450) as another example according to some embodiments.

[0041] In the example illustrated in FIG. 4A, the conversion circuit (410) includes a resistor (412), an analog-to-digital converter (ADC; 414), and other components. The sense current (Isense) is a higher power rail (e.g., V DD It is indicated as a current source connected between ) and node (D). The resistor (412) is connected between node (D) and a lower power rail (e.g., V SS It is connected between (or ground). The voltage level at node (D) is calculated according to Vsense = Isense * R, where R is the resistance of resistor (412). The voltage level at node (D) is input to the ADC (414), and the ADC (414) converts it into a digital value. However, the ADC (414) occupies a relatively large chip area and is typically associated with a relatively high cost.

[0042] In the example illustrated in FIG. 4B, the conversion circuit (450) includes a capacitor (452), a comparator (454), a counter (456), and other components. The sense current (Isense) is a higher power rail (e.g., V DD It is represented as a current source connected between ) and node (E). The capacitor (452) is connected between node (E) and a lower power rail (e.g., V SS It is connected between (or ground). The negative input terminal of the comparator (454) is connected to node (E), and a reference voltage is supplied to the positive input terminal of the comparator (454). The output terminal of the comparator (454) is connected to the input terminal of the counter (456).

[0043] As illustrated in FIG. 4B, the sensing current charges the capacitor (452), and the charge stored by the capacitor (452) can be calculated according to Q=C*V=Isense*△t, where C is the capacitance of the capacitor (452), V is the voltage drop across the capacitor (452), and △t is the charging cycle. Therefore, Isense can be calculated according to Isense=(C*V) / △t.

[0044] The voltage drop (V) has a ramp signal waveform (labeled "462" in FIG. 4B). The voltage drop (V) is compared with a reference voltage (labeled "Vref" in FIG. 4B), and the output signal according to the comparator (454) has a PWM waveform (labeled "464" in FIG. 4B). The pulse width of the PWM waveform corresponds to the charging period (△t). The counter (456) receives a high-frequency clock signal as an input and counts the number of cycles of the counter clock signal for each pulse width of the PWM waveform. Thus, the charging period (△t) is calculated, and the sense current (Isense) can be calculated according to Isense=(C*V) / △t, as described above. Thus, the calculated sense current (Isense) is digitized.

[0045] As described above, for different output resistance values ​​(R1 indicated in FIG. 3B), the absolute value of the error rate of the current sensing circuit (300) illustrated in FIG. 3A and FIG. 3B is 0.4% to 1.3%. Specifically, when the output resistance is 4 ohms, the error rate is 0.4%; when the output resistance is 5 ohms, the error rate is -0.9%; when the output resistance is 6 ohms, the error rate is -1.3%; when the output resistance is 7 ohms, the error rate is -1.1%; and when the output resistance is 8 ohms, the error rate is -1%.

[0046] Therefore, this error rate has a significantly better absolute value than the error rate of the current sensing circuit shown in FIG. 2D, and the absolute value is typically 10%. This advantage is achieved by using a peak detector (310) to capture the peak value of the first output signal (OUTM), as described above.

[0047] FIG. 5 is a flowchart illustrating an exemplary method of operating a Class D amplifier according to some embodiments. In the example illustrated in FIG. 5, the method (500) includes operations (or steps) 502, 504, and 506. If necessary, the method (500) may perform additional operation steps.

[0048] In step 502, at the output node of the output driver stage, the output driver stage of the Class D amplifier (e.g., the output driver stage (390) shown in FIG. 3B) outputs an output signal (e.g., the first output signal (OUTM) shown in FIG. 3B).

[0049] In step 504, a peak detector (e.g., the peak detector (310) shown in FIG. 3B) captures the peak value of the output signal.

[0050] In step 506, based on the peak value of the output signal, the current sensor (e.g., the current sensor (350) shown in FIG. 3B) generates a sensing current.

[0051] The features of various embodiments have been described above to enable those skilled in the art to fully understand the aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same effect as the embodiments described herein. Furthermore, those skilled in the art will understand that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various modifications, substitutions, and changes within the scope of the spirit of the present disclosure. Explanation of the symbols

[0053] 100: Class D amplifier 101: First comparator 102: Second comparator 103: Oscillator 106: 1st PWM signal 107: 2nd PWM signal 110: Load 191: Output transistor 192: Output transistor 193: Output transistor 194: Output transistor 290: Output driver stage 291: p-type output transistor 292: n-type output transistor 293: p-type output transistor 294: n-type output transistor 295: Sensing transistor 300: Current sensing circuit 310: Peak detector 312: First operational amplifier 314: First n-type transistor 316: First capacitor 318: Second n-type transistor 320: Second capacitor 322: Third n-type transistor 350: Current sensor 352: Another operational amplifier 354: First p-type transistor 356: Second p-type transistor 358: Third p-type transistor 360: Current Mirror 390: Output Driver Stage 392: n-type output transistor 395: sensing transistor 410: Exemplary conversion circuit 412: Resistor 414: Analog-to-Digital Converter (ADC) 450: Another exemplary conversion circuit 452: Capacitor 454: Comparator 456: Counter 462: Ramp signal waveform 464: PWM waveform 500: Method 502: Step 504: Step 506: Step A: Output Node B: Node C: Node CK: Clock signal CKB: Clock signal D: Node E: Node INM: Second audio input signal INP: First audio input signal I_out: Output current Ipeak: Peak current Isense: Detected current I_out_peak: Peak value L1: Inductor OUTM: First output signal OUTP: Second output signal R1: Resistor R S : Resistance R S1 : 1st sensing resistor R S2 : 2nd sensing resistor T OUTM : First output terminal T OUTP : 2nd output terminal V: Voltage drop V DD : Higher power rail V DS : Voltage drop V GS : Gate-source voltage Vout: Sampled output signal Vpeak: Peak value VREF: Triangle wave signal Vref: Reference voltage V s : Voltage drop V SS : Lower power rail

Claims

Claim 1 A Class D amplifier comprises an output driver stage configured to output an output signal at an output node, and a current sensing circuit connected to the output node of the output driver stage, wherein the current sensing circuit comprises a peak detector connected to the output node of the output driver stage and configured to capture a peak value of the output signal, and a current sensor connected to the peak detector and configured to receive the peak value of the output signal and generate a sensing current based on the peak value of the output signal, wherein the peak detector comprises a first operational amplifier, a first n-type transistor, and a first capacitor. Claim 2 In claim 1, the peak detector is a Class D amplifier that locks the peak value of the output signal. Claim 3 A Class D amplifier according to claim 1, wherein the peak detector includes an output node, and when the output signal of the output node of the output driver stage increases, the voltage level of the output node of the peak detector increases, and when the output signal of the output node of the output driver stage decreases, the voltage level of the output node of the peak detector is maintained without change. Claim 4 A Class D amplifier according to paragraph 3, wherein the positive input terminal of the first operational amplifier is connected to the output node of the output driver stage, the negative input terminal of the first operational amplifier is connected to the output node of the peak detector, and the output terminal of the first operational amplifier is connected to the gate of the first n-type transistor. Claim 5 In paragraph 4, a Class D amplifier in which the drain of the first n-type transistor is connected to a higher power rail and the source of the first n-type transistor is connected to the output node of the peak detector. Claim 6 In paragraph 5, the first capacitor is connected between the output node of the peak detector and a lower power rail, and the lower power rail is lower than the higher power rail, a Class D amplifier. Claim 7 In claim 6, the peak detector is a Class D amplifier further comprising a second n-type transistor, a third n-type transistor, and a second capacitor. Claim 8 A Class D amplifier according to claim 7, wherein the drain of the second n-type transistor is connected to the output node of the peak detector, the source of the second n-type transistor is connected to the second node, the second capacitor is connected between the second node and the lower power rail, the drain of the third n-type transistor is connected to the second node, and the source of the third n-type transistor is connected to the lower power rail. Claim 9 A Class D amplifier according to claim 8, wherein the gate of the second n-type transistor is connected to a first clock signal, the gate of the third n-type transistor is connected to a second clock signal, and the second clock signal is complementary to the first clock signal. Claim 10 In claim 9, a Class D amplifier in which the capacitance of the second capacitor is smaller than the capacitance of the first capacitor. Claim 11 A Class D amplifier comprises an output driver stage configured to output an output signal at an output node, and a current sensing circuit connected to the output node of the output driver stage, wherein the current sensing circuit comprises a peak detector connected to the output node of the output driver stage and configured to capture a peak value of the output signal, and a current sensor connected to the peak detector and configured to receive the peak value of the output signal and generate a sensing current based on the peak value of the output signal, wherein the current sensor comprises a second operational amplifier, a sensing transistor, a first p-type transistor, and a current mirror. Claim 12 A Class D amplifier according to claim 11, wherein the negative input terminal of the second operational amplifier is connected to the peak detector to receive the peak value of the output signal of the output driver stage, the positive input terminal of the second operational amplifier is connected to a third node, the output terminal of the second operational amplifier is connected to the gate of the first p-type transistor, the source of the first p-type transistor is connected to the current mirror, and the drain of the first p-type transistor is connected to the third node. Claim 13 In paragraph 12, a Class D amplifier in which the drain of the sensing transistor is connected to the third node and the source of the sensing transistor is connected to a lower power rail. Claim 14 In claim 13, the current mirror comprises a second p-type transistor and a third p-type transistor, wherein the source of the first p-type transistor is connected to the drain and gate of the second p-type transistor, the source of the second p-type transistor is connected to a higher power rail higher than the lower power rail, the source of the third p-type transistor is connected to the higher power rail, the gate of the third p-type transistor is connected to the gate of the second p-type transistor, and the drain of the third p-type transistor is connected to the output terminal of the current sensor, a Class D amplifier. Claim 15 In claim 14, the output terminal of the current sensor is connected to a conversion circuit, and the conversion circuit comprises a capacitor connected between the output terminal of the current sensor and the lower power rail, a comparator including a negative input terminal connected to the output terminal of the current sensor and a positive input terminal receiving a reference voltage, and a counter connected to the output terminal of the comparator, a Class D amplifier. Claim 16 A method for operating a Class D amplifier, comprising the steps of: outputting an output signal at an output node of an output driver stage; capturing a peak value of the output signal by a peak detector; and generating a sensing current by a current sensor based on the peak value of the output signal, wherein the peak detector comprises a first operational amplifier, a first n-type transistor, and a first capacitor. Claim 17 A method for operating a Class D amplifier, wherein, in paragraph 16, the step of capturing the peak value of the output signal comprises the step of fixing the peak value of the output signal. Claim 18 A method for operating a Class D amplifier according to claim 17, wherein when the output signal increases, the voltage level of the output node of the peak detector increases, and when the output signal decreases, the voltage level of the output node of the peak detector is maintained without change. Claim 19 A method for operating a Class D amplifier according to claim 16, further comprising the step of converting the sensed current into a digital sensed current using a comparator and a counter. Claim 20 delete

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