A semiconductor device and an image sensor including the semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device comprises a substrate extending in first and second directions intersecting each other, a gate structure disposed on the substrate and including a first side and a second side extending parallel to the first direction and spaced apart from each other in the second direction, and a third side extending parallel to the second direction, and a plurality of source / drain regions of a first conductivity type disposed within the substrate, wherein the plurality of source / drain regions includes a first and second source / drain region spaced apart from each other in the second direction and a third source / drain region spaced apart from at least one of the first and second source / drain regions in the first direction, wherein the first and second source / drain regions each overlap with the first and second sides in a third direction perpendicular to the first and second directions, and the third source / drain region overlaps with either the first side or the third side in the third direction, and operates based on the voltage applied to the first and second source / drain regions and the voltage applied to the third source / drain region being different values.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and an image sensor including the semiconductor device. Background Technology

[0002] As the feature size of a MOS transistor decreases, the gate length and width, as well as the length and width of the channel formed beneath it, also shrink. As the transistor's channel length decreases, the magnitude of the electric field applied in the channel increases, leading to increased variability in characteristics such as threshold voltage. A decrease in the transistor's channel width also contributes to this increased variability, resulting in performance issues such as reduced transconductance. This degradation of characteristics can be an obstacle for products that utilize transistors as read-out circuits, such as image sensors.

[0003] Therefore, various studies are being conducted to improve characteristic dispersion and performance in transistors. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device with improved operating performance of a transistor.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor device according to some embodiments of the present invention for solving the above problem comprises: a substrate extending in first and second directions intersecting each other; a gate structure disposed on the substrate and including a first side and a second side extending parallel to the first direction and spaced apart from each other in a second direction, and a third side extending parallel to the second direction; and a plurality of source / drain regions of a first conductivity type disposed within the substrate, wherein the plurality of source / drain regions includes a first and second source / drain region spaced apart from each other in a second direction and a third source / drain region spaced apart from at least one of the first and second source / drain regions in a first direction, wherein the first and second source / drain regions each overlap with the first and second sides in a third direction perpendicular to the first and second directions, and the third source / drain region overlaps with either the first side or the third side in a third direction, and the voltage applied to the first and second source / drain regions and the voltage applied to the third source / drain region are different It operates based on the value.

[0007] A semiconductor device according to some other embodiments of the present invention for solving the above problem comprises: a substrate extending in first and second directions intersecting each other; a gate structure comprising first and second sides disposed on the substrate and extending parallel to the first direction and spaced apart from each other in the second direction; and a source / drain region disposed within the substrate to overlap with at least one of the first and second sides of the gate structure in a third direction perpendicular to the first and second directions and having an impurity of a first conductivity type, wherein the source / drain region comprises a plurality of source regions and at least one drain region spaced apart from each of the plurality of source regions.

[0008] An image sensor according to another embodiment of the present invention for solving the above problem comprises: a gate structure comprising a first side and a second side that are spaced apart from each other in a second direction that extends parallel to a first direction and intersects the first direction, and a third side that extends parallel to the second direction, wherein a voltage according to the charge accumulated by a light sensing element is applied; and a source follower transistor comprising a plurality of source / drain regions of a first conductivity type, wherein the plurality of source / drain regions includes a first and second source / drain region spaced apart from each other in a second direction and a third source / drain region spaced apart from at least one of the first and second source / drain regions in a first direction, wherein the first and second source / drain regions each overlap with the first and second sides in a third direction perpendicular to the first and second directions, and the third source / drain region overlaps with either the first side or the third side in a third direction, and the voltage applied to the first and second source / drain regions and the third The voltage applied to the source / drain region operates based on different values.

[0009] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. Figure 2 is a cross-sectional view taken along A-A of Figure 1. Figure 3 is a cross-sectional view taken along B-B of Figure 1. FIG. 4 is a drawing for explaining a semiconductor device according to some embodiments of the present invention. FIG. 5 is a drawing for explaining a semiconductor device according to some embodiments of the present invention. FIG. 6 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 7 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 8 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 9 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 10 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 11 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 12 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. Figure 13 is a cross-sectional view taken along C-C of Figure 12. FIG. 14 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 15 is a cross-sectional view schematically showing the structure of a source follower transistor according to some embodiments of the present invention. FIG. 16 is a drawing showing an image sensor according to some embodiments of the present invention. FIG. 17 is a circuit diagram schematically showing the structure of a pixel according to some embodiments of the present invention. Specific details for implementing the invention

[0011] Hereinafter, with reference to FIGS. 1 to 5, a semiconductor device according to some embodiments of the present invention will be described.

[0012] FIG. 1 is a layout diagram schematically illustrating a semiconductor device according to some embodiment of the present invention. FIG. 2 is a cross-sectional view taken along A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along B-B of FIG. 1. FIG. 4 is a drawing illustrating a semiconductor device according to some embodiment of the present invention. FIG. 5 is a drawing illustrating a semiconductor device according to some embodiment of the present invention.

[0013] Referring to FIGS. 1 to 5, a semiconductor device (1000) according to some embodiments of the present invention may include a substrate (100), a gate structure (200), and a plurality of source / drain regions (300).

[0014] The substrate (100) can be extended in a first direction (DR1) and a second direction (DR2) that intersect each other.

[0015] In some embodiments, the substrate (100) may include an N-type transistor forming region. Alternatively, the substrate (100) may include a P-type transistor forming region.

[0016] The substrate (100) may include, for example, bulk silicon, SOI (Silicon-on-Insulator), silicon substrate, silicon germanium, SGOI (Silicon-Germanium-on-Insulator), silicon carbide, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0017] In some embodiments, the substrate (100) is described as a silicon substrate containing silicon.

[0018] A trench (120T) defining an active region (ACT) between the substrate (100) and the gate structure (200) described later may be formed inside the substrate (100). In some embodiments, the trench (120T) may form a shallow trench isolation structure.

[0019] An insulating film (120) may be formed to fill the interior of a trench (120T). The insulating film (120) may be formed from a dielectric oxide material such as silicon oxide, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0020] Referring to FIG. 2, a threshold voltage adjustment ion implantation layer (110) may be disposed on a substrate (100) below a gate structure (200) described later. The threshold voltage adjustment ion implantation layer (110) may include impurities of a different conductivity type than the impurities contained in the substrate (100). However, the technical concept of the present invention is not limited thereto.

[0021] A semiconductor device (1000) may include a gate structure (200) on a substrate (100). The gate structure (200) may include a gate insulating film (GI), a gate electrode (GE) on the gate insulating film (GI), and a spacer structure (210). The gate insulating film (GI) may include a silicon oxide film or a high dielectric constant insulating film having a dielectric constant greater than that of the silicon oxide film.

[0022] Although not specifically illustrated, the gate electrode (GE) may include a metal gate electrode layer and / or a semiconductor gate electrode layer. The metal gate electrode layer may include a conductive metal nitride film such as titanium nitride, tantalum nitride, or tungsten nitride. The semiconductor gate electrode layer may include polycrystalline silicon.

[0023] Although not specifically illustrated, a contact electrode may be provided on the gate electrode (GE). The contact electrode may comprise a metal-semiconductor compound. For example, the contact electrode may comprise a metal silicide material such as titanium silicide or nickel silicide.

[0024] Referring to FIGS. 1 and 2, the gate structure (200) may include a first_1 side (200_11), a first_2 side (200_12), a first_3 side (200_13) and a first_4 side (200_14) that extend parallel to the first direction (DR1).

[0025] The first_1 side (200_11) and the first_2 side (200_12) may be spaced apart to face each other with respect to the first direction (DR1), and the first_3 side (200_13) and the first_4 side (200_14) may be spaced apart to face each other with respect to the first direction (DR1). The first_1 side (200_11) and the first_3 side (200_13) may be spaced apart to face each other with respect to the second direction (DR2), and the first_2 side (200_12) and the first_4 side (200_14) may be spaced apart to face each other with respect to the second direction (DR2).

[0026] Additionally, the gate structure (200) may include a second_1 side (200_21) and a second_2 side (200_22) that extend parallel to the second direction (DR2). The second_1 side (200_21) and the second_2 side (200_22) may be spaced apart to face each other with respect to the first direction (DR1).

[0027] In some embodiments, the first_1 side (200_11), first_2 side (200_12), first_3 side (200_13), first_4 side (200_14), second_1 side (200_21) and second_2 side (200_22) of the gate structure (200) may refer to the side walls of the gate structure (200) itself, each of which includes a gate electrode (GE) or a spacer structure (210) described later. Additionally, the first and second inner walls (200_31, 200_32) of the gate structure (200) may refer to the inner walls of the gate structure (200) itself, each of which includes a gate electrode (GE) or a spacer structure (210).

[0028] The gate structure (200) may include a first inner wall (200_31) extending along a second direction (DR2) from the first_1 and first_2 sides (200_11, 200_12) and a second inner wall (200_32) connected to the first inner wall (200_31) and extending along a first direction (DR1). In this case, referring to FIG. 1, the gate structure (200) may have an I-shape.

[0029] The first and second inner walls (200_31, 200_32) of the gate structure (200) may represent an exposed area of ​​the gate structure (200) formed by etching at least a portion of the gate structure (200). In some embodiments, the etching method of the gate structure (200) is not particularly limited as long as it is capable of etching at least a portion of the gate structure (200).

[0030] A spacer structure (210) may be provided on the sidewall of a gate electrode (GE). The spacer structure (210) may include a first spacer pattern (211) and a second spacer pattern (212) stacked sequentially on the sidewall of the gate electrode (GE). For example, the thickness of the second spacer pattern (212) may be thicker than the thickness of the first spacer pattern (211). However, the technical concept of the present invention is not limited thereto.

[0031] The second spacer pattern (212) may include a material that is etch-selective with respect to the first spacer pattern (211). For example, the second spacer pattern (212) may include silicon oxide, and the first spacer pattern (211) may include silicon nitride. However, the technical concept of the present invention is not limited thereto.

[0032] A plurality of source / drain regions (300) may be provided within the substrate (100). The plurality of source / drain regions (300) may contain impurities of a first conductivity type or a second conductivity type different from the first conductivity type, depending on the type of semiconductor device (1000). For example, if the semiconductor device (1000) is an N-type transistor, the first conductivity type may be N-type, and if the semiconductor device (1000) is a P-type transistor, the second conductivity type may be P-type.

[0033] Referring to FIGS. 1 and 2, a plurality of source / drain regions (300) may include first and second source / drain regions (311, 312) that are spaced apart to face each other in a second direction (DR2) and overlap with the first_1 side (200_11) and the first_3 side (200_13) of the gate structure (200), respectively in a third direction (DR3), and a third source / drain region (321) that is spaced apart from at least one of the first and second source / drain regions (311, 312) in a first direction (DR1) and overlaps with the first_2 side (200_12) of the gate structure (200) in a third direction (DR3).

[0034] In some embodiments, the first and second source / drain regions (311, 312) may be source regions, and the third source / drain region (321) may be a drain region. The magnitude of the voltage applied to the first and second source / drain regions (311, 312) may be different from the magnitude of the voltage applied to the third source / drain region (321). In this case, the voltage applied to the first and second source / drain regions (311, 312) may operate based on a value different from the voltage applied to the third source / drain region (321).

[0035] For example, if the semiconductor device (1000) is an N-type transistor, the voltage applied to the third source / drain region (321), which is the drain region, may be greater than the voltage applied to the first and second source / drain regions (311, 312), which are the source regions. Or, for example, if the semiconductor device (1000) is a P-type transistor, the voltage applied to the third source / drain region (321), which is the drain region, may be smaller than the voltage applied to the first and second source / drain regions (311, 312), which are the source regions.

[0036] On the other hand, alternatively, the first and second source / drain regions (311, 312) may be drain regions, and the third source / drain region (321) may be a source region. The magnitude of the voltage applied to the first and second source / drain regions (311, 312) may be different from the magnitude of the voltage applied to the third source / drain region (321).

[0037] For example, if the semiconductor device (1000) is a P-type transistor, the voltage applied to the third source / drain region (321), which is a source region, may be greater than the voltage applied to the first and second source / drain regions (311, 312), which are drain regions. Or, for example, if the semiconductor device (1000) is an N-type transistor, the voltage applied to the third source / drain region (321), which is a source region, may be smaller than the voltage applied to the first and second source / drain regions (311, 312), which are drain regions.

[0038] A plurality of source / drain regions (300) may further include a fourth source / drain region (322) that overlaps with the first_4 side (200_14) of the gate structure (200) in the third direction (DR3) and is spaced apart from the first and second source / drain regions (311, 312) in the first direction (DR1).

[0039] In some embodiments, the first and second source / drain regions (311, 312) may be source regions, and the fourth source / drain region (322) may be a drain region. The voltage applied to the first and second source / drain regions (311, 312) may be different from the voltage applied to the fourth source / drain region (322). In this case, the voltage applied to the first and second source / drain regions (311, 312) may operate based on a value different from the voltage applied to the fourth source / drain region (322).

[0040] In this case, for example, if the semiconductor device (1000) is an N-type transistor, the voltage applied to the fourth source / drain region (322), which is the drain region, may be greater than the voltage applied to the first and second source / drain regions (311, 312), which are the source regions. At this time, if the third source / drain region (321) is the source region, the voltage applied to the fourth source / drain region (322), which is the drain region, may be greater than the voltage applied to the third source / drain region (321). Alternatively, for example, if the semiconductor device (1000) is a P-type transistor, the voltage applied to the fourth source / drain region (322), which is the drain region, may be smaller than the voltage applied to the first and second source / drain regions (311, 312), which are the source regions.

[0041] On the other hand, alternatively, the first and second source / drain regions (311, 312) may be drain regions, and the fourth source / drain region (322) may be a source region. The voltage applied to the first and second source / drain regions (311, 312) may be different from the voltage applied to the fourth source / drain region (322).

[0042] In this case, for example, if the semiconductor device (1000) is a P-type transistor, the voltage applied to the fourth source / drain region (322), which is a source region, may be greater than the voltage applied to the first and second source / drain regions (311, 312), which are drain regions. Or, for example, if the semiconductor device (1000) is an N-type transistor, the voltage applied to the fourth source / drain region (322), which is a source region, may be smaller than the voltage applied to the first and second source / drain regions (311, 312), which are drain regions. At this time, if the third source / drain region (321) is a drain region, the voltage applied to the third source / drain region (321) may be greater than the voltage applied to the fourth source / drain region (322), which is a source region.

[0043] Conventionally, as the channel length of a transistor decreases, a problem may arise in which the dispersion characteristics of the threshold voltage deteriorate. In some embodiments, the path for carriers, such as charge, to travel can be increased by increasing the number or area of ​​source / drain regions within a single transistor. As a result, the operating performance of the transistor can be improved under the same area.

[0044] Referring to FIG. 1, with respect to the first direction (DR1), the length of at least one of the first and second source / drain regions (311, 312) and the length of the third source / drain region (321) may be substantially the same. However, the technical concept of the present invention is not limited thereto, and as described below, the lengths of the plurality of source / drain regions (300) according to the first direction (DR1) may differ from each other.

[0045] Low-doping regions (131, 132) may be provided within the substrate (100). The low-doping regions (131, 132) may be regions doped to a lower concentration than the plurality of source / drain regions (300). The low-doping regions (131, 132) may have impurities of the same conductivity type as the plurality of source / drain regions (300). The low-doping regions (131, 132) may be regions extending from the plurality of source / drain regions (300) toward the gate electrode (GE).

[0046] Referring to FIGS. 1 and 3, the trench (120T) may include a first side (not shown) extending along a second direction (DR2) from a first side (200_11, 200_12) of the gate structure (200), and a second side (120T_2) connected to the first side and extending along a first direction (DR1). Although not specifically illustrated, the first side may be formed at the same level as the first inner wall (200_31) of the gate structure (200) and the third direction (DR3). The second side (120T_2) may be formed at the same level as the second inner wall (200_32) of the gate structure (200) and the third direction (DR3).

[0047] The trench (120T) may refer to an area formed by etching at least a portion of the substrate (100). In this case, at least a portion of the substrate (100) may be etched so that the second side (120T_2) is positioned at the same level as the second inner wall (200_32) of the gate structure (200) and the third direction (DR3).

[0048] Referring to FIG. 3, the second side (120T_2) of the trench (120T) is depicted as being perpendicular to the second direction (DR2), but the technical concept of the present invention is not limited thereto. That is, the second side (120T_2) of the trench (120T) may be formed to have an inclination other than 90 degrees with respect to the second direction (DR2) parallel to one side of the substrate (100). For example, the second side (120T_2) of the trench (120T) may be formed at an incline so that the shallow trench isolation structure has an inverted trapezoidal shape.

[0049] Referring to FIGS. 1 and 3, a shallow trench isolation structure may be formed between the first and third source / drain regions (311, 321) and between the second and fourth source / drain regions (312, 322). In this case, an insulating film (120) may be disposed between the first and third source / drain regions (311, 321) spaced apart with respect to the first direction (DR1). Additionally, an insulating film (120) may be disposed between the second and fourth source / drain regions (312, 322) spaced apart with respect to the first direction (DR1).

[0050] Referring to FIG. 4, the depths of the multiple source / drain regions (300) may differ from each other. For example, the depth (T1) along the third direction (DR3) of the first source / drain region (311) may be deeper than the depth (T2) along the third direction (DR3) of the fourth source / drain region (322). Although not specifically illustrated, in this case, the depth (T1) along the third direction (DR3) of the first source / drain region (311) may be deeper than the depth along the third direction (DR3) of the third source / drain region (321).

[0051] Also, although not specifically illustrated, the depth along the third direction (DR3) of the second source / drain area (312) may be deeper than the depth along the third direction (DR3) of the third and fourth source / drain areas (321, 322).

[0052] In some embodiments, the depths of each source / drain region within a single transistor can be formed differently to increase the path for carriers, such as charge. As a result, the operating performance of the transistor can be further improved under the same area.

[0053] Referring to FIG. 5, the semiconductor device (1000) may include source / drain electrodes (411, 421) provided on the sidewalls of a spacer structure (210). The source / drain electrodes (411, 421) may include a metal-semiconductor compound. For example, the source / drain electrodes (411, 421) may include a metal silicide material such as titanium silicide or nickel silicide.

[0054] An interlayer insulating film (141) may be provided on a substrate (100) and a gate structure (200). The interlayer insulating film (141) may include silicon oxide.

[0055] Contacts (412, 422) connected to source / drain electrodes (411, 421) through the interlayer insulating film (141) may be provided. The lower portion of the contacts (412, 422) may be provided within the upper portion of the source / drain electrodes (411, 421). Conductive patterns (413, 423) connected to the contacts (412, 422), respectively, may be provided on the interlayer insulating film (141). For example, the contacts (412, 422) and the conductive patterns (413, 423) may comprise metals such as copper, aluminum, tungsten, titanium, tantalum, etc., and / or metal nitrides thereof.

[0056] FIG. 6 is a layout diagram for schematically describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0057] Referring to FIG. 6, the gate structure (200) may include a first source / drain region (311_1) extending in a first direction (DR1) adjacent to the first_1 side (200_11) of the gate structure (200), and a second source / drain region (312_1) and a third source / drain region (321_1) respectively disposed adjacent to the first_3 side (200_13) of the gate structure (200) and spaced apart from each other in the first direction (DR1). Referring to FIG. 6, the gate structure (200) may have a C-shape.

[0058] In this case, the length (D_1) along the first direction (DR1) of the first source / drain region (311_1) may be longer than the length (d_1) along the first direction (DR1) of the second source / drain region (312_1) and the third source / drain region (321_1).

[0059] The first source / drain region (311_1) and the second source / drain region (312_1) may be source regions, and the third source / drain region (321_1) may be a drain region. Meanwhile, the technical concept of the present invention is not limited thereto, and the first source / drain region (311_1) may be a drain region, and the second and third source / drain regions (312_1, 321_1) may be source regions.

[0060] Although not specifically illustrated, in this case, the depth along the third direction (DR3) of the first source / drain region (311_1) may be deeper than the depth along the third direction (DR3) of the second source / drain region (312_1) and the third source / drain region (321_1). Meanwhile, the technical concept of the present invention is not limited thereto, and in the case where the first source / drain region (311_1) is a drain region and the third source / drain region (321_1) is a source region, the depth along the third direction (DR3) of the third source / drain region (321_1) may be deeper than the depth along the third direction (DR3) of the first source / drain region (311_1).

[0061] FIG. 7 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0062] Referring to FIG. 7, the lengths along the first direction (DR1) of a plurality of source / drain regions (300) may differ from each other. Specifically, the length (d_2) along the first direction (DR1) of a first source / drain region (311_2) positioned adjacent to the first_1 side (200_11) of a gate structure (200) may be shorter than the length (D_2) along the first direction (DR1) of a third source / drain region (321_2) positioned adjacent to the first_2 side (200_12) of a gate structure (200).

[0063] Additionally, the length along the first direction (DR1) of the second source / drain region (312_2) positioned adjacent to the first_3 side (200_13) of the gate structure (200) may be shorter than the length along the first direction (DR1) of the fourth source / drain region (322_2) positioned adjacent to the first_4 side (200_14) of the gate structure (200).

[0064] In this case, the first source / drain area (311_2) and the second source / drain area (312_2) may be source areas, and the third source / drain area (321_2) and the fourth source / drain area (322_2) may be drain areas.

[0065] FIG. 8 is a layout diagram for schematically describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions of content that is identical or duplicates content described using FIG. 1 to 5 may be simplified or omitted.

[0066] Referring to FIG. 8, the lengths along the first direction (DR1) of a plurality of source / drain regions (300) may differ from each other. Specifically, the length (D_3) along the first direction (DR1) of a first source / drain region (311_3) disposed adjacent to the first_1 side (200_11) of a gate structure (200) may be longer than the length (d_3) along the first direction (DR1) of a third source / drain region (321_3) disposed adjacent to the first_2 side (200_12) of a gate structure (200).

[0067] Additionally, the length along the first direction (DR1) of the second source / drain region (312_3) positioned adjacent to the first_3 side (200_13) of the gate structure (200) may be longer than the length along the first direction (DR1) of the fourth source / drain region (322_3) positioned adjacent to the first_4 side (200_14) of the gate structure (200).

[0068] In this case, the first source / drain area (311_3) and the second source / drain area (312_3) may be source areas, and the third source / drain area (321_3) and the fourth source / drain area (322_3) may be drain areas.

[0069] FIG. 9 is a layout diagram for schematically describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions of content that is identical or duplicates content described using FIG. 1 to 5 may be simplified or omitted.

[0070] Referring to FIG. 9, a first source / drain region (311_4) positioned adjacent to the first_1 side (200_11) of the gate structure (200), a second source / drain region (312_4) positioned adjacent to the first_3 side (200_13) of the gate structure (200), and a third source / drain region (321_4) positioned adjacent to the first_2 side (200_12) of the gate structure (200) may be source regions. Additionally, a fourth source / drain region (322_4) positioned adjacent to the first_4 side (200_14) of the gate structure (200) may be a drain region. That is, three source / drain regions may be source regions, and one source / drain region may be a drain region.

[0071] Meanwhile, the locations of multiple source regions are not limited to a specific sidewall of the aforementioned gate structure and can be formed in various ways.

[0072] Meanwhile, the technical concept of the present invention is not limited thereto, and three source / drain regions may be drain regions, and one source / drain region may be a source region.

[0073] Although not specifically illustrated, in this case, the depth along the third direction (DR3) of the first source / drain area (311_4), the second source / drain area (312_4), and the third source / drain area (321_4) may be deeper than the depth along the third direction (DR3) of the fourth source / drain area (322_4). Meanwhile, the technical concept of the present invention is not limited thereto, and in the case where the first to third source / drain regions (311_4, 312_4, 321_4) are drain regions and the fourth source / drain region (322_4) is a source region, the depth along the third direction (DR3) of the first source / drain region (311_4), the second source / drain region (312_4), and the third source / drain region (321_4) may be shallower than the depth along the third direction (DR3) of the fourth source / drain region (322_4).

[0074] FIG. 10 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0075] Referring to FIG. 10, a first source / drain region (311_5) positioned adjacent to the first_1 side (200_11) of the gate structure (200) and a second source / drain region (312_5) positioned adjacent to the first_3 side (200_13) of the gate structure (200) are source regions, and a third source / drain region (321_5) positioned adjacent to the second_2 side (200_22) of the gate structure (200) may be a drain region. In this case, the third source / drain region (321_5) may overlap with the second_2 side (200_22) in the third direction (DR3). That is, two source / drain regions may be source regions, and one source / drain region may be a drain region. Additionally, a drain region may be placed between two source / drain regions. In this case, the gate structure (200) may be T-shaped.

[0076] Meanwhile, the locations of multiple source regions are not limited to a specific sidewall of the aforementioned gate structure and can be formed in various ways.

[0077] Meanwhile, the technical concept of the present invention is not limited thereto, and two source / drain regions may be drain regions, and one source / drain region may be a source region.

[0078] Although not specifically illustrated, in this case, the depth along the third direction (DR3) of the first source / drain region (311_5) and the second source / drain region (312_5) may be deeper than the depth along the third direction (DR3) of the third source / drain region (321_5). Meanwhile, the technical concept of the present invention is not limited thereto, and in the case where the first and second source / drain regions (311_5, 312_5) are drain regions and the third source / drain region (321_5) is a source region, the depth along the third direction (DR3) of the first source / drain region (311_5) and the second source / drain region (312_5) may be shallower than the depth along the third direction (DR3) of the third source / drain region (321_5).

[0079] FIG. 11 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0080] Referring to FIG. 11, the inner wall (200_3) of the gate structure (200) may have a rounded curved shape. In this case, the exposed area of ​​the gate structure (200) formed by etching at least a portion of the gate structure (200) may have a rounded shape.

[0081] Although not specifically described, the side of the trench (120T) may also have a rounded shape.

[0082] FIG. 12 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. FIG. 13 is a cross-sectional view taken along C-C of FIG. 12. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0083] Referring to FIG. 12, the lengths along the first direction (DR1) of a plurality of source / drain regions (300) may differ from each other.

[0084] Referring to FIGS. 12 and 13, at least a portion of the substrate (100) can be etched so that the second side (120T_2) of the trench (120T) is positioned at a different level in the third direction (DR3) from the second inner wall (200_32) of the gate structure (200) shown in FIG. 1.

[0085] Thus, the second side (120T_2) can be positioned closer to the center of the gate structure (200) than the first side (200_11, 200_12, 200_13, 200_14) of the gate structure (200) with respect to the second direction (DR2).

[0086] FIG. 14 is a layout diagram for schematically illustrating a semiconductor device according to some embodiments of the present invention. For convenience of explanation, descriptions that are identical or duplicates of the descriptions made using FIG. 1 to 5 may be simplified or omitted.

[0087] Referring to FIG. 14, the lengths along the first direction (DR1) of a plurality of source / drain regions (300) may differ from each other.

[0088] Referring to FIG. 14, at least a portion of the substrate (100) can be etched so that the side of the trench (120T) is positioned at a different level in the third direction (DR3) and the second inner wall (200_32) of the gate structure (200) shown in FIG. 1.

[0089] In this case, the side of the trench (120T) may have a rounded curved shape.

[0090] FIG. 15 is a cross-sectional view schematically showing the structure of a source follower transistor according to some embodiment of the present invention. FIG. 16 is a drawing showing an image sensor according to some embodiment of the present invention. FIG. 17 is a circuit diagram schematically showing the structure of a pixel according to some embodiment of the present invention. For convenience of explanation, details that are identical or duplicates those described using FIG. 1 to FIG. 14 may be briefly explained or omitted.

[0091] Referring to FIG. 15, the source follower transistor (1000) may include a substrate (100), a gate structure (200), and a plurality of source / drain regions (300). The details regarding the semiconductor device (1000) described below using FIG. 1 to FIG. 14 may be applied in the same way to the source follower transistor (1000). Meanwhile, the semiconductor device (1000) according to some embodiments is not limited to the source follower transistor (1000) and may be applied to various types of transistors.

[0092] The source region (311) and drain region (322) may contain impurities of the first conductivity type or the second conductivity type. The gate structure (200) may contain a conductive material, and the gate insulating film (GI) may contain an insulating material to insulate the gate structure (200).

[0093] A channel, which is a passage for carriers such as charge to move from a source region (311) to a drain region (322), can be formed according to the voltage applied to the gate structure (200) of the source follower transistor (1000). According to some embodiments, the channel can be formed in a portion of the substrate (100) at a predetermined distance from the gate insulating film (GI).

[0094] Referring to FIG. 1 and FIG. 15, a plurality of source / drain regions (300) may include first and second source / drain regions (311, 312) that are respectively overlapped in the third direction (DR3) with the first_1 and first_3 sides (200_11, 200_13) of the gate structure (200) and spaced apart from each other in the second direction (DR2), and a third source / drain region (321 or 322) that is overlapped in the third direction (DR3) with at least one of the first_2 and first_4 sides (200_12, 200_14) of the gate structure (200) and spaced apart from at least one of the first and second source / drain regions (311, 312) in the first direction (DR1).

[0095] In this case, the voltage applied to the first and second source / drain regions (311, 312) and the voltage applied to the third source / drain region (321 or 322) may be different from each other. In this case, the voltage applied to the first and second source / drain regions (311, 312) may operate based on a value different from the voltage applied to the third source / drain region (321 or 322).

[0096] As illustrated in FIG. 16, the module lens (3000) can refract light and cause it to be incident on the image sensor (2000). The image sensor (2000) can output data (DATA) based on the incident light, and the output data can be processed into image data by an image processor, etc.

[0097] Referring to FIG. 16, the image sensor (2000) may include a pixel array (2100), a row driver (2220), a lead circuit (2240), a controller (2260), and a voltage supply circuit (2280). The pixel array (2100) may include a plurality of pixels (1000A). A pixel (1000A) may include a light-sensing element, and the light-sensing element may generate an electrical signal according to the intensity of the absorbed light. A pixel (1000A) may be controlled by a row signal (R_SIG) output by a row driver (2220). For example, a pixel (1000A) may include at least one transistor, and the gate of the transistor may be connected to the row signal (R_SIG). Additionally, the pixel (1000A) may include a transistor that amplifies an electrical signal generated by a light-sensing element, and may include, for example, a source follower transistor (1000) shown in FIG. 15.

[0098] Pixels (1000A) included in a row of the pixel array (2100) can be controlled by the same row signal (R_SIG). The pixel (1000A) can output a signal according to an electrical signal generated by a light-sensing element. For example, pixels (1000A) included in a column of the pixel array (2100) can output an output voltage (V_OUT) to the outside of the pixel array (2100) through the same signal line.

[0099] The low driver (2220) can be controlled by the controller (2260) and can control each pixel (1000A) included in the pixel array (2100) by outputting a low signal (R_SIG). For example, the low driver (2220) can control, through the low signal (R_SIG), to reset the node to which the electrical signal generated by the light-sensing element of the pixel (1000A) absorbing light is transmitted, or to move the generated electrical signal to the outside of the pixel.

[0100] The lead circuit (2240) can receive an output voltage (V_OUT) from the pixel array (2100) and output data (DATA) according to the output voltage (V_OUT). For example, the lead circuit (2240) may include an Analog to Digital Converter (ADC), and the ADC may receive an output voltage (V_OUT), which is an analog signal, and output data (DATA), which is a digital signal. The controller (2260) can output at least one control signal and can control the row driver (2220) and the lead circuit (2240) through the control signal.

[0101] The voltage supply circuit (2280) can supply voltage to the pixel array (2100). For example, as shown in FIG. 16, the voltage supply circuit (2280) can generate and supply first and second voltages (V_1, V_2) to the pixel array (2100). The first and second voltages (V_1, V_2) can be applied to the transistors included in the pixels (1000A) of the pixel array (2100).

[0102] Referring to FIG. 17, the pixel (1000A) can be controlled by a low signal (R_SIG) and can output an output voltage (V_OUT). As illustrated in FIG. 17, the pixel (1000A) may include a photodiode (110A), a transfer transistor (120A), a source follower transistor (1000), a select transistor (140A), and a reset transistor (150A). Additionally, the low signal (R_SIG) received by the pixel (1000A) from the low driver (2220) may include a reset signal (Rx), a transfer signal (Tx), and a select signal (Sx). The transistors included in the pixel (1000A) may be MOS transistors.

[0103] The pixel (1000A) may include a light-sensing element that absorbs light and generates an electrical signal, and, for example, the light-sensing element may be a photodiode, a photogate, or a phototransistor. In the following description, the light-sensing element is described as a photodiode (110A) as shown in FIG. 17, but the present invention is not limited thereto.

[0104] The transfer transistor (120A) can pass or block the charge accumulated by the light-sensing element (110A) to the floating diffusion region (FD) depending on the transfer signal (Tx). For example, while the light-sensing element (110A) absorbs light and accumulates charge, a transfer signal (Tx) of a voltage capable of turning off the transfer transistor (120A) can be applied to the gate of the transfer transistor (120A). Additionally, when the light-sensing element (110A) accumulates charge for a certain period of time, a transfer signal (Tx) of a voltage capable of turning on the transfer transistor (120A) can be applied to the gate of the transfer transistor (120A).

[0105] The source follower transistor (1000) can amplify the voltage of the floating diffusion region (FD), and the select transistor (140A) can selectively output the amplified voltage according to the select signal (Sx). The reset transistor (150A) can set the voltage of the floating diffusion region (FD) to a reset voltage close to the second voltage (V_2) by connecting or disconnecting the floating diffusion region (FD) and the second voltage (V_2) according to the reset signal (Rx). In this way, a pixel (1000A) including a component that amplifies the electrical signal converted by the light-sensing element (110A) absorbing light can be referred to as an Active Pixel Sensor (APS).

[0106] As illustrated in FIG. 17, a voltage of a floating diffusion region (FD) can be applied to the gate structure of a source follower transistor (1000), and a first voltage (V_1) can be applied to a drain region. Accordingly, the source follower transistor (1000) can output a voltage corresponding to the voltage of the floating diffusion region (FD) through the drain region.

[0107] Referring to FIGS. 16 and 17, the first and second voltages (V_1, V_2) can be generated by the voltage supply circuit (2280) of the image sensor (2000). The second voltage (V_2) is intended to reset the floating diffusion region (FD) through the reset transistor (150A). Since the reset of the floating diffusion region (FD) is performed with the transfer transistor (120A) turned off, current can flow due to the movement of charges trapped in the floating diffusion region (FD) prior to the reset.

[0108] As shown in FIG. 17, the voltages of the gate, source, and drain regions of the source follower transistor (1000) included in the pixel (1000A) can be referred to as V_G, V_S, and V_D, respectively. V_G, V_S, and V_D can represent the voltages of the gate, source, and drain regions of the source follower transistor (1000) with respect to the ground voltage, respectively.

[0109] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0110] 100: Substrate 120T: Trench 120: Insulating film 200: Gate structure GI: Gate insulating film GE: Gate electrode 210: Spacer structure 300: Source / drain area 1000: Semiconductor device

Claims

Claim 1 A substrate extending in first and second directions intersecting each other; a gate structure disposed on the substrate and comprising a first side and a second side extending parallel to the first direction and spaced apart from each other in the second direction, and a third side extending parallel to the first direction or the second direction; The invention includes a plurality of source / drain regions of a first conductivity type disposed within the substrate, wherein the plurality of source / drain regions comprises a first and second source / drain region spaced apart from each other in the second direction and a third source / drain region spaced apart from at least one of the first and second source / drain regions in the first direction, wherein the first and second source / drain regions overlap with the first and second sides, respectively, in a third direction perpendicular to the first and second directions, and the third source / drain region overlaps with the third side in the third direction, and the operation is based on the voltage applied to the first and second source / drain regions and the voltage applied to the third source / drain region being different values, wherein in the first direction, the length of the first source / drain region is equal to the length of the first side, and the length of the second source / drain region is equal to the length of the second side, and from a planar perspective, the gate structure is an I-shaped semiconductor Device. Claim 2 A semiconductor device according to claim 1, wherein the voltage applied to the third source / drain region is greater than the voltage applied to the first and second source / drain regions. Claim 3 A semiconductor device according to claim 1, wherein the voltage applied to the third source / drain region is smaller than the voltage applied to the first and second source / drain regions. Claim 4 A semiconductor device according to claim 1, wherein, with respect to the first direction, the length of at least one of the first and second source / drain regions and the length of the third source / drain region are different. Claim 5 delete Claim 6 A semiconductor device according to claim 1, wherein the gate structure further comprises a fourth side that extends parallel to the first direction and is spaced apart from the third side and the second direction, and further comprises a fourth source / drain region that overlaps the fourth side of the gate structure with the third direction and is spaced apart from the first and second source / drain regions, respectively, in the first direction. Claim 7 A semiconductor device according to claim 6, wherein the voltage applied to the third source / drain region is greater than the voltage applied to the fourth source / drain region. Claim 8 A semiconductor device according to claim 1, wherein the gate structure comprises a first inner wall extending along the second direction from the first side and a second inner wall connected to the first inner wall and extending along the first direction. Claim 9 A semiconductor device according to claim 1, wherein a trench defining an active region between the substrate and the gate structure and an insulating film filling the interior of the trench are formed within the substrate, and the insulating film is disposed between the first and third source / drain regions. Claim 10 A gate structure comprising a first side and a second side that are spaced apart from each other in a second direction that extends parallel to a first direction and intersects the first direction, and a third side that extends parallel to the first direction or the second direction, wherein a voltage corresponding to the charge accumulated by a light sensing element is applied; A source follower transistor comprising a plurality of source / drain regions of a first conductivity type, wherein the plurality of source / drain regions comprises a first and second source / drain region spaced apart from each other in the second direction and a third source / drain region spaced apart from at least one of the first and second source / drain regions in the first direction, wherein the first and second source / drain regions each overlap with the first and second sides in a third direction perpendicular to the first and second directions, and the third source / drain region overlaps with the third side in the third direction, and the operation is based on the voltage applied to the first and second source / drain regions and the voltage applied to the third source / drain region being different values, wherein in the first direction, the length of the first source / drain region is equal to the length of the first side, and the length of the second source / drain region is equal to the length of the second side, and in a planar view, the gate structure is I-shaped. Image sensor.

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