A low-density parity-check (LDPC) decoder of reconstruction-computation-quantization (RCQ) approach for a storage device

Abstract

The disclosed device includes an input buffer for receiving a first short bit width message. A reconstruction circuit for generating a first long bit width message may implement a reconstruction function for the first short bit width message. A computation circuit for generating a second long bit width message may implement a computation function for the first long bit width message. A quantization circuit for generating a second short bit width message may implement a quantization function for the second long bit width message. A decision buffer may store the second short bit width message. The reconstruction function and the quantization function may vary depending on the iteration and hierarchy of the device.

Description

Technology Field

[0001] The present disclosure generally relates to storage devices, and more specifically, to an improved measurement of codewords. Background Technology

[0002] The measurement of information bits from encoded codewords stored in storage devices, referred to as decoding, can be computationally difficult. Dedicated circuits for decoding can utilize resources that would otherwise be used for other purposes. However, if the resources allocated to the decoder are limited, the decoder's performance may degrade. Specifically, the decoder may take more time to measure, which can slow down other processes within the storage device that depend on the codewords. Furthermore, due to the limited resources allocated to decoding, the decoder may inaccurately measure the original information bits, leading to more decoding failures.

[0003] There is a need to decode information faster and more accurately without requiring significant additional resources. The problem to be solved

[0004] The object of the present invention is to provide an apparatus comprising an LDPC decoder using a reconstruction-computation-quantization (RCQ) approach and a corresponding LDPC decoding method. means of solving the problem

[0005] Embodiments of the present disclosure include a low-density parity-check (LDPC) decoder. The LDPC decoder may use a reconstruction-computation-quantization (RCQ) approach at each layer of the decoder that potentially implements different reconstruction and quantization functions. In this way, improved decoder performance can be achieved. Effects of the invention

[0006] According to an embodiment of the present disclosure, the performance of an LDPC decoder can be improved by using an RCQ approach. Brief explanation of the drawing

[0007] The drawings described below are examples of how embodiments of the present disclosure may be implemented and are not intended to limit the embodiments of the present disclosure. Individual embodiments of the present disclosure may include elements not shown in specific drawings and / or may omit elements shown in specific drawings. The drawings are provided for illustrative purposes only and may not be drawn in proportion. FIG. 1 shows a system including a storage device capable of using an RCQ approach in a QC-LDPC decoder according to embodiments of the present disclosure. FIG. 2 specifically shows the machine of FIG. 1 according to embodiments of the present disclosure. FIG. 3 specifically shows a case where the storage device of FIG. 1 according to embodiments of the present disclosure is implemented as an SSD. FIG. 4 shows a general layout of the QC-LDPC code of the SSD of FIG. 3 according to embodiments of the present disclosure. FIG. 5 shows a general layout of the RCQ approach in the QC-LDPC code of the SSD of FIG. 3 according to embodiments of the present disclosure. FIG. 6 shows the structure of the decoder of FIG. 4 according to an embodiment of the present disclosure. FIG. 7 shows the memory of FIG. 6 storing tables for reconstruction and quantization functions according to an embodiment of the present disclosure. Figure 8 shows a graph comparing the error rates when using other decoders and the decoder of Figure 4. Figure 9 shows a graph comparing the average repetition time when using other decoders and the decoder of Figure 4. FIGS. 10A and 10B show a flowchart of an exemplary procedure using the decoder of FIG. 6 according to embodiments of the present disclosure. Specific details for implementing the invention

[0008] Hereinafter, reference will be made to embodiments of the present disclosure in detail, and examples thereof will be described in the accompanying drawings. In the following description of the invention, many specific details are provided for a thorough understanding of the present disclosure. However, it should be understood that a person skilled in the art can practice the present disclosure without these specific details. In other cases, conventional methods, procedures, components, circuits, and networks are not described so as not to unnecessarily obscure the embodiments.

[0009] Terms such as “first,” “second,” etc., may be used to describe various elements, but it should be understood that these elements are not limited to these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first module may be named the second module, and similarly, the second module may be named the first module.

[0010] The terms used in the following description of the disclosure are intended to describe specific embodiments and are not intended to limit the disclosure. As used in the description of the disclosure and in the appended claims, the singular forms of “single,” “one,” and “above” are intended to include the plural forms unless clearly indicated in the context. The term “and / or” used below shall be understood to refer to and include all possible combinations of one or more of the related enumerated items. Additionally, the terms “comprising” and / or “comprising” used below shall be understood to specify the presence of the mentioned features, integers, steps, actions, elements, and / or components, but not to exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or combinations thereof. The components and features of the drawings are not necessarily drawn to scale.

[0011] Quasi-cyclic (hereinafter QC) low-density parity-check (hereinafter LDPC) codes are a family of structured LDPC codes that are linear block codes characterized by a parity check matrix H composed of square submatrices that are cyclic permutations (also called circulants) of a zero matrix or an identity matrix. Because QC-LDPC codes can reduce data processing latency and improve throughput, QC-LDPC codes can be used in solid-state drives (SSDs) or other storage devices.

[0012] The QC-LDPC code is the UXW matrix H P It can be expressed in a simplified way like this. H P Each element of is 0 or defined as the zero matrix and the cyclic matrix cyclically shifted by i. is. If the size of the square submatrix is ​​m x m, it must follow Equation 1.

[0013]

[0014] Unlike flooding scheduled decoding, layered decoding can converge faster because it can utilize updated messages. In one implementation, layered decoding is horizontal layered decoding. The QC-LDPC code can be compatible with horizontal layered decoding by dividing inspection nodes into U consecutive groups. When using QC-LDPC with horizontal layered decoding, each variable node can be connected to at most one inspection node in each layer.

[0015] The MinSum (minimum sum) decoder is a low-complexity decoder for QC-LDPC codes that can be used. In the i-th iteration, according to Equations 2 to 4, the horizontally layered MinSum decoder can update the soft information of variable node h connected to check node l.

[0016]

[0017]

[0018]

[0019] As an alternative to the MinSum decoder, a reconstruction-computation-quantization (RCQ) decoder can be used for both variable node and check node operations. The RCQ decoder may include three parts.

[0020] 1. Reconstruction function is a low-bit external message (u) from a connected node i Receive ) and internal high-bit message (r i ) low-bit external message (u iIt can be mapped to ).

[0021] 2. Calculation Functions is a high-bit message (r i high-bit output (r) from ) out ) can be calculated.

[0022] 3. Quantization function is high-bit output (r out ) low-bit external message (u out Quantized into ) and low-bit external message (u) to connected nodes out It can pass )

[0023] If the computation module implements belief propagation, this decoder may be named a belief propagation RCQ (hereinafter bpRCQ). If the computation module implements MinSum, this decoder may be named a MinSum RCQ (hereinafter msRCQ). Three tuples including the accuracy of the external message, the internal message of the check node, and the internal message of the mutable node ( ) can be used to describe the accuracy of the RCQ decoder. Consequently, It can be used to represent floating-point operations.

[0024] In contrast to the RCQ decoder, a layered RCQ (hereinafter L-RCQ) decoder can be described. The structure of the L-RCQ decoder is a function and It may differ from the basic structure of an RCQ decoder in that it can vary depending on the hierarchy and iteration. can be used to represent the variable node quantization function of layer l in the i-th iteration. Layer-specific parameters of the L-RCQ decoder can be selected so that the probability density of the message coming from each layer can be tracked.

[0025] To construct the parameters for each layer of the L-msRCQ decoder, the probability density function (pdf) of the messages emerging from each layer must be known. For this purpose, L-MIM-DDE (layered mutual-information-maximization discrete density evolution) can be used. In L-MIM-DDE, the coupling probability between the code bits and the output messages (T) from the variable nodes and variable nodes can be tracked in each iteration. , , can be used to represent the probability distribution of the inspection node output messages of layer l in the i-th iteration. Similarly, It can be used to represent the probability distribution of variable node output messages of layer l in the i-th iteration.

[0026] If the layer size is equal to the lifting size m, L-MIM-DDE is H p It can be calculated through. The l layer is H p It can be identical to the inspection node l. The degree of inspection node l is d cl It is defined as.

[0027] L-MIM-DDE can be implemented using an AWGN (additive white Gaussian noise) channel. HDQ (hierarchical dynamic quantization) can be used to realize MIM quantization of channel observations. , , It can be used to represent the probability distribution of a quantized channel.

[0028] In the i-th iteration and l-level, mutable nodes The probability distribution of output messages from can be calculated by mathematical formula 5.

[0029]

[0030] Binary operator It can be used to calculate the sum of the LLR (log-likelihood ratio) of two input messages and can follow the relationship of Equation 6.

[0031]

[0032] Equation 6 does not assume that all messages coming from other layers have the same probability. On the contrary, Equation 6 can utilize updated messages in a timely manner: k<l 일 때, 수학식 6은 업데이트된 메시지를 활용할 수 있고, k> When l, Equation 6 can use old messages. Therefore, Equation 6 can solve the information discrepancy problem.

[0033] By using layer-specific RCQ parameters, the L-RCQ decoder ensures that all messages assigned to other variable nodes connected to the same layer can have the same probability distribution. And It can be calculated by mathematical formula 7.

[0034]

[0035] Consequently, , , and The HDQ that quantizes can be calculated by mathematical formula 8.

[0036]

[0037] L-MIM-DDE can be implemented using symmetric AWGN channels. If is used to represent the LLR of messages (t) from variable nodes connected to layer l in the i-th iteration, It can be calculated by mathematical formula 9.

[0038]

[0039] Because of symmetry, It can have the following attributes.

[0040] Monotonic increasing: When,

[0041] symmetry:

[0042] Based on the two properties described above, the MinSum operation can be implemented in relation to the label and can follow the relationship of Equation 10.

[0043]

[0044] Here, It identifies labels where LLR is m.

[0045] Since it is assumed that all messages from different variable nodes in each layer have the same probability density, It can be calculated by mathematical formula 11.

[0046]

[0047] The msRCQ decoder can be calculated by Equation 12.

[0048]

[0049] Since Equation 12 does not increase the cardinality of the output message and This can be derived. An example of pseudocode for L-MIM-DDE is shown below. The OSA (one-step annealing) algorithm can be a coarse quantization algorithm that reduces the computation required for HDQ.

[0050] Algorithm 1:

[0051]

[0052] In one implementation of the code, the following properties may be used: n = 37632, r = 0.8707, m = 128, I T= 20. The 5-bit L-msRCQ can be compared with the 5-bit msRCQ, BP, and fixed-point offset MinSum decoder. All decoders can be implemented as a horizontally layered schedule with a layer size of 128.

[0053] 5-bit L-msRCQ demonstrates better performance than 5-bit msRCQ and 10-bit offset MinSum. Excluding error correction performance, L-msRCQ appears to have a shorter average iteration time than msRCQ. The average iteration time of the L-msRCQ decoder with trust propagation is When is high, it is similar to the average iteration time of the 10-bit offset MinSum. The better frame error rate (FER) and shorter average iteration time of L-msRCQ may both be issues of the parameter design of the layered msRCQ, which tracks the probability density of messages at each layer. Consequently, Table 1 summarizes the FER and average iteration times of the three decoders and shows the L-RCQ decoder with the best performance among the three decoders.

[0054] Offset MinSum RCQ L-RCQ bit width 10 5 5 Average iteration time 7.5 12.5 7.5

[0055] FIG. 1 shows a system including a storage device capable of using an RCQ approach in a QC-LDPC decoder according to embodiments of the present disclosure. In FIG. 1, the machine (105) may include a processor (110), memory (115), and a storage device (120). The processor (110) may be any various processor. (The processor (110) is shown outside the machine for convenience of explanation, together with other components described below: embodiments of the present disclosure may include these components within the machine.) Although FIG. 1 shows a single processor (110), the machine (105) may include any number of processors, each of which may be a single-core or multi-core processor, may have a RISC (reduced instruction set computer) architecture or a CISC (complex instruction set computer) architecture (among other possibilities), and may be combined in any desired combination. The processor (110) may be connected to memory (115). The memory (115) may be any various type of memory, such as flash memory, DRAM (dynamic random access memory), SRAM (static random access memory), PRAM (persistent random access memory), FRAM (ferroelectric random access memory), NVRAM (non-volatile random access memory), MRAM (magnetoresistive random access memory), etc. The memory (115) may be any desired combination of other memory types and may be managed by a memory controller (125). The memory (115) may be used to store data referred to as “short-term” (i.e., data not expected to be stored for an extended period).Examples of short-term data may include temporary files and data used locally by applications (which can be copied from other storage locations).

[0056] Additionally, the processor (110) and memory (115) may support an operating system in which various applications are running. These applications may issue requests to read data from memory (115) or storage device (120) or to write data to memory (115) or storage device (120). For example, the storage device (120) may be used to store initial parameters used to initialize a simulation (or, along with the type of behavior represented by the range of values ​​of the initial parameters). The storage device (120) may be accessed using a device driver (130). Although FIG. 1 uses the general term “storage device,” embodiments of the present disclosure may include any type of storage device capable of utilizing an LDPC decoder using an RCQ access method, such as a hard disk drive or a solid state drive (SSD). Any reference to “SSD” described below should be understood to include such other embodiments of the present disclosure.

[0057] FIG. 2 specifically illustrates the machine (105) of FIG. 1 according to embodiments of the present disclosure. In FIG. 2, typically, the machine (105) includes one or more processors (110) including memory controllers (125) and a clock (205) that can be used to coordinate the operation of the components of the machine (105). Additionally, the processors (110) may be connected to memories (115) that may include, for example, RAM (random access memory), ROM (read-only memory), or other state storage media. Additionally, the processors (110) may be connected to storage devices (120) and a network connector (210) that may be, for example, an Ethernet connector or a wireless connector. Additionally, the processors (110) may be connected to buses (215) to which user interfaces (220) may be attached and I / O interface ports that can be managed using I / O engines (225) among other components may be attached.

[0058] FIG. 3 specifically illustrates a case where the storage device (120) of FIG. 1 according to embodiments of the present disclosure is implemented as an SSD. In FIG. 3, the SSD (120) may include an interface (305). The interface (305) may be an interface used to connect the SSD (120) to the machine (105) of FIG. 1. The SSD (120) may include one or more interfaces (305): for example, one interface may be used for block-based read and write requests, and another interface may be used for key-value read and write requests. While FIG. 3 suggests that the interface (305) is a physical connection between the SSD (120) and the machine (105) of FIG. 1, the interface (305) may represent a protocol difference that can be used across a common physical interface. For example, the SSD (120) can be connected to the machine (105) using a U.2 or M.2 connector, but can support block-based requests and key-value requests: processing other types of requests can be performed by other interfaces (305).

[0059] Additionally, the SSD (120) may include a host interface layer (310) capable of managing interfaces (305). If the SSD (120) includes one or more interfaces (305), a single host interface layer (310) may manage all interfaces, the SSD (120) may include a host interface layer for each interface, or a combination thereof may be used.

[0060] Additionally, the SSD (120) may include an SSD controller (315) and various channels (320-1, 320-2, 320-3, 320-4), and accordingly, various flash memory chips (325-1, 325-2, 325-3, 325-4, 325-5, 325-6, 325-7, 325-8) may be arranged. The SSD controller (315) may manage the transmission of read requests and write requests to the flash memory chips (325-1 to 325-8) through the channels (320-1 to 320-4). Although FIG. 3 illustrates four channels and eight flash memory chips, embodiments of the present disclosure may include any number of channels (one or more, and without limitation) including any number of flash memory chips.

[0061] Within each flash memory chip, space can be organized into blocks, which can be further divided into pages and grouped into superblocks. A page is generally the smallest unit of data that can be read or written in an SSD. Page sizes can vary: for example, a page can be 4KB of data. When less than the total amount of data written is less than the entire page, the excess space is "unused."

[0062] While pages are being written and read, SSDs generally do not allow data to be overwritten: that is, existing data is not replaced “in place” with new data. Instead, when data is updated, the new data is written to a new page on the SSD, and the existing page is invalidated (marked as ready for deletion). Therefore, SSD pages typically have one of three states: free (ready to write), valid (contains valid data), and invalid (no longer contains valid data and cannot be used until deleted). The naming of these states may vary.

[0063] However, while pages can be written and read individually, a block is the basic unit of data that can be erased. That is, pages are not erased individually: all pages within a block are generally erased simultaneously. For example, if a block contains 256 pages, all 256 pages within the block are erased simultaneously. This arrangement can lead to management issues for SSDs: if a block containing some valid data is selected for erasure, that valid data may need to be copied to a free page elsewhere in the SSD before the block is erased. (In some embodiments of the present disclosure, the unit of erasure may differ from a block: for example, the unit of erasure may be a superblock, which may be a set of multiple blocks.)

[0064] The SSD controller (315) may include a flash translation layer (330) (which, more generally, may be referred to as a logical-to-physical translation layer in storage devices that do not use flash storage) and an error correction code (335). The flash translation layer (330) may handle the translation of a logical block address (LBA) or other logical ID (used by the processor (110) of FIG. 1), and a physical block address (PBA) or other physical address where data is stored in the flash chips (325-1 to 325-8). The error correction code (335) may apply (i.e., set and / or use) error correction codes to data being written to or / or read from the flash memory chips (325-1 to 325-8). FIG. 3 illustrates one flash conversion layer (330), but embodiments of the present disclosure may include any number (one or more, without limitation) of flash conversion layers (330). FIG. 3 illustrates one error correction code (335), but embodiments of the present disclosure may include any number (one or more, without limitation) of error correction codes (335).

[0065] While direct calculation of codewords (or direct use of codewords to perform error correction) is possible, implementing this function in hardware can consume significant resources (e.g., space on the printed circuit board (PCB) within the SSD (120) of FIG. 3). To reduce the resources required to implement error correction, other approaches may be used. One approach that can be used is an iterative approach. In an iterative approach, the problem is not solved directly (e.g., by using complex formulas), but instead is solved sequentially (e.g., by using simple formulas). For example, consider the problem of identifying the points where a complex curve intersects the x-axis (i.e., x-intercepts). Using algebra, one can take the equation defining the curve and solve for where the x-intercepts lie, but teaching a computer or circuit to perform such calculations can be excessively difficult. On the other hand, given an equation defining a function, calculating y=f(x) can be simple. If the derivative (f') of a function is also easily determined, finding the location of the x-intercept for the function f(x) is easily defined.

[0066] 1) Select x0.

[0067] 2) Calculate y0 = f(x0).

[0068] 3) Calculate y'0 = f'(x0). (This represents the slope of the tangent to the curve at (x0, y0).)

[0069] 4) Using x0, y0, and y'0, a straight line passing through (x0, y0) with a slope of y'0 can be calculated.

[0070] 5) Calculate the x-intercept for the identified line.

[0071] This process can be repeated by replacing the most recently determined x-intercept with x0. Each iteration of this sequence yields a point on the curve that is closer to the curve's x-intercept.

[0072] This process is said to converge when the points in a successive iteration of this sequence get close enough to be considered effectively equivalent to the correct answer (e.g., within a specific value denoted by Λ or ε). The circuitry involved in calculating the value of a function or its derivative and identifying a line passing through a specific point with a specific slope is relatively simple (and generally simpler than the circuitry involved in calculating a direct solution to the problem). Therefore, the problem of finding the x-intercepts for a curve can be solved using fewer resources than attempting a direct solution to the problem. The tradeoff is that while a direct solution can immediately identify the x-intercepts, using an iterative approach like the one described above may require multiple iterations before the sequence converges to a solution (if the sequence fully converges), and thus may take more time.

[0073] In the same way, using an iterative approach to decode codewords can use fewer resources, but it may require numerous iterations to complete the computation (for the decoder to identify a solution). By using an iterative approach, fewer resources (fewer circuits and / or shorter bit widths for the data) can be used to decode codewords.

[0074] However, when using an iterative approach instead of a direct approach, additional considerations may arise. The first consideration may be the number of iterations required to solve the problem. The number of iterations does not necessarily have to be predictable; that is, it may vary depending on the problem being solved. Reconsidering an iterative solution for finding the x-intercept of a curve, many iterations may be required if each iteration provides only a slight improvement over the previous iteration in approximating the x-intercept, whereas the x-intercept can be found quickly if the curve approximates a straight line. The second consideration is the time required to complete the iterations for the solution. For example, if a single iteration of one algorithm takes, say, 10 seconds and a single iteration of another algorithm takes only 1 second, 10 iterations of the second algorithm could be completed in the same amount of time as the first algorithm. An algorithm with a smaller average iteration time may be superior to an algorithm with a longer average iteration time.

[0075] Of course, it can be important to balance the average iteration time with the resources used to implement the iteration algorithm. For some implementations, faster performance may be required, while for others, using fewer resources may be required.

[0076] FIG. 4 shows a general layout of the QC-LDPC code of the SSD (120) of FIG. 3 according to embodiments of the present disclosure. In FIG. 4, an error correction code (335) is shown. The error correction code (335) may include a QC-LDPC (405). The QC-LDPC (405) may include many layers, as shown in layers (410). The QC-LDPC (405) may include an encoder (415) (used to generate an error correction codeword) and a decoder (420) (used to attempt to perform error correction using the error correction codeword).

[0077] Layers such as layers (410) represent variations of the concept of repetition. Using layers (410), other functions may be used as part of a decoder (which may be named a device): the individual functions used may vary depending on the layer. On the other hand, repetition may represent a sequence of using each layer (410) in a specified order. Thus, when speaking of decoding a codeword using a decoder (420), this approach may include both repetition and layers.

[0078] FIG. 5 shows a general layout of the RCQ approach in the QC-LDPC code of the SSD (120) of FIG. 3 according to embodiments of the present disclosure. In FIG. 5, various short bit width messages (505) may be inputs. A reconstruction circuit (510) may be applied to each input of short bit width messages (505). (Although FIG. 5 illustrates multiple copies of the reconstruction circuit (510), a single reconstruction circuit (510) or multiple reconstruction circuits (510) may be provided for repeated use as required for each input message (505) in implementation.) The reconstruction circuit (510) may then generate long bit width messages (515) for each input short bit width message (505).

[0079] Various long bit width messages (515) can be input to the computation circuit (520). (Depending on the implementation, C () or FA computation circuit (520), which may be implemented as a function described by () and may also be described by other names, can subsequently perform functions for long bit-width messages (515). For example, the computation circuit (520) can generate a sum of long bit-width messages (515) or implement a minimum function of long bit-width messages (515). Embodiments of the present disclosure may also implement other functions using the computation circuit (520). The computation circuit (520) can subsequently generate a long bit-width message (525).

[0080] The quantization circuit (530) can take a long bit width message (525) and quantize the long bit width message (525) to generate a short bit width message (535).

[0081] In some embodiments of the present disclosure, short bit-width messages (505, 535) may have a width of 5 bits, and long bit-width messages (515, 525) may have a width of 10 bits. However, in other embodiments of the present disclosure, short bit-width messages (505, 535) and long bit-width messages (515, 525) may have different bit widths. However, having the general meanings of “short” and “long,” some embodiments of the present disclosure may include short bit-width messages (505, 535) having fewer bits than long bit-width messages (515, 525). (However, other embodiments of the present disclosure may have more bits in short bit-width messages (505, 535) than in long bit-width messages (515, 525).)

[0082] In FIG. 5, the reconfiguration circuit (510) It shows the implementation of the function, and the quantization circuit (530) It shows the implementation of a function. The subscript v indicates that the decoder (420) of FIG. 4 can be implemented using two nodes (variable node and check node). In some embodiments of the present disclosure, each node can perform reconstruction and quantization: thus, the subscript v may reflect the fact that the reconstruction circuit (510) and the quantization circuit (530) are illustrated for the variable node of the decoder (420). However, the reconstruction and quantization circuits for the check node may operate similarly (although using different functions of reconstruction and quantization).

[0083] function and The superscript (l, i) of may reflect the fact that the corresponding function may depend on both iteration i and layer l to which a specific reconstruction and quantization function is applied. In some embodiments of the present disclosure, the function and It can vary depending on the layer. (However, while each layer may use a different function, the function can be the same for the corresponding layers over time.) In other words, for example, and can all be different functions, but and may be the same function. In other embodiments of the present disclosure, the function and It can vary based on the execution layer and the repetition of the sequence. In other words, for example, , , and All of them can be different functions.

[0084] function and can be determined using a desired technique. In some embodiments of the present disclosure, a layered mutual-information-maximization discrete density evolution (L-MIM-DDE), or more generally a density evolution technique, is a function as described in Algorithm 1 above. and It can be used to design.

[0085] FIG. 6 shows the structure of the decoder (420) of FIG. 4 according to an embodiment of the present disclosure. In FIG. 4, the decoder (420) may include a variable node (605) and a check node (610). The variable node (605) may perform the main implementation of the RCQ approach, and the check node (610) may perform a check to see if the calculation is being performed correctly.

[0086] The decoder (420) may include an input buffer (615) that receives short message width messages from the QC-LDPC code (405) of FIG. 4 to perform decoding. Subsequently, the variable node (605) may use a reconstruction circuit (510), a calculation circuit (520) (shown in FIG. 6 as implementing an addition operation), and a quantization circuit (530) to move messages between short bit width and long bit width and to perform calculations on long bit width messages.

[0087] The variable node (605) is S h It is depicted as including. S h can represent “soft” information associated with one or more encoded bits. In each iteration, S h It can be used to make decisions in relation to the encoded bit(s).

[0088] The inspection node (610) may include its own reconstruction circuit (620) and quantization circuit (625), along with a calculation circuit (630) (illustrated as implementing a minimum function) for performing calculations on long bit width messages. The inspection node (610) generally operates on short bit width messages: the reconstruction circuit (620) and quantization circuit (625) may map between label messages and LLR messages used in the variable node (605). However, while FIG. 6 illustrates a calculation circuit (630) using the same bit width as short bit width messages in the variable node (605), embodiments of the present disclosure may include an inspection node (610) using a different bit width (such as a long bit width or another bit width).

[0089] Consequently, when the messages converge to a solution, the output can be sent back to the requester (e.g., QC-LDPC code (405) of FIG. 4) using the decision buffer (635), at which time the requester can read the decoded bits from the decision buffer (635), for example. These solution / decoded bits may be an optimal approximation of the input data received by the decoder (420). That is, considering that the data received by the decoder (420) may have errors, the output of the decoder (420) may be the input data with errors corrected by the decoder (420).

[0090] Additionally, the decoder (420) may include memory (640). Memory (640) contains various functions used in different layers and different iterations and It can be used to store. Although FIG. 6 shows the memory (640) as part of the decoder (420), the memory (640) may exist anywhere inside the SSD (120) of FIG. 3, or it may be the memory (115) of FIG. 1.

[0091] function and Although it may be implemented as a mathematical function capable of performing operations on any possible input values, in some embodiments of the present disclosure, the functions and It can be implemented as a lookup table. That is, given a specific short bit-width message, the function It can store a corresponding long bit-width message, and given a specific long bit-width message, the function It can store a corresponding short bit-width message. Consequently, the function and It may not be a continuous function and may not be defined for any input not listed in the lookup table. Such a lookup table may be stored in memory (640) as shown in FIG. 7.

[0092] FIG. 7 shows the memory (640) of FIG. 6 storing tables for reconstruction and quantization functions according to an embodiment of the present disclosure. In FIG. 7, tables (705, 710) are shown. Table (705) shows reconstruction functions, and table (710) shows quantization functions.

[0093] In FIG. 7, the table (705, 710) is composed of rows, each row per layer. In some embodiments of the present disclosure, the same function may be used in a specific layer across different iterations. In these embodiments of the present disclosure, each entry in the table (705, 710) may be a definition of the appropriate function. However, in other embodiments of the present disclosure, different functions may be used in each iteration as well as in each layer. In these embodiments of the present disclosure, each row in the table (705, 710) may actually contain a table for that layer. Thus, the table (715) shows an extension of the reconstruction function for layer 1. As illustrated, the table (715) shows multiple entries paired with short bit-width messages and long bit-width messages. For example, entry (720-1) pairs a short bit-width message (1, 1) with a long bit-width message (1, 1), entry (720-2) pairs a short bit-width message (1, 2) with a long bit-width message (1, 2), and entry (720-3) pairs a short bit-width message (1, i) with a long bit-width message (1, i). In table (715), identifier “1, 1” can be understood as identifying layer 1, iteration 1, identifier “1, 2” can be understood as identifying layer 1, iteration 2, and identifier “1, i” can be understood as identifying layer 1, iteration i. Entries for quantization functions can be managed similarly.

[0094] FIG. 7 shows that the table (705, 710) is stored organized by layers, but embodiments of the present disclosure may organize the table (705, 710). For example, in an embodiment of the present disclosure where different functions are used in a corresponding layer in a different iteration, the table (705, 710) may be organized by iteration and then organized by layers.

[0095] FIG. 8 shows a graph comparing the error rates when using other decoders and the decoder (420) of FIG. 4. In FIG. 8, the decoder (420) identified as 5-bit L-RCQ is compared with 5-bit RCQ and 10-bit MinSum. The graph in FIG. 8 shows the frame error rate (FER) and (E b The state of the channel (represented by / N0) can be compared. E b The larger / N0 is, the clearer the channel can be, which shows that the error rate can be lower and the decoder can perform decoding more easily. Given the target FER, E b A decoder operating at a low value for / N0 can be superior because it can perform more coding even if the channel is more noisy. As illustrated, the error rate for the decoder (420) is consistently superior to other decoders, even when compared to decoders using a higher bit width (e.g., 10-bit MinSum).

[0096] FIG. 9 shows a graph comparing the average iteration time when using other decoders and the decoder (420) of FIG. 4. In FIG. 9, the average iteration time is expressed in units of time, but may not be measured in units of seconds or fractions: for example, the average iteration time may be measured using processor cycles. Referring to FIG. 8, the decoder (420) of FIG. 4 demonstrates performance comparable to at least the other decoders. (It also provides an average iteration time superior to that of the 5-bit RCQ.)

[0097] As illustrated in FIGS. 8 and 9, when comparing the decoder (420) of FIG. 4 with a 5-bit RCQ and a 10-bit MinSum, the decoder (420) of FIG. 4 is superior in at least one measure of performance.

[0098] FIGS. 10A and 10B show a flowchart of an exemplary procedure using the decoder of FIG. 6 according to embodiments of the present disclosure. In FIG. 10A, at step 1005, the decoder (420) of FIG. 4 may receive an input message, which may be a short bit width message. At step 1010, the reconstruction circuit (510) of FIG. 5 may be used to construct a long bit width message from the short bit width message. At step 1015, the calculation circuit (520) of FIG. 5 may calculate another long bit width message from the first long bit width message. At step 1020, the quantization circuit (530) of FIG. 5 may quantize the long bit width message into the short bit width message.

[0099] At step 1025 (Fig. 10B), the decoder (420) of Fig. 4 can perform a check to determine whether all layers of the iteration have been completed, and at step 1030, the decoder (420) of Fig. 4 can perform a check to determine whether the decoder (420) of Fig. 4 has converged to a solution at the end of the iteration. If not all layers are completed or the messages have not converged to a solution, processing can return to step 1010 for another layer / iteration. Otherwise, at block 1035, the decoder (420) of Fig. 4 can output a final message.

[0100] In FIGS. 10A and 10B, several embodiments of the present disclosure are illustrated. However, a person skilled in the art may recognize other possible embodiments of the present disclosure by changing the order of blocks, omitting blocks, or including connections not illustrated in the drawings. Any component or any combination of described components may be used to perform one or more operations of the flowchart. The operations described above are exemplary operations and may include various additional steps not explicitly addressed. Additionally, the chronological order of operations may be changed. All such variations of the flowchart, whether explicitly described or not, are considered embodiments of the present disclosure.

[0101] The embodiments of the present disclosure provide technical advantages over the prior art. Functions that vary depending on both hierarchy and iteration. and A decoder implemented using [this] can be executed with an average iteration time at least equivalent to other decoders and with a bit width at least equivalent to other decoders. When considering only one criterion, the decoder may not be superior to other decoders, but when considering all criteria, the decoder is superior to other decoders according to at least one criterion.

[0102] The discussion set forth below is intended to provide a brief and general description of suitable machines or machines in which specific aspects of the present disclosure may be implemented. Machines or machines may be controlled at least partially by input from conventional input devices such as keyboards, mice, etc., as well as by instructions received from other machines, interaction with a virtual reality (VR) environment, biofeedback, or other input signals. As used herein, the term “machine” is intended to broadly include a single machine, a virtual machine, or a system of machines, counting machines, or devices operating together that are connected to communicate. Exemplary machines include computing devices such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc., as well as transportation devices such as automobiles, trains, taxis, etc., personal or public transportation.

[0103] Machines or machines may include programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), embedded computers, smart cards, and embedded controllers. Machines or machines may utilize one or more connections to one or more remote machines via network interfaces, modems, or other communication couplings. Machines may be interconnected via physical and / or logical networks such as intranets, the Internet, local area networks, and wide area networks. A person skilled in the art will understand that network communication may utilize various wired and / or radio short-range or long-range carriers and protocols, including radio frequency (RF), satellite, microwave, IEEE 802.11, Bluetooth®, optical, infrared, cable, laser, etc.

[0104] Embodiments of the present disclosure may be described with reference to or in relation to relevant data, including functions, procedures, data structures, application programs, etc., which, when accessed by a machine, allow the machine to perform operations or define abstract data types or low-level hardware contents. For example, relevant data may be stored in volatile and / or non-volatile memory such as RAM, ROM, etc., or in other storage devices and related storage media including hard drives, floppy disks, optical storage, tapes, flash memory, memory sticks, digital video discs, biometric storage, etc. Relevant data may be transmitted in the form of packets, serial data, parallel data, propagated signals, etc., through a transmission environment including physical and / or logical networks, and may be used in a compressed or encrypted format. Relevant data may be used in a distributed environment and may be stored locally and / or remotely for machine access.

[0105] Embodiments of the present disclosure may comprise a non-transient machine-readable medium comprising instructions executable by one or more processors, wherein the instructions comprise instructions for performing elements of the present disclosure as described herein.

[0106] Various operations of the method described above may be performed by any suitable means capable of performing operations, such as various hardware and / or software component(s), circuit(s), and / or module(s). The software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any “processor-readable medium” for use by or connected to an instruction execution system, mechanism, or device, such as a single or multi-core processor or a processor-containing system.

[0107] Blocks or steps of methods or algorithms and functions described in connection with the embodiments disclosed herein may be directly implemented in hardware, software modules executed by a processor, or a combination of both. When implemented in software, functions may be stored or transmitted as one or more instructions or code on a tangible, non-transient, computer-readable medium. Software modules may be in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0108] Although the principles of the present disclosure have been explained and illustrated with reference to the exemplified embodiments, it will be recognized that the exemplified embodiments may be modified in arrangement and detail and combined in any desired manner without departing from these principles. Furthermore, while the foregoing discussion has focused on specific embodiments, other configurations may be considered. In particular, even if expressions such as “according to an embodiment of the present disclosure” are used in this specification, such phrases generally refer to the possibility of a reference embodiment and are not intended to limit the present disclosure to a specific embodiment configuration. As used in this specification, these terms may refer to the same or different embodiments that can be combined into other embodiments.

[0109] The exemplary embodiments described above should not be construed as limiting the present disclosure. Although some embodiments have been described, a person skilled in the art will readily understand that many modifications to these embodiments are possible without substantially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

[0110] Embodiments of the present disclosure may be extended without limitation to the statements set forth below:

[0111] Statement 1. An embodiment of the present disclosure includes a device, and the device comprises:

[0112] Input buffer for receiving a first low bit width message;

[0113] A reconstruction circuit that implements a reconstruction function for the first short bit width message, which generates a first high bit width message;

[0114] A computation circuit that implements a computation function for the first long bit width message, which generates a second long bit width message;

[0115] A quantization circuit implementing a quantization function for the second long bit width message that generates a second short bit width message; and

[0116] The above includes a decision buffer for storing the second short bit width message,

[0117] The above reconstruction function and the above quantization function depend on at least one of the iteration and layer of the device.

[0118] Statement 2. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein the apparatus is part of a linear block code circuit.

[0119] Statement 3. An embodiment of the present disclosure includes a device according to Statement 2, wherein the linear block code circuit is part of a storage device.

[0120] Statement 4. An embodiment of the present disclosure includes a device according to Statement 3, wherein the storage device includes a solid state drive (SSD).

[0121] Statement 5. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein the apparatus includes at least two layers.

[0122] Statement 6. An embodiment of the present disclosure comprises an apparatus according to Statement 5, wherein the reconstruction circuit, the computation circuit, and the quantization circuit are used in at least two layers in one iteration.

[0123] Statement 7. An embodiment of the present disclosure includes an apparatus according to Statement 6, wherein

[0124] The reconstruction circuit implementing the reconstruction function, the calculation circuit, and the quantization circuit implementing the quantization function generate a first decoding; and

[0125] The reconstruction circuit implementing the second reconstruction function, the calculation circuit, and the quantization circuit implementing the second quantization function generate the second decoding.

[0126] Statement 8. An embodiment of the present disclosure includes an apparatus according to Statement 7, wherein, based on a comparison of at least the first decoding and the second decoding, the reconstruction circuit implementing the third reconstruction function, the calculation circuit, and the quantization circuit implementing the third quantization function generate the third decoding.

[0127] Statement 9. An embodiment of the present disclosure comprises an apparatus according to Statement 7, wherein the reconstruction circuit implementing the reconstruction function, the computation circuit, and the quantization circuit implementing the quantization function generate the first decoding at a first layer; and

[0128] The reconstruction circuit implementing the second reconstruction function, the computation circuit, and the quantization circuit implementing the second quantization function generate the second decoding at the second layer.

[0129] Statement 10. An embodiment of the present disclosure comprises an apparatus according to Statement 7, wherein the reconstruction circuit implementing the reconstruction function, the computation circuit, and the quantization circuit implementing the quantization function generate the first decoding in a first iteration; and

[0130] The reconstruction circuit implementing the second reconstruction function, the calculation circuit, and the quantization circuit implementing the second quantization function generate the second decoding in the second iteration.

[0131] Statement 11. An embodiment of the present disclosure includes an apparatus according to Statement 6, wherein, based on the result of comparing at least one of the first decoding and the second decoding, the second short bit width message is the first decoding.

[0132] Statement 12. An embodiment of the present disclosure includes an apparatus according to Statement 6, wherein, based on the result of comparing at least one of the first decoding and the second decoding, the second long bit width message is the first decoding.

[0133] Statement 13. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein

[0134] The above reconstruction function is implemented using a first lookup table; and

[0135] The above quantization function is implemented using a second lookup table.

[0136] Statement 14. An embodiment of the present disclosure includes the apparatus according to Statement 13, wherein

[0137] The storage device includes the device and memory, and

[0138] The memory includes the first lookup table and the second lookup table.

[0139] Statement 15. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein

[0140] The above reconstruction function is based on a density evolution technique, and

[0141] The above quantization function is based on the above density evolution technique.

[0142] Statement 16. An embodiment of the present disclosure includes an apparatus according to Statement 1, wherein

[0143] The above first short bit width message is a first 5-bit message, and

[0144] The above second short bit width message is a second 5-bit message, and

[0145] The above first long bit width message is a first 10-bit message, and

[0146] The above second long bit width message is the second 10-bit message.

[0147] Statement 17. An embodiment of the present disclosure comprises a method, and the method is:

[0148] Step of receiving a first short bit width message from a device;

[0149] A step of reconstructing a first long bit width message from the first short bit width message using a reconstruction function;

[0150] A step of calculating a calculation function for the first long bit width message to generate a second long bit width message; and

[0151] The method includes the step of quantizing the second long bit width message using a quantization function to generate a second short bit width message, wherein

[0152] The above reconstruction function and the above quantization function depend on at least one of the iteration and layer of the device.

[0153] Statement 18. An embodiment of the present disclosure comprises the method according to Statement 17, but further comprises the step of repeating the reconstruction, calculation, and quantization operations for at least two layers in one iteration, at least partially based on the result of comparing the first decoding from the first layer and the second decoding from the second layer.

[0154] Statement 19. An embodiment of the present disclosure includes a method according to Statement 18, wherein the first decoding includes the first long bit width message and the second decoding includes the second short bit width message.

[0155] Statement 20. An embodiment of the present disclosure includes a method according to Statement 18, wherein the first decoding includes the first long bit width message and the second decoding includes the second long bit width message.

[0156] Statement 21. An embodiment of the present disclosure comprises a method according to Statement 18, but further comprises the step of repeating the reconstruction, calculation, and quantization operations for at least two iterations in one iteration based at least partially on the result of comparing the first decoding from the first iteration and the second decoding from the second iteration.

[0157] Statement 22. An embodiment of the present disclosure includes a method according to Statement 21, wherein the first decoding includes the first short bit width message and the second decoding includes the second short bit width message.

[0158] Statement 23. An embodiment of the present disclosure includes a method according to Statement 21, wherein the first decoding includes the first long bit width message and the second decoding includes the second long bit width message.

[0159] Statement 24. An embodiment of the present disclosure includes the method according to Statement 17, wherein

[0160] The method further includes the step of outputting at least one of the second short bit width message or the second long bit width message from the device.

[0161] Statement 25. An embodiment of the present disclosure includes the method according to Statement 17, wherein

[0162] The above device is part of a linear block code circuit.

[0163] Statement 26. An embodiment of the present disclosure includes the method according to Statement 25, wherein

[0164] The above linear block code circuit is part of the storage device.

[0165] Statement 27. An embodiment of the present disclosure includes the method according to Statement 16, wherein

[0166] The above storage device includes an SSD.

[0167] Statement 28. An embodiment of the present disclosure includes the method according to Statement 17, wherein

[0168] The above reconstruction function is implemented using a first lookup table; and

[0169] The above quantization function is implemented using a second lookup table.

[0170] Statement 29. An embodiment of the present disclosure includes the method according to Statement 17, wherein

[0171] The above reconstruction function is based on a density evolution technique, and

[0172] The above quantization function is based on the above density evolution technique.

[0173] Statement 30. An embodiment of the present disclosure includes the method according to Statement 17, wherein

[0174] The above first short bit width message is a first 5-bit message, and

[0175] The above second short bit width message is a second 5-bit message, and

[0176] The above first long bit width message is a first 10-bit message, and

[0177] The above second long bit width message is the second 10-bit message.

[0178] Statement 31. An embodiment of the present disclosure comprises an article comprising a non-transient storage medium, wherein instructions stored in the non-transient storage medium, when executed by a machine, cause the following steps:

[0179] Step of receiving a first short bit width message from a device;

[0180] A step of reconstructing a first long bit width message from the first short bit width message using a reconstruction function;

[0181] A step of calculating a calculation function for the first long bit width message to generate a second long bit width message; and

[0182] Inducing a step of quantizing the second long bit width message to generate a second short bit width message using a quantization function,

[0183] The above reconstruction function and the above quantization function depend on at least one of the iteration and layer of the device.

[0184] Statement 32. An embodiment of the present disclosure comprises an article according to Statement 31, wherein the instructions stored in the non-transient storage medium, when executed by the machine, cause the step of repeating the reconstruction, calculation, and quantization operations for at least two layers based at least partially on the result of comparing a first decoding from a first layer and a second decoding from a second layer.

[0185] Statement 33. An embodiment of the present disclosure comprises an article according to Statement 32, wherein the first decoding comprises the first short bit width message and the second decoding comprises the second short bit width message.

[0186] Statement 34. An embodiment of the present disclosure comprises an article according to Statement 32, wherein the first decoding comprises the first long bit width message and the second decoding comprises the second long bit width message.

[0187] Statement 35. An embodiment of the present disclosure comprises an article according to Statement 32, wherein the instructions stored in the non-transient storage medium, when executed by the machine, cause the step of repeating the reconstruction, calculation, and quantization operations for at least two iterations based at least partially on the result of comparing the first decoding from the first iteration and the second decoding from the second iteration.

[0188] Statement 36. An embodiment of the present disclosure comprises an article according to Statement 35, wherein the first decoding comprises the first low bit width message and the second decoding comprises the second low bit width message.

[0189] Statement 37. An embodiment of the present disclosure comprises an article according to Statement 35, wherein the first decoding comprises the first long bit width message and the second decoding comprises the second long bit width message.

[0190] Statement 38. An embodiment of the present disclosure comprises an article according to Statement 31, wherein the instructions stored in the non-transient storage medium when executed by the machine:

[0191] The above device causes a step of outputting at least one of the second short bit width message or the second long bit width message.

[0192] Statement 39. An embodiment of the present disclosure comprises an article according to Statement 31, wherein the device is part of a linear block code circuit.

[0193] Statement 40. An embodiment of the present disclosure comprises an article according to Statement 39, wherein the linear block code circuit is part of a storage device.

[0194] Statement 41. An embodiment of the present disclosure includes an article according to Statement 40, wherein the storage device includes an SSD.

[0195] Statement 42. An embodiment of the present disclosure includes an article according to Statement 31, wherein

[0196] The above reconstruction function is implemented using a first lookup table; and

[0197] The above quantization function is implemented using a second lookup table.

[0198] Statement 43. An embodiment of the present disclosure includes an article according to Statement 31, wherein

[0199] The above reconstruction function is based on a density evolution technique, and

[0200] The above quantization function is based on the above density evolution technique.

[0201] Statement 44. An embodiment of the present disclosure includes an article according to Statement 31, wherein

[0202] The above first short bit width message is a first 5-bit message, and

[0203] The above second short bit width message is a second 5-bit message, and

[0204] The above first long bit width message is a first 10-bit message, and

[0205] The above second long bit width message is the second 10-bit message.

[0206] Consequently, in light of a wide range of various permutations of the embodiments described herein, the description of the invention and the accompanying materials are intended merely to be illustrative and should not be construed as limiting the scope of the disclosure. Accordingly, what is claimed in this disclosure is all modifications that may come within the scope of the following claims and their corresponding scopes. Explanation of the symbols

[0207] 105: Machine 110: Processor 115: Memory 120: Storage device 125: Memory controller 130: Device driver 205: Clock 210: Network Connector 215: Buses 220: User Interfaces 225: I / O Engines 305: Interface 310: Host Interface Layer 315: SSD controller 320-1, 320-2, 320-3, 320-4: Channel 325-1, 325-2, 325-3, 325-4, 325-5, 325-6, 325-7, 325-8: Flash memory chips 330: Flash conversion layer 335: Error correction code 405: QC-LDPC Code 410: Hierarchies 415: Encoder 420: Decoder 505, 535: Short bit width messages 510, 620: Reconstruction circuit 515, 525: Long bit width messages 520, 630: Calculation circuit 530, 625: Quantization circuit 605: Variable Node 610: Inspection Node 615: Input buffer 635: Decision buffer 640: Memory 705, 710, 715: Table 720-1, 720-2, 720-3: Entry

Claims

Claim 1 A low-density parity-check (LDPC) device comprising: an input buffer for receiving a first low bit width message for a plurality of layers corresponding to a plurality of rows of a parity check matrix of a low-density parity-check code; a reconstruction circuit for generating a first high bit width message by implementing a reconstruction function for the first low bit width message; a calculation circuit for generating a second high bit width message by implementing a calculation function for the first high bit width message; and a quantization circuit for generating a second low bit width message by implementing a quantization function for the second high bit width message. The device comprises a decision buffer for storing the second short bit width message, wherein the low-density parity check device generates the first long bit width message, the second long bit width message, and the second short bit width message in a specified order for each of the plurality of layers, and the low-density parity check device generates the first long bit width message, the second long bit width message, and the second short bit width message for each of the plurality of layers in each of the plurality of iterations, and the reconstruction function and the quantization function vary according to at least one of the plurality of iterations and the plurality of layers. Claim 2 delete Claim 3 delete Claim 4 A device according to claim 1, wherein if the reconstruction circuit implements a first reconstruction function and the quantization circuit implements a first quantization function, the second short bit width message is a first decoding, and if the reconstruction circuit implements a second reconstruction function and the quantization circuit implements a second quantization function, the second short bit width message is a second decoding. Claim 5 A device configured to output the first decoding based on the result of comparing the first decoding and the second decoding in claim 4. Claim 6 An apparatus according to claim 4, wherein in the first layer among the plurality of layers, the reconstruction circuit is configured to implement the first reconstruction function and the quantization circuit is configured to implement the first quantization function, and in the second layer among the plurality of layers, the reconstruction circuit is configured to implement the second reconstruction function and the quantization circuit is configured to implement the second quantization function. Claim 7 An apparatus according to claim 4, wherein in the first iteration among the plurality of iterations, the reconstruction circuit is configured to implement the first reconstruction function and the quantization circuit is configured to implement the first quantization function, and in the second iteration among the plurality of iterations, the reconstruction circuit is configured to implement the second reconstruction function and the quantization circuit is configured to implement the second quantization function. Claim 8 A device according to claim 1, wherein the reconstruction function is implemented using a first lookup table and the quantization function is implemented using a second lookup table. Claim 9 In claim 8, the low-density parity check device further comprises a memory, and the memory comprises the first lookup table and the second lookup table. Claim 10 In claim 1, the reconstruction function is based on a density evolution technique, and the quantization function is a device based on the density evolution technique. Claim 11 A method for decoding operation of a low-density parity-check (LDPC) device comprises: receiving a first short bit width message for a plurality of layers corresponding to a plurality of rows of a parity check matrix of a low-density parity-check code; reconstructing a first long bit width message from the first short bit width message using a reconstruction function; using a calculation function for the first long bit width message to generate a second long bit width message; and quantizing the second long bit width message using a quantization function to generate a second short bit width message, wherein the low-density parity-check device performs the reconstructing step, the using step, and the quantizing step in a specified order for each of the plurality of layers, and the low-density parity-check device performs the reconstructing step, the using step, and the quantizing step for each of the plurality of layers in each of the plurality of iterations, and wherein the reconstruction function and the quantization function vary according to at least one of the plurality of iterations and the plurality of layers. Claim 12 A method according to claim 11, further comprising the step of repeating the reconstructing step, the using step, and the quantizing step for at least two of the plurality of layers in one iteration of the plurality of iterations, based at least partially on the result of comparing the first decoding corresponding to the second short bit width message for the first layer among the plurality of layers and the second decoding corresponding to the second short bit width message for the second layer among the plurality of layers. Claim 13 A method according to claim 12, wherein the first decoding includes the first short bit width message for the second layer, and the second decoding includes the second short bit width message for the second layer. Claim 14 A method according to claim 12, further comprising the step of repeating the reconstructing, using, and quantizing steps for at least two of the plurality of iterations based at least partially on the result of comparing the first decoding corresponding to the second short bit width message for the first iteration among the plurality of iterations and the second decoding corresponding to the second short bit width message for the second iteration among the plurality of iterations. Claim 15 A method according to claim 14, wherein the first decoding includes the first short bit width message for the second iteration, and the second decoding includes the second short bit width message for the second iteration. Claim 16 A method according to claim 11, further comprising the step of outputting at least one of the second short bit width message or the second long bit width message from the device. Claim 17 A method according to claim 11, wherein the reconstruction function is implemented using a first lookup table and the quantization function is implemented using a second lookup table. Claim 18 In claim 11, the reconstruction function is based on a density evolution technique, and the quantization function is based on a density evolution technique. Claim 19 In a computer-readable non-transient storage medium, when instructions stored in the computer-readable non-transient storage medium are executed by a machine, a low-density parity-check (LDPC) device comprises: receiving a first short bit-width message for a plurality of layers corresponding to a plurality of rows of a parity check matrix of a low-density parity-check code; reconstructing a first long bit-width message from the first short bit-width message using a reconstruction function; and using a calculation function on the first long bit-width message to generate a second long bit-width message. A computer-readable non-transient storage medium wherein the reconstructing function and the quantization function are varied according to at least one of the multiple iterations and the quantization function. Claim 20 In claim 19, the reconstruction function is based on a density evolution technique, and the quantization function is a computer-readable non-transient storage medium based on the density evolution technique.

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