Image sensor preventing image degradation

Abstract

This description relates to an image sensor. The image sensor of the present invention comprises a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and each of the plurality of pixels comprises a photodiode, a transfer transistor connected between the photodiode and a floating diffusion node, a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied, a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a first source follower transistor including a second terminal connected to the first node, a precharge transistor connected between the first node and the floating node, a first precharge select transistor connected between the floating node and a ground node, a second precharge select transistor connected between the first node and the second node, a first capacitor and a first sampling transistor connected between the third power node to which a third power supply voltage is applied and the second node, a second capacitor and a second sampling transistor connected between the third power node and the second node, a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and a second terminal. It includes a second source follower transistor, a select transistor connected to a second terminal of the second source follower transistor and a corresponding column line among a plurality of column lines, and a third capacitor connected between the gate of the precharge transistor and a floating node.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to an image sensor that prevents image quality degradation caused by coupling between sub-lines of a row line. Background Technology

[0002] Image sensors, which capture images and convert them into electrical signals, are used not only in general consumer electronic devices such as digital cameras, mobile phone cameras, and portable camcorders, but also in cameras mounted in automobiles, security devices, and robots.

[0003] An image sensor can determine the amount of photoelectrons that form the basis of electrical signals by controlling the exposure time. Image sensors can control exposure time using rolling shutter and global shutter methods. In this case, the rolling shutter method can control the photoelectron accumulation time differently for each row of the pixel array. The global shutter method can control the photoelectron accumulation time equally for different rows of the pixel array. The problem to be solved

[0004] The purpose of this invention is to provide an image sensor that prevents the image quality of the image data from degrading due to coupling between sub-lines of a row line. means of solving the problem

[0005] An image sensor according to an embodiment of the present invention comprises a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and each of the plurality of pixels comprises a photodiode, a transfer transistor connected between the photodiode and a floating diffusion node, a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied, a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a first source follower transistor including a second terminal connected to the first node, a precharge transistor connected between the first node and the floating node, a first precharge select transistor connected between the floating node and a ground node, a second precharge select transistor connected between the first node and the second node, a first capacitor and a first sampling transistor connected between the third power node to which a third power supply voltage is applied and the second node, a second capacitor and a second sampling transistor connected between the third power node and the second node, a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and a second It includes a second source follower transistor including a terminal, a select transistor connected to a corresponding column line among a plurality of column lines and the second terminal of the second source follower transistor, and a third capacitor connected between the gate of the precharge transistor and a floating node.

[0006] An image sensor according to an embodiment of the present invention comprises a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and each of the plurality of pixels comprises a photodiode, a transfer transistor connected between the photodiode and a floating diffusion node, a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied, a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a first source follower transistor including a second terminal connected to the first node, a first precharge select transistor connected between the first node and the second node, a precharge transistor connected between the second node and the floating node, a second precharge select transistor connected between the precharge transistor and a ground node, a first capacitor and a first sampling transistor connected between the third power node to which a third power supply voltage is applied and the second node, a second capacitor and a second sampling transistor connected between the third power node and the second node, a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and It includes a second source follower transistor having a second terminal, a select transistor connected to the second terminal of the second source follower transistor and a corresponding column line among a plurality of column lines, and a third capacitor connected between the gate of the precharge transistor and a floating node.

[0007] An image sensor according to an embodiment of the present invention comprises a plurality of pixels connected to a plurality of row lines and a plurality of column lines, and a row driver connected to the plurality of pixels through the plurality of row lines, wherein each of the plurality of pixels comprises a photodiode, a transfer transistor connected between the photodiode and a floating diffusion node, a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied, a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a first source follower transistor including a second terminal connected to the first node, a precharge transistor connected between the first node and the floating node, a first precharge select transistor connected between the floating node and a ground node, a second precharge select transistor connected between the first node and the second node, a first capacitor and a first sampling transistor connected between the third power node to which a third power supply voltage is applied and the second node, a second capacitor and a second sampling transistor connected between the third power node and the second node, and a gate connected to the second node. A second source follower transistor comprising a first terminal to which a fourth power supply voltage is applied and a second terminal, a select transistor connected to a corresponding column line among a plurality of column lines and the second terminal of the second source follower transistor, and a third capacitor connected between the gate of a precharge transistor and a floating node, wherein each of the plurality of pixels comprises a substrate including a photodiode and an active region, a semiconductor pattern region forming a transfer transistor, a reset transistor, a first source follower transistor, a precharge transistor, a first precharge select transistor, a second precharge select transistor, a first sampling transistor, a second sampling transistor, a second source follower transistor, and a select transistor together with the active region on the substrate, and a plurality of row lines on the semiconductor pattern region.The invention further comprises a metal pattern region including a plurality of column lines, a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor, the second capacitor, and the third capacitor are manufactured by the same process, and the first capacitor, the second capacitor, and the third capacitor include an OCS (One Cylinder Stack) type capacitor or a Pillar type capacitor, and the row driver is configured to reset the voltage level of each floating diffusion node of a plurality of pixels by simultaneously turning on the reset transistors of a plurality of pixels, store a voltage corresponding to the reset level of the floating diffusion node in the first capacitor through each of the first sampling transistors of a plurality of pixels, dump electrons generated by a photodiode in each of the plurality of pixels to the floating diffusion node by simultaneously turning on the reset transistors of a plurality of pixels, and store a voltage corresponding to the voltage level of the floating diffusion node to which electrons were dumped in the second capacitor through each of the second sampling transistors of a plurality of pixels, and the row driver is configured to sequentially select a plurality of row lines and simultaneously select the selection transistors of the selected pixels connected to the selected row lines It is configured to sequentially transmit voltages corresponding to the voltage of the first capacitor and the voltage of the second capacitor of each selected pixel to the column lines by turning on. Effects of the invention

[0008] According to the embodiments of the present invention, a capacitor is provided between the gate and the floating node of a precharge transistor. Accordingly, the amount of current flowing through the precharge transistor is prevented from changing, and the quality of the image data is prevented from deteriorating. Brief explanation of the drawing

[0009] FIG. 1 shows an image sensor according to an embodiment of the present invention. FIG. 2 is a drawing for explaining the operation of an image sensor according to an embodiment of the present invention. FIG. 3 shows an example of a pixel according to an embodiment of the present invention. FIG. 4 shows an example of signals transmitted through sub-lines of a row line to one pixel of an image sensor according to an embodiment of the present invention. FIG. 5 shows an example of a pixel according to another embodiment of the present invention. FIG. 6 shows an example of a pixel according to another embodiment of the present invention. FIG. 7 shows an example of signals transmitted to a pixel of an image sensor according to an embodiment of the present invention through sub-lines of a row line. FIG. 8 shows an example of a pixel according to another embodiment of the present invention. FIG. 9 shows an example of a pixel according to another embodiment of the present invention. FIG. 10 shows an example of a pixel according to another embodiment of the present invention. Figure 11 shows an example of a vertical cross-sectional view of a pixel array of an image sensor. FIG. 12 shows an example of a pixel according to another embodiment of the present invention. FIG. 13 shows an example of a pixel according to another embodiment of the present invention. FIG. 14 shows an example of a pixel according to another embodiment of the present invention. Specific details for implementing the invention

[0010] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention. In the following, the term 'and / or' is interpreted to include any one of the items listed in association with the term, and a combination of some or all of the items listed in association.

[0011] FIG. 1 shows an image sensor (100) according to an embodiment of the present invention. Referring to FIG. 1, the image sensor (100) may include a pixel array (110), a row driver (120), a ramp signal generator (130) (RSG), an analog-to-digital conversion circuit (140), a memory circuit (150), and a timing generator (160) (TG).

[0012] A pixel array (110) may include a plurality of pixels (PX) arranged in a matrix form along rows and columns. Each of the plurality of pixels (PX) may include photodetectors. For example, the photodetectors may include a photodiode, a phototransistor, a photogate, or a pinned photodiode. Each of the plurality of pixels (PX) may detect light using a photodetector and convert the amount of detected light into an electrical signal, for example, voltage or current.

[0013] A color filter array (CFA) and a lens may be stacked on a pixel array (110). The color filter array may include red (R), green (G), and blue (B) filters. Two or more different color filters may be placed on a plurality of pixels (PX). For example, at least one blue color filter, at least one red color filter, and at least two green color filters may be placed on a plurality of pixels (PX).

[0014] A row driver (120) can be connected to each row of pixels (PX) of a pixel array (110) through the first to m-th row lines (RL1 to RLm) (m is a positive integer). Each of the first to m-th row lines (RL1 to RLm) may include a plurality of sub-lines that are commonly connected to the pixels of one row. The row driver (120) can decode an address and / or control signal generated by a timing generator (160) to select the first to m-th row lines (RL1 to RLm) of the pixel array (110) simultaneously or sequentially, and drive a plurality of sub-lines of the selected row lines to specific voltages. For example, the row driver (120) can drive a plurality of sub-lines of the first to m-th row lines (RL1 to RLm) to voltages suitable for light detection, or drive a plurality of sub-lines of the selected row lines to voltages suitable for outputting a detected voltage.

[0015] Each of the multiple sub-lines of the first to m-th row lines (RL1~RLm) connected to the rows of pixels (PX) can each transmit various signals, such as a signal for selecting (or activating) the photodetectors of the pixels, a signal for resetting the floating diffusion node, a signal for selecting a column line, a signal for adjusting the conversion gain (CG), etc.

[0016] The ramp signal generator (130) can generate a ramp signal (RAMP). The ramp signal generator (130) can operate under the control of the timing generator (160). For example, the ramp signal generator (130) can operate in response to control signals such as a ramp enable signal, a mode signal, etc. In response to the activation of the ramp enable signal, the ramp signal generator (130) can generate a ramp signal having a slope set based on the mode signal. For example, the ramp signal generator (130) can generate a ramp signal (RAMP) that continuously decreases or increases from an initial level over time.

[0017] The analog-to-digital conversion circuit (140) may be connected to the columns of pixels (PX) of the pixel array (110) through the first to nth column lines (CL1 to CLn) (n is a positive integer). The analog-to-digital conversion circuit (140) may include first to nth analog-to-digital converters (AD1 to ADn) connected to the first to nth column lines (CL1 to CLn) respectively. The first to nth analog-to-digital converters (AD1 to ADn) may receive a ramp signal (RAMP) in common from the ramp signal generator (130).

[0018] The first to nth analog-to-digital converters (AD1 to ADn) can compare the voltages (or currents) of the first to nth column lines (CL1 to CLn) with a ramp signal (RAMP). The ramp signal is a signal that decreases (or increases) at a constant rate. The first to nth analog-to-digital converters (AD1 to ADn) can latch a count value until the ramp signal (RAMP) becomes smaller (or larger) than the pixel voltages (or pixel currents) of the first to nth column lines (CL1 to CLn), and then convert the latched count value into a digital value and output it. That is, the first to nth analog-to-digital converters (AD1 to ADn) can output digital values ​​corresponding to the magnitude (or amount) of the voltages (or currents) output from the pixels (PX) to the first to nth column lines (CL1 to CLn).

[0019] Each of the first to nth analog-to-digital converters (AD1 to ADn) may include at least two sub-converters. The sub-converters are connected in common to a corresponding column line and may receive a ramp signal (RAMP) in common. The sub-converters may have the same resolution or different resolutions. The sub-converters are activated at different timings to convert the voltage (or current) of the corresponding column line into digital values ​​(or digital signals), e.g., pixel values.

[0020] The memory circuit (150) may include first to nth memories (M1 to Mn) corresponding to each of the first to nth analog-to-digital converters (AD1 to ADn). The first to nth memories (M1 to Mn) may store digital values ​​(or digital signals) received from the first to nth analog-to-digital converters (AD1 to ADn) and output the stored values ​​(or signals) as a digital signal (DS).

[0021] The timing generator (160) (TG) can control the timings at which the image sensor (100) operates. The timing generator (160) can control the timings at which the row driver (120) selects the first to m row lines (RL1 to RLm) simultaneously or sequentially, and can control the timings at which signals are transmitted through two or more lines included in the selected row line among the first to m row lines (RL1 to RLm).

[0022] The timing generator (160) can control the timings at which the ramp signal generator (130) generates a ramp signal (RAMP) and initializes the ramp signal. The timing generator (160) can control the timings at which the first to n analog-to-digital converters (AD1 to ADn) begin counting and comparing, and the timings at which the first to n analog-to-digital converters (AD1 to ADn) initialize.

[0023] FIG. 2 is a diagram for explaining the operation of an image sensor (100) according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2, the image sensor (100) can be operated in a Global Shutter mode. In the Global Shutter mode, the image sensor (100) can perform a Global Signal Dumping operation during a Global Signal Dumping period (GSDP) and a Readout operation during a Readout period (ROP).

[0024] In the global signal dumping interval (GSDP), the image sensor (100) can reset the voltage of each floating diffusion node of the pixels (PX) during the reset time (RT). In the global signal dumping interval (GSDP), after the reset time (RT), during the accumulation time (IT), the image sensor (100) can accumulate electrons in each photoelectric conversion element of the pixels (PX), for example, a photodiode. In the global signal dumping interval (GSDP), after the accumulation time (IT), during the dumping time (DT), the image sensor (100) can dump the electrons accumulated in each photoelectric conversion element of the pixels (PX), for example, a photodiode, to the floating diffusion node.

[0025] For example, in the global signal dumping interval (GSDP), the image sensor (100) can simultaneously control pixels (PX). For example, the image sensor (100) can simultaneously reset pixels (PX) connected to the first to m-th row lines (RL1 to RLm), simultaneously accumulate electrons in pixels (PX) connected to the first to m-th row lines (RL1 to RLm), and simultaneously dump the electrons accumulated in pixels (PX) connected to the first to m-th row lines (RL1 to RLm) to corresponding floating nodes. For example, the image sensor (100) can operate in a global shutter mode.

[0026] In the readout section (ROP), the image sensor (100) can sequentially select the first to m-th row lines (RL1 to RLm). For example, the image sensor (100) can sequentially select the first to m-th row lines (RL1 to RLm) in order from the top m-th row line (RLm) to the bottom first row line (RL1).

[0027] In the readout section (ROP), in a selected row line among the first to m-th row lines (RL1 to RLm), during the readout time (ROT), the image sensor (100) can read voltages corresponding to voltage levels of floating diffusion nodes of pixels (PX) of the selected row line through the first to n-th column lines (CL1 to CLn). The image sensor (100) sequentially selects the first to m-th row lines (RL1 to RLm) and can read out voltages corresponding to voltage levels of floating diffusion nodes of pixels (PX) of the selected row line. For example, the image sensor (100) can operate in a rolling readout manner.

[0028] FIG. 3 shows an example of a pixel (PX) according to an embodiment of the present invention. Referring to FIG. 3, the pixel (PX) of the image sensor (100) may include a photodiode (PD), a transmission transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), and a third capacitor (C3).

[0029] A photodiode (PD) may be connected between a ground node to which a ground voltage (GND) is applied and a first terminal of a transfer transistor (TX). The transfer transistor (TX) may include a gate to which a transfer control signal (TS) is applied, a first terminal connected to the photodiode (PD), and a second terminal connected to a floating diffusion node (FD). The transfer transistor (TX) may be turned on or turned off in response to the transfer control signal (TS). When turned on by the transfer control signal (TS), the transfer transistor (TX) may dump electrons generated by the photodiode (PD) to the floating diffusion node (FD).

[0030] The reset transistor (RX) may include a gate to which a reset control signal (RS) is applied, a first terminal connected to a first power node to which a first power voltage (VPIX1) is applied, and a second terminal connected to a floating diffusion node (FD). The reset transistor (RX) may be turned on or turned off in response to the reset control signal (RS). When turned on by the reset control signal (RS), the reset transistor (RX) may reset the floating diffusion node (FD) by supplying the first power voltage (VPIX1) to the floating diffusion node (FD).

[0031] The first source follower transistor (SF1) may include a gate connected to a floating diffusion node (FD), a first terminal connected to a second power node to which a second power voltage (VPIX2) is applied, and a second terminal connected to a first node (NO1). The second power voltage (VPIX2) may be the same as or different from the first power voltage (VPIX1). When the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1) are turned on, the first source follower transistor (SF1) may operate as a source follower amplifier that transmits a voltage change of the floating diffusion node (FD), for example, a voltage change of the floating diffusion node (FD) caused by the dumping of the transfer transistor (TX), to the first node (NO1).

[0032] The precharge transistor (PCX) may include a gate to which a precharge control signal (PC) is applied, a first terminal connected to a first node (NO1), and a second terminal connected to a floating node (FN). The precharge transistor (PCX) may be turned on or turned off in response to the precharge control signal (PC). When the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1) are turned on, the precharge transistor (PCX) may operate as a current source that causes a constant current to flow through the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1). As a constant current flows through the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1), the first source follower transistor (SF1) can transmit the voltage change of the floating diffusion node (FD) to the first node (NO1) without distortion or noise.

[0033] The first precharge select transistor (PSX1) may include a gate to which the first precharge select control signal (PSEL1) is applied, a first terminal connected to a floating node (FN), and a second terminal connected to a ground node to which a ground voltage (GND) is applied. The first precharge select transistor (PSX1) may be turned on or turned off in response to the first precharge select control signal (PSEL1). The first precharge select transistor (PSX1) may be used to form or block a current path through the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1).

[0034] The second precharge select transistor (PSX2) may include a gate to which the second precharge select control signal (PSEL2) is applied, a first terminal connected to the first node (NO1), and a second terminal connected to the second node (NO2). The second precharge select transistor (PSX2) may be turned on or turned off in response to the second precharge select control signal (PSEL2). The second precharge select transistor (PSX2) may be used to form or block a current path between the first node (NO1) and the second node (NO2).

[0035] The first capacitor (C1) may be connected between the third power node to which the third power voltage (VPIX3) is applied and the first terminal of the first sampling transistor (SAMP1). The third power voltage (VPIX3) may be equal to or different from the first power voltage (VPIX1) or the second power voltage (VPIX2). The first capacitor (C1) may be used as a memory to store the voltage level of the first node (NO1) transmitted through the second precharge select transistor (PSX2) and the first sampling transistor (SAMP1).

[0036] The first sampling transistor (SAMP1) may include a gate to which a first sampling control signal (SAMPS1) is applied, a first terminal connected to a first capacitor (C1), and a second terminal connected to a second node (NO2). The first sampling transistor (SAMP1) may be turned on or turned off in response to the first sampling control signal (SAMPS1). The first sampling transistor (SAMP1) may be used to form or block a current path between the second node (NO2) and the first capacitor (C1).

[0037] The second capacitor (C2) may be connected between the third power node to which the third power voltage (VPIX3) is applied and the second terminal of the second sampling transistor (SAMP2). The third power voltage (VPIX3) may be equal to or different from the second power voltage (VPIX2) or the second power voltage (VPIX2). The second capacitor (C2) may be used as a memory to store the voltage level of the second node (NO2) transmitted through the second precharge select transistor (PSX2) and the second sampling transistor (SAMP2).

[0038] The second sampling transistor (SAMP2) may include a gate to which a second sampling control signal (SAMPS2) is applied, a second terminal connected to a second capacitor (C2), and a second terminal connected to a second node (NO2). The second sampling transistor (SAMP2) may be turned on or turned off in response to the second sampling control signal (SAMPS2). The second sampling transistor (SAMP2) may be used to form or block a current path between the second node (NO2) and the second capacitor (C2).

[0039] The second source follower transistor (SF2) may include a gate connected to the second node (NO2), a first terminal connected to the fourth power node to which the fourth power voltage (VPIX4) is applied, and a second terminal applied to the select transistor (SX). The fourth power voltage (VPIX4) may be equal to or different from the first power voltage (VPIX1), the second power voltage (VPIX2), or the third power voltage (VPIX3). When the second source follower transistor (SF2) and the select transistor (SX) are turned on, the second source follower transistor (SF2) may operate as a source follower amplifier that transmits a change in the voltage level of the second node (NO2) to the corresponding column line (CL).

[0040] The select transistor (SX) may include a gate to which a select control signal (SELS) is applied, a first terminal connected to a second terminal of the second source follower transistor (SF2), and a second terminal connected to a column line (CL). The select transistor (SX) may be turned on or turned off in response to the select control signal (SELS). The select transistor (SX) may be used to form or block a current path between the second source follower transistor (SF2) and the column line (CL).

[0041] A pixel (PX) may have a memory including a first capacitor (C1) and a second capacitor (C2). The intensity of light detected by a photodiode (PD), i.e., the voltage change of a floating diffusion node (FD), may be stored in the first capacitor (C1) or the second capacitor (C2). The reset voltage level of the floating diffusion node (FD) may be stored in the second capacitor (C2) or the first capacitor (C1). Thus, while pixels (PX) in one row output voltage levels stored in the first capacitor (C1) and the second capacitor (C2) through the first to nth column lines (CL1 to CLn), pixels in another row may maintain voltage levels stored in the first capacitor (C1) and the second capacitor (C2).

[0042] For example, the transmission control signal (TS), reset control signal (RS), precharge control signal (PC), first precharge selection control signal (PSEL1), second precharge selection control signal (PSEL2), first sampling control signal (SAMPS1), second sampling control signal (SAMPS2), and selection control signal (SELS) can each be transmitted to a pixel (PX) through sub-lines of one of the first to m row lines (RL1 to RLm).

[0043] As the manufacturing technology of the pixels (PX) improves, the size of the pixels (PX) can be reduced. When the size of the pixels (PX) is reduced, the distance between the sub-lines transmitting the transmission control signal (TS), reset control signal (RS), precharge control signal (PC), first precharge selection control signal (PSEL1), second precharge selection control signal (PSEL2), first sampling control signal (SAMPS1), second sampling control signal (SAMPS2), and selection control signal (SELS) decreases, and the coupling between the sub-lines can increase. When the coupling between the sub-lines increases, a voltage change in one sub-line can cause a voltage change in other sub-lines.

[0044] For example, the precharge transistor (PCX) may be designed to flow a constant current when the first source follower transistor (SF1), the precharge transistor (PCX), and the first precharge select transistor (PSX1) are turned on. However, if the voltage level of the precharge control signal (PC) or the voltage level of the floating node (FN) changes due to voltage changes in other sub-lines, the amount of current flowing through the precharge transistor (PCX) may change. If the amount of current flowing through the precharge transistor (PCX) changes, noise may occur during the process in which the first source follower transistor (SF1) transmits the change in the voltage level of the floating diffusion node (FD) to the first node (NO1). This may cause degradation of the image quality of the image data generated by the pixels (PX).

[0045] A pixel (PX) of an image sensor (100) according to an embodiment of the present invention may further include a third capacitor (C3) connected between the gate of a precharge transistor (PCX) and a floating node (FN). The third capacitor (C3) can maintain a voltage difference between the gate of the precharge transistor (PCX) and the floating node (FN). For example, if the voltage of the gate of the precharge transistor (PCX) changes due to coupling with another sub-line, the change in the gate voltage can be transmitted to the floating node (FN) through the third capacitor (C3). Thus, the voltage of the floating node (FN) can also change. Conversely, if the voltage of the floating node (FN) changes due to coupling with another sub-line, the change in voltage can be transmitted to the gate of the precharge transistor (PCX) through the third capacitor (C3). Thus, the voltage of the gate of the precharge transistor (PCX) can also change.

[0046] That is, even if the voltage of the gate of the precharge transistor (PCX) or the voltage of the floating node (FN) changes due to coupling with other sub-lines, the voltage difference between the gate of the precharge transistor (PCX) and the floating node (FN) is maintained. Therefore, the precharge transistor (PCX) can conduct a constant current.

[0047] A pixel (PX) of an image sensor (100) according to an embodiment of the present invention can maintain a voltage difference between the gate of a precharge transistor (PCX) and a floating node (FN) by providing a coupling (e.g., a third capacitor (C3)) that is greater than the coupling between sub-lines (e.g., parasitic coupling). Accordingly, degradation of the image quality of the image data generated by the pixels (PX) is prevented.

[0048] FIG. 4 shows an example of signals transmitted through sub-lines of a row line to one pixel among the pixels (PX) of an image sensor (100) according to an embodiment of the present invention. Referring to FIG. 3 and FIG. 4, the operations described below can be performed in a global signal dumping interval (GSDP).

[0049] The reset control signal (RS) can transition from a second level (e.g., low level) to a first level (e.g., high level) and maintain the first level during a first reset time (RT1). Afterward, the reset control signal (RS) can maintain a low level. As the reset transistor (RX) is turned on by the high-level reset control signal (RS), the floating diffusion node (FD) can be reset (reset operation). For example, the voltage of the floating diffusion node (FD) can be reset to a first power supply voltage (VPIX1). For example, the first reset time (RT1) can correspond to the reset time (RT) of FIG. 2.

[0050] The first source follower transistor (SF1) can generate a voltage at the first node (NO1) corresponding to the voltage level of the floating diffusion node (FD). The voltage of the first node (NO1) can be transmitted to the second node (NO2) through the second precharge select transistor (PSX2). That is, as the reset control signal (RS) transitions to a high level, the floating diffusion node (FD), the first node (NO1), and the second node (NO2) can be initialized.

[0051] The transmission control signal (TS) can transition from a second level (e.g., low level) to a first level (e.g., high level) and maintain the first level during a first reset time (RT1). Afterward, the transmission control signal (TS) can maintain the low level. As the transmission transistor (TX) is turned on by the high-level transmission control signal (TS), the photoelectrons integrated in the photodiode (PD) can be reset (reset operation). For example, the photoelectrons integrated in the photodiode (PD) can be discharged through the transmission transistor (TX) and the reset transistor (RX) to a first power node to which a first power voltage (VPIX1) is applied. For example, the first reset time (RT1) may correspond to the reset time (RT) of FIG. 2.

[0052] After the reset control signal (RS) and the transmission control signal (TS) transition from a high level to a low level, the first sampling control signal (SAMPS1) may transition from a low level to a high level. During the reset settling time (RCS), the first sampling control signal (SAMPS1) may remain at a high level. As the first sampling transistor (SAMP1) is turned on by the high-level first sampling control signal (SAMPS1), a voltage corresponding to the voltage level of the reset floating diffusion node (FD) (e.g., a voltage transmitted through the first source follower transistor (SF1)) may be sampled into the first capacitor (C1) (or second capacitor (C2)) connected to the second node (NO2).

[0053] After the first sampling control signal (SAMPS1) transitions from a high level to a low level, the transmission control signal (TS) can transition from a low level to a high level. The transmission control signal (TS) can maintain a high level during a dumping time (DT). As the transmission transistor (TX) is turned on by the high-level transmission control signal (TS), electrons generated by the photodiode (PD) can be dumped to the floating diffusion node (FD). As the electrons generated by the photodiode (PD) are dumped, the voltage of the floating diffusion node (FD) can gradually decrease from the first power supply voltage (VPIX1). The first source follower transistor (SF1) can amplify the change in voltage of the floating diffusion node (FD), for example, a decrease in the voltage level, and transmit it to the first node (NO1).

[0054] For example, the time from when the transmission control signal (TS) transitions from a high level to a low level at the first reset time (RT1) until it transitions from a low level to a high level at the dumping time (DP) can correspond to the integration time (IT) of FIG. 2.

[0055] After the transmission control signal (TS) transitions from a high level to a low level, the second sampling control signal (SAMPS2) can transition from a low level to a high level. The second sampling control signal (SAMPS2) can maintain a high level during the signal settling time (SCS). As the second sampling transistor (SAMP2) is turned on by the high level second sampling control signal (SAMPS2), the voltage of the floating diffusion node (FD) can be sampled to the second capacitor (C2) connected to the second node (NO2).

[0056] The first precharge selection control signal (PSEL1) and the second precharge selection control signal (PSEL2) can transition from a low level to a high level when the reset control signal (RS) and the transmission control signal (TS) transition from a low level to a high level. The first precharge selection control signal (PSEL1) and the second precharge selection control signal (PSEL2) can maintain a high level until the second sampling control signal (SAMPS2) transitions from a high level to a low level. For example, the first precharge selection control signal (PSEL1) can maintain a high level for a 11th time (T11), and the second precharge selection control signal (PSEL2) can maintain a high level for a 21st time (T21).

[0057] In an exemplary embodiment, the 11th time (T11) of the first precharge selection control signal (PSEL1) and the 21st time (T21) of the second precharge selection control signal (PSEL2) may overlap each other. For example, the 11th time (T11) of the first precharge selection control signal (PSEL1) and the 21st time (T21) of the second precharge selection control signal (PSEL2) may coincide with each other, but the embodiments of the present invention are not limited. Since the first precharge selection transistor (PSX1) and the second precharge selection transistor (PSX2) remain in the ON state, the voltage of the floating diffusion node (FD) may be sampled to the first capacitor (C1) or the second capacitor (C2) connected to the second node (NO2).

[0058] The precharge control signal (PC) can be transitioned from a low level to a high level before the reset control signal (RS) and the transmission control signal (TS) transition from a low level to a high level. The precharge control signal (PC) can remain at a high level until the second sampling control signal (SAMPS2) transitions from a high level to a low level. The precharge transistor (PCX) can be turned on by the high level precharge control signal (PC).

[0059] In the global signal dumping interval (GSDP), the select control signal (SELS) can be maintained at a low level.

[0060] The operations described below can be performed in the readout section (ROP).

[0061] During the readout interval (ROP), the precharge control signal (PC) can maintain a high level. The reset control signal (RS) can maintain a high level for a second reset time (RT2) after transitioning from a low level to a high level. The first precharge selection control signal (PSEL1) and the second precharge selection control signal (PSEL2) can transition from a low level to a high level. The first precharge selection control signal (PSEL1) can maintain a high level for a 12-time (T12). The second precharge selection control signal (PSEL2) can maintain a high level for a 22-time (T22). At this time, the second reset time (RT2), the 12-time (T12) of the first precharge selection control signal (PSEL1), and the 22-time (T22) of the second precharge selection control signal (PSEL2) may overlap each other.

[0062] The second node (NO2) can be reset by a high-level reset control signal (RS), a high-level first precharge selection control signal (PSEL1), and a high-level second precharge selection control signal (PSEL2). For example, the floating diffusion node (FD) is reset to a first power supply voltage (VPIX1), and the first source follower transistor (SF1) can generate a voltage at the first node (NO1) corresponding to the voltage level of the floating diffusion node (FD). The voltage of the first node (NO1) can be transferred to the second node (NO2). That is, as the reset control signal (RS) transitions to a high level, the floating diffusion node (FD), the first node (NO1), and the second node (NO2) can be initialized.

[0063] In an exemplary embodiment, the transmission control signal (TS) may remain in a low state during the second reset time (RT2). Alternatively, in the readout interval (ROP), the transmission control signal (TS) may transition to a low level after transitioning to a high level within the range of the second reset time (RT2).

[0064] When the reset of the floating diffusion node (FD), the first node (NO1), and the second node (NO2) is completed, the first sampling control signal (SAMPS1) can transition from a low level to a high level. The first sampling control signal (SAMPS1) can maintain a high level during the first settling time (ST1). At this time, during the first settling time (ST1) period in which the first sampling control signal (SAMPS1) maintains a high level, the selection control signal (SELS) can be at a high level. The selection transistor (SX) is turned on by the high-level selection control signal (SELS), and the voltage sampled in the first capacitor (C1) can be output to the corresponding column line (CL).

[0065] After the select transistor (SX) is turned on, the ramp signal (RAMP) can be generated to decrease (or increase) with a constant slope during the first time (T1). During the first time (T1) in which the voltage level of the ramp signal (RAMP) changes at a constant rate, the analog-to-digital conversion circuit (140) can generate a digital value corresponding to the reset level of the floating diffusion node (FD) by comparing the ramp signal (RAMP) with the signal of the column line (CL).

[0066] After the first settling time (ST1) has elapsed and the first sampling control signal (SAMPS1) has transitioned from a high level to a low level, the second sampling control signal (SAMPS2) may transition from a low level to a high level. The second sampling control signal (SAMPS2) may maintain a high level during the second settling time (ST2). At this time, during the second settling time (ST2) period in which the second sampling control signal (SAMPS2) maintains a high level, the selection control signal (SELS) may be at a high level. The selection transistor (SX) is turned on by the high-level selection control signal (SELS), and the voltage sampled in the second capacitor (C2) may be output to the corresponding column line (CL).

[0067] After the select transistor (SX) is turned on, the ramp signal (RAMP) can be generated to decrease (or increase) with a constant slope during the second time (T2). During the second time (T2) in which the voltage level of the ramp signal (RAMP) changes at a constant rate, the analog-to-digital conversion circuit (140) can generate a digital value corresponding to the signal level of the floating diffusion node (FD) by comparing the ramp signal (RAMP) with the signal of the column line (CL).

[0068] The analog-to-digital conversion circuit (140) can obtain a digital value corresponding to the amount of electrons generated by the photodiode (PD) by subtracting the digital value obtained at the first time (T1) from the digital value obtained at the second time (T2). That is, the analog-to-digital conversion circuit (140) can obtain a digital value corresponding to the brightness of the incident light.

[0069] In FIG. 4, it is shown that after the first sampling control signal (SAMPS1) transitions from a low level to a high level in the readout section (ROP), the second sampling control signal (SAMPS2) transitions from a low level to a high level. However, the image sensor (100) according to the embodiment of the present invention is not limited thereto. After the second sampling control signal (SAMPS2) transitions from a low level to a high level in the readout section (ROP), the first sampling control signal (SAMPS1) may transition from a low level to a high level. That is, the pixel (PX) may output the voltage of the first capacitor (C1) to the column line (CL) after outputting the voltage of the second capacitor (C2) to the column line (CL).

[0070] The operation of the global signal dumping interval (GSDP) can be performed simultaneously on pixels (PX) connected to the first to m rows (RL1 to RLm). The operation of the readout interval (ROP) can be performed sequentially on pixels (PX) connected to the first to m rows (RL1 to RLm).

[0071] For example, the operation of the readout section (ROP) illustrated in FIG. 4 can be performed simultaneously on pixels (PX) connected to the m-th row (RLm). Subsequently, the operation of the readout section (ROP) illustrated in FIG. 4 can be performed on pixels (PX) connected to the m-1st row. The image sensor (100) sequentially selects the first to m-th rows (RL1 to RLm) and can perform the operation of the readout section (ROP) on pixels (PX) of the selected rows.

[0072] As described with reference to FIG. 4, when the voltages of the sub-lines of the row line connected to a single pixel (PX) change, the voltage of the gate of the precharge transistor (PCX) or the voltage of the floating node (FN) can change due to coupling. The change in the voltage of the gate of the precharge transistor (PCX) or the voltage of the floating node (FN) can be transmitted to the floating node (FN) or the gate of the precharge transistor (PCX) through the third capacitor (C3). Thus, the voltage difference between the voltage of the gate of the precharge transistor (PCX) and the voltage of the floating node (FN) is maintained constant, and the precharge transistor (PCX) can flow a constant current. Since the precharge transistor (PCX) flows a constant current, the degradation of the image data quality is prevented.

[0073] FIG. 5 shows an example of a pixel (PX1) according to another embodiment of the present invention. Referring to FIG. 5, the pixel (PX1) of the image sensor (100) may include a photodiode (PD), a transmission transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), and a third capacitor (C3).

[0074] The photodiode (PD), transmission transistor (TX), reset transistor (RX), first source follower transistor (SF1), first precharge select transistor (PSX1), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) of the pixel (PX) described with reference to FIG. 3 are configured and can operate in the same way as the photodiode (PD), transmission transistor (TX), reset transistor (RX), first source follower transistor (SF1), first precharge select transistor (PSX1), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3). Therefore, redundant descriptions are omitted.

[0075] The precharge transistor (PCX) may include a gate to which a precharge control signal (PC) is applied, a first terminal connected to a second node (NO2), and a second terminal connected to a floating node (FN). The second precharge select transistor (PSX2) may include a gate to which a second precharge select control signal (PSEL2) is applied, a first terminal connected to a first node (NO1), and a second terminal connected to a second node (NO2).

[0076] The pixel (PX1) can operate in the same manner as described with reference to FIGS. 3 and 4. The third capacitor (C3) is connected between the gate and the floating node (FN) of the precharge transistor (PCX) so that the precharge transistor (PCX) can conduct a constant current.

[0077] FIG. 6 shows an example of a pixel (PX2) according to another embodiment of the present invention. Referring to FIG. 6, the pixel (PX2) of the image sensor (100) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a dynamic conversion gain transistor (DCGX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), a third capacitor (C3), a third sampling transistor (SAMP3), and a fourth capacitor (C4).

[0078] The photodiode (PD), transmission transistor (TX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) are configured and can operate in the same way as the photodiode (PD), transmission transistor (TX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) described with reference to FIG. 3. Therefore, redundant explanations are omitted.

[0079] The reset transistor (RX) may include a gate to which a reset control signal (RS) is applied, a first terminal connected to a first power node to which a first power voltage (VPIX1) is applied, and a second terminal connected to the first terminal of a dynamic conversion gain transistor (DCGX).

[0080] The dynamic conversion gain transistor (DCGX) may include a gate to which a dynamic conversion gain control signal (DCG) is applied, a first terminal connected to a second terminal of a reset transistor (RX), and a second terminal connected to a floating diffusion node (FD). By adjusting the capacitance of the floating diffusion node (FD), the dynamic conversion gain transistor (DCGX) can control the conversion gain in which the voltage of the floating diffusion node (FD) changes due to electrons of the photodiode (PD).

[0081] The fourth capacitor (C4) may be connected between the third power node to which the third power supply voltage (VPIX3) is applied and the third sampling transistor (SAMP3). The third sampling transistor (SAMP3) may include a gate to which the third sampling control signal (SAMPS3) is applied, a first terminal connected to the fourth capacitor (C4), and a second terminal connected to the second node (NO2).

[0082] Each of the first capacitor (C1), the second capacitor (C2), and the fourth capacitor (C4) can store one of the following: a voltage corresponding to the reset level of the floating diffusion node (FD), a voltage corresponding to the signal level of the floating diffusion node (FD) when the dynamic conversion gain transistor (DCGX) is turned on, and a voltage corresponding to the signal level of the floating diffusion node (FD) when the dynamic conversion gain transistor (DCGX) is turned off.

[0083] For example, the first source follower transistor (SF1), precharge transistor (PCX), and second precharge select transistor (PSX2) of the pixel (PX2) can be connected as in the pixel (PX1) of FIG. 5.

[0084] FIG. 7 shows an example of signals transmitted to a pixel (PX2) of an image sensor (100) according to an embodiment of the present invention through sub-lines of a row line. Referring to FIG. 6 and FIG. 7, the operations described below can be performed in a global signal dumping interval (GSDP).

[0085] The global signal dumping interval (GSDP) may include a first time interval (TI1) and a second time interval (TI2). In the first time interval (TI1), the reset control signal (RS), the transmission control signal (TS), the first sampling control signal (SAMPS1), the second sampling control signal (SAMPS2), the first precharge selection control signal (PSEL1), the second precharge selection control signal (PSEL2), the precharge control signal (PC), the selection control signal (SELS), and the ramp signal (RAMP) may be controlled in the same way as in the global signal dumping interval (GSDP) of FIG. 4. In the first time interval (TI1), the third sampling control signal (SAMPS3) may be maintained at a low level. In the first time interval (TI1), the dynamic conversion gain control signal (DCG) may be maintained at a low level.

[0086] At the beginning of the second time interval (TI2), the reset control signal (RS), transmission control signal (TS), first sampling control signal (SAMPS1), second sampling control signal (SAMPS2), first precharge selection control signal (PSEL1), second precharge selection control signal (PSEL2), precharge control signal (PC), selection control signal (SELS), and ramp signal (RAMP) can maintain their previous levels.

[0087] In the second time interval (TI2), the dynamic conversion gain control signal (DCG) can maintain a high level for the second signal settling time (SCS2) after transitioning from a low level to a high level. When the dynamic conversion gain control signal (DCG) transitions from a low level to a high level, the dynamic conversion gain transistor (DCGX) can be turned on. Consequently, the capacitance of the floating diffusion node (FD) increases, and the voltage of the floating diffusion node (FD) can decrease. The first source follower transistor (SF1) can transmit the change in voltage of the floating diffusion node (FD) to the first node (NO1). Consequently, the voltage of the first node (NO1) can also decrease.

[0088] In the second time interval (TI2), the third sampling control signal (SAMPS3) can maintain a high level for the second signal settling time (SCS2) after transitioning from a low level to a high level. When the third sampling control signal (SAMPS3) transitions from a low level to a high level, the third sampling transistor (SAMP3) can be turned on. The voltage of the first node (NO1) can be stored in the fourth capacitor (C4) through the second precharge select transistor (PSX2) and the third sampling transistor (SAMP3).

[0089] That is, during the reset settling time (RCS), a voltage corresponding to the reset level of the floating diffusion node (FD) can be stored in the first capacitor (C1). During the signal settling time (SCS), a voltage corresponding to the voltage level of the floating diffusion node (FD) corresponding to the High Conversion Gain (HCG) can be stored in the second capacitor (C2). During the second signal settling time (SCS2), a voltage corresponding to the voltage level of the floating diffusion node (FD) corresponding to the Low Conversion Gain (LCG) can be stored in the third capacitor (C3).

[0090] After the third sampling control signal (SAMPS3) and the dynamic conversion gain control signal (DCG) transition from a high level to a low level, the first precharge selection control signal (PSEL1) and the second precharge selection control signal (PSEL2) can transition from a high level to a low level.

[0091] The readout section (ROP) may include a third time section (TI3) and a fourth time section (TI4). In the third time section (TI3), the reset control signal (RS), the transmission control signal (TS), the first sampling control signal (SAMPS1), the second sampling control signal (SAMPS2), the first precharge selection control signal (PSEL1), the second precharge selection control signal (PSEL2), the precharge control signal (PC), and the selection control signal (SELS) may be controlled in the same way as in the readout section (ROP) of FIG. 4. The ramp signal (RAMP) may rise to a higher level than the ramp signal (RAMP) of FIG. 4.

[0092] In the third time interval (TI3), the third sampling control signal (SAMPS3) can be maintained at a low level. In the third time interval (TI3), the dynamic conversion gain control signal (DCG) can be maintained at a low level.

[0093] At the beginning of the fourth time interval (TI4), the reset control signal (RS), transmission control signal (TS), first sampling control signal (SAMPS1), second sampling control signal (SAMPS2), first precharge selection control signal (PSEL1), second precharge selection control signal (PSEL2), precharge control signal (PC), selection control signal (SELS), and ramp signal (RAMP) can maintain their previous levels.

[0094] In the fourth time interval (TI4), the third sampling control signal (SAMPS3) rises from a low level to a high level and then maintains the low level for the third settling time (ST3). When the third sampling control signal (SAMPS3) becomes high, the third sampling transistor (SAMP3) can be turned on. When the third sampling transistor (SAMP3) is turned on, the voltage stored in the fourth capacitor (C4) can be transferred to the second node (NO2). The second source follower transistor (SF2) and the select transistor (SX) can output a voltage corresponding to the voltage level of the second node (NO2) to the corresponding column line (CL).

[0095] After the third sampling control signal (SAMPS3) transitions from a low level to a high level, the ramp signal (RAMP) can gradually decrease (or increase). The analog-to-digital conversion circuit (140) can generate a digital value corresponding to the voltage level of the floating diffusion node (FD) by comparing the voltage level of the column line (CL) with the ramp signal (RAMP).

[0096] That is, during the first settling time (ST1), the pixel (PX2) can output a voltage corresponding to the reset level of the floating diffusion node (FD) to the column line (CL) using the first capacitor (C1). During the second settling time (ST2), the pixel (PX2) can output a voltage corresponding to the high conversion gain signal level of the floating diffusion node (FD) to the column line (CL) using the second capacitor (C2). During the third settling time (ST3), the pixel (PX2) can output a voltage corresponding to the low conversion gain signal level to the column line (CL) using the fourth capacitor (C4).

[0097] As described with reference to FIG. 7, when the voltages of the sub-lines of the row line connected to a single pixel (PX) change, the voltage of the gate of the precharge transistor (PCX) or the voltage of the floating node (FN) can change due to coupling. The change in the voltage of the gate of the precharge transistor (PCX) or the voltage of the floating node (FN) can be transmitted to the floating node (FN) or the gate of the precharge transistor (PCX) through the third capacitor (C3). Thus, the voltage difference between the voltage of the gate of the precharge transistor (PCX) and the voltage of the floating node (FN) is maintained constant, and the precharge transistor (PCX) can flow a constant current. Since the precharge transistor (PCX) flows a constant current, the degradation of the image data quality is prevented.

[0098] FIG. 8 shows an example of a pixel (PX3) according to another embodiment of the present invention. Referring to FIG. 8, the pixel (PX3) of the image sensor (100) may include a photodiode (PD), a transfer transistor (TX), a second photodiode (PD2), a second transfer transistor (TX2), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), and a third capacitor (C3). Compared to the pixel (PX) of FIG. 3, the pixel (PX3) of FIG. 8 may further include a second photodiode (PD2) and a second transfer transistor (TX2).

[0099] The second photodiode (PD2) may be connected between the second transfer transistor (TX2) and a ground node to which a ground voltage (GND) is applied. The second transfer transistor (TX2) may include a gate to which a second transfer control signal (TS2) is applied, a first terminal connected to the second photodiode (PD2), and a second terminal connected to a floating diffusion node (FD). The second transfer transistor (TX2) may be turned on or turned off in response to the second transfer control signal (TS2). When turned on by the second transfer control signal (TS2), the second transfer transistor (TX2) may dump electrons generated by the second photodiode (PD2) to the floating diffusion node (FD).

[0100] For example, during the signal settling time (SCS) described with reference to FIG. 4, the image sensor (100) may dump electrons generated by the photodiode (PD) of the pixel (PX3) to the floating diffusion node (FD) through the transfer transistor (TX). Alternatively, the image sensor may dump electrons generated by the photodiode (PD) of the pixel (PX3) and the second photodiode (PD2) to the floating diffusion node (FD) through the transfer transistor (TX) and the second transfer transistor (TX2).

[0101] For example, if the average illuminance of the image data generated by the pixels (PX3) is higher than the first threshold, the image sensor (100) can dump only the electrons generated by the photodiode (PD) to the floating diffusion node (FD). If the average illuminance of the image data generated by the pixels (PX3) is lower than the second threshold, the image sensor (100) can dump the electrons generated by the photodiode (PD) and the second photodiode (PD2) to the floating diffusion node (FD). The first threshold may be greater than the second threshold.

[0102] For example, the first source follower transistor (SF1), precharge transistor (PCX), and second precharge select transistor (PSX2) of the pixel (PX3) can be connected as in the pixel (PX1) of FIG. 5.

[0103] For example, similar to the pixel (PX2) in FIG. 6, a dynamic conversion gain transistor (DCGX) may be added between the reset transistor (RX) of the pixel (PX3) and the floating diffusion node (FD). Additionally, a fourth capacitor (C4) and a third sampling transistor (SAMP3) may be added between the power node to which the third power supply voltage (VPIX3) is applied and the second node (NO2).

[0104] FIG. 9 shows an example of a pixel (PX3) according to another embodiment of the present invention. Referring to FIG. 9, the pixel (PX3) of the image sensor (100) may include a photodiode (PD), a transfer transistor (TX), a second photodiode (PD2), a second transfer transistor (TX2), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a fourth capacitor (C4), a third sampling transistor (SAMP3), a second source follower transistor (SF2), a select transistor (SX), and a third capacitor (C3). Compared to the pixel (PX3) of FIG. 8, the pixel (PX4) of FIG. 9 may further include a fourth capacitor (C4) and a third sampling transistor (SAMP3).

[0105] The fourth capacitor (C4) may be connected between the third power node to which the third power supply voltage (VPIX3) is applied and the third sampling transistor (SAMP3). The third sampling transistor (SAMP3) may include a gate to which the third sampling control signal (SAMPS3) is applied, a first terminal connected to the fourth capacitor (C4), and a second terminal connected to the second node (NO2).

[0106] As described with reference to FIG. 7, the image sensor (100) may have three signal settling times in the global signal dumping interval (GSDP) when generating image data using a pixel (PX4). In the first signal settling time, a voltage corresponding to the reset level of the floating diffusion node (FD) may be stored in the first capacitor (C1). In the second signal settling time, electrons generated by the photodiode (PD) are dumped to the floating diffusion node (FD), and a voltage corresponding to the first signal level of the floating diffusion node (FD) may be stored in the second capacitor (C2). In the third signal settling time, electrons generated by the second photodiode (PD2) are dumped to the floating diffusion node (FD), and a voltage corresponding to the second signal level of the floating diffusion node (FD) may be stored in the third capacitor (C3).

[0107] As described with reference to FIG. 7, the image sensor (100) may have three settling times in the readout section (ROP) when generating image data using a pixel (PX4). In the first settling time, the pixel (PX4) may output a voltage corresponding to the reset level of the floating diffusion node (FD) to the column line (CL) using the first capacitor (C1). In the second settling time, the pixel (PX4) may output a voltage corresponding to the first signal level of the floating diffusion node (FD) to the column line (CL2) using the second capacitor (C2). In the third settling time, the pixel (PX4) may output a voltage corresponding to the second signal level of the floating diffusion node (FD) to the column line (CL2) using the third capacitor (C3).

[0108] The analog-to-digital conversion circuit (140) can convert voltages output from the pixel (PX4) into digital values. By subtracting the digital value obtained at the first settling time from the digital value obtained at the second settling time, the image sensor (100) can obtain a first digital value corresponding to the intensity of light incident on the photodiode (PD). By subtracting the digital value obtained at the second settling time and the digital value obtained at the first settling time from the digital value obtained at the third settling time, the image sensor (100) can obtain a second digital value corresponding to the intensity of light incident on the second photodiode (PD2). The first digital value and the second digital value can be used for autofocusing.

[0109] For example, the first source follower transistor (SF1), precharge transistor (PCX), and second precharge select transistor (PSX2) of the pixel (PX4) can be connected as in the pixel (PX1) of FIG. 5.

[0110] FIG. 10 shows an example of a pixel (PX5) according to another embodiment of the present invention. Referring to FIG. 10, a pixel (PX) of an image sensor (100) comprises a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), a third capacitor (C3), a second photodiode (PD2), a second transfer transistor (TX2), a second reset transistor (RX2), a third source follower transistor (SF3), a second precharge transistor (PCX2), a third precharge select transistor (PSX3), a fourth capacitor (C4), a third sampling transistor (SAMP3), a fifth capacitor (C5), a fourth sampling transistor (SAMP4), a first switch transistor (SWX1), and a second switch It may include a transistor (SWX2).

[0111] Compared to the pixel (PX) of FIG. 1, the pixel (PX5) may further include a second photodiode (PD2), a second transmission transistor (TX2), a second reset transistor (RX2), a third source follower transistor (SF3), a second precharge transistor (PCX2), a third precharge select transistor (PSX3), a fourth capacitor (C4), a third sampling transistor (SAMP3), a fifth capacitor (C5), a fourth sampling transistor (SAMP4), a first switch transistor (SWX1), and a second switch transistor (SWX2).

[0112] The second photodiode (PD2) may be connected between a ground node to which a ground voltage (GND) is applied and a second transfer transistor (TX2). The second transfer transistor (TX2) may include a gate to which a second transfer control signal (TS2) is applied, a first terminal connected to the second photodiode (PD2), and a second terminal connected to the second floating diffusion node (FD2). The second transfer transistor (TX2) may operate similarly to the transfer transistor (TX).

[0113] The second reset transistor (RX2) may include a gate to which a second reset control signal (RS2) is applied, a first terminal connected to a first power node to which a first power voltage (VPIX1) is applied, and a second terminal connected to a second floating diffusion node (FD2). The second reset transistor (RX2) may operate similarly to the reset transistor (RX).

[0114] The third source follower transistor (SF3) may include a gate connected to the second floating diffusion node (FD2), a first terminal connected to the second power node to which the second power supply voltage (VPIX2) is applied, and a second terminal connected to the third node (NO3). The third source follower transistor (SF3) may operate similarly to the first source follower transistor (SF1).

[0115] The second precharge transistor (PC2) may include a gate to which the second precharge control signal (PS2) is applied, a first terminal connected to the third node (NO3), and a second terminal connected to the floating node (FN). The second precharge transistor (PCX2) may operate similarly to the precharge transistor (PCX).

[0116] The third precharge select transistor (PSX3) may include a gate to which the third precharge select control signal (PSEL3) is applied, a first terminal connected to the third node (NO3), and a second terminal connected to the fourth node (NO4). The third precharge select transistor (PSX3) may operate similarly to the second precharge select transistor (PSX2).

[0117] The fourth capacitor (C4) may be connected between the third power node to which the third power voltage (VPIX3) is applied and the first terminal of the third sampling transistor (SAMP3). The third sampling transistor (SAMP3) may include a gate to which the third sampling control signal (SAMPS3) is applied, a first terminal connected to the fourth capacitor (C4), and a second terminal connected to the fourth node (NO4). The third sampling transistor (SAMP3) may operate similarly to the first sampling transistor (SAMP1).

[0118] The fifth capacitor (C5) may be connected between the third power node to which the third power voltage (VPIX3) is applied and the first terminal of the fourth sampling transistor (SAMP4). The fourth sampling transistor (SAMP4) may include a gate to which the fourth sampling control signal (SAMPS4) is applied, a first terminal connected to the fifth capacitor (C5), and a second terminal connected to the fourth node (NO4). The fourth sampling transistor (SAMP4) may operate similarly to the second sampling transistor (SAMP2).

[0119] The first switch transistor (SWX1) may include a gate to which the first switch control signal (SW1) is applied, a first terminal connected to the second node (NO2), and a second terminal connected to the gate of the second source follower transistor (SF2). The first switch transistor (SWX1) may form or block a current path between the second node (NO2) and the gate of the second source follower transistor (SF2).

[0120] The second switch transistor (SWX2) may include a gate to which the second switch control signal (SW2) is applied, a first terminal connected to the fourth node (NO4), and a second terminal connected to the gate of the second source follower transistor (SF2). The second switch transistor (SWX2) may form or block a current path between the fourth node (NO4) and the gate of the second source follower transistor (SF2).

[0121] The sixth capacitor (C6) can be connected between the gate of the second precharge transistor (PCX2) and the floating node (FN). The sixth capacitor (C6) can cause the second precharge transistor (PCX2) to flow a constant current.

[0122] As described with reference to FIGS. 3 and 4, the voltage corresponding to the reset level of the floating diffusion node (FD) and the voltage corresponding to the signal level can be stored in the first capacitor (C1) and the second capacitor (C2), respectively. Similarly, the voltage corresponding to the reset level of the second floating diffusion node (FD2) and the voltage corresponding to the signal level can be stored in the fourth capacitor (C4) and the fifth capacitor (C5), respectively.

[0123] The image sensor (100) can sequentially turn on and off the first switch transistor (SWX1) and the second switch transistor (SWX2) to output a voltage corresponding to the reset level of the floating diffusion node (FD) and a voltage corresponding to the signal level to the column line (CL), and output a voltage corresponding to the reset level of the second floating diffusion node (FD2) and a voltage corresponding to the signal level to the column line (CL).

[0124] For example, the first source follower transistor (SF1), the precharge transistor (PCX), and the second precharge select transistor (PSX2) of the pixel (PX5) can be connected as in the pixel (PX1) of FIG. 5. Additionally, the third source follower transistor (SF3), the second precharge transistor (PCX2), and the third precharge select transistor (PSX3) of the pixel (PX5) can be connected as in the pixel (PX1) of FIG. 5.

[0125] For example, similar to the pixel (PX2) in FIG. 6, a dynamic conversion gain transistor may be added between the reset transistor (RX) of the pixel (PX5) and the floating diffusion node (FD). Additionally, an additional capacitor and a sampling transistor may be added between the power node to which the third power supply voltage (VPIX3) is applied and the second node (NO2).

[0126] Likewise, a dynamic conversion gain transistor may be added between the second reset transistor (RX2) of the pixel (PX5) and the second floating diffusion node (FD2). Additionally, an additional capacitor and a sampling transistor may be added between the power node to which the third power supply voltage (VPIX3) is applied and the fourth node (NO4).

[0127] For example, as described with reference to FIGS. 8 and 9, two or more photodiodes and two or more transfer transistors may be connected to the floating diffusion node (FD). Likewise, two or more photodiodes and two or more transfer transistors may be connected to the second floating diffusion node (FD2).

[0128] As described with reference to FIG. 8, depending on the average illuminance, electrons generated by some or all of the two or more photodiodes may be dumped to a floating diffusion node (FD). Likewise, depending on the average illuminance, electrons generated by some or all of the two or more photodiodes may be dumped to a second floating diffusion node (FD2).

[0129] As described with reference to FIG. 9, the signal level of the floating diffusion node (FD) when electrons generated by some of the two or more photodiodes are dumped into the floating diffusion node (FD), and the signal level of the floating diffusion node (FD) when electrons generated by all of the two or more photodiodes are dumped into the floating diffusion node (FD). Likewise, the signal level of the second floating diffusion node (FD2) when electrons generated by some of the two or more photodiodes are dumped into the second floating diffusion node (FD2), and the signal level of the second floating diffusion node (FD2) when electrons generated by all of the two or more photodiodes are dumped into the second floating diffusion node (FD2) may be sampled.

[0130] FIG. 11 shows an example of a vertical cross-sectional view of a pixel array (110) of an image sensor (100). Referring to FIG. 11, the pixel array (110) of the image sensor (100) may include a circuit portion and a lens portion. The circuit portion may be manufactured along a first direction, and the lens portion may be manufactured along a direction opposite to the first direction. In the circuit portion, the expressions 'on' or 'on' may refer to the first direction. Likewise, in the lens portion, the expressions 'on' or 'on' may refer to the first direction.

[0131] The circuit portion may include a substrate (SUB), a semiconductor pattern region (SPA), and a metal pattern region (MPA). The substrate (SUB) may include a photodiode (PD) and an active region (AA). The photodiode (PD) may be formed on the lower part of the substrate. On the upper part of the photodiode (PD), an active region (AA) for forming transistors may be provided.

[0132] A semiconductor pattern region (SPA) may be provided on a substrate (SUB). The semiconductor pattern region (SPA) may include semiconductor patterns that form transistors together with an active region (AA). For example, the semiconductor patterns may include patterns of polysilicon.

[0133] A metal pattern region (MPA) may be provided on a semiconductor pattern region (SPA). The metal pattern region (MPA) may include metal patterns for connecting transistors to each other, metal patterns for contacting an active region, and metal patterns for connecting the metal patterns to each other.

[0134] The metal pattern region (MPA) may include a capacitor region (CA). The capacitor region (CA) may include capacitors formed using metal patterns. For example, the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), the fourth capacitor (C4), the fifth capacitor (C5), and the sixth capacitor (C6) described with reference to FIGS. 3 through 10 may all be provided in the capacitor region (CA).

[0135] The capacitors in the capacitor region (CA) may be capacitors of the same type manufactured by the same process. For example, the capacitors in the capacitor region (CA) may include OCS (One Cylinder Stack) type capacitors or Pillar type capacitors. Since the capacitors are manufactured by the same process, the overhead associated with an increase in the number of capacitors can be minimized.

[0136] The lens portion may include a microlens area (MLA) and a color filter area (CPA). The microlens area (MLA) may include microlenses (ML) corresponding to a plurality of pixels. The microlenses (ML) can concentrate incident light and transmit it to the circuit portion.

[0137] A color filter area (CPA) may be provided on the microlens area (MLA). The color filter area (CPA) may include red, green, and blue color filters. For example, one color filter may be provided for one pixel, or one color filter may be provided in common for two or more pixels.

[0138] FIG. 12 shows an example of a pixel (PX6) according to another embodiment of the present invention. Referring to FIG. 12, the pixel (PX6) of the image sensor (100) may include a photodiode (PD), a transmission transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), a third capacitor (C3), and a precharge control transistor (PCTX).

[0139] The photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) are configured identically to the photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) described with reference to FIG. 3, and identically It can operate. Therefore, redundant explanations are omitted.

[0140] For example, compared to the pixel (PX) of FIG. 3, the pixel (PX6) may further include a precharge control transistor (PCTX). The precharge control transistor (PCTX) may include a gate into which a precharge control signal (PC_CTRL) is input, a first terminal into which a precharge control signal (PC) is applied, and a second terminal connected to the gate of the precharge transistor (PCX).

[0141] For example, the precharge signal (PC_CTRL) and the precharge control signal (PC) may have a high level while the reset control signal (RS) or the transmission control signal (TS) has a high level, and may have a low level while the reset control signal (RS) or the transmission control signal (TS) has a low level. As another example, the length of the time interval during which the precharge control signal (PC_CTRL) and the precharge control signal (PC) have a high level may be shorter than the time interval during which the reset control signal (RS) or the transmission control signal (TS) has a high level, and may be included in the time interval during which the reset control signal (RS) or the transmission control signal (TS) has a high level.

[0142] When the precharge signal (PC_CTRL) and the precharge control signal (PC) are at a high level, the gate of the precharge transistor (PCX) can be charged to the voltage of the precharge control signal (PC) (e.g., a high level voltage). When the precharge signal (PC_CTRL) and the precharge control signal (PC) are at a low level, the gate of the precharge transistor (PCX) can be floated. The voltage difference between the voltage of the gate of the precharge transistor (PCX) and the voltage of the floating node (FN) can be maintained by the third capacitor (C3). Since both the floating node (FN) and the gate of the precharge transistor (PCX) are floating, the effect of maintaining the voltage difference by the third capacitor (C3) can be further enhanced.

[0143] For example, a precharge control transistor (PCTX) is connected to the gate of a precharge transistor (PCX) in the pixel (PX1) described with reference to FIG. 5, the pixel (PX2) described with reference to FIG. 6, the pixel (PX3) described with reference to FIG. 8, the pixel (PX4) described with reference to FIG. 9, and the pixel (PX5) described with reference to FIG. 10, and a precharge control signal (PC) can be transmitted to the gate of the precharge transistor (PCX) through the precharge control transistor (PCTX).

[0144] FIG. 13 shows an example of a pixel (PX7) according to another embodiment of the present invention. Referring to FIG. 13, the pixel (PX7) of the image sensor (100) may include a photodiode (PD), a transmission transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), a third capacitor (C3), and a fourth capacitor (C4).

[0145] The photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) are configured identically to the photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), select transistor (SX), and third capacitor (C3) described with reference to FIG. 3, and identically It can operate. Therefore, redundant explanations are omitted.

[0146] For example, compared to the pixel (PX) of FIG. 3, the pixel (PX7) may further include a fourth capacitor (C4). The fourth capacitor (C4) may be connected between the gate of the precharge transistor (PCX) and a ground node. The fourth capacitor (C4) may stabilize the voltage of the gate of the precharge transistor (PCX).

[0147] The third capacitor (C3) can stabilize the voltage difference between the gate of the precharge transistor (PCX) and the floating node (FN), and the fourth capacitor (C4) can stabilize the voltage difference between the gate of the precharge transistor (PCX) and the ground node.

[0148] For example, a fourth capacitor (C4) may also be added to the pixel (PX1) described with reference to FIG. 5, the pixel (PX2) described with reference to FIG. 6, the pixel (PX3) described with reference to FIG. 8, the pixel (PX4) described with reference to FIG. 9, and the pixel (PX5) described with reference to FIG. 10.

[0149] Additionally, as described with reference to FIG. 12, a precharge control transistor (PCTX) is connected to the gate of a precharge transistor (PCX), and a precharge control signal (PC) can be transmitted to the gate of the precharge transistor (PCX) through the precharge control transistor (PCTX). A fourth capacitor (C4) can be connected between the node between the gate of the precharge control transistor (PCTX) and the gate of the precharge transistor (PCX) and the ground node.

[0150] FIG. 14 shows an example of a pixel (PX8) according to another embodiment of the present invention. Referring to FIG. 14, a pixel (PX7) of an image sensor (100) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a first source follower transistor (SF1), a precharge transistor (PCX), a first precharge select transistor (PSX1), a second precharge select transistor (PSX2), a first sampling transistor (SAMP1), a first capacitor (C1), a second sampling transistor (SAMP2), a second capacitor (C2), a second source follower transistor (SF2), a select transistor (SX), and a fourth capacitor (C4).

[0151] The photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), and select transistor (SX) are configured and can operate in the same way as the photodiode (PD), transfer transistor (TX), reset transistor (RX), first source follower transistor (SF1), precharge transistor (PCX), first precharge select transistor (PSX1), second precharge select transistor (PSX2), first sampling transistor (SAMP1), first capacitor (C1), second sampling transistor (SAMP2), second capacitor (C2), second source follower transistor (SF2), and select transistor (SX) described with reference to FIG. 3. Therefore, redundant descriptions are omitted.

[0152] Compared to the pixel (PX7) of FIG. 13, the third capacitor (C3) may not be provided in the pixel (PX8). The fourth capacitor (C4) can stabilize the voltage of the gate of the precharge transistor (PCX).

[0153] For example, a fourth capacitor (C4) may be provided instead of a third capacitor (C3) in the pixel (PX1) described with reference to FIG. 5, the pixel (PX2) described with reference to FIG. 6, the pixel (PX3) described with reference to FIG. 8, the pixel (PX4) described with reference to FIG. 9, and the pixel (PX5) described with reference to FIG. 10.

[0154] Additionally, as described with reference to FIG. 12, a precharge control transistor (PCTX) is connected to the gate of a precharge transistor (PCX), and a precharge control signal (PC) can be transmitted to the gate of the precharge transistor (PCX) through the precharge control transistor (PCTX). A fourth capacitor (C4) can be connected between the node between the gate of the precharge control transistor (PCTX) and the gate of the precharge transistor (PCX) and the ground node.

[0155] In the embodiments described above, components according to the technical concept of the present invention have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish the components from one another and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply a sequential order or any numerical meaning.

[0156] In the embodiments described above, components according to embodiments of the present invention are referenced using blocks. The blocks may be implemented in various forms such as ICs (Integrated Circuits), ASICs (Application Specific ICs), FPGAs (Field Programmable Gate Arrays), CPLDs (Complex Programmable Logic Devices), software such as firmware or applications running on hardware devices, or a combination of hardware devices and software. Additionally, the blocks may include circuits composed of semiconductor devices within an IC or circuits registered as IPs (Intellectual Property).

[0157] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention. Explanation of the symbols

[0158] 100: Image sensor 110: Pixel array 120: Hang driver 130: Ramp signal generator 140: Analog-to-Digital Conversion Circuit 150: Memory circuit 160: Timing Generator

Claims

Claim 1 An image sensor comprising a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels comprises: a photodiode; a transfer transistor connected between the photodiode and a floating diffusion node; a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied; a first source follower transistor comprising a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a second terminal connected to the first node; a precharge transistor connected between the first node and the floating node; a first precharge select transistor connected between the floating node and a ground node; a second precharge select transistor connected between the first node and the second node; and a first capacitor connected between the gate of the precharge transistor and the floating node. Claim 2 An image sensor according to claim 1, wherein each of the plurality of pixels comprises: a substrate including the photodiode and an active region; a semiconductor pattern region on the substrate forming the transfer transistor, the reset transistor, the first source follower transistor, the precharge transistor, the first precharge select transistor, and the second precharge select transistor together with the active region; and a metal pattern region on the semiconductor pattern region further comprising the plurality of row lines, the plurality of column lines, and the first capacitor. Claim 3 In paragraph 2, each of the plurality of pixels comprises: a second capacitor and a first sampling transistor connected between a third power node to which a third power supply voltage is applied and the second node; a third capacitor and a second sampling transistor connected between the third power node and the second node; a second source follower transistor including a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and a second terminal; and a selection transistor connected to the second terminal of the second source follower transistor and a corresponding column line among the plurality of column lines, wherein the first capacitor, the second capacitor and the third capacitor are manufactured by the same process, an image sensor. Claim 4 In paragraph 3, the image sensor comprising the first capacitor, the second capacitor, and the third capacitor as OCS (One Cylinder Stack) type capacitors or Pillar type capacitors. Claim 5 An image sensor further comprising a row driver connected to the plurality of row lines, configured to reset the voltage level of each of the plurality of pixels by simultaneously turning on the reset transistors of the plurality of pixels, store a voltage corresponding to the reset level of the floating diffusion node in the second capacitor through each of the plurality of pixels' first sampling transistors, dump electrons generated by the photodiode in each of the plurality of pixels into the floating diffusion node by simultaneously turning on the reset transistors of the plurality of pixels, and store a voltage corresponding to the voltage level of the floating diffusion node into which the electrons were dumped through each of the plurality of pixels' second sampling transistors in the third capacitor. Claim 6 An image sensor according to claim 5, wherein the row driver is configured to sequentially select the plurality of row lines and simultaneously turn on the selection transistors of the selected pixels connected to the selected row lines, thereby sequentially transmitting voltages corresponding to the voltage of the second capacitor and the voltage of the third capacitor of each of the selected pixels to the column lines. Claim 7 In paragraph 3, each of the plurality of pixels further comprises: a dynamic conversion gain transistor connected between the floating diffusion node and the reset transistor; and a fourth capacitor and a third sampling transistor connected in series between the third power node and the second node. Claim 8 An image sensor according to claim 1, wherein each of the plurality of pixels comprises: a second photodiode; and a second transmission transistor connected between the second photodiode and the floating diffusion node. Claim 9 An image sensor according to claim 1, further comprising a precharge control transistor including a gate into which a precharge signal is input, a first terminal into which a precharge control signal is input, and a second terminal connected to the gate of the precharge transistor. Claim 10 An image sensor according to claim 9, wherein the precharge signal and the precharge control signal have a high level while the reset control signal applied to the gate of the reset transistor has a high level, and the precharge signal and the precharge control signal have a low level while the reset control applied to the gate of the reset transistor has a low level. Claim 11 An image sensor according to claim 9, wherein the precharge signal and the precharge control signal have a high level while the transmission control signal applied to the gate of the transmission transistor has a high level, and the precharge signal and the precharge control signal have a low level while the transmission control signal applied to the gate of the transmission transistor has a low level. Claim 12 An image sensor according to claim 9, further comprising a second capacitor connected between the gate of the precharge transistor and the ground node. Claim 13 An image sensor according to claim 1, further comprising a second capacitor connected between the gate of the precharge transistor and the ground node. Claim 14 In claim 1, each of the plurality of pixels comprises: a second capacitor and a first sampling transistor connected between a third power node to which a third power supply voltage is applied and the second node; a third capacitor and a second sampling transistor connected between the third power node and the second node; a second source follower transistor comprising a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and a second terminal; a select transistor connected to the second terminal of the second source follower transistor and a corresponding column line among the plurality of column lines; a second photodiode; a second transfer transistor connected between the second photodiode and a second floating diffusion node; a second reset transistor connected between the second floating diffusion node and the first power node; a third source follower transistor comprising a gate connected to the second floating diffusion node, a first terminal connected to the second power node, and a second terminal connected to the third node; a second precharge transistor connected between the third node and the floating node; and between the third node and the fourth node An image sensor further comprising: a third precharge select transistor connected; a fourth capacitor and a third sampling transistor connected between the third power node and the fourth node; a fifth capacitor and a fourth sampling transistor connected between the third power node and the fourth node; a first switch connected between the second node and the gate of the second source follower transistor; a second switch connected between the fourth node and the gate of the second source follower transistor; and a sixth capacitor connected between the gate of the second precharge transistor and the floating node. Claim 15 An image sensor comprising: a substrate including the photodiode and an active region; a semiconductor pattern region on the substrate forming, together with the active region, the transfer transistor, the reset transistor, the first source follower transistor, the precharge transistor, the first precharge select transistor, the second precharge select transistor, the first sampling transistor, the second sampling transistor, the second source follower transistor, the select transistor, the second transfer transistor, the second reset transistor, the third source follower transistor, the second precharge transistor, the third precharge select transistor, the third sampling transistor, the fourth sampling transistor, the first switch, and the second switch; and a metal pattern region on the semiconductor pattern region including the plurality of row lines, the plurality of column lines, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor. Claim 16 In claim 15, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are image sensors manufactured by the same process. Claim 17 In claim 15, the image sensor comprising the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are OCS (One Cylinder Stack) type capacitors or Pillar type capacitors. Claim 18 An image sensor according to claim 1, wherein each of the plurality of pixels comprises: a second capacitor and a first sampling transistor connected between a third power node to which a third power supply voltage is applied and the second node; a third capacitor and a second sampling transistor connected between the third power node and the second node; a second source follower transistor including a gate connected to the second node, a first terminal to which a fourth power supply voltage is applied, and a second terminal; a selection transistor connected to the second terminal of the second source follower transistor and a corresponding column line among the plurality of column lines; a second photodiode; a second transfer transistor connected between the second photodiode and the floating diffusion node; and a fourth capacitor and a third sampling transistor connected between the third power node and the second node. Claim 19 An image sensor comprising a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels comprises: a photodiode; a transfer transistor connected between the photodiode and a floating diffusion node; a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied; a first source follower transistor comprising a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a second terminal connected to the first node; a first precharge select transistor connected between the first node and the second node; a precharge transistor connected between the second node and the floating node; a second precharge select transistor connected between the precharge transistor and a ground node; and a capacitor connected between the gate of the precharge transistor and the ground node. Claim 20 Multiple pixels connected to multiple row lines and multiple column lines; And includes a row driver connected to the plurality of pixels through the plurality of row lines, wherein each of the plurality of pixels comprises: a photodiode; a transfer transistor connected between the photodiode and a floating diffusion node; a reset transistor connected between the floating diffusion node and a first power node to which a first power supply voltage is applied; a first source follower transistor comprising a gate connected to the floating diffusion node, a first terminal connected to a second power node to which a second power supply voltage is applied, and a second terminal connected to the first node; a precharge transistor connected between the first node and the floating node; a first precharge select transistor connected between the floating node and a ground node; a second precharge select transistor connected between the first node and the second node; a first capacitor and a first sampling transistor connected between a third power node to which a third power supply voltage is applied and the second node; a second capacitor and a second sampling transistor connected between the third power node and the second node; a gate connected to the second node, and a first to which a fourth power supply voltage is applied A second source follower transistor including a terminal and a second terminal; a select transistor connected to the second terminal of the second source follower transistor and a corresponding column line among the plurality of column lines; and a third capacitor connected between the gate of the precharge transistor and the floating node, wherein each of the plurality of pixels comprises: a substrate including the photodiode and an active region;An image sensor comprising: a semiconductor pattern region on the substrate, forming the transfer transistor, the reset transistor, the first source follower transistor, the precharge transistor, the first precharge select transistor, the second precharge select transistor, the first sampling transistor, the second sampling transistor, the second source follower transistor, and the select transistor together with the active region; and further comprising a metal pattern region on the semiconductor pattern region, including the plurality of row lines, the plurality of column lines, the first capacitor, the second capacitor, and the third capacitor, wherein the first capacitor, the second capacitor, and the third capacitor are manufactured by the same process, and the first capacitor, the second capacitor, and the third capacitor are OCS (One Cylinder Stack) type capacitors or Pillar type capacitors.

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