Display panel

Abstract

A display panel of one embodiment may include a base layer comprising a boundary region and a pixel region, a pixel circuit superimposed on the pixel region, a plurality of insulating layers having an opening defined corresponding to the boundary region, a first signal line superimposed on the boundary region and the pixel region, an organic layer comprising a first portion filling the opening, and a light-emitting element electrically connected to the pixel circuit. The insulating layers may include at least a first insulating layer, and the first signal line may be disposed on the first insulating layer. The opening may include a first region superimposed on the first signal line and having a first depth, and a second region having a second depth greater than the first depth. Accordingly, the display panel of one embodiment may exhibit characteristics of improved manufacturing efficiency.

Description

Technology Field

[0001] The present invention relates to a flexible display panel. Background Technology

[0002] A display device includes a display panel, and the display panel includes a light-emitting element and transistors for controlling an electrical signal applied to the light-emitting element. In order to accurately control the light emission level of the light-emitting element, the number of transistors electrically connected to a single light-emitting element is increasing, and the number of wires transmitting electrical signals to these transistors is also increasing. Accordingly, measures are required to improve the design integration and manufacturing efficiency of the display panel. The problem to be solved

[0003] The objective of the present invention is to provide a display panel with improved manufacturing efficiency and integration density. means of solving the problem

[0004] One embodiment provides a display panel comprising: a base layer including a boundary region and a pixel region; a pixel circuit superimposed on the pixel region; a plurality of insulating layers including at least a first insulating layer, wherein an opening corresponding to the boundary region is defined; an organic layer including a first signal line disposed above the first insulating layer and superimposing the boundary region and the pixel region; and a first portion filling the opening; and a light-emitting element disposed above the insulating layers and electrically connected to the pixel circuit; wherein the opening is a first region superimposed on the first signal line and having a first depth; and a second region having a second depth greater than the first depth.

[0005] The above insulating layers further include a second insulating layer disposed above the first insulating layer, and the display panel further includes a second signal line disposed above the second insulating layer and overlapping the boundary region and the pixel region, and the opening may further include a third region that overlaps the second signal line and has a third depth smaller than the first depth.

[0006] The second region may be non-overlapping with the first signal line and the second signal line.

[0007] Each of the first signal line and the second signal line extends in a first direction, and within a second direction intersecting the first direction, the first region and the third region may be spaced apart with the second region in between.

[0008] Within the pixel area, the second insulating layer can cover the first signal line.

[0009] Within the above boundary region, the lower surface of the organic layer can come into contact with the first signal line and the second signal line.

[0010] It further includes a barrier layer disposed above the base layer, and the opening may expose the barrier layer within the second region.

[0011] In the second region above, the barrier layer may be in contact with the organic layer.

[0012] The pixel circuit comprises: a first transistor including a first source region, a first drain region, a first channel region, and a first gate; and a second transistor including a second source region, a second drain region, a second channel region disposed on a different layer from the first channel region, and a second gate disposed on a different layer from the first gate; wherein the first signal line may be disposed on the same layer as the first gate or the second gate.

[0013] The second transistor may be electrically connected to the second gate and may further include a third gate disposed on a different layer from the first gate and the second gate.

[0014] The first transistor above may be a silicon transistor, and the second transistor may be an oxide transistor.

[0015] The above boundary area includes a first boundary area extended in a first direction and a second boundary area extended in a second direction intersecting the first direction, and the first signal line may be extended in the first direction.

[0016] The above insulating layers further include a buffer layer disposed below the first insulating layer, a second insulating layer disposed above the first insulating layer, and a third insulating layer disposed above the second insulating layer, wherein the first region penetrates the second insulating layer and the third insulating layer, and the second region penetrates the buffer layer and the first insulating layer to the third insulating layer.

[0017] The first insulating layer includes a first insulating portion that overlaps the boundary region, and the first insulating layer has a first opening and a second opening defined with the first insulating portion in between, and the first opening and the second opening may constitute a part of the openings of the insulating layers.

[0018] The above insulating layers further include a second insulating layer disposed above the first insulating layer, the second insulating layer includes a second insulating portion that overlaps the boundary region, and the second insulating layer has a third opening and a fourth opening defined with the second insulating portion in between, and the third opening and the fourth opening may constitute a part of the openings of the insulating layers.

[0019] It may further include an organic insulating layer disposed above the insulating layer of the uppermost layer among the first part and the insulating layers and in contact with the first part and the insulating layer of the uppermost layer; and a data line disposed above the organic insulating layer.

[0020] The above data line may be connected to the pixel circuit through a contact hole penetrating the organic layer.

[0021] The above organic layer may further include a second portion that extends from the first portion and overlaps the boundary region and the pixel region.

[0022] It further includes a data line positioned on the upper side of the second part, and the data line may be connected to the pixel circuit through a contact hole penetrating the second part.

[0023] The pixel regions are provided in plurality, and the boundary regions surround each of the plurality of pixel regions on a plane, and one, two, or four light-emitting elements may be arranged in each of the pixel regions. Effects of the invention

[0024] A display panel of one embodiment may include an organic layer that fills openings of different depths, thereby exhibiting characteristics of improved manufacturing efficiency and integration density. Brief explanation of the drawing

[0025] FIG. 1 is a plan view of a display panel according to one embodiment. FIG. 2 is a cross-sectional view of a display panel according to one embodiment. FIG. 3a is a block diagram of a display device according to one embodiment. FIG. 3b is an equivalent circuit diagram of a pixel according to one embodiment. FIG. 3c is a waveform diagram of driving signals for driving a pixel according to one embodiment. FIG. 4 is an enlarged plan view of a display panel according to one embodiment. FIG. 5a is a cross-sectional view of a display panel according to one embodiment. FIG. 5b is a cross-sectional view of a display panel according to one embodiment. FIG. 6 is a plan view of a pixel area according to one embodiment. FIGS. 7a to 7h are plan views illustrating the configurations arranged in a pixel area according to one embodiment in a stacking order. FIG. 8a is a cross-sectional view showing the part corresponding to line I-I' of FIG. 6. FIG. 8b is a cross-sectional view showing the part corresponding to line II-II' of FIG. 6. FIG. 8c is a cross-sectional view showing a part of a display panel according to one embodiment. FIG. 9a is an enlarged plan view of a display panel according to one embodiment. FIG. 9b is an enlarged plan view of a display panel according to one embodiment. Specific details for implementing the invention

[0026] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0027] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0031] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0033] Hereinafter, a display panel of one embodiment is described with reference to the drawings.

[0034] FIG. 1 is a plan view of a display panel (100) according to one embodiment. FIG. 2 is a cross-sectional view of a display panel (100) according to one embodiment.

[0035] Referring to FIG. 1, a display panel (100) may include a display area (100-A) and a non-display area (100-NA). The non-display area (100-NA) is adjacent to the display area (100-A) and may surround at least a portion of the display area (100-A). Pixels (PX) may be placed in the display area (100-A), and pixels (PX) may not be placed in the non-display area (100-NA). A data driving circuit (DDC) may be placed on one side of the non-display area (100-NA).

[0036] The display area (100-A) may include a plane defined by a first direction (DR1) and a second direction (DR2). The thickness direction of the display panel (100) may be parallel to a third direction (DR3), which is the normal direction of the display area (100-A). The front (or top) and back (or bottom) surfaces of the members constituting the display panel (100) may be defined based on the third direction (DR3).

[0037] The display panel (100) may be a light-emitting display panel. For example, the display panel (100) may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel. The display panel (100) may be flexible. Although not illustrated, the display panel (100) may be folded along at least one folding axis. The folding area may cross the display area (100-A).

[0038] Referring to FIG. 2, the display panel (100) may include a base layer (110), a circuit layer (120), a light-emitting element layer (130), and an encapsulation layer (140). Unlike what is shown, another functional layer may be disposed between two adjacent layers among the base layer (110), the circuit layer (120), the light-emitting element layer (130), and the encapsulation layer (140).

[0039] The base layer (110) may provide a base surface on which the circuit layer (120) is placed. The base layer (110) may be a flexible substrate capable of bending, folding, rolling, etc. The base layer (110) may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, the embodiment is not limited thereto, and the base layer (110) may include an inorganic layer, an organic layer, or a composite material layer.

[0040] The base layer (110) may include multiple layers. For example, the base layer (110) may include a first synthetic resin layer, a multilayer or single-layer inorganic layer, and a second synthetic resin layer disposed above the multilayer or single-layer inorganic layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, and is not particularly limited.

[0041] The circuit layer (120) may be disposed on the upper side of the base layer (110). The circuit layer (120) may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line, etc.

[0042] The light-emitting element layer (130) may be disposed on the upper side of the circuit layer (120). The light-emitting element layer (130) may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0043] The encapsulation layer (140) may be disposed on the upper side of the light-emitting element layer (130). The encapsulation layer (140) may protect the light-emitting element layer (130) from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer (140) may include at least one inorganic layer. The encapsulation layer (140) may include a structure in which an inorganic layer, an organic layer, and an inorganic layer are sequentially stacked.

[0044] FIG. 3a is a block diagram of a display device (DD) according to one embodiment. FIG. 3b is an equivalent circuit diagram of a pixel (PX) according to one embodiment. FIG. 3c is a waveform diagram of driving signals for driving a pixel (PX) according to one embodiment.

[0045] The display device (DD) may include a timing control unit (TC), a scanning driving circuit (SDC), a data driving circuit (DDC), and a display panel (100). At least one of the timing control unit (TC), the scanning driving circuit (SDC), and the data driving circuit (DDC) may be provided in the form of a driving chip or formed directly on the display panel (100).

[0046] The timing control unit (TC) receives input video signals and can generate video data (D-RGB) by converting the data format of the input video signals to match the interface specifications with the scanning drive circuit (SDC). The timing control unit (TC) outputs the video data (D-RGB) and various control signals (DCS, SCS).

[0047] The scanning driving circuit (SDC) can receive a scanning control signal (SCS) from the timing control unit (TC). The scanning control signal (SCS) may include a vertical start signal that initiates the operation of the scanning driving circuit (SDC), a clock signal that determines the timing of the output of signals, etc. The scanning driving circuit (SDC) can generate a plurality of scan signals and sequentially output the scan signals to corresponding signal lines (SL1 to SLn, GL1 to GLn, HL1 to HLn). Additionally, the scanning driving circuit (SDC) can generate a plurality of light emission control signals in response to the scanning control signal (SCS) and output the light emission control signals to corresponding light emission lines (EL1 to ELn).

[0048] Although FIG. 3a illustrates that multiple scan signals and multiple light emission control signals are output from a single scanning drive circuit (SDC), the embodiment is not limited thereto. For example, the scanning drive circuit may be provided in multiple units. Multiple scanning drive circuits may divide and generate scan signals and output them, and divide and generate multiple light emission control signals and output them. Additionally, the driving circuit that generates and outputs multiple scan signals and the driving circuit that generates and outputs multiple light emission control signals may be distinguished separately.

[0049] The data driving circuit (DDC) can receive a data control signal (DCS) and image data (D-RGB) from the timing control unit (TC). The data driving circuit (DDC) can convert the image data (D-RGB) into data signals and output the data signals to a plurality of data lines (DL1 to DLm) described below. The data signals may be analog voltages corresponding to the grayscale values ​​of the image data (D-RGB).

[0050] The display panel (100) may include a plurality of groups of signal lines. When any one of the plurality of groups of signal lines is defined as a first signal line, another may be defined as a second signal line, and yet another may be defined as a third signal line. Hereinafter, names of the signal lines are defined to distinguish the plurality of groups of signal lines.

[0051] The signal lines of a plurality of groups may include first group scanning lines (SL1 to SLn), second group scanning lines (GL1 to GLn), third group scanning lines (HL1 to HLn), light emission lines (EL1 to ELn), data lines (DL1 to DLm), first voltage line (PL), second voltage line (VL1), and third voltage line (VL2). The first group scanning lines (SL1 to SLn), second group scanning lines (GL1 to GLn), third group scanning lines (HL1 to HLn), and light emission lines (EL1 to ELn) may be extended in a first direction (DR1) and arranged in a second direction (DR2) that intersects the first direction (DR1). Multiple data lines (DL1 to DLm) can intersect insulatedly with the first group of scanning lines (SL1 to SLn), the second group of scanning lines (GL1 to GLn), the third group of scanning lines (HL1 to HLn), and the light-emitting lines (EL1 to ELn).

[0052] Each of the first voltage line (PL), the second voltage line (VL1), and the third voltage line (VL2) may include at least one of a component extended in the first direction (DR1) and a component extended in the second direction (DR2). Each of the first voltage line (PL), the second voltage line (VL1), and the third voltage line (VL2) may include a component extended in the first direction (DR1) and a component extended in the second direction (DR2). The structure and shape of the first voltage line (PL), the second voltage line (VL1), and the third voltage line (VL2) may be designed independently of each other.

[0053] Each of the multiple pixels (PX) can be electrically connected to a corresponding signal line among the aforementioned signal lines. Depending on the configuration of the driving circuit of the pixels (PX), the connection relationship between the pixels (PX) and the signal lines may be changed.

[0054] The first voltage line (PL) can receive the first power supply voltage (ELVDD). The display panel (100) may have a second power supply voltage (ELVSS) applied to it. The second power supply voltage (ELVSS) may have a lower level than the first power supply voltage (ELVDD).

[0055] The second voltage line (VL1) can receive the first initialization voltage (Vint). The first initialization voltage (Vint) may have a level lower than the first power supply voltage (ELVDD). The third voltage line (VL2) can receive the second initialization voltage (VAint). The second initialization voltage (VAint) may have a level lower than the first power supply voltage (ELVDD). The first initialization voltage (Vint) and the second initialization voltage (VAint) may be bias voltages having a constant level. The first initialization voltage (Vint) and the second initialization voltage (VAint) may have different levels. The second initialization voltage (VAint) may have a lower voltage than the first initialization voltage (Vint).

[0056] A plurality of pixels (PX) may include a plurality of groups that generate light of different colors. For example, the plurality of pixels (PX) may include red pixels that generate red light, green pixels that generate green light, and blue pixels that generate blue light. The light-emitting elements of the red pixels, the light-emitting elements of the green pixels, and the light-emitting elements of the blue pixels may include light-emitting layers formed of different materials.

[0057] FIG. 3b illustrates an exemplary pixel (PXij) connected to the i-th scanning line (SLi) of the first group of scanning lines (SL1 to SLn) and connected to the j-th data line (DLj) of a plurality of data lines (DL1 to DLm). The pixel (PXij) may include a pixel driving circuit (PC, hereinafter pixel circuit) and a light-emitting element (LD).

[0058] In one embodiment, the pixel circuit (PC) may include first to seventh transistors (T1 to T7) and a capacitor (Cst). The first transistor (T1), the second transistor (T2), and the fifth transistor (T5) to the seventh transistor (T7) may be P-type transistors, and the third transistor (T3) and the fourth transistor (T4) may be N-type transistors. However, not limited thereto, the first to seventh transistors (T1 to T7) may be implemented as either P-type transistors or N-type transistors.

[0059] In the following description, the input region (or input electrode) of an N-type transistor is described as a drain (or drain region), the input region of a P-type transistor is described as a source (or source region), the output region (or output electrode) of an N-type transistor is described as a source (or source region), and the output region of a P-type transistor is described as a drain (or drain region). Meanwhile, at least one of the first to seventh transistors (T1 to T7) may be omitted.

[0060] The first transistor (T1) may be a driving transistor, and the second transistor (T2) may be a switching transistor. A capacitor (Cst) may be electrically connected between a first voltage line (PL) that receives a first power supply voltage (ELVDD) and a reference node (RN). The capacitor (Cst) may include a first electrode (CE10) electrically connected to the reference node (RN) and a second electrode (CE20) electrically connected to the first voltage line (PL).

[0061] The first transistor (T1) may be electrically connected between the first voltage line (PL) and one electrode (e.g., an anode) of the light-emitting element (LD). The source (S1) of the first transistor (T1) may be electrically connected to the first voltage line (PL). In this specification, "electrically connected between a transistor and a signal line or between a transistor and a transistor" means that "the source, drain, and gate of the transistor have an integral shape with the signal line or are connected through a connecting electrode." Another transistor may be placed or omitted between the source (S1) of the first transistor (T1) and the first voltage line (PL).

[0062] The drain (D1) of the first transistor (T1) can be electrically connected to the anode of the light-emitting element (LD). Another transistor may be placed or omitted between the drain (D1) of the first transistor (T1) and the anode of the light-emitting element (LD). The gate (G1) of the first transistor (T1) can be electrically connected to the reference node (RN).

[0063] The second transistor (T2) can be electrically connected between the j-th data line (DLj) and the source (S1) of the first transistor (T1). The source (S2) of the second transistor (T2) is electrically connected to the j-th data line (DLj), and the drain (D2) of the second transistor (T2) is electrically connected to the source (S1) of the first transistor (T1). The gate (G2) of the second transistor (T2) can be electrically connected to the i-th scan line (SLi) of the first group.

[0064] The third transistor (T3) may be electrically connected between the reference node (RN) and the drain (D1) of the first transistor (T1). The drain (D3) of the third transistor (T3) may be electrically connected to the drain (D1) of the first transistor (T1), and the source (S3) of the third transistor (T3) may be electrically connected to the reference node (RN). The gates (G3-1, G3-2) of the third transistor (T3) may be electrically connected to the i-th scan line (GLi) of the second group. Although the third transistor (T3) is illustrated as including a plurality of gates, the embodiment is not limited thereto and may include only one gate.

[0065] The fourth transistor (T4) may be electrically connected between the reference node (RN) and the second voltage line (VL1). The drain (D4) of the fourth transistor (T4) may be electrically connected to the reference node (RN), and the source (S4) of the fourth transistor (T4) may be electrically connected to the second voltage line (VL1). The gates (G4-1, G4-2) of the fourth transistor (T4) may be electrically connected to the i-th scan line (HLi) of the third group. Although the fourth transistor (T4) is illustrated as having multiple gates, the embodiment is not limited thereto, and the fourth transistor (T4) may have only one gate.

[0066] The fifth transistor (T5) can be electrically connected between the first voltage line (PL) and the source (S1) of the first transistor (T1). The source (S5) of the fifth transistor (T5) is electrically connected to the first voltage line (PL), and the drain (D5) of the fifth transistor (T5) can be electrically connected to the source (S1) of the first transistor (T1). The gate (G5) of the fifth transistor (T5) can be electrically connected to the i-th light-emitting line (ELi).

[0067] The sixth transistor (T6) can be electrically connected between the drain (D1) of the first transistor (T1) and the light-emitting element (LD). The source (S6) of the sixth transistor (T6) is electrically connected to the drain (D1) of the first transistor (T1), and the drain (D6) of the sixth transistor (T6) can be electrically connected to the anode of the light-emitting element (LD). The gate (G6) of the sixth transistor (T6) can be electrically connected to the i-th light-emitting line (ELi). Alternatively, the gate (G6) of the sixth transistor (T6) may be connected to a different signal line than the gate (G5) of the fifth transistor (T5).

[0068] The seventh transistor (T7) can be electrically connected between the drain (D6) of the sixth transistor (T6) and the third voltage line (VL2). The source (S7) of the seventh transistor (T7) is electrically connected to the drain (D6) of the sixth transistor (T6), and the drain (D7) of the seventh transistor (T7) is electrically connected to the third voltage line (VL2). The gate (G7) of the seventh transistor (T7) can be electrically connected to the i+1th scan line (SLi+1) of the first group.

[0069] The operation of the pixel (PXij) is described in more detail with reference to FIGS. 3b and 3c. A display device (DD) can display an image for each frame interval. During each frame interval, the signal lines of each of the first group of scan lines (SL1 to SLn), the second group of scan lines (GL1 to GLn), the third group of scan lines (HL1 to HLn), and the light-emitting lines (EL1 to ELn) can be scanned sequentially. FIG. 3c shows a part of one frame interval.

[0070] Referring to FIG. 3c, each of the signals (EMi, GIi, GWi, GCi, GWi+1) may have a high level (V-HIGH) for some periods and a low level (V-LOW) for some periods. N-type transistors may be turned on when the corresponding signal has a high level (V-HIGH), and P-type transistors may be turned on when the corresponding signal has a low level (V-LOW).

[0071] When the light emission control signal (EMi) has a high level (V-HIGH), the fifth transistor (T5) and the sixth transistor (T6) can be turned off. When the fifth transistor (T5) and the sixth transistor (T6) are turned off, a current path may not be formed between the first voltage line (PL) and the light-emitting element (LD). Therefore, the corresponding section can be defined as a non-luminous section.

[0072] When the scan signal (GIi) applied to the i-th scan line (HLi) of the third group has a high level (V-HIGH), the fourth transistor (T4) can be turned on. When the fourth transistor (T4) is turned on, the reference node (RN) can be initialized by the first initialization voltage (Vint). When the scan signal (GWi) applied to the i-th scan line (SLi) of the first group has a low level (V-LOW) and the scan signal (GCi) on the i-th scan line (GLi) of the second group has a high level (V-HIGH), the second transistor (T2) and the third transistor (T3) can be turned on.

[0073] Since the reference node (RN) is initialized with an initialization voltage (Vint), the first transistor (T1) may be in a turned-on state. When the first transistor (T1) is turned on, a voltage corresponding to the data signal (Dj, FIG. 2) is provided to the reference node (RN). At this time, the capacitor (Cst) can store the voltage corresponding to the data signal (Dj). The voltage corresponding to the data signal (Dj) may be a voltage that is reduced from the data signal (Dj) by the threshold voltage (Vth) of the first transistor (T1).

[0074] When the scan signal (GWi+1) applied to the i+1th scan line (SLi+1) of the first group has a low level (V-LOW), the 7th transistor (T7) can be turned on. As the 7th transistor (T7) is turned on, the anode of the light-emitting element (LD) is initialized to a second initialization voltage (VAint). The parasitic capacitor of the light-emitting element (LD) can be discharged.

[0075] When the light emission control signal (EMi) has a low level (V-LOW), the fifth transistor (T5) and the sixth transistor (T6) can be turned on. When the fifth transistor (T5) is turned on, the first power supply voltage (ELVDD) can be supplied to the first transistor (T1). When the sixth transistor (T6) is turned on, the first transistor (T1) and the light-emitting element (LD) can be electrically connected. The light-emitting element (LD) can generate light of brightness corresponding to the amount of current supplied.

[0076] FIG. 4 is an enlarged plan view of a display panel (100) according to one embodiment, and more specifically, an enlarged view of the display area (100-A) of the display panel (100). FIG. 5a and FIG. 5b are cross-sectional views of a display panel (100) according to one embodiment.

[0077] In Fig. 4, there are 2 pixel rows (PLX i , PLX i-1 ) was enlarged and illustrated. The i-th pixel row (PLX i ) may include a first color pixel (PX1), a second color pixel (PX2), a third color pixel (PX3), and a second color pixel (PX2) arranged in a first direction (DR1). Additionally, the i-th pixel row (PLX i In ), the first color pixel (PX1), the second color pixel (PX2), the third color pixel (PX3), and the second color pixel (PX2) can be repeatedly arranged along the first direction (DR1).

[0078] i-1th pixel row (PLX i-1 ) may include a third color pixel (PX3), a second color pixel (PX2), a first color pixel (PX1), and a second color pixel (PX2) arranged in a first direction (DR1). The i-1th pixel row (PLX i-1 In ), the third color pixel (PX3), the second color pixel (PX2), the first color pixel (PX1), and the second color pixel (PX2) can be repeatedly arranged along the first direction (DR1). Additionally, the pixel row (PLX) shown in FIG. 4 i, PLX i-1 Color pixels of ) can be repeatedly arranged along the second direction (DR2). In FIG. 4, the anodes of the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) are each shown as dotted lines. FIG. 4 illustrates that two light-emitting elements are arranged in one pixel area (PA).

[0079] The display area (100-A) may include a plurality of pixel areas (PA) and a boundary area (BA) between the plurality of pixel areas (PA). The boundary area (BA) may be positioned adjacent to at least a portion of each of the plurality of pixel areas (PA). Two adjacent color pixels among the first color pixel (PX1), the second color pixel (PX2), and the third color pixel (PX3) may be surrounded by the boundary area (BA). The boundary area (BA) may include a first boundary area (BA1) extended in a first direction and a second boundary area (BA2) extended in a second direction (DR2).

[0080] Pixel circuits (PC1, PC2, PC3) of a first color pixel (PX1), a second color pixel (PX2), and a third color pixel (PX3) may be respectively arranged in a plurality of pixel regions (PA). Each of the pixel circuits (PC1, PC2, PC3) may be identical to the pixel circuit (PC) described with reference to FIG. 3b. Although each of the pixel circuits (PC1, PC2, PC3) in FIG. 4 is depicted as substantially corresponding to the pixel region (PA), the embodiment is not limited thereto.

[0081] A pixel area (PA) can be defined as an area within a display area (100-A) that is not a boundary area (BA). A boundary area (BA) is an area defined by an aperture (BA-OP, FIG. 5a) described later, and a display area (100-A) that does not overlap with the aperture (BA-OP) may correspond to a pixel area (PA).

[0082] In FIGS. 5a and 5b, the silicon transistor (S-TFT) and oxide transistor (O-TFT) of the first light-emitting element (LD1) and the first pixel circuit (PC1, FIG. 4) are illustrated. In the equivalent circuit illustrated in FIG. 3b, the third and fourth transistors (T3, T4) may be oxide transistors (O-TFT), and the remaining transistors (T1, T2, T5, T6, T7) may be silicon transistors (S-TFT). Alternatively, the pixel circuit may include only one of the silicon transistors (S-TFT) and oxide transistors (O-TFT). Hereinafter, the silicon transistor (S-TFT) is described as the first transistor (T1) in FIG. 3b, and the oxide transistor (O-TFT) is described as the third transistor (T3) in FIG. 3b.

[0083] A barrier layer (BR) may be disposed on a base layer (110). The barrier layer (BR) can prevent foreign substances from entering from the outside. The barrier layer (BR) may include at least one inorganic layer. For example, the barrier layer (BR) may include a silicon oxide layer and / or a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in multiple numbers, and the silicon oxide layers and the silicon nitride layers may be stacked alternately.

[0084] A first shielding electrode (BMLa) may be disposed on a barrier layer (BR). The first shielding electrode (BMLa) may include a metal. The first shielding electrode (BMLa) may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium, which have good heat resistance. The first shielding electrode (BMLa) may receive a bias voltage. The first shielding electrode (BMLa) may also receive a first power supply voltage (ELVDD). The first shielding electrode (BMLa) may block electrical potentials caused by polarization phenomena from affecting the silicon transistor (S-TFT). The first shielding electrode (BMLa) may block external light from reaching the silicon transistor (S-TFT). Meanwhile, the first shielding electrode (BMLa) may be a floating electrode in a form isolated from other electrodes or wiring.

[0085] A buffer layer (BF) may be disposed on the barrier layer (BR). The buffer layer (BF) can prevent metal atoms or impurities from the base layer (110) from diffusing into the first semiconductor pattern (SP1) disposed on the upper side. The buffer layer (BF) may include at least one inorganic layer. The buffer layer (BF) may include a silicon oxide layer and / or a silicon nitride layer.

[0086] A first semiconductor pattern (SP1) may be disposed on a buffer layer (BF). The first semiconductor pattern (SP1) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. More specifically, the first semiconductor pattern (SP1) may include low-temperature polysilicon.

[0087] FIGS. 5A and 5B illustrate a portion of the first semiconductor pattern (SP1), and the first semiconductor pattern (SP1) may be further disposed in other regions. The first semiconductor pattern (SP1) may be arranged according to a specific rule across the pixel region (PA, FIG. 4). The electrical properties of the first semiconductor pattern (SP1) may differ depending on whether it is doped. The first semiconductor pattern (SP1) may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped portion doped with a P-type dopant, and an N-type transistor may include a doped portion doped with an N-type dopant. The second portion may be an undoped portion or a portion doped at a lower concentration compared to the first portion.

[0088] The conductivity of the first part is greater than the conductivity of the second part, and the first part can substantially function as an electrode or a signal line. The second part can substantially correspond to the channel region (or active region) of the transistor. That is, a part of the first semiconductor pattern (SP1) may be the channel of the transistor, another part may be the source or drain of the transistor, and yet another part may be a connecting electrode or a connecting signal line.

[0089] The source region (SE1), channel region (AC1, or active region), and drain region (DE1) of the silicon transistor (S-TFT) can be formed from the first semiconductor pattern (SP1). The source region (SE1) and the drain region (DE1) can extend in opposite directions from the channel region (AC1) on a cross-section.

[0090] A first insulating layer (10) may be disposed on a buffer layer (BF). The first insulating layer (10) may cover a first semiconductor pattern (SP1). The first insulating layer (10) may be an inorganic layer. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer (10) may be a single-layer silicon oxide layer. Each of the first insulating layer (10) and the second to fifth insulating layers (20, 30, 40, 50) described below may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto.

[0091] A gate (GT1) of a silicon transistor (S-TFT) may be disposed on the first insulating layer (10). The gate (GT1) may be part of a metal pattern. The gate (GT1) may overlap with the channel region (AC1). In the process of doping the first semiconductor pattern (SP1), the gate (GT1) may be a mask. The gate (GT1) may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), an alloy containing titanium, etc., which have good heat resistance, but is not limited thereto.

[0092] A first electrode (CE10) of a storage capacitor (Cst) is placed on the first insulating layer (10). Unlike what is illustrated, the first electrode (CE10) may have a shape that is integral with the gate (GT1).

[0093] A second insulating layer (20) is disposed on a first insulating layer (10), and the second insulating layer (20) can cover a gate (GT1). An upper electrode (UE) that overlaps with the gate (GT1) can be disposed on the second insulating layer (20). A second electrode (CE20) that overlaps with the first electrode (CE10) can be disposed on the second insulating layer (20). Unlike what is shown in FIGS. 5a and 5b, the second electrode (CE20) may have an integral shape with the upper electrode (UE). The second electrode (CE20) and the upper electrode (UE) may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), and an alloy containing titanium, which have good heat resistance.

[0094] A second shielding electrode (BMLb) may be disposed on the second insulating layer (20). The second shielding electrode (BMLb) may be disposed corresponding to the bottom of the oxide transistor (O-TFT). Unlike what is illustrated, the second shielding electrode (BMLb) may be omitted. The first shielding electrode (BMLa) may extend to the bottom of the oxide transistor (O-TFT) to replace the second shielding electrode (BMLb). If the oxide transistor (O-TFT) includes two gates, the second shielding electrode (BMLb) may be a gate disposed on the lower side of the oxide transistor (O-TFT).

[0095] A third insulating layer (30) may be disposed on the second insulating layer (20). A second semiconductor pattern (SP2) may be disposed on the upper side of the third insulating layer (30). The second semiconductor pattern (SP2) may include a channel region (AC2) of an oxide transistor (O-TFT). The second semiconductor pattern (SP2) may include an oxide semiconductor. The second semiconductor pattern (SP2) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx), or indium oxide (In2O3). Zinc oxide (ZnOx) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0096] The oxide semiconductor may include multiple regions distinguished by whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter, the reduced region) has greater conductivity than the region where it is not reduced (hereinafter, the non-reduced region). The reduced region substantially serves as the source / drain or signal line of the transistor. The non-reduced region substantially corresponds to the semiconductor region (or channel) of the transistor. That is, some regions of the second semiconductor pattern (SP2) may be the semiconductor region of the transistor, some regions may be the source / drain region of the transistor, and yet another part may be the signal transmission region.

[0097] A fourth insulating layer (40) may be disposed on the third insulating layer (30). The fourth insulating layer (40) may cover the second semiconductor pattern (SP2). A gate (GT2) of an oxide transistor (O-TFT) is disposed on the fourth insulating layer (40). In one embodiment, the oxide transistor (O-TFT) may include two gates, and the two gates may be a second shielding electrode (BMLb) on the second insulating layer (20) and a gate (GT2) disposed on the upper side of the fourth insulating layer (40). The second shielding electrode (BMLb) on the second insulating layer (20) and the gate (GT2) disposed on the upper side of the fourth insulating layer (40) may be electrically connected.

[0098] The gate (GT2) of the oxide transistor (O-TFT) may be part of a metal pattern. The gate (GT2) of the oxide transistor (O-TFT) overlaps with the channel region (AC2). The gate (GT2) may include molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy that has good heat resistance. The gate (GT2) may include a titanium layer and a molybdenum layer disposed above the titanium layer.

[0099] A fifth insulating layer (50) is disposed on the fourth insulating layer (40), and the fifth insulating layer (50) can cover the gate (GT2). Each of the first insulating layer (10) to the fifth insulating layer (50) may be an inorganic layer.

[0100] The buffer layer (BF) and the first to fifth insulating layers (10, 20, 30, 40, 50) can be defined as a laminated structure of inorganic materials. An opening (BA-OP) can be defined in the laminated structure of inorganic materials. The opening (BA-OP) can correspond to the boundary region (BA) described with reference to FIG. 4.

[0101] The inorganic layered structure can be divided into multiple islands corresponding to multiple pixels (PX1, PX2, PX3) shown in FIG. 4. Each of the multiple islands may include at least one pixel area and a boundary area surrounding the at least one pixel area. Since the multiple islands can disperse external impact, it is possible to prevent cracks from occurring in the inorganic layered structure due to external impact.

[0102] In one embodiment, the organic layer (ORP) may be placed to fill the opening (BA-OP). The organic layer (ORP) may have a closed-line shape on a plane. For example, the organic layer (ORP) may have a closed-line shape that surrounds the pixel area (PA).

[0103] Organic insulating layers (60, 70) may be disposed on the fifth insulating layer (50). A first organic insulating layer (60) may be disposed on the fifth insulating layer (50), and a second organic insulating layer (70) may be disposed on the upper side of the first organic insulating layer (60).

[0104] The first organic insulating layer (60) can eliminate a step difference, such as a fifth insulating layer (50) disposed below the first organic insulating layer (60), and form a flat upper surface. The first organic insulating layer (60) can cover the organic layer (ORP). The first organic insulating layer (60) can come into contact with the organic layer (ORP) and the fifth insulating layer (50). The first organic insulating layer (60) may overlap the entire surface with the base layer (110).

[0105] Each of the first organic insulating layer (60) and the second organic insulating layer (70) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0106] Although not shown, a plurality of conductive patterns may be disposed between the fifth insulating layer (50) and the first organic insulating layer (60). Additionally, a plurality of conductive patterns may be disposed between the first organic insulating layer (60) and the second organic insulating layer (70). The conductive patterns will be described in more detail later.

[0107] The first electrode (AE1) of the first light-emitting element (LD1) may be disposed on the upper side of the second organic insulating layer (70). The first light-emitting element (LD1) may include a first electrode (AE1), a light-emitting layer (EML1), and a second electrode (CE, or a common electrode). The second electrode of the first light-emitting element (LD1) and the second electrode of the third light-emitting element (LD3), as described with reference to FIG. 4, may have an integral shape with the second electrode (CE) of the first light-emitting element (LD1). That is, the second electrode (CE) may be provided in common to the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3).

[0108] The first electrode (AE1) may be a transparent electrode, a translucent electrode, or a reflective electrode. The first electrode (AE1) may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (AE1) may include a three-layer structure of ITO / Ag / ITO, but is not limited thereto.

[0109] A pixel defining film (PDL) may be disposed on the upper side of the second organic insulating layer (70). The pixel defining film (PDL) may have transparent properties or light-absorbing properties. For example, a light-absorbing pixel defining film (PDL) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or oxides thereof. The pixel defining film (PDL) may correspond to a shielding pattern having light-blocking properties.

[0110] The pixel defining layer (PDL) can cover a portion of the first electrode (AE1). For example, an opening (PDL-OP) that exposes a portion of the first electrode (AE1) can be defined in the pixel defining layer (PDL). The pixel defining layer (PDL) can increase the distance between the edge of the first electrode (AE1) and the second electrode (CE). Therefore, the pixel defining layer (PDL) can serve to prevent the occurrence of arcs, etc., at the edge of the first electrodes (AE1).

[0111] Although not shown, a hole transport layer may be disposed between the first electrode (AE1) and the light-emitting layer (EML1). Additionally, a hole injection layer may be disposed between the first electrode (AE1) and the hole transport layer. An electron transport layer may be disposed between the light-emitting layer (EML1) and the second electrode (CE). An electron injection layer may be disposed between the electron transport layer and the second electrode (CE). Each of the hole transport layer, hole injection layer, electron transport layer, and electron injection layer comprises a plurality of pixel rows (PLX i , PLX i-1 , can be commonly formed in Fig. 4).

[0112] The encapsulation layer (140) may be disposed on the upper side of the light-emitting element layer (130). The encapsulation layer (140) may include sequentially stacked inorganic encapsulation layers (141), organic encapsulation layers (142), and inorganic encapsulation layers (143), but the layers constituting the encapsulation layer (140) are not limited thereto.

[0113] Inorganic encapsulation layers (141, 143) can protect the light-emitting element layer (130) from moisture and oxygen, and organic encapsulation layer (142) can protect the light-emitting element layer (130) from foreign substances such as dust particles. The inorganic encapsulation layers (141, 143) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic encapsulation layer (142) may include an acrylic-based organic layer, but is not limited thereto.

[0114] Unlike FIG. 5a, FIG. 5b illustrates an organic layer (ORP-a) comprising a first portion (OA1) and a second portion (OA2). In one embodiment, the organic layer (ORP, ORP-a) may include a first portion (OA1) that fills an opening (BA-OP) corresponding to a boundary region (BA). Additionally, the organic layer (ORP-a) may include a second portion (OA2) that extends from the first portion (OA1) and overlaps the pixel region (PA) and the boundary region (BA). FIG. 5a illustrates an organic layer (ORP) that includes the first portion (OA1) and does not include the second portion (OA2).

[0115] The second portion (OA2) of the organic layer (ORP-a) may be positioned above the fifth insulating layer (50), which is the uppermost inorganic insulating layer included in the circuit layer (120). The second portion (OA2) may have an integral shape with the first portion (OA1). The second portion (OA2) may overlap the entire surface with the base layer (110). The second portion (OA2) may eliminate the step difference between the insulating layers (10 to 50) positioned below and form a flat upper surface.

[0116] FIG. 6 is a plan view of a pixel area (PA) according to one embodiment. FIG. 7a to 7h are plan views illustrating the configurations arranged in the pixel area (PA) in the order in which they are stacked.

[0117] Referring to FIG. 7a, a first conductive layer (CL1) may be disposed on a barrier layer (BR, FIG. 5a). The first conductive layer (CL1) may include a first shielding electrode (BMLa). The first shielding electrode (BMLa) may include a portion extending in a first direction (DR1) and a portion extending in a second direction (DR2). The portion of the first shielding electrode (BMLa) extending in the first direction (DR1) may overlap with a second boundary region (BA2), and the portion extending in the second direction (DR2) may overlap with a first boundary region (BA1).

[0118] Referring to FIG. 7b, a first semiconductor pattern (SP1) can be disposed on a barrier layer (BR, FIG. 5a). Two first semiconductor patterns (SP1) are illustrated exemplarily in FIG. 7b.

[0119] The first semiconductor pattern (SP1) may include a plurality of regions with different doping concentrations. The first semiconductor pattern (SP1) may include source regions (S1, S2, S5, S6, S7), channel regions (A1, A2, A5, A6, A7), and drain regions (D1, D2, D5, D6, D7) of the first, second, fifth, sixth, and seventh transistors (T1, T2, T5, T6, T7). The first semiconductor pattern (SP1) may further include a signal transmission region (STA). The source regions (S1, S2, S5, S6, S7) and drain regions (D1, D2, D5, D6, D7) may correspond to the source (S1, S2, S5, S6, S7) and drain (D1, D2, D5, D6, D7) described with reference to FIG. 3b, respectively.

[0120] In FIG. 7b, for convenience of explanation, the source regions (S1, S2, S5, S6, S7) and drain regions (D1, D2, D5, D6, D7) of adjacent semiconductor regions are shown separately. Additionally, a signal transmission region (STA) is shown, but is not limited thereto. Practically, the signal transmission region (STA) is a region having the same doping concentration as the source regions (S1, S2, S5, S6, S7) or drain regions (D1, D2, D5, D6, D7), and may not be distinguished from the source regions (S1, S2, S5, S6, S7) or drain regions (D1, D2, D5, D6, D7).

[0121] Referring to FIG. 7c, a second conductive layer (CL2) may be disposed on the first insulating layer (10, FIG. 5a). The second conductive layer (CL2) may include a plurality of conductive patterns.

[0122] The second conductive layer (CL2) may include the gate (G1) of the first transistor (T1), the i-th scanning line (SLi) of the first group, and the i-th light-emitting line (ELi). The i-th scanning line (SLi) and the i-th light-emitting line (ELi) of the first group may be extended in a first direction (DR1). The i-th scanning line (SLi) and the i-th light-emitting line (ELi) of the first group extended in the first direction (DR1) may overlap with a boundary region (BA) and a pixel region (PA). More specifically, the i-th scanning line (SLi) and the i-th light-emitting line (ELi) of the first group extended in the first direction (DR1) may overlap with a second boundary region (BA2). The i-th scanning line (SLi) and the i-th light-emitting line (ELi) of the first group may be extended to an adjacent pixel region.

[0123] For example, the i-th scanning line (SLi) and the i-th emitting line (ELi) of the first group may each have a multilayer structure. Each of the i-th scanning line (SLi) and the i-th emitting line (ELi) of the first group may include an aluminum layer and a titanium layer disposed above the aluminum layer.

[0124] A portion of the i-th scan line (SLi) of the first group superimposed on the first semiconductor pattern (SP1) may be the gate (G2) of the second transistor (T2), and another portion of the i-th scan line (SLi) of the first group superimposed on the first semiconductor pattern (SP1) may be the gate (G7) of the seventh transistor (T7). However, the seventh transistor (T7) is the i-1th pixel row (PLX i-1 The light-emitting element of , Fig. 4) can be initialized. The i-th pixel row (PLX i The light-emitting element of Fig. 4) can be initialized by a seventh transistor (T7) placed in the i+1th pixel row not shown.

[0125] A portion of the i-th light-emitting line (ELi) overlapping the first semiconductor pattern (SP1) may be the gate (G5) of the fifth transistor (T5), and another portion overlapping the first semiconductor pattern (SP1) may be the gate (G6) of the sixth transistor (T6).

[0126] After forming a conductive pattern of the second conductive layer (CL2), a doping process can be performed on the first semiconductor pattern (SP1, FIG. 7b). Through the doping process, the source regions (S1, S2, S5, S6, S7), channel regions (A1, A2, A5, A6, A7), and drain regions (D1, D2, D5, D6, D7) shown in FIG. 7b can be distinguished.

[0127] Referring to FIG. 7d, a third conductive layer (CL3) may be disposed on the second insulating layer (20, FIG. 5a). The third conductive layer (CL3) may include an upper electrode (UE), the i-th scan line (GLi) of the second group, and the i-th scan line (HLi) of the third group.

[0128] An opening (UE-OP) may be defined in the upper electrode (UE). The i-th scan line (GLi) of the second group and the i-th scan line (HLi) of the third group may extend in the first direction (DR1) and overlap with the boundary region (BA) and the pixel region (PA). More specifically, the i-th scan line (GLi) of the second group and the i-th scan line (HLi) of the third group may extend in the first direction (DR1) and overlap with the second boundary region (BA2). The i-th scan line (GLi) of the second group and the i-th scan line (HLi) of the third group may extend into an adjacent pixel region.

[0129] For example, the i-th injection line (GLi) of the second group and the i-th injection line (HLi) of the third group may each have a multilayer structure. The i-th injection line (GLi) of the second group and the i-th injection line (HLi) of the third group may each include an aluminum layer and a titanium layer disposed above the aluminum layer.

[0130] A portion of the i-th scan line (GLi) of the second group may be the 3-1 gate (G3-1) of the third transistor (T3), and a portion of the i-th scan line (HLi) of the third group may be the 4-1 gate (G4-1) of the fourth transistor (T4). Additionally, the 3-1 gate (G3-1) and the 4-1 gate (G4-1) may be replaced with the second shielding electrode (BMLb, FIG. 5a).

[0131] Referring to FIG. 7e, a second semiconductor pattern (SP2) may be disposed on the upper side of the third insulating layer (30, FIG. 5a). In FIG. 7e, one second semiconductor pattern (SP2) is illustrated as an example.

[0132] The second semiconductor pattern (SP2) may include a plurality of regions distinguished by whether the metal oxide is reduced. The second semiconductor pattern (SP2) may include source regions (S3, S4), channel regions (A3, A4), and drain regions (D3, D4) of the third and fourth transistors (T3, T4).

[0133] Referring to FIG. 7f, a fourth conductive layer (CL4) may be disposed on a fourth insulating layer (40, FIG. 5a). The fourth conductive layer (CL4) may include a first conductive pattern (CP1) and a second conductive pattern (CP2). The first conductive pattern (CP1) and the second conductive pattern (CP2) may include a gate (GT2) of an oxide transistor (O-TFT, FIG. 5a). The first conductive pattern (CP1) may include an upper gate of a third transistor (T3), and the second conductive pattern (CP2) may include an upper gate of a fourth transistor. More specifically, the first conductive pattern (CP1) may include a gate (T3-2) that overlaps the channel region (A3) of the third transistor (T3). The second conductive pattern (CP2) may include a gate (T4-2) that overlaps the channel region (A4) of the fourth transistor (T4). After forming the conductive pattern of the fourth conductive layer (CL4), a doping process (or reduction process) for the second semiconductor pattern (SP2) can be performed.

[0134] Referring to FIG. 7g, a fifth conductive layer (CL5) may be disposed on the fifth insulating layer (50, FIG. 5a). The fifth conductive layer (CL5) may include a plurality of conductive patterns.

[0135] Before forming the fifth conductive layer (CL5), an opening (BA-OP) may be formed to correspond to the boundary region (BA) shown in FIGS. 4 and 5a, and an organic layer (ORP) that fills the opening (BA-OP) may be formed. The opening (BA-OP) may be formed by etching the buffer layer (BF) and the insulating layers (10 to 50). Meanwhile, as shown in FIG. 5b, if the organic layer (ORP-a) includes a first part (OA1) and a second part (OA2), the first part (OA1) and the second part (OA2) may be formed by the same process. However, the embodiment is not limited thereto, and the first part (OA1) and the second part (OA2) may be formed by separate processes.

[0136] The fifth conductive layer (CL5) may include a second voltage line (VL1) and a third voltage line (VL2). Each of the second voltage line (VL1) and the third voltage line (VL2) may extend in a first direction (DR1) and overlap with a boundary region (BA) and a pixel region (PA). Additionally, the fifth conductive layer (CL5) may include a plurality of connecting electrodes and a plurality of contact holes.

[0137] The first connection electrode (CNE1) can connect the drain region (D1, FIG. 7b) of the first transistor (T1) and the drain region (D3, FIG. 7e) of the third transistor (T3) through the first contact hole (CH1) and the second contact hole (CH2). The second connection electrode (CNE2) can connect the gate (G1, FIG. 7b) of the first transistor (T1) and the source region (S3, FIG. 7e) of the third transistor (T3) through the third contact hole (CH3) and the fourth contact hole (CH4). The third connection electrode (CNE3) can connect the source region (S5, FIG. 7b) of the fifth transistor (T5) and the upper electrode (UE, see FIG. 7d) through the fifth contact hole (CH5) and the sixth contact hole (CH6).

[0138] The fourth connection electrode (CNE4) can be connected to the source region (S7, FIG. 7b) of the seventh transistor (T7) through the seventh contact hole (CH7). The fourth connection electrode (CNE4) is connected to the i-1th pixel row (PLX i-1 It can be electrically connected to the anode of an unillustrated light-emitting diode (LD). The fifth connection electrode (CNE5) can be connected to the drain region (D6, FIG. 7b) of the sixth transistor (T6) through the eighth contact hole (CH8). The fifth connection electrode (CNE5) can be connected to the source region of the seventh transistor of the i+1th pixel row, which is not illustrated.

[0139] The sixth connecting electrode (CNE6) can be connected to the source region (S2, FIG. 7b) of the second transistor (T2) through the ninth contact hole (CH9). The second voltage line (VL1) can be connected to the source region (S4, FIG. 7e) of the fourth transistor (T4) through the tenth contact hole (CH10). The third voltage line (VL3) can be connected to the drain region (D7, FIG. 7b) of the seventh transistor (T7) through the eleventh contact hole (CH11). The tenth contact hole (CH10) and the eleventh contact hole (CH11) can penetrate the fifth insulating layer (50, FIG. 5a).

[0140] The seventh connection electrode (CNE7) can be connected to the first conductivity pattern (CP1) through the twelfth contact hole (CH12). More specifically, the seventh connection electrode (CNE7) can be connected to a gate (T3-2) that overlaps the channel region (A3) of the third transistor (T3) formed from the first conductivity pattern (CP1) through the twelfth contact hole (CH12). Additionally, the seventh connection electrode (CNE7) can be connected to the i-th scan line (GLi) of the second group through the thirteenth contact hole (CH13).

[0141] The eighth connection electrode (CNE8) can be connected to the second conductivity pattern (CP2) through the 14th contact hole (CH14). More specifically, the eighth connection electrode (CNE8) can be connected to a gate (T4-2) that overlaps the channel region (A4) of the fourth transistor (T4) formed from the second conductivity pattern (CP2) through the 14th contact hole (CH14). Additionally, the eighth connection electrode (CNE8) can be connected to the i-th scan line (HLi) of the third group through the 15th contact hole (CH15).

[0142] Referring to FIG. 7h, a sixth conductive layer (CL6) may be disposed on a first organic insulating layer (60, FIG. 5a). The sixth conductive layer (CL6) may include a plurality of conductive patterns. The sixth conductive layer (CL6) may include a j-th data line (DLj), a first voltage line (PL), and a ninth connecting electrode (CNE-A). The j-th data line (DLj) and the first voltage line (PL) may extend in a second direction (DR2). The j-th data line (DLj) and the first voltage line (PL) may overlap with a first boundary region (BA1) and a pixel region (PA).

[0143] The j-th data line (DLj) can be connected to the 6th connecting electrode (CNE6, FIG. 7g) through the 16th contact hole (CH16). The 1st voltage line (PL) can be connected to the 3rd connecting electrode (CNE3, FIG. 7g) through the 17th contact hole (CH17). The 9th connecting electrode (CNE-A) can be connected to the 5th connecting electrode (CNE5, FIG. 7g) through the 18th contact hole (CH18). The 16th contact hole (CH16) to the 18th contact hole (CH18) can penetrate the 1st organic insulating layer (60, FIG. 5a). Although not shown, a first electrode (AE1, FIG. 5a) is disposed on the upper side of the second organic insulating layer (70, FIG. 5a) and can be connected to a ninth connecting electrode (CNE-A) through a contact hole penetrating the second organic insulating layer (70, FIG. 5a).

[0144] FIG. 8a is a cross-sectional view showing a portion corresponding to line I-I' of FIG. 6. In one embodiment, a first signal line (SLE1) may be positioned above the first insulating layer (10). In FIG. 8a, one of the two first signal lines (SLE1) may be a light-emitting line (ELi, FIG. 6), and the other may be the i-th scanning line (SLi, FIG. 6) of the first group. The first signal line (SLE1) may be covered by a second insulating layer (20). The upper portion of the first signal line (SLE1) may be in contact with the second insulating layer (20).

[0145] The second signal line (SLE2) may be positioned above the second insulating layer (20). In FIG. 8a, one of the two second signal lines (SLE2) may be the i-th scan line (GLi, FIG. 6) of the second group, and the other may be the i-th scan line (HLi, FIG. 6) of the third group. The third insulating layer (30) may cover the second signal line (SLE2). The upper portion of the second signal line (SLE2) may be in contact with the third insulating layer (30).

[0146] Referring to FIG. 8a, the opening (BA-OP) may include a first region (A10) having a first depth (DT1) and a second region (A20) having a second depth (DT2). The first depth (DT1) of the first region (A10) may be smaller than the second depth (DT2) of the second region (A20). The first region (A10) may be a region that overlaps with a first signal line (SLE1). More specifically, the first region (A10) may be a region that overlaps with a buffer layer (BF), a first insulating layer (10) disposed above the buffer layer (BF), and a first signal line (SLE1) disposed above the first insulating layer (10). The first region (A10) may penetrate the second insulating layer (20) and the third insulating layer (30) above the first signal line (SLE1). Additionally, the first region (A10) can penetrate the fourth insulating layer (40) and the fifth insulating layer (50) positioned above the third insulating layer (30).

[0147] The second region (A20) may be a region that does not overlap with the first signal line (SLE1) and the second signal line (SLE2). In the second region (A20), the barrier layer (BR) may be exposed, and the organic layer (ORP) and the barrier layer (BR) may come into contact in the second region (A20). The second region (A20) may penetrate the buffer layer (BF) and the first to third insulating layers (10, 20, 30). Additionally, the second region (A20) may penetrate the fourth insulating layer (40) and the fifth insulating layer (50). The third insulating layer (30) and the fourth insulating layer (40) and the fifth insulating layer (50) positioned above the third insulating layer (30) may have openings formed at substantially the same depth.

[0148] An organic layer (ORP) placed to fill the opening (BA-OP) may come into contact with a first signal line (SLE1). More specifically, the lower surface of the organic layer (ORP) in the first region (A10) may come into contact with the first signal line (SLE1). In one embodiment, the display panel (100) may include a plurality of insulating layers (BF, 10 to 50), and the plurality of insulating layers (BF, 10 to 50) may have an opening (BA-OP) defined therein. The organic layer (ORP) may fill the opening (BA-OP) including the first region (A10) and the second region (A20).

[0149] The first insulating layer (10) may include a first insulating portion (P10) that overlaps the boundary region (BA). In the first insulating layer (10), a first opening (P10-1) and a second opening (P10-2) may be defined with the first insulating portion (P10) in between. The second insulating layer (20) may include a second insulating portion (P20) that overlaps the boundary region (BA). In the second insulating layer (20), a third opening (P20-3) and a fourth opening (P20-4) may be defined with the second insulating portion (P20) in between.

[0150] The first to fourth openings (P10-1, P10-2, P20-3, P20-4) may constitute part of the opening (BA-OP). The first opening (P10-1) and the second opening (P10-2) may constitute a second region (A20) of the opening (BA-OP). The third opening (P20-3) and the fourth opening (P20-3) may constitute a second region (A20) of the opening (BA-OP). That is, the opening (BA-OP) filled with an organic layer (ORP) may be formed from the openings (P10-1, P10-2, P20-3, P20-4) of the insulating layers (10, 20, 30, 40, 50). Openings (P10-1, P10-2, P20-3, P20-4) of insulating layers (10, 20, 30, 40, 50) can be combined to define an opening (BA-OP) filled with an organic layer (ORP).

[0151] In one embodiment, the opening (BA-OP) may include a third region (A30) that overlaps with the second signal line (SLE2). The third region (A30) has a third depth (DT3), and the third depth (DT3) may be smaller than the first depth (DT1). The third region (A30) may be spaced apart from the first region (A10) with the second region (A20) in between. An organic layer (ORP) placed and filling the opening (BA-OP) may come into contact with the second signal line (SLE2). More specifically, the lower surface of the organic layer (ORP) in the third region (A30) may come into contact with the second signal line (SLE2).

[0152] As the first region (A10), second region (A20), and third region (A30) of the opening (BA-OP) have different depths (DT1, DT2, DT3), the organic layer (ORP) filling the opening (BA-OP) may have different thicknesses. That is, on a cross-section parallel to the thickness direction, the organic layer (ORP) may not have a uniform thickness.

[0153] In a display panel (100) of one embodiment, an organic layer (ORP) may fill an opening (BA-OP). The opening (BA-OP) is defined to correspond to a boundary region (BA) and may include a first region (A10) having a first depth (DT1) that overlaps with a first signal line (SLE1) and a second region (A20) having a second depth (DT2) greater than the first depth (DT1). The first signal line (SLE1) that overlaps with the opening (BA-OP) may overlap with the boundary region (BA) and the pixel region (PA) and may extend in one direction (e.g., the first direction). Accordingly, the signal line may be integrally formed in adjacent pixel regions (PA). That is, since the display panel (100) does not divide the data line (DLj) and the signal line (SLE1, SEL2) for each pixel region (PA), an additional metal layer for connecting the divided signal lines may be omitted. Therefore, the time and cost of the process for manufacturing the display panel (100) can be reduced. The display panel (100) according to one embodiment may exhibit characteristics of improved manufacturing efficiency.

[0154] FIG. 8b is a cross-sectional view showing the portion corresponding to line II-II' of FIG. 6. Referring to FIG. 8b, the j-th data line (DLj) disposed on the upper side of the second organic insulating layer (70) can be electrically connected to the second transistor (T2) disposed on the upper side of the first insulating layer (10). As previously described, the j-th data line (DLj) can be connected to the source (S2) of the second transistor (T2) through a contact hole. More specifically, the j-th data line (DLj) can be connected to the sixth connecting electrode (CNE6) through the 16th contact hole (CH16), and the sixth connecting electrode (CNE6) can be connected to the source (S2) of the second transistor (T2) through the 9th contact hole (CH9). The 16th contact hole (CH16) can penetrate the first organic insulating layer (60). The sixth connecting electrode (CNE6) is positioned above the fifth insulating layer (50), and the ninth contact hole (CH9) can penetrate the first to fifth insulating layers (10 to 50). Although not shown, the first shielding electrode (BMLa, FIG. 5a) may be positioned below the second transistor (T2).

[0155] Unlike FIG. 8b, FIG. 8c is illustrated as having a second portion (OA2) of the organic layer (ORP-a) positioned above the fifth insulating layer (50). Organic insulating layers (60, 70) may be positioned above the second portion (OA2). The j-th data line (DLj) may be connected to the 10th connecting electrode (CNE-O) through the 16th contact hole (CH16), and the 10th connecting electrode (CNE-O) may be electrically connected to the source (S2) of the second transistor (T2) through the 20th contact hole (CH20). The 16th contact hole (CH16) penetrates the second portion (OA2), and the 20th contact hole (CH20) may penetrate the second portion (OA2) and the first to fifth insulating layers (10 to 50).

[0156] FIGS. 9A and 9B are enlarged plan views of a display panel (100) according to one embodiment. FIGS. 9A and 9B show that, unlike FIG. 4, one or four light-emitting elements are arranged in one pixel area (PA).

[0157] As illustrated in FIG. 9a, one of the first color pixel (PX1), the second color pixel (PX2), and the third color pixel (PX3) is placed in each pixel region (PA), and each pixel region (PA) can be surrounded by a boundary region (BA). That is, FIG. 9a illustrates that one pixel is placed in one pixel region (PA). Also, unlike FIG. 4, FIG. 9a illustrates that the first color pixel (PX1) and the second color pixel (PX2) are separated by a second boundary region (BA2).

[0158] As illustrated in FIG. 9b, one first color pixel (PX1), one third color pixel (PX3), and two second color pixels (PX2) may be placed in one pixel area (PA). Each pixel area (PA) may be enclosed by a boundary area (BA). That is, FIG. 9b illustrates that four pixels are placed in one pixel area (PA). Also, unlike FIG. 4, in FIG. 9b, the i-th pixel row (PLX i ) and the i-1th pixel row (PLX i-1 It was illustrated that the pixels of ) constitute a single pixel area (PA).

[0159] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0160] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0163] 100: Display panel BA: Boundary area PA: Pixel area 110: Base layer PC: Pixel circuit 10: First insulating layer 20: Second insulating layer 30: Third insulating layer BA-OP: Opening SLE1: First signal line SLE2: Second signal line OA1: First part OA2: Part 2 ORP: Organic layer A10: Area 1 A20: Area 2 A30: Third Zone

Claims

Claim 1 A display panel comprising: a base layer including a plurality of pixel regions and a boundary region disposed between the pixel regions; a pixel circuit superimposed on any one of the pixel regions; a plurality of insulating layers including at least a first insulating layer and having an opening defined corresponding to the boundary region; a first signal line disposed above the first insulating layer and superimposed on the boundary region and any one of the pixel regions; an organic layer including a first portion filling the opening; and a light-emitting element disposed above the insulating layers and electrically connected to the pixel circuit; wherein the opening is a first region superimposed on the first signal line and having a first depth; and a second region having a second depth greater than the first depth. Claim 2 In claim 1, the insulating layers further include a second insulating layer disposed above the first insulating layer, and the display panel further includes a second signal line disposed above the second insulating layer and overlapping the boundary region and any one pixel region, and the opening further includes a third region that overlaps the second signal line and has a third depth smaller than the first depth. Claim 3 In claim 2, the second region is a display panel that does not overlap with the first signal line and the second signal line. Claim 4 In claim 2, each of the first signal line and the second signal line extends in a first direction, and within a second direction intersecting the first direction, the first area and the third area are spaced apart with the second area in between, forming a display panel. Claim 5 In claim 2, within any one of the pixel areas, the second insulating layer is a display panel covering the first signal line. Claim 6 In claim 2, within the boundary region, the lower surface of the organic layer is a display panel in contact with the first signal line and the second signal line. Claim 7 A display panel according to claim 1, further comprising a barrier layer disposed above the base layer, wherein the opening exposes the barrier layer within the second region. Claim 8 In claim 7, in the second region, the barrier layer is a display panel in contact with the organic layer. Claim 9 In claim 1, the pixel circuit comprises: a first transistor including a first source region, a first drain region, a first channel region, and a first gate; and a second transistor including a second source region, a second drain region, a second channel region disposed on a layer different from the first channel region, and a second gate disposed on a layer different from the first gate; and the first signal line is a display panel disposed on the same layer as the first gate or the second gate. Claim 10 In claim 9, the display panel further comprises a second transistor electrically connected to the second gate and a third gate disposed on a different layer from the first gate and the second gate. Claim 11 A display panel according to claim 9, wherein the first transistor is a silicon transistor and the second transistor is an oxide transistor. Claim 12 In claim 1, the boundary area includes a first boundary area extended in a first direction and a second boundary area extended in a second direction intersecting the first direction, and the first signal line is a display panel extending in the first direction. Claim 13 In claim 1, the insulating layers further comprise a buffer layer disposed below the first insulating layer, a second insulating layer disposed above the first insulating layer, and a third insulating layer disposed above the second insulating layer, wherein the first region penetrates the second insulating layer and the third insulating layer, and the second region penetrates the buffer layer and the first insulating layer to the third insulating layer, forming a display panel. Claim 14 In claim 1, the first insulating layer includes a first insulating portion that overlaps the boundary region, and the first insulating layer has a first opening and a second opening defined with the first insulating portion in between, and the first opening and the second opening constitute a part of the openings of the insulating layers. Claim 15 In claim 14, the insulating layers further comprise a second insulating layer disposed above the first insulating layer, the second insulating layer comprises a second insulating portion that overlaps the boundary region, and the second insulating layer has a third opening and a fourth opening defined with the second insulating portion in between, and the third opening and the fourth opening constitute a part of the openings of the insulating layers, a display panel. Claim 16 A display panel according to claim 1, further comprising: an organic insulating layer disposed above the insulating layer of the uppermost layer among the first portion and the insulating layers, and in contact with the first portion and the insulating layer of the uppermost layer; and a data line disposed above the organic insulating layer. Claim 17 In claim 16, the data line is a display panel connected to the pixel circuit through a contact hole penetrating the organic layer. Claim 18 A display panel according to claim 1, wherein the organic layer further comprises a second portion extending from the first portion and overlapping with the boundary region and any one of the pixel regions. Claim 19 In claim 18, a display panel further comprising a data line disposed on the upper side of the second part, wherein the data line is connected to the pixel circuit through a contact hole penetrating the second part. Claim 20 In claim 1, the boundary region surrounds each of the pixel regions on a plane, and the display panel has one, two, or four light-emitting elements disposed in each of the pixel regions.

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