Semiconductor memory device

Abstract

The present invention includes a semiconductor memory device comprising a semiconductor substrate including a first circuit group and a second circuit group spaced apart from each other, a memory cell array superimposed on the semiconductor substrate, and a vertical conductive line that crosses the memory cell array and is commonly connected to the first circuit group and the second circuit group.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device. Background Technology

[0002] A semiconductor memory device may include a memory cell array and a peripheral circuit structure. The memory cell array may include a plurality of memory cells capable of storing data. The peripheral circuit structure may be configured to control various operations of the memory cells.

[0003] A memory cell array of a three-dimensional semiconductor memory device may include a plurality of memory cells arranged in three dimensions. Accordingly, the area occupied by memory cells per unit area of ​​the substrate can be reduced, and the integration density of the semiconductor memory device can be improved. To improve efficiency per unit area of ​​the substrate, a peripheral circuit structure can be superimposed on the memory cell array. In this case, wiring for electrically connecting the memory cell array to the peripheral circuit structure may be a factor that limits the miniaturization of the semiconductor memory device. The problem to be solved

[0005] An embodiment of the present invention provides a semiconductor memory device capable of reducing the size of the semiconductor memory device. means of solving the problem

[0007] A semiconductor memory device according to an embodiment of the present invention may include a plurality of conductive patterns stacked spaced apart from each other, a first gate stack and a second gate stack adjacent to each other; a vertical conductive line disposed between the first gate stack and the second gate stack; and a semiconductor substrate extended to overlap the first gate stack, the second gate stack, and the vertical conductive line. The semiconductor substrate may include a plurality of pass transistors connected to at least one of the plurality of conductive patterns among the first gate stack and the second gate stack. The vertical conductive line may be commonly connected to a plurality of gate electrodes of the plurality of pass transistors.

[0009] A semiconductor memory device according to an embodiment of the present invention may include: a semiconductor substrate including a peripheral circuit structure; a vertical conductive line disposed on the semiconductor substrate, extending in a first direction in a plane parallel to the semiconductor substrate and connected to the peripheral circuit structure; a vertical insulating film extending along the sidewall of the vertical conductive line; and a first gate stack and a second gate stack adjacent to each other in a second direction intersecting the vertical conductive line. The vertical conductive line and the vertical insulating film are disposed between the first gate stack and the second gate stack, and each of the first gate stack and the second gate stack may include a plurality of interlayer insulating films and a plurality of conductive patterns alternately stacked on the semiconductor substrate.

[0011] A semiconductor memory device according to an embodiment of the present invention may include: a semiconductor substrate comprising a first circuit group and a second circuit group spaced apart from each other; a memory cell array superimposed on the semiconductor substrate; a vertical conductive line superimposed on the semiconductor substrate and traversing the memory cell array; a plurality of first conductive bonding patterns disposed at a level between the semiconductor substrate and the memory cell array and connected to the first circuit group and the second circuit group, respectively; and a plurality of second conductive bonding patterns disposed at a level between the plurality of first conductive bonding patterns and the memory cell array, connected to the vertical conductive line and the memory cell array, and bonded to the plurality of first conductive bonding patterns. The vertical conductive line may be commonly connected to the first circuit group and the second circuit group via some of the plurality of first conductive bonding patterns and some of the plurality of second conductive bonding patterns. Effects of the invention

[0013] Embodiments of the present technology can construct a peripheral circuit structure through vertical conductive lines disposed in the space between gate stacks of a memory cell array and interconnect spaced-apart circuit groups. Accordingly, embodiments of the present technology can reduce the area of ​​the semiconductor substrate occupied by the peripheral circuit structure and the wiring connected to the peripheral circuit structure, thereby reducing the size of the semiconductor memory device. Brief explanation of the drawing

[0015] FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention. FIGS. 2A and 2B show circuit diagrams of a switching circuit group and a memory cell array according to embodiments of the present invention. FIG. 3 is a block diagram showing a multi-plane structure according to one embodiment of the present invention. FIG. 4 is a perspective view schematically showing a semiconductor memory device according to one embodiment of the present invention. FIGS. 5a to 5d are cross-sectional views showing exemplary configurations of a semiconductor memory device illustrated in FIG. 4. FIGS. 6a, FIGS. 6b, FIGS. 6c, FIGS. 6d, FIGS. 7a, FIGS. 7b, FIGS. 7c, FIGS. 7d, FIGS. 8a, FIGS. 8b, FIGS. 9a, FIGS. 9b, FIGS. 9c, FIGS. 9d, FIGS. 10a, FIGS. 10b, FIGS. 10c, FIGS. 10d, FIGS. 11a, FIGS. 11b, FIGS. 11c, FIGS. 11d, FIGS. 12a, FIGS. 12b, FIGS. 12c, and FIGS. 12d are cross-sectional views illustrating exemplary embodiments of a method for manufacturing a semiconductor memory device illustrated in FIGS. 5a, FIGS. 5b, FIGS. 5c, and FIGS. 5d, in order of process steps. FIG. 13 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention. FIG. 14 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention. Specific details for implementing the invention

[0016] The specific structural or functional descriptions disclosed below are illustrative of embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention are not to be interpreted as being limited to the embodiments described below, but can be modified in various ways and replaced with other equivalent embodiments.

[0017] In the following description, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another, and the order or number of components is not limited by said terms.

[0019] FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention.

[0020] Referring to FIG. 1, a semiconductor memory device may include a memory cell array (10) and a peripheral circuit structure (20[1], 20[2], 30, 40, 50, 60, 70). The peripheral circuit structure may include a plurality of circuit groups (20[1], 20[2], 30, 40, 50, 60, 70).

[0021] A plurality of circuit groups (20[1], 20[2], 30, 40, 50, 60, 70) of the peripheral circuit structure may include a first circuit group (e.g., 20[1]) and a second circuit group (e.g., 20[2]) disposed on both sides of the memory cell array (10), and a third circuit group (e.g., 30) configured to control the first circuit group and the second circuit group in common. Each of the first circuit group and the second circuit group may be connected to the third circuit group through a vertical conductive line (e.g., BSEL[A] to BSEL[D]) disposed across the memory cell array (10). A plurality of transistors constituting the third circuit group (e.g., 30) may not be distributed adjacent to each of the first circuit group (e.g., 20[1]) and the second circuit group (e.g., 20[2]), but may be disposed in a partial area. According to such an embodiment of the present invention, the area occupied by the third circuit group and the wiring connected thereto can be reduced compared to the case where a plurality of transistors of the third circuit group are distributed in mutually spaced regions. Therefore, the structure according to the embodiment of the present invention may be advantageous for reducing the size of a semiconductor memory device.

[0022] A plurality of circuit groups of the peripheral circuit structure may include a first switching circuit group (20[1]), a second switching circuit group (20[2]), a row decoder (30), a voltage generation circuit (40), a control circuit (50), a page buffer (60), and a column decoder (70). In one embodiment, the first switching circuit group (20[1]) may be the first circuit group described above, the second circuit group (20[2]) may be the second circuit group described above, and the row decoder (30) may be the third circuit group described above. Hereinafter, drawings are shown and described in detail based on embodiments in which the first circuit group, the second circuit group, and the third circuit group correspond to the first switching circuit group (20[1]), the second switching circuit group (20[2]), and the row decoder (30), respectively. However, the embodiments of the present invention are not limited thereto.

[0023] A memory cell array (10) may include a plurality of memory blocks (10A to 10D). Each of the memory blocks (10A to 10D) may include a plurality of memory cell strings. Each memory cell string may include a plurality of memory cells in which data is stored. Each memory cell may store single-bit or multi-bit data of two or more bits.

[0024] A memory cell array (10) can be connected to a first switching circuit group (20[1]) through a plurality of first local lines (LGA1, LGB1, LGC1, LGD1) and can be connected to a second switching circuit group (20[2]) through a plurality of second local lines (LGA2, LGB2, LGC2, LGD2). The plurality of first local lines (LGA1, LGB1, LGC1, LGD1) and the plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may be composed of conductive patterns stacked spaced apart on the first switching circuit group (20[1]) and the second switching circuit group (20[2]). The memory cell array (10) can be connected to a page buffer (60) through a plurality of bit lines (BL).

[0025] The control circuit (50) can output an operation signal (OP_S), a row address (RADD), a page buffer control signal (PB_S), and a column address (CADD) in response to a command (CMD) and an address (ADD).

[0026] The voltage generation circuit (40) can output operating voltages required for a program operation, a verify operation, a read operation, or an erase operation to a plurality of first global lines (GG1) and a plurality of second global lines (GG2) in response to an operation signal (OP_S) of the control circuit (50).

[0027] The row decoder (30) can output a plurality of block selection signals (BSEL[A] to BSEL[D]) for selecting at least one memory block among a plurality of memory blocks (10A to 10D) in response to a row address (RADD) of the control circuit (50).

[0028] The column decoder (70) can transmit data (DATA) input from an input / output circuit (not shown) to the page buffer (60) in response to a column address (CADD), or transmit data (DATA) stored in the page buffer (60) to the input / output circuit (not shown). The column decoder (70) can exchange data (DATA) with the page buffer (60).

[0029] The page buffer (60) can temporarily store data (DATA) received through the bit line (BL) in response to the page buffer control signal (PB_S). The page buffer (60) can sense the voltage or current of the bit line (BL) during a read operation.

[0030] The first switching circuit group (20[1]) and the second switching circuit group (20[2]) can transmit operating voltages output to the plurality of first global lines (GG1) and the plurality of second global lines (GG2) to the first local lines and the second local lines of the selected memory block in response to the plurality of block selection signals (BSEL[A] to BSEL[D]) output from the row decoder (30).

[0031] The configuration of the first switching circuit group (20[1]), the configuration of the plurality of first local lines (LGA1, LGB1, LGC1, LGD1), the configuration of the second switching circuit group (20[2]), the configuration of the plurality of second local lines (LGA2, LGB2, LGC2, LGD2), the connection relationship between the first switching circuit group (20[1]) and the memory cell array (10), and the connection relationship between the second switching circuit group (20[2]) and the memory cell array (10) may vary. As an example embodiment, the first switching circuit group (20[1]) may include a plurality of first sub-switching circuit groups (20A1 to 20D1), and the second switching circuit group (20[2]) may include a plurality of second sub-switching circuit groups (20A2 to 20D2). The first sub-switching circuit groups (20A1 to 20D1) can be individually connected to a plurality of memory blocks (10A to 10D), and the second sub-switching circuit groups (20A2 to 20D2) can be individually connected to a plurality of memory blocks (10A to 10D). For example, the first memory block (10A) can be connected to the corresponding first sub-switching circuit group (20A1) and second sub-switching circuit group (20A2), and the second memory block (10B) can be connected to the corresponding first sub-switching circuit group (20B1) and second sub-switching circuit group (20B2).

[0033] FIGS. 2A and 2B illustrate circuit diagrams of a switching circuit group and a memory cell array according to embodiments of the present invention. For example, a circuit diagram according to a first embodiment and a circuit diagram according to a second embodiment for a first memory block (10A) described with reference to FIG. 1, first and second sub-switching circuit groups (20A1 and 20A2) connected to the first memory block (10A), a second memory block (10B), and first and second sub-switching circuit groups (20B1 and 20B2) connected to the second memory block (10B) are respectively illustrated in FIG. 2A and 2B.

[0034] Referring to FIGS. 1, 2a, and 2b, each of the memory blocks (10A to 10D) may include a plurality of memory cell strings (CS) connected to a plurality of bit lines (BL) and a common source line (CSL). Each memory cell string (CS) may include at least one drain select transistor (DST), a plurality of memory cells (MC), and at least one source select transistor (SST) connected in series. At least one drain select transistor (DST) may be connected between the plurality of memory cells (MC) and the bit line (BL). In the following, an embodiment is described based on a structure in which two drain select transistors (DST) are connected in series between the plurality of memory cells (MC) and the bit line (BL), but the present invention is not limited thereto. At least one source select transistor (SST) may be connected between the plurality of memory cells (MC) and the common source line (CSL). In the following, embodiments are described based on a structure in which two source select transistors (SST) are connected in series between a plurality of memory cells (MC) and a common source line (CSL), but the present invention is not limited thereto.

[0035] Each memory cell string (CS) may be connected to at least one drain select line (DSL), a plurality of word lines (WL), and at least one source select line (SSL). The drain select line (DSL) may be connected to the gate of a drain select transistor (DST), the plurality of word lines (WL) may be connected to a plurality of gates of a plurality of memory cells (MC), and the source select line (SSL) may be connected to the gate of a source select transistor (SST). In the following, an embodiment is described based on a structure in which two drain select lines (DSL) individually connected to the gates of two drain select transistors (DST) and two source select lines (SSL) individually connected to the gates of two source select transistors (SST) are connected to each memory cell string (CS), but the present invention is not limited thereto.

[0036] The configuration of the plurality of first local lines (LGA1, LGB1, LGC1, LGD1) and the plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may vary. The first local lines (LGA1, LGB1, LGC1, LGD1) may be connected to first sub-switching circuit groups (20A1 to 20D1) in groups, and the second local lines (LGA2, LGB2, LGC2, LGD2) may be connected to second sub-switching circuit groups (20A2 to 20D2) in groups.

[0038] Referring to FIG. 1 and FIG. 2a, as a first embodiment, a plurality of memory cell strings (CS) of each of the memory blocks (10A to 10D) can be connected to each other by source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL), respectively.

[0039] A plurality of first local lines (LGA1, LGB1, LGC1, LGD1) may be composed of source select lines (SSL) of a plurality of memory blocks (10A, 10B, 10C, 10D). A plurality of first local lines (LGA1, LGB1, LGC1, LGD1) may be divided into groups corresponding to each memory block (10A, 10B, 10C, or 10D). For example, the source select lines (SSL) of the first memory block (10A) may constitute the first local lines (LGA1) of the first group, and the source select lines (SSL) of the second memory block (10B) may constitute the first local lines (LGB1) of the second group. Each group of multiple first local lines (LGA1, LGB1, LGC1, LGD1) can be connected to a corresponding first sub-switching circuit group (20A1, 20B1, 20C1, or 20D1). For example, source select lines (SSL) of a first memory block (10A) constituting the first local lines (LGA1) of the first group can be connected to the first sub-switching circuit group (20A1), and source select lines (SSL) of a second memory block (10B) constituting the first local lines (LGB1) of the second group can be connected to the first sub-switching circuit group (20B1).

[0040] A plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may be composed of a plurality of word lines (WL) and drain select lines (DSL) of a plurality of memory blocks (10A, 10B, 10C, 10D). A plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may be divided into groups corresponding to each memory block (10A, 10B, 10C, or 10D). For example, a plurality of word lines (WL) and drain select lines (DSL) of a first memory block (10A) may constitute the second local lines (LGA2) of a first group, and a plurality of word lines (WL) and drain select lines (DSL) of a second memory block (10B) may constitute the second local lines (LGB2) of a second group. Each group of multiple second local lines (LGA2, LGB2, LGC2, LGD2) can be connected to a corresponding second sub-switching circuit group (20A2, 20B2, 20C2, or 20D2). For example, multiple word lines (WL) and drain select lines (DSL) of a first memory block (10A) constituting the second local lines (LGA2) of a first group can be connected to a second sub-switching circuit group (20A2), and multiple word lines (WL) and drain select lines (DSL) of a second memory block (10B) constituting the second local lines (LGB2) of a second group can be connected to a second sub-switching circuit group (20B2).

[0042] Referring to FIG. 1 and FIG. 2b, as a second embodiment, a plurality of memory cell strings (CS) of each of the memory blocks (10A to 10D) may be divided into a first group of memory cell strings and a second group of memory cell strings. For example, a plurality of memory cell strings (CS1) of the first memory block (10A) may be divided into a first group of memory cell strings (10A1) and a second group of memory cell strings (10A2), and a plurality of memory cell strings (CS2) of the second memory block (10B) may be divided into a first group of memory cell strings (10B1) and a second group of memory cell strings (10B2).

[0043] A plurality of first local lines (LGA1, LGB1, LGC1, LGD1) may be composed of source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to the memory cell strings of a first group of a plurality of memory blocks (10A, 10B, 10C, 10D). The plurality of first local lines (LGA1, LGB1, LGC1, LGD1) may be divided into groups corresponding to each memory block (10A, 10B, 10C, or 10D). For example, source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to a first group of memory cell strings (10A1) of a first memory block (10A) can form the first local lines (LGA1) of the first group, and source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to a first group of memory cell strings (10B1) of a second memory block (10B) can form the first local lines (LGB1) of the second group. Each group of the plurality of first local lines (LGA1, LGB1, LGC1, LGD1) can be connected to a corresponding first sub-switching circuit group (20A1, 20B1, 20C1, or 20D1). For example, source select lines (SSL), multiple word lines (WL), and drain select lines (DSL) constituting the first local lines (LGA1) of the first group of the first memory block (10A) may be connected to the first sub-switching circuit group (20A1). Additionally, source select lines (SSL), multiple word lines (WL), and drain select lines (DSL) constituting the first local lines (LGB1) of the second group of the second memory block (10B) may be connected to the first sub-switching circuit group (20B1).

[0044] A plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may be composed of source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to memory cell strings of a second group of a plurality of memory blocks (10A, 10B, 10C, 10D). The plurality of second local lines (LGA2, LGB2, LGC2, LGD2) may be divided into groups corresponding to each memory block (10A, 10B, 10C, or 10D). For example, source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to a second group of memory cell strings (10A2) of a first memory block (10A) can form the second local lines (LGA2) of the first group, and source select lines (SSL), a plurality of word lines (WL), and drain select lines (DSL) connected to a second group of memory cell strings (10B2) of a second memory block (10B) can form the second local lines (LGB2) of the second group. Each group of the plurality of second local lines (LGA2, LGB2, LGC2, LGD2) can be connected to a corresponding second sub-switching circuit group (20A2, 20B2, 20C2, or 20D2). For example, source select lines (SSL), multiple word lines (WL), and drain select lines (DSL) constituting the second local lines (LGA2) of the first group of the first memory block (10A) may be connected to the second sub-switching circuit group (20A2). Additionally, source select lines (SSL), multiple word lines (WL), and drain select lines (DSL) constituting the second local lines (LGB2) of the second group of the second memory block (10B) may be connected to the second sub-switching circuit group (20B2).

[0046] Referring to FIGS. 1, 2a, and 2b, the first global lines (GG1) and the second global lines (GG2) may include global lines (GSSL, GWL, GDSL) for supplying operating voltages to a plurality of first local lines (LGA1, LGB1, LGC1, LGD1) and a plurality of second local lines (LGA1, LGB1, LGC1, LGD1). The global lines (GSSL, GWL, GDSL) may include global source select lines (GSSL), global word lines (WL), and global drain select lines (GDSL). Global source select lines (GSSL) can transmit voltages supplied to source select lines (SSL), global word lines (WL) can transmit voltages supplied to word lines (WL), and global drain select lines (GDSL) can transmit voltages supplied to drain select lines (DSL).

[0047] Each of the first sub-switching circuit groups (20A1 to 20D1) may include first pass transistors (PT1). The gates of the first pass transistors (PT1) may be commonly connected to a block word line that transmits a corresponding block selection signal. For example, the gates of the first pass transistors (PT1) of the first sub-switching circuit group (20A1) connected to the first memory block (10A) may be connected to a first block word line (BLKWL[A]) that transmits a first block selection signal (BSEL[A]), and the gates of the first pass transistors (PT1) of the first sub-switching circuit group (20B1) connected to the second memory block (10B) may be connected to a second block word line (BLKWL[B]) that transmits a second block selection signal (BSEL[B]).

[0048] Each of the second sub-switching circuit groups (20A2 to 20D2) may include second pass transistors (PT2). The gates of the second pass transistors (PT2) may be commonly connected to a block word line that transmits a corresponding block selection signal. For example, the gates of the second pass transistors (PT2) of the second sub-switching circuit group (20A2) connected to the first memory block (10A) may be connected to a first block word line (BLKWL[A]) that transmits a first block selection signal (BSEL[A]), and the gates of the second pass transistors (PT2) of the second sub-switching circuit group (20B2) connected to the second memory block (10B) may be connected to a second block word line (BLKWL[B]) that transmits a second block selection signal (BSEL[B]).

[0049] According to the above-described embodiment of the present invention, each block word line (e.g., BLKWL[A]) transmitting a block selection signal may be commonly connected to the gates of the first pass transistors (PT1) of the corresponding first switching circuit group (20A1) and the gates of the second pass transistors (PT2) of the second switching circuit group (20A2).

[0050] The memory cell array (10) described with reference to FIGS. 1 and 2a or FIGS. 1 and 2b may form part of a multi-plane structure.

[0052] FIG. 3 is a block diagram showing a multi-plane structure according to one embodiment of the present invention.

[0053] Referring to FIG. 3, the multi-plane structure may include two or more planes (PL1 to PL4) controlled by a row decoder (30). FIG. 3 illustrates a multi-plane structure including a first plane (PL1), a second plane (PL2), a third plane (PL3), and a fourth plane (PL4), but the present invention is not limited thereto.

[0054] The first to fourth planes (PL1 to PL4) may be disposed on different regions of a semiconductor substrate. Each of the first to fourth planes (PL1 to PL4) may include a plurality of memory blocks (10A to 10D) described with reference to FIG. 1 and FIG. 2. The memory blocks (10A to 10D) may be connected to a first switching circuit group (20[1]) and a second switching circuit group (20[2]), as described with reference to FIG. 1.

[0055] The first switching circuit group (20[1]) and the second switching circuit group (20[2]) involved in the operation of each of the first to fourth planes (PL1 to PL4) can be controlled by a row decoder (30) placed in a portion of a semiconductor memory device adjacent to any one of them.

[0056] The first switching circuit group (20[1]) and the second switching circuit group (20[2]) can be overlapped by both ends of each of the gate stacks composed of local lines of memory blocks (10A to 10D).

[0058] FIG. 4 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present invention. For example, the arrangement of a semiconductor substrate (101), a first gate stack (GST[A]), a second gate stack (GST[B]), and a block word line (BLKWL) is schematically illustrated in FIG. 4. Hereinafter, the directions in which axes intersect each other in a plane parallel to the upper surface of the semiconductor substrate (101) are directed are defined as the first direction (D1) and the second direction (D2), and the direction intersecting the upper surface of the semiconductor substrate (101) is defined as the third direction (D3). For example, the first direction (D1), the second direction (D2), and the third direction (D3) may be the directions in which the X-axis, Y-axis, and Z-axis of the XYZ coordinate system are directed.

[0059] Referring to FIG. 4, the semiconductor substrate (101) may include a peripheral circuit structure comprising first sub-switching circuit groups (20A1 to 20D1) of a first switching circuit group (20[1]) shown in at least one of FIG. 1, FIG. 2a and FIG. 2b, second sub-switching circuit groups (20A2 to 20D2) of a second switching circuit group (20[2]), a row decoder (30), a voltage generation circuit (40), a control circuit (50), a page buffer (60), and a column decoder (70). The semiconductor substrate (101) may include a row decoder region (RDA), a first contact region (CTA1), a second contact region (CTA2), a third contact region (CTA3), and a cell array region (CAR). A row decoder (30) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may be placed in a row decoder region (RDA) of a semiconductor substrate (101). Each of the first sub-switching circuit groups (20A1 to 20D1) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may be placed in a corresponding first contact region (CTA1). Each of the second sub-switching circuit groups (20A2 to 20D2) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may be placed in a corresponding second contact region (CTA2). A cell array region (CAR) may be defined between the first contact region (CTA1) and the second contact region (CTA2). A third contact region (CTA3) may be defined on the semiconductor substrate (101) between adjacent gate stacks. For example, a third contact region (CTA3) may be defined on a semiconductor substrate (101) between a first gate stack (GST[A]) and a second gate stack (GST[B]).

[0060] The row decoder region (RDA) faces the second contact region (CTA2), and the first contact region (CTA1) and the cell array region (CAR) may be positioned between the row decoder region (RDA) and the second contact region (CTA2). The row decoder region (RDA) may be extended to be adjacent to the third contact region (CTA3).

[0061] Each of the plurality of memory blocks (10A to 10D) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may include at least one gate stack. In one embodiment, the first memory block (10A) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may include a first gate stack (GST[A]), and the second memory block (10B) illustrated in at least one of FIGS. 1, FIGS. 2a, and FIGS. 2b may include a second gate stack (GST[B]). The present invention is not limited thereto, and each memory block may include two or more gate stacks separated from each other by a slit (SI).

[0062] Each of the gate stacks may include first local lines and second local lines stacked apart in a third direction (D3). In one embodiment, the first gate stack (GST[A]) may include source select lines (SSL), word lines (WL), and drain select lines (DSL) of the first memory block (10A) shown in at least one of FIG. 1, FIG. 2a, and FIG. 2b, and the second gate stack (GST[B]) may include source select lines (SSL), word lines (WL), and drain select lines (DSL) shown in at least one of FIG. 1, FIG. 2a, and FIG. 2b.

[0063] A slit (SI) may be defined between adjacent gate stacks. For example, the slit (SI) may be placed between a first gate stack (GST[A]) and a second gate stack (GST[B]).

[0064] A vertical conductive line (233) may be positioned across a memory cell array. In one embodiment, the vertical conductive line (233) may be positioned between a first gate stack (GST[A]) and a second gate stack (GST[B]), and may be positioned inside a slit (SI). The vertical conductive line (233) may be used as a block word line (BLKWL) that transmits one of the block select signals (BSEL[A] to BSEL[D]) described with reference to FIG. 1. For example, the block word line (BLKWL) may transmit the first block select signal (BSEL[A]) shown in FIG. 1 and may be used as the first block word line (BLKWL[A]) shown in FIG. 2a and FIG. 2b.

[0065] The vertical conduction line (233) may be extended in a first direction (D1). The first gate stack (GST[A]) and the second gate stack (GST[B]) may be adjacent to each other in a second direction (D2) that intersects the vertical conduction line (233).

[0066] The row decoder region (RDA) of the semiconductor substrate (101) may not overlap with the first gate stack (GST[A]) and the second gate stack (GST[B]). The third contact region (CTA3) of the semiconductor substrate (101) may overlap with the vertical conduction line (233). The first contact region (CTA1) and the second contact region (CTA2) of the semiconductor substrate (101) may overlap with both ends of the corresponding gate stack. For example, the first gate stack (GST[A]) may include a first end and a second end spaced apart from the first end in a first direction (D1). The first contact region (CTA1) may overlap with the first end of the first gate stack (GST[A]), and the second contact region (CTA2) may overlap with the second end of the first gate stack (GST[B]).

[0067] As described above, by configuring the block word line (BLKWL) with a vertical conductive line (233) placed between adjacent first gate stacks (GST[A]) and second gate stacks (GST[B]), the separate space for the block word line (BLKWL) can be eliminated. Accordingly, the size of the semiconductor memory device can be reduced.

[0069] FIGS. 5a to 5d are cross-sectional views showing exemplary configurations of a semiconductor memory device illustrated in FIG. 4.

[0070] FIG. 5a is a cross-sectional view taken along the first direction (D1) of a first contact region (CTA1) of a semiconductor substrate (101) shown in FIG. 4, a part of a cell array region (CAR) adjacent to the first contact region (CTA1), and configurations superimposed thereon. FIG. 5b is a cross-sectional view taken along the first direction (D1) of a second contact region (CTA2) of a semiconductor substrate (101) shown in FIG. 4, a part of a cell array region (CAR) adjacent to the second contact region (CTA2), and configurations superimposed thereon. FIG. 5c is a cross-sectional view taken along the second direction (D2) of a third contact region (CTA3) of a semiconductor substrate (101) shown in FIG. 4, a part of each of the cell array regions (CAR) on both sides of the third contact region (CTA3), and configurations superimposed thereon. FIG. 5d is a cross-sectional view taken along the first direction (D1) of a portion of the row decoder region (RDA) and the third contact region (CTA3) of the semiconductor substrate (101) shown in FIG. 4, and the configurations superimposed thereon. The first superimposed region (OLA1) shown in FIG. 5d can be defined as a portion of the third contact region (CTA3) adjacent to the first contact region (CTA1) shown in FIG. 4, the second superimposed region (OLA2) shown in FIG. 5d can be defined as a portion of the third contact region (CTA3) adjacent to the second contact region (CTA2) shown in FIG. 4, and the third superimposed region (OLA3) shown in FIG. 5d can be defined as a portion of the third contact region (CTA3) adjacent to the cell array region (CAR) shown in FIG. 4.

[0071] Referring to FIGS. 5a to 5d, the semiconductor substrate (101) of the semiconductor memory device may include a peripheral circuit structure. The peripheral circuit structure may include a first pass transistor (PT1), a first transistor (TR1), a second pass transistor (PT2), and a second transistor (TR2).

[0072] For example, the first pass transistor (PT1) may be a component of the first sub-switching circuit group (20A1) of the first switching circuit group (20[1]) described with reference to FIGS. 1, 2a, and 3, and the second pass transistor (PT2) may be a component of the second sub-switching circuit group (20A2) of the second switching circuit group (20[2]) described with reference to FIGS. 1, 2a, and 3. The first transistor (TR1) may be a component of the page buffer (60) described with reference to FIG. 1, and the second transistor (TR2) may be a component of the row decoder (30) described with reference to FIGS. 1, 2a, and 3.

[0073] Each of the first pass transistor (PT1), the first transistor (TR1), the second pass transistor (PT2), and the second transistor (TR2) may include a gate insulating film (105), a gate electrode (107), and junction regions (101J). The gate insulating film (105) and the gate electrode (107) may be laminated on an active region of a semiconductor substrate (101). The active region of the semiconductor substrate (101) may be partitioned by an isolation layer (103) embedded within the semiconductor substrate (101). The junction regions (101J) may be defined as regions in which at least one of n-type impurities and p-type impurities is injected into the active region of the semiconductor substrate (101) on both sides of the gate electrode (107). The junction regions (101J) may be provided as source and drain regions of the corresponding transistors.

[0074] A memory cell array of a semiconductor memory device may be superimposed on a semiconductor substrate (101). The memory cell array may include a first gate stack (GST[A]) and a second gate stack (GST[B]) that surround a plurality of cell plugs (CPL).

[0075] The first gate stack (GST[A]) and the second gate stack (GST[B]) may be separated from each other in a second direction (D2) by a slit (SI). Each of the first gate stack (GST[A]) and the second gate stack (GST[B]) may include a plurality of interlayer insulating films (211) and a plurality of conductive patterns (213) alternately stacked on a semiconductor substrate (101). The plurality of conductive patterns (213) may be insulated from each other by the plurality of interlayer insulating films (211) and may be separated from each other in a third direction (D3). The plurality of conductive patterns (213) may form drain select lines (DSL), word lines (WL), and source select lines (SSL). The word lines (WL) may be placed between the drain select line (DSL) and the source select line (SSL).

[0076] Each of the first gate stack (GST[A]) and the second gate stack (GST[B]) may overlap the cell array region (CAR), the first contact region (CTA1), and the second contact region (CTA2) of the semiconductor substrate (101). The first end of each of the first gate stack (GST[A]) and the second gate stack (GST[B]) may not only overlap the first contact region (CTA1) where the first pass transistor (PT1) is formed, but may also include a first step structure (SW1) composed of first local lines. The second end of each of the first gate stack (GST[A]) and the second gate stack (GST[B]) may not only overlap the second contact region (CTA2) where the second pass transistor (PT2) is formed, but may also include a second step structure (SW2) composed of second local lines. In one embodiment, the first local lines may be composed of source select lines (SSL) among a plurality of conduction patterns (213), and the second local lines may be composed of word lines (WL) and drain select lines (DSL) among a plurality of conduction patterns (213). The source select lines (SSL) may form a first step structure (SW1) by extending in a plane parallel to the upper surface of the semiconductor substrate (101) as they move away from the semiconductor substrate (101). The word lines (WL) and drain select lines (DSL) may form a second step structure (SW2) by extending in a plane parallel to the upper surface of the semiconductor substrate (101) as they move away from the semiconductor substrate (101).

[0077] A plurality of cell plugs (CPLs) may be superimposed on a cell array region (CAR) of a semiconductor substrate (101). Each cell plug (CPL) may include a memory film (215), a channel film (217), and a core insulating film (219).

[0078] The channel film (217) can penetrate the plurality of interlayer insulating films (211) and plurality of conductive patterns (213) of each of the first gate stack (GST[A]) and the second gate stack (GST[B]). The memory film (215) can be disposed between the channel film (217) and each of the first gate stack (GST[A]) and the second gate stack (GST[B]), and can wrap the sidewall of the channel film (217).

[0079] Although not illustrated in the drawing, the memory film (215) may include a blocking insulating film, a data storage film, and a tunnel insulating film. The blocking insulating film may be placed between each conductive pattern (213) and the channel film (217), the data storage film may be placed between the blocking insulating film and the channel film (217), and the tunnel insulating film may be placed between the data storage film and the channel film (217). The data storage film may be composed of a material film capable of storing data that is modified using Fowler-Noderheim tunneling. The material film may include a nitride film capable of charge trapping. The tunnel insulating film may be composed of an insulator capable of charge tunneling.

[0080] The channel film (217) may be in contact with the source film (311S). The source film (311S) may form the common source line (CSL) described with reference to FIG. 2a. The source film (311S) may be extended to overlap the first gate stack (GST[A]) and the second gate stack (GST[B]). The first gate stack (GST[A]) and the second gate stack (GST[B]) may be disposed between the source film (311S) and the semiconductor substrate (101). The source film (311S) may be composed of a doped semiconductor film. In one embodiment, the source film (311S) may be composed of n-type doped silicon.

[0081] The channel film (217) may be composed of a semiconductor film such as silicon. The channel film (217) may include a first portion (P1) protruding in a third direction (D3) toward the source film (311S) from each of the first gate stack (GST[A]), the second gate stack (GST[B]), and the memory film (215). The first portion (P1) may be surrounded by the source film (311S) and may be in direct contact with the source film (311S). The channel film (217) may include a second portion (P2) extending from the first portion (P1) toward the semiconductor substrate (101). The second portion (P2) may be formed in a tubular shape. The tubular second portion (P2) may wrap around the sidewall of the core insulating film (219). The core insulating film (219) may protrude in a third direction (D3) from the memory film (215) and may be wrapped around a first portion (P1) of the channel film (217). The channel film (217) may include a third portion (P3) extending from a second portion (P2) toward the semiconductor substrate (101). The third portion (P3) of the channel film (217) may be doped with a conductive impurity. In one embodiment, the third portion (P3) of the channel film (217) may be doped with an n-type impurity. The third portion (P3) of the channel film (217) may include an overlap region wrapped around a portion of each of the first gate stack (GST[A]) and the second stack (GST[B]), and a protruding region protruding toward the semiconductor substrate (101) from each of the first gate stack (GST[A]) and the second stack (GST[B]). The overlap area of ​​the third part (P3) can be designed with various lengths in the third direction (D3) according to design rules. The third part (P3) of the channel film (217) can extend along the surface of the core insulating film (219) toward the semiconductor substrate (101).

[0082] Memory cells may be formed at the intersections of the channel film (217) and word lines (WL), source select transistors may be formed at the intersections of the channel film (217) and source select lines (SSL), and drain select transistors may be formed at the intersections of the channel film (217) and drain select lines (DSL). The source select transistors, drain select transistors, and memory cells may be connected in series by the channel film (217) to form a memory cell string (CS) as described with reference to FIG. 2.

[0083] A semiconductor memory device may further include a filling insulating film (221) disposed between a memory cell array comprising a first gate stack (GST[A]) and a second gate stack (GST[B]) and a semiconductor substrate (101). The filling insulating film (221) may fill grooves defined by the first step structure (SW1) and the second step structure (SW2) of the first gate stack (GST[A]) and the second gate stack (GST[B]), respectively. The filling insulating film (221) may wrap the end of a cell plug (CPL) facing the semiconductor substrate (101).

[0084] A semiconductor memory device may include a first gate vertical contact (223A) superimposed on a first step structure (SW1) and a second gate vertical contact (223B) superimposed on a second step structure (SW2). Each of the first local lines of the first step structure (SW1) may be in contact with the corresponding first gate vertical contact (223A), and each of the second local lines of the second step structure (SW2) may be connected to the corresponding second gate vertical contact (223B). For example, a source select line (SSL) constituting the first local line may be in contact with the first gate vertical contact (223A), and a drain select line (DSL) constituting the second local line may be in contact with the second gate vertical contact (223B). The first gate vertical contact (223A) and the second gate vertical contact (223B) can penetrate the filling insulating film (221) and the interlayer insulating films (211).

[0085] The filling insulating film (221) may be extended to overlap the row decoder region (RDA). A portion of the filling insulating film (221) overlapping the row decoder region (RDA) may be penetrated by a peripheral vertical contact (223C).

[0086] The first gate vertical contact (223A), the second gate vertical contact (223B), and the peripheral vertical contact (223C) may be composed of the same conductive material.

[0087] The filling insulating film (221) may be penetrated by a slit (SI). The slit (SI) is positioned between the first gate stack (GST[A]) and the second gate stack (GST[B]) and may extend in a first direction (D1). The slit (SI) may be filled with a vertical insulating film (231) and a vertical conductive line (233). The vertical insulating film (231) and the vertical conductive line (233) may extend into the source film (311S).

[0088] The vertical conduction line (233) can form a block word line (BLKWL) that is commonly connected to the gate electrodes of a plurality of first pass transistors (PT1) and a plurality of second pass transistors (PT2) as shown in FIG. 2a. The vertical conduction line (233) can be extended in a first direction (D1) so as to overlap the row decoder region (RDA), the first overlap region (OLA1), the second overlap region (OLA2), and the third overlap region (OLA3).

[0089] The source film (311S) may be extended to overlap the first gate stack (GST[A]) and the second gate stack (GST[B]) as well as the vertical conductive line (233). The vertical conductive line (233) may be insulated from the plurality of conductive patterns (213) and the source film (311S) by a vertical insulating film (231). The vertical insulating film (231) may be extended along the sidewall of the vertical conductive line (233) and may be extended between the vertical conductive line (233) and the source film (311S). Alternatively, the vertical insulating film (231) may be extended along the surfaces of the vertical conductive line (233) toward the first gate stack (GST[A]), the second gate stack (GST[B]), and the source film (311S).

[0090] The vertical conductive line (233) and the vertical insulating film (231) may protrude toward the source film (311S) more than the memory film (215). The vertical insulating film (231) may be formed with a thickness greater than that of the memory film (215). Thus, the vertical conductive line (233) can be protected by the vertical insulating film (231) during the process of removing a portion of the memory film (215) to expose the first portion (P1) of the channel film (217).

[0091] Multiple insulating films may be disposed between the semiconductor substrate (101) and the filling insulating film (221). For example, a peripheral circuit insulating structure (131), a first insulating structure (251), a second insulating structure (261), a third insulating structure (271), and a fourth insulating structure (281) may be disposed between the semiconductor substrate (101) and the filling insulating film (221).

[0092] The peripheral circuit side insulation structure (131) may be extended to cover the semiconductor substrate (101) and the first pass transistor (PT1), the second pass transistor (PT2), the first transistor (TR1), and the second transistor (TR2). The peripheral circuit side insulation structure (131) may include two or more insulating films. A plurality of first interconnections (110) and a plurality of first conductive bonding patterns (121) may be embedded within the peripheral circuit side insulation structure (131).

[0093] Each first interconnection (110) may include two or more conductive patterns stacked in a third direction (D3). In one embodiment, each first interconnection (110) may include a first conductive pattern (111) connected to a junction region (101J) or a gate electrode (107), a second conductive pattern (113) on the first conductive pattern (111), a third conductive pattern (115) on the second conductive pattern (113), and a fourth conductive pattern (117) on the third conductive pattern (115). Hereinafter, the present invention is described based on an embodiment in which the first interconnection (110) is composed of a stacked structure of the first conductive pattern (111), the second conductive pattern (113), the third conductive pattern (115), and the fourth conductive pattern (117), but the present invention is not limited thereto.

[0094] A plurality of first interconnections (110) may include conduction patterns individually connected to a first pass transistor (PT1), a second pass transistor (PT2), a first transistor (TR1), and a second transistor (TR2). For example, some of the plurality of fourth conduction patterns (117) may form a first lower conduction line (117L1), a second lower conduction line (117L2), a third lower conduction line (117L3), and a fourth lower conduction line (117L4).

[0095] The first lower conductive line (117L1) can be connected to the gate electrode (107) of the first pass transistor (PT1). The first lower conductive line (117L1) can be placed between the first pass transistor (PT1) and the corresponding gate stack (e.g., GST[A]). The first lower conductive line (117L1) can be connected to the first pass transistor (PT1). The first lower conductive line (117L1) can be overlapped with the first contact region (CTA1). The first lower conductive line (117L1) can be extended between the vertical conductive line (233) and the first overlap region (OLA1) of the semiconductor substrate (101). Thus, the first lower conductive line (117L1) can be overlapped by the vertical conductive line (233). Among the plurality of conduction patterns (213), the first local line (e.g., SSL) can be connected to the first pass transistor (PT1) via at least one conduction pattern connected to the junction region (101J) of the first pass transistor (PT1) among the fourth conduction patterns (117).

[0096] The second lower conductive line (117L2) can be connected to the gate electrode (107) of the second pass transistor (PT2). The second lower conductive line (117L2) can be positioned between the second pass transistor (PT2) and the corresponding gate stack (e.g., GST[A]). The second lower conductive line (117L2) can be overlapped with the second contact region (CTA2). The second lower conductive line (117L2) can be extended between the vertical conductive line (233) and the second overlap region (OLA2) of the semiconductor substrate (101). Thus, the second lower conductive line (117L2) can be overlapped by the vertical conductive line (233). Among the plurality of conduction patterns (213), the second local line (e.g., WL) can be connected to the second pass transistor (PT2) via at least one conduction pattern connected to the junction region (101J) of the second pass transistor (PT2) among the fourth conduction patterns (117).

[0097] The third lower conductive line (117L3) may be connected to the second transistor (TR2) of the row decoder. The third lower conductive line (117L3) may be placed at a level between the first pass transistor (PT1) and the first gate stack (GST[A]). In one embodiment, the third lower conductive line (117L3) may be placed substantially at the same level as the first lower conductive line (117L1) and the second lower conductive line (117L2). The third lower conductive line (117L3) may be placed between the row decoder region (RDA) of the semiconductor substrate (101) and the vertical conductive line (233). Thus, the third lower conductive line (117L3) may be overlapped by the vertical conductive line (233). The second transistor (TR2) may be connected to the vertical conductive line (233) via the third lower conductive line (117L3). The third lower conductive line (117L3) can be connected to a junction region (101J) corresponding to the block select signal output terminal of the second transistor (TR2).

[0098] The fourth lower conduction line (117L4) may be connected to the first transistor (TR1) of the page buffer. The fourth lower conduction line (117L4) may be placed at a level between the first pass transistor (PT1) and the first gate stack (GST[A]). In one embodiment, the fourth lower conduction line (117L4) may be placed substantially at the same level as the first lower conduction line (117L1) and the second lower conduction line (117L2). The first transistor (TR1) may be connected to the channel film (217) via the fourth lower conduction line (117L4).

[0099] A plurality of first conductive bonding patterns (121) may be placed at a level between a plurality of first interconnections (110) and a memory cell array. A plurality of first conductive bonding patterns (121) may be connected to a first pass transistor (PT1), a second pass transistor (PT2), a first transistor (TR1), and a second transistor (TR2) that constitute a peripheral circuit structure via a plurality of first interconnections (110).

[0100] The first insulating structure (251), the second insulating structure (261), the third insulating structure (271), and the fourth insulating structure (281) can be placed at a level between the plurality of first conductive bonding patterns (121) and the memory cell array.

[0101] The first insulating structure (251) may be in contact with the filling insulating film (221) and extend parallel to the semiconductor substrate (101). The first insulating structure (251) may include at least one insulating film. The first insulating structure (251) may be penetrated by a plurality of fifth conductive patterns (255A to 255G). A plurality of fifth conduction patterns (255A to 255G) may include a fifth conduction pattern (255A) in contact with a first gate vertical contact (223A), a fifth conduction pattern (255B) in contact with a second gate vertical contact (223B), a fifth conduction pattern (255C) in contact with a channel membrane (217) of a cell plug (CPL), a fifth conduction pattern (255D) in contact with a part of a vertical conduction line (233) superimposed on a first overlap region (OLA1), a fifth conduction pattern (255E) in contact with a part of a vertical conduction line (233) superimposed on a second overlap region (OLA2), a fifth conduction pattern (255F) in contact with a part of a vertical conduction line (233) superimposed on a row decoder region (RDA3), and a fifth conduction pattern (255G) in contact with a peripheral vertical contact (223C). The fifth conductive pattern (255C) can penetrate the filling insulating film (221) between the first insulating structure (251) and the channel film (217).

[0102] The second insulating structure (261) may be in contact with the first insulating structure (251) and extend parallel to the semiconductor substrate (101). A plurality of sixth conductive patterns (263A to 263G) and a plurality of seventh conductive patterns (265A to 265G) may be embedded within the second insulating structure (261). The second insulating structure (261) may include at least one insulating film. In one embodiment, the second insulating structure (261) may include a first insulating film penetrated by a plurality of sixth conductive patterns (263A to 263G) and a second insulating film penetrated by a plurality of seventh conductive patterns (265A to 265G).

[0103] A plurality of sixth conductive patterns (263A to 263G) include a sixth conductive pattern (263A) connected to the first gate vertical contact (223A) via the fifth conductive pattern (255A), a sixth conductive pattern (263B) connected to the second gate vertical contact (223B) via the fifth conductive pattern (255B), a sixth conductive pattern (263C) connected to the channel membrane (217) via the fifth conductive pattern (255C), a sixth conductive pattern (263D) connected to the vertical conductive line (233) via the fifth conductive pattern (255D), a sixth conductive pattern (263E) connected to the vertical conductive line (233) via the fifth conductive pattern (255E), and a sixth conductive pattern (263) connected to the vertical conductive line (233) via the fifth conductive pattern (255F). It may include a sixth conductive pattern (263G) connected to a surrounding vertical contact (223C) via a conductive pattern (263F) and a fifth conductive pattern (255G).

[0104] A plurality of seventh conduction patterns (265A to 265G) are a seventh conduction pattern (265A) connected to a fifth conduction pattern (255A) via a sixth conduction pattern (263A), a seventh conduction pattern (265B) connected to a fifth conduction pattern (255B) via a sixth conduction pattern (263B), a seventh conduction pattern (265C) connected to a fifth conduction pattern (255C) via a sixth conduction pattern (263C), a seventh conduction pattern (265D) connected to a fifth conduction pattern (255D) via a sixth conduction pattern (263D), a seventh conduction pattern (265E) connected to a fifth conduction pattern (255E) via a sixth conduction pattern (263E), and a fifth conduction pattern via a sixth conduction pattern (263F). It may include a seventh challenge pattern (263F) connected to a challenge pattern (255F) and a seventh challenge pattern (263G) connected to a fifth challenge pattern (255G) via a sixth challenge pattern (263G).

[0105] The fifth conductive pattern (255A), the sixth conductive pattern (263A), and the seventh conductive pattern (265A) connected to the first gate vertical contact (223A) can form a first conductive contact structure (CT1). The fifth conductive pattern (255B), the sixth conductive pattern (263B), and the seventh conductive pattern (265B) connected to the second gate vertical contact (223B) can form a second conductive contact structure (CT2). The fifth conductive pattern (255C), the sixth conductive pattern (263C), and the seventh conductive pattern (265C) connected to the channel membrane (217) can form a bitline contact (BCC). A fifth conductive pattern (255D), a sixth conductive pattern (263D), and a seventh conductive pattern (265D) connected to a vertical conductive line (233) and superimposed on a first overlap area (OLA1) can form a third conductive contact structure (CT3). A fifth conductive pattern (255E), a sixth conductive pattern (263E), and a seventh conductive pattern (265E) connected to a vertical conductive line (233) and superimposed on a second overlap area (OLA2) can form a fourth conductive contact structure (CT4). A fifth conductive pattern (255F), a sixth conductive pattern (263F), and a seventh conductive pattern (265F) connected to a vertical conductive line (233) and superimposed on a row decoder area (RDA) can form a fifth conductive contact structure (CT5). The fifth conductive pattern (255G), the sixth conductive pattern (263G), and the seventh conductive pattern (265G) connected to the surrounding vertical contact (223C) can form a sixth conductive contact structure (CT6). Hereinafter, embodiments of the present invention are described based on the first to sixth conductive contact structures (CT1 to CT6) and bitline contact (BCC) configured as described above, but the present invention is not limited thereto. The first to sixth conductive contact structures (CT1 to CT6) and bitline contact (BCC) described above may be positioned between the level where the vertical conductive line (233) is positioned and the level where the first to fourth lower conductive lines (117L1 to 117L4) are positioned.

[0106] The third insulating structure (271) may be in contact with the second insulating structure (261) and extend parallel to the semiconductor substrate (101). The third insulating structure (271) may be penetrated by a plurality of eighth conductive patterns (275A to 275G). A plurality of eighth conductive patterns (275A to 275G) include an eighth conductive pattern (275A) connected to the first gate vertical contact (223A) via the first conductive contact structure (CT1), an eighth conductive pattern (275B) connected to the second gate vertical contact (223B) via the second conductive contact structure (CT2), an eighth conductive pattern (275C) connected to the channel membrane (217) via the bitline contact (BCC), an eighth conductive pattern (275D) connected to the vertical conductive line (233) via the third conductive contact structure (CT3), an eighth conductive pattern (275E) connected to the vertical conductive line (233) via the fourth conductive contact structure (CT4), and an eighth conductive pattern (275F) connected to the vertical conductive line (233) via the fifth conductive contact structure (CT5). It may include an eighth conductive pattern (275G) connected to a surrounding vertical contact (223C) via a sixth conductive contact structure (CT6). The eighth conductive pattern (275C) may form a bit line (BL). The bit line (BL) may extend in a direction intersecting the vertical conductive line (233). In one embodiment, the bit line (BL) may extend in a second direction (D2). The bit line (BL) may be insulated from the vertical conductive line (233) by the first insulating structure (251) and the second insulating structure (261).

[0107] The fourth insulating structure (281) may be placed between the third insulating structure (271) and the peripheral circuit side insulating structure (131). The fourth insulating structure (281) may include insulating films of two or more layers. A plurality of second interconnections (280) and a plurality of second conductive bonding patterns (291) may be embedded within the fourth insulating structure (281).

[0108] Each second interconnect (280) may include two or more layers of conductive patterns stacked in a third direction (D3). In one embodiment, each second interconnect (280) may include a ninth conductive pattern (283) connected to each of a plurality of eighth conductive patterns (275A to 275G), a tenth conductive pattern (285) between the ninth conductive pattern (283) and the first conductive bonding pattern (121), and an eleventh conductive pattern (287) between the tenth conductive pattern (285) and the first conductive bonding pattern (121). Hereinafter, the present invention is described based on an embodiment in which the second interconnect (280) is configured with a stacked structure of the ninth conductive pattern (283), the tenth conductive pattern (285), and the eleventh conductive pattern (287), but the present invention is not limited thereto.

[0109] A plurality of second interconnections (280) can be connected to a first gate vertical contact (233A), a second gate vertical contact (233B), a vertical conductive line (233), a peripheral vertical contact (223C), and a channel membrane (217) via first to sixth conductive contact structures (CT1 to CT6) and a bitline contact (BCC).

[0110] A plurality of second conductive bonding patterns (291) may be disposed between a plurality of first conductive bonding patterns (121) and a plurality of second interconnections (280). A plurality of second conductive bonding patterns (291) may be bonded to a plurality of first conductive bonding patterns (121). A plurality of second conductive bonding patterns (291) may be connected to a first gate vertical contact (233A), a second gate vertical contact (233B), a vertical conductive line (233), a peripheral vertical contact (223C), and a channel membrane (217) via a plurality of second interconnections (280).

[0111] According to the structure described above, the gate electrode (107) of the first pass transistor (PT1) and the gate electrode (107) of the second pass transistor (PT2) can be commonly connected to a vertical conductive line (233) via a first lower conductive line (117L1), a second lower conductive line (117L2), a third conductive contact structure (CT3), and a fourth conductive contact structure (CT4). Additionally, the vertical conductive line (233) can be connected to a third lower conductive line (117L3) that transmits a block selection signal via a fifth conductive contact (CT5).

[0112] A semiconductor memory device may include an upper insulating film (313) on a source film (311S), an upper contact (315CT), a source contact (315S), a plurality of upper conductive lines (321UL1, 321UL2, 321UL3), and an upper source line (321S). The upper insulating film (313) may extend to cover the source film (311S), a vertical insulating film (231), and a filling insulating film (221). The upper contact (315CT) may penetrate the upper insulating film (313) to contact a surrounding vertical contact (223C). The source contact (315S) may penetrate the upper insulating film (313) to contact the source film (311S). The plurality of upper conductive lines (321UL1, 321UL2, 321UL3) may transmit signals for the operation of the semiconductor memory device. For example, among a plurality of upper conductive lines (321UL1, 321UL2, 321UL3), the upper conductive line (e.g., 321UL3) transmitting a block selection signal can be connected to the second transistor (TR2) of the row decoder via the upper contact (315CT), the peripheral vertical contact (223C), and the sixth conductive contact structure (CT6). The upper conductive line (321UL3) can be connected to the junction region (101J) corresponding to the block selection signal input terminal of the second transistor (TR2). The upper source line (321S) can be connected to the source film (311S) via the source contact (315S). A source voltage for the operation of the semiconductor memory device can be supplied to the source film (311S) through the upper source line (321S).

[0114] FIGS. 6a, 6b, 6c, 6d, 7a, 7b, 7c, 7d, 8a, 8b, 9a, 9b, 9c, 9d, 10a, 10b, 10c, 10d, 11a, 11b, 11c, 11d, 12a, 12b, 12c, and 12d are cross-sectional views illustrating exemplary embodiments of a method for manufacturing a semiconductor memory device illustrated in FIGS. 5a, 5b, 5c, and 5d, in order of process steps. Hereinafter, redundant descriptions of configurations identical to those illustrated in FIGS. 5a, 5b, 5c, and 5d are omitted.

[0116] FIGS. 6a to 6d are cross-sectional views illustrating the steps of forming a first circuit structure.

[0117] Referring to FIGS. 6a to 6d, the step of forming the first circuit structure (410) may include the step of forming a peripheral circuit structure including a first pass transistor (PT1), a second pass transistor (PT2), a first transistor (TR1), and a second transistor (TR2). The first pass transistor (PT1), the second pass transistor (PT2), the first transistor (TR1), and the second transistor (TR2) may be insulated from each other by a device isolation film (103) formed inside a semiconductor substrate (101).

[0118] The first pass transistor (PT1), the second pass transistor (PT2), the first transistor (TR1), and the second transistor (TR2) may be formed in active regions defined in the first contact region (CTA1), the cell array region (CAR), the second contact region (CTA2), the third contact region (CTA3), and the row decoder region (RDA) of the semiconductor substrate (101). The gate electrode (107) of each of the first pass transistor (PT1), the second pass transistor (PT2), the first transistor (TR1), and the second transistor (TR2) may be formed on a gate insulating film (105) disposed on the corresponding active region. The junction regions (101J) of each of the first pass transistor (PT1), the second pass transistor (PT2), the first transistor (TR1), and the second transistor (TR2) may be formed within the active region on both sides of the gate electrode (107).

[0119] The third contact region (CTA3) of the semiconductor substrate may include a first overlap region (OLA1), a second overlap region (OLA2), and a third overlap region (OLA3), as described above with reference to FIGS. 5a to 5d.

[0120] The step of forming the first circuit structure (410) may include the step of forming a plurality of first interconnections (110) and a plurality of first conductive bonding patterns (121) embedded within the surrounding circuit-side insulation structure (131). As described with reference to FIGS. 5A to 5D, the plurality of first interconnections (110) may include a plurality of first conductive patterns (111), a plurality of second conductive patterns (113), a plurality of third conductive patterns (115), and a plurality of fourth conductive patterns (117). As described with reference to FIGS. 5A to 5D, the plurality of fourth conductive patterns (117) may include a first lower conductive line (117L1), a second lower conductive line (117L2), a third lower conductive line (117L3), and a fourth lower conductive line (117L4).

[0122] FIGS. 7a to 7d are cross-sectional views illustrating the steps of forming a memory cell array.

[0123] Referring to FIGS. 7a to 7d, a memory cell array can be formed on a sacrificial substrate (201). The steps of forming the memory cell array may include: alternately stacking a plurality of first material films and a plurality of second material films on the sacrificial substrate (201); forming a hole (H) that penetrates the plurality of first material films and a plurality of second material films and extends into the sacrificial substrate (201) by an etching process using a mask pattern as an etching barrier; forming a cell plug (CPL) inside the hole (H); etching the plurality of first material films and a plurality of second material films so that a first step structure (SW1) and a second step structure (SW2) are defined; removing the mask pattern; forming a filling insulating film (221) on the sacrificial substrate (201); and forming a slit (SI) that penetrates the filling insulating film (221) and the plurality of first material films and a plurality of second material films and extends into the sacrificial substrate (201). The first material film and the second material film may be composed of various materials. In one embodiment, the first material film may be composed of an insulating material identical to a plurality of interlayer insulating films (211), and the second material film may be composed of a sacrificial material having an etching selectivity ratio with respect to the insulating material. For example, the first material film may be composed of silicon oxide, and the second material film may be composed of silicon nitride. Hereinafter, embodiments of the present invention are described based on an embodiment in which the first material film is composed of an insulating material and the second material film is composed of a sacrificial material, but the present invention is not limited thereto.

[0124] The step of forming a memory cell array may further include the step of selectively removing second material films composed of sacrificial materials and the step of filling the regions from which the second material films have been removed with a plurality of conductive patterns (213).

[0125] By the process described above, a first gate stack (GST[A]) and a second gate stack (GST[B]) of a memory cell array can be formed. Each of the first gate stack (GST[A]) and the second gate stack (GST[B]) can wrap a cell plug (CPL) and may include a plurality of interlayer insulating films (211) and a plurality of conductive patterns (213) alternately stacked on a sacrificial substrate (201). The plurality of conductive patterns (213) may form a first step structure (SW1) and a second step structure (SW2). As an example of one embodiment, source select lines (SSL) constituting the first local lines among the plurality of conduction patterns (213) can form a first step structure (SW1), and word lines (WL) and drain select lines (DSL) constituting the second local lines among the plurality of conduction patterns (213) can form a second step structure (SW2).

[0126] The step of forming a cell plug (CPL) may include forming a memory film (215), forming a liner semiconductor film on the memory film (215), filling a portion of the central region of the hole (H) opened by the liner semiconductor film with a core insulating film (219), and filling the remaining portion of the central region of the hole (H) with a doft semiconductor film. The doft semiconductor film and the liner semiconductor film may form a channel film (217). Since the memory film (215) extends along the sidewall and bottom surface of the hole (H), the memory film (215) may be placed between the sacrificial substrate (201) and the channel film (217). The channel film (217) may include a first portion (P1) extended to the level of the sacrificial substrate (201), a second portion (P2) extended from the first portion (P1), and a third portion (P3) extended from the second portion (P2) onto the core insulating film (219). The third part (P3) may contain conductive impurities, and as an example, may contain n-type impurities.

[0128] FIGS. 8A and FIGS. 8B are cross-sectional views illustrating the steps of forming a vertical insulating film (231) and a vertical conductive line (233).

[0129] Referring to FIGS. 8a and 8b, a vertical insulating film (231) can be formed along the surface of the slit (SI). The thickness of the vertical insulating film (231) formed on the surface of the slit (SI) can be controlled to be greater than the thickness of the memory film (215) formed on the surface of the hole (H).

[0131] FIGS. 9a to 9d are cross-sectional views illustrating exemplary subsequent processes following the formation of a vertical conductive line (233).

[0132] Referring to FIGS. 9a to 9d, a first gate vertical contact (223A), a second gate vertical contact (223B), and a peripheral vertical contact (223C) can be formed through the filling insulating film (221).

[0133] Each of the first gate vertical contact (223A) and the second gate vertical contact (223B) can penetrate the interlayer insulating film (211) to contact the conductive pattern (213). For example, the first gate vertical contact (223A) can be in contact with the source select line (SSL) constituting the first step structure (SW1), and the second gate vertical contact (223B) can be in contact with the drain select line (DSL) constituting the second step structure (SW2).

[0134] The surrounding vertical contact (223C) can be in contact with the sacrificial substrate (201) that is not superimposed on the first gate stack (GST[A]), the second gate stack (GST[B]), the vertical insulating film (231), and the vertical conductive line (233).

[0135] Next, a first insulating structure (251) can be formed on the filling insulating film (221). The first insulating structure (251) can be extended to cover the first gate vertical contact (223A), the second gate vertical contact (223B), the peripheral vertical contact (223C), the vertical insulating film (231), and the vertical conductive line (233).

[0136] Afterwards, a plurality of fifth conductive patterns (255A to 255G) can be formed that penetrate at least one of the first insulating structure (251) and the filling insulating film (221). Subsequently, the steps of forming a plurality of sixth conductive patterns (263A to 263G) and forming a plurality of seventh conductive patterns (265A to 265G) can be performed sequentially. The second insulating structure (261) may include an insulating film penetrated by the plurality of sixth conductive patterns (263A to 263G) and an insulating film penetrated by the plurality of seventh conductive patterns (265A to 265G). A plurality of fifth conductive patterns (255A to 255G), a plurality of sixth conductive patterns (263A to 263G) and a plurality of seventh conductive patterns (265A to 265G) can form a first conductive contact structure (CT1), a second conductive contact structure (CT2), a bitline contact structure (BCC), a third conductive contact structure (CT3), a fourth conductive contact structure (CT4), a fifth conductive contact structure (CT5), and a sixth conductive contact structure (CT6).

[0137] Next, the steps of forming a third insulating structure (271) on a second insulating structure (261), forming a plurality of eighth conductive patterns (275A to 275G) penetrating the third insulating structure (271), forming second interconnections (280) connected to the plurality of eighth conductive patterns (275A to 275G), and forming a plurality of second conductive bonding patterns (291) connected to the plurality of second interconnections (280) can be performed sequentially.

[0138] The step of forming a plurality of second interconnections (280) may include the step of forming a first insulating film on a third insulating structure (271), the step of forming a plurality of ninth conductive patterns (283) penetrating the first insulating film, the step of forming a second insulating film on the first insulating film, the step of forming a plurality of tenth conductive patterns (285) penetrating the second insulating film, the step of forming a third insulating film on the second insulating film, and the step of forming a plurality of eleventh conductive patterns (287) penetrating the third insulating film. The step of forming a plurality of second conductive bonding patterns (291) may be performed after forming a fourth insulating film on the third insulating film. A plurality of second conductive bonding patterns (291) may be formed to penetrate the fourth insulating film. The first to fourth insulating films described above may constitute a fourth insulating structure (281).

[0139] A second circuit structure (420) can be defined on a sacrificial substrate (201) by the processes described with reference to FIGS. 7a to 7d, FIGS. 8a and 8b, and FIGS. 9a to 9d.

[0141] FIGS. 10a to 10d illustrate the step of interconnecting the first circuit structure (410) and the second circuit structure (420).

[0142] Referring to FIGS. 10a through 10d, the individually provided first circuit structure (410) and second circuit structure (420) can be interconnected by a bonding process. A plurality of first conductive bonding patterns (121) of the first circuit structure (410) can be bonded to a plurality of second conductive bonding patterns (291). Accordingly, a plurality of conductive patterns (213) and bit line (BL), vertical conductive line (233) and peripheral vertical contact (223C) of the second circuit structure (420) can be connected to a first pass transistor (PT1), a second pass transistor (PT2), a first transistor (TR1), and a second transistor (TR2) of the peripheral circuit structure via a plurality of first interconnections (110), a plurality of first conductive bonding patterns (121), a plurality of second conductive bonding patterns (291), and a plurality of second interconnections (280).

[0144] FIGS. 11a to 11d illustrate the step of exposing the first portion (P1) and the surrounding vertical contact (223C) of the channel membrane (217).

[0145] Referring to FIGS. 11a through 11d, by removing the sacrificial substrate (201) illustrated in FIGS. 10a through 10d, a portion of the surrounding vertical contact (223C) and the memory film (215) can be exposed. At this time, a portion of the vertical insulating film (231) and a portion of the filling insulating film (221) may be exposed. Subsequently, a portion of the memory film (215) may be removed by an etching process so that a first portion (P1) of the channel film (217) may be exposed. While removing the memory film (215), a portion of the vertical insulating film (231) may be etched. Since the vertical insulating film (231) is formed to be thicker than the memory film (215), the vertical insulating film (231) may remain to block the vertical conductive line (233).

[0147] FIGS. 12a to 12d illustrate the step of forming a source film (311S).

[0148] Referring to FIGS. 12a through 12d, the step of forming a source film (311S) may include the step of forming a doped semiconductor film to cover a first portion (P1) of a channel film (217), a vertical insulating film (231), and a filling insulating film (221), and the step of defining the source film (311S) by etching the doped semiconductor film. The doped semiconductor film may be etched so that a peripheral vertical contact (223C) is exposed.

[0149] Subsequently, subsequent processes can be performed to form the upper insulating film (313), upper contact (315CT), source contact (315S), a plurality of upper conductive lines (321UL1, 321UL2, 321UL3) and upper source line (321S) as illustrated in FIGS. 5a to 5d.

[0151] FIG. 13 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

[0152] Referring to FIG. 13, the memory system (1100) includes a memory device (1120) and a memory controller (1110).

[0153] The memory device (1120) may be a multi-chip package composed of a plurality of flash memory chips. The memory device (1120) may include a memory cell array and a vertical conductive line disposed across the memory cell array. In one embodiment, the vertical conductive line may be disposed between a first gate stack and a second gate stack of the memory cell array that are spaced apart from each other. Additionally, the memory device (1120) may include circuit groups that are commonly connected to the vertical conductive line and disposed in spaced-apart regions.

[0154] The memory controller (1110) is configured to control the memory device (1120) and may include a Static Random Access Memory (SRAM) (1111), a Central Processing Unit (CPU) (1112), a host interface (1113), an Error Correction Block (1114), and a memory interface (1115). The SRAM (1111) is used as the operating memory of the CPU (1112), the CPU (1112) performs various control operations for data exchange of the memory controller (1110), and the host interface (1113) is equipped with a data exchange protocol of a host connected to the memory system (1100). The Error Correction Block (1114) detects errors contained in data read from the memory device (1120) and corrects the detected errors. The memory interface (1115) performs interfacing with the memory device (1120). The memory controller (1110) may further include a ROM (Read Only Memory) that stores code data for interfacing with a host.

[0155] The memory system (1100) described above may be a memory card or a Solid State Drive (SSD) in which a memory device (1120) and a memory controller (1110) are combined. For example, if the memory system (1100) is an SSD, the memory controller (1110) may communicate with an external source (e.g., a host) through one of various interface protocols such as USB (Universal Serial Bus), MMC (MultiMedia Card), PCI-E (Peripheral Component Interconnection-Express), SATA (Serial Advanced Technology Attachment), PATA (Parallel Advanced Technology Attachment), SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), etc.

[0157] FIG. 14 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

[0158] Referring to FIG. 14, the computing system (1200) may include a CPU (1220), RAM (Random Access Memory: 1230), a user interface (1240), a modem (1250), and a memory system (1210) electrically connected to a system bus (1260). If the computing system (1200) is a mobile device, a battery for supplying operating voltage to the computing system (1200) may be further included, and an application chipset, an image processor, a mobile DRAM, etc. may be further included.

[0159] The memory system (1210) may be composed of a memory device (1212) and a memory controller (1211).

[0160] The memory device (1212) may include a memory cell array and a vertical conductive line disposed across the memory cell array. In one embodiment, the vertical conductive line may be disposed between a first gate stack and a second gate stack of the memory cell array that are spaced apart from each other. Additionally, the memory device (1212) may include circuit groups that are commonly connected to the vertical conductive line and disposed in spaced-apart regions.

[0161] The memory controller (1211) can be configured in the same way as the memory controller (1110) described above with reference to FIG. 13. Explanation of the symbols

[0163] 101: Semiconductor substrate CTA1: First contact region CTA2: Second contact area RDA: Row decoder area CTA3: Third contact area CAR: Cell array area 30: Row decoder 20[1]: First switching circuit group 20[2]: Second switching circuit group PT1: First pass transistor PT2: Second pass transistor 107: Gate electrode 117L1 to 117L3: First to third lower conductive lines GST[A]: 1st gate stack GST[B]: 2nd gate stack 213: Conductive pattern 211: Interlayer insulation film 215: Memory Mark 217: Channel Mark BL: Bitline 233: Vertical Challenge Line 231: Vertical insulating film CT1 to CT6: Conductive contact structure 311S: Source membrane 121: First conductive bonding pattern 291: Second conductive bonding pattern

Claims

Claim 1 A semiconductor memory device comprising: a first gate stack and a second gate stack that are adjacent to each other and each having conductive patterns stacked spaced apart from each other; a vertical conductive line disposed between the first gate stack and the second gate stack and extending in a first direction; and a semiconductor substrate superimposed on the first gate stack, the second gate stack, and the vertical conductive line, wherein the semiconductor substrate comprises a row decoder and pass transistors connected to at least one of the conductive patterns of the first gate stack and the second gate stack, wherein the pass transistors comprise a first pass transistor and a second pass transistor spaced apart from each other in the first direction, and the vertical conductive line connects the row decoder to the gate electrodes of the first and second pass transistors in common. Claim 2 A semiconductor memory device according to claim 1, wherein the first gate stack and the second gate stack are adjacent to each other in a second direction intersecting the vertical conductive line, the first gate stack includes a first end and a second end spaced apart from the first end in the first direction, and the first pass transistor is superimposed on the first end of the first gate stack and the second pass transistor is superimposed on the second end of the first gate stack. Claim 3 In claim 2, the semiconductor substrate comprises: a first contact region in which the first pass transistor is disposed; a second contact region in which the second pass transistor is disposed; a cell array region between the first contact region and the second contact region; a third contact region superimposed on the vertical conductive line; and a row decoder region in which the row decoder is disposed, wherein the row decoder region is spaced apart from the second contact region with the first contact region and the cell array region in between, and is adjacent to the third contact region, a semiconductor memory device. Claim 4 A semiconductor memory device according to claim 3, further comprising: a first lower conductive line disposed between the first pass transistor and the first gate stack and interconnecting the first local line among the conductive patterns with the first pass transistor; a second lower conductive line disposed between the second pass transistor and the first gate stack and interconnecting the second local line among the conductive patterns with the second pass transistor; and a third lower conductive line disposed at a level between the first pass transistor and the first gate stack and connected to the row decoder. Claim 5 In claim 4, the first lower conductive line, the second lower conductive line, and the third lower conductive line are each a semiconductor memory device that overlaps with the vertical conductive line. Claim 6 A semiconductor memory device according to claim 5, further comprising conductive contact structures disposed between a level where the vertical conductive line is disposed and a level where the first to third lower conductive lines are disposed, wherein the vertical conductive line is connected to the first lower conductive line, the second lower conductive line, and the third lower conductive line via the conductive contact structures. Claim 7 A semiconductor memory device according to claim 3, further comprising: a channel film that overlaps the cell array region of the semiconductor substrate and penetrates the first gate stack; a memory film between the channel film and the first gate stack; a bit line disposed between the channel film and the semiconductor substrate and connected to the channel film; and a source film that extends to overlap the first gate stack and the second gate stack and is in contact with the channel film. Claim 8 A semiconductor memory device according to claim 7, further comprising a vertical insulating film extending along the surfaces of the vertical conductive lines toward the first gate stack, the second gate stack, and the source film, wherein the vertical insulating film is thicker than the memory film. Claim 9 A semiconductor substrate including a peripheral circuit structure; a vertical conductive line extending in a first direction on the semiconductor substrate and connected to the peripheral circuit structure; a vertical insulating film extending along the sidewall of the vertical conductive line; and a first gate stack and a second gate stack adjacent to each other with the vertical conductive line and the vertical insulating film in between, wherein each of the first gate stack and the second gate stack includes interlayer insulating films and conductive patterns alternately stacked on the semiconductor substrate, and the vertical conductive line transmits a signal between circuits included in the peripheral circuit structure. Claim 10 In claim 9, the peripheral circuit structure comprises a first circuit group, a second circuit group, and a third circuit group that are spaced apart from each other and connected to the vertical conductive line, and the vertical conductive line transmits a signal output from the third circuit group to the first circuit group and the second circuit group, a semiconductor memory device. Claim 11 A semiconductor memory device according to claim 10, wherein the third circuit group is configured to output the signal corresponding to the block selection signal, and the first circuit group and the second circuit group are configured to transmit operating voltages to the conductive patterns of one of the first gate stack and the second gate stack in response to the block selection signal. Claim 12 A semiconductor memory device according to claim 11, wherein the conduction patterns include a first local line and a second local line spaced apart from each other in a direction intersecting the upper surface of the semiconductor substrate, the first circuit group includes a first pass transistor connected to the first local line, the second circuit group includes a second pass transistor connected to the second local line, and the vertical conduction line is commonly connected to the first gate electrode of the first pass transistor and the second gate electrode of the second pass transistor. Claim 13 A semiconductor memory device according to claim 10, further comprising: a channel film penetrating the first gate stack and the second gate stack; a memory film surrounding the sidewall of the channel film; a bit line disposed between the peripheral circuit structure and the channel film and connected to the channel film; and a source film extending to overlap the first gate stack and the second gate stack and contacting the channel film. Claim 14 In claim 13, the semiconductor memory device wherein each of the channel film and the vertical conductive line protrudes toward the source film more than the memory film. Claim 15 In claim 13, the vertical insulating film is a semiconductor memory device extending between the source film and the vertical conductive line. Claim 16 In claim 13, the vertical insulating film is a semiconductor memory device thicker than the memory film. Claim 17 A semiconductor memory device comprising: a semiconductor substrate including a first circuit group and a second circuit group spaced apart from each other; a memory cell array superimposed on the semiconductor substrate; a vertical conductive line superimposed on the semiconductor substrate and crossing the memory cell array; first conductive bonding patterns disposed at a level between the semiconductor substrate and the memory cell array and connected to the first circuit group and the second circuit group, respectively; and second conductive bonding patterns disposed at a level between the first conductive bonding patterns and the memory cell array, connected to the vertical conductive line and the memory cell array, and bonded to the first conductive bonding patterns, wherein the vertical conductive line is commonly connected to the first circuit group and the second circuit group so that the same block selection signal is transmitted through some of the first conductive bonding patterns and some of the second conductive bonding patterns. Claim 18 In claim 17, the memory cell array comprises: interlayer insulating films and conductive patterns alternately stacked on the semiconductor substrate; a channel film penetrating the interlayer insulating films and the conductive patterns; and a memory film surrounding the sidewall of the channel film. Claim 19 A semiconductor memory device according to claim 18, further comprising: a source film extended to be in contact with the channel film and to overlap with the vertical conductive line; and a vertical insulating film extended along the surfaces of the interlayer insulating films, the conductive patterns, and the vertical conductive line toward the source film. Claim 20 In claim 19, the vertical insulating film is a semiconductor memory device thicker than the memory film.

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