Display device and manufacturing method thereof

Abstract

The present disclosure relates to a display device comprising: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a semiconductor layer located on the substrate and overlapping with the display region and including a channel; a gate electrode overlapping with the channel of the semiconductor layer; an insulating layer located on the gate electrode and including a first inorganic insulating film and a second inorganic insulating film located on the first inorganic insulating film; a first electrode located on the insulating layer; a light-emitting layer located on the first electrode; and a second electrode located on the light-emitting layer, wherein the second inorganic insulating film is also interrupted in an open region in which the light-emitting layer and the second electrode are interrupted in the peripheral region.

Description

Technology Field

[0001] The present disclosure relates to a display device and a method for manufacturing the same, and more specifically, to a display device having an opening region in which at least a portion of the area is perforated, and a method for manufacturing the same. Background Technology

[0002] Recently, as various portable electronic devices include camera functions, the number of people carrying only an electronic device with a built-in camera is rapidly increasing, rather than carrying a separate camera.

[0003] Conventionally, cameras, flashes, speakers, light sensors, etc., were located outside the display area of ​​electronic devices, which tended to reduce the space available for the electronic device to display images. The problem to be solved

[0004] The embodiments are intended to provide a display device comprising an opening area in which at least a portion of the area is perforated. Additionally, the invention is intended to provide a display device and a method for manufacturing the same, wherein a camera is positioned to capture a photograph or video through the opening area. The invention is intended to provide a display device and a method for manufacturing the same, wherein an image can be displayed over a relatively wide area by positioning the opening area and the camera within the display area. means of solving the problem

[0005] A display device according to one embodiment comprises: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a semiconductor layer located on the substrate and overlapping with the display region and including a channel; a gate electrode overlapping with the channel of the semiconductor layer; an insulating layer located on the gate electrode and including a first inorganic insulating film and a second inorganic insulating film located on the first inorganic insulating film; a first electrode located on the insulating layer; a light-emitting layer located on the first electrode; and a second electrode located on the light-emitting layer, wherein the second inorganic insulating film is also interrupted in an open region in the peripheral region where the light-emitting layer and the second electrode are interrupted.

[0006] The severed end of the second inorganic insulating film and the severed end of the light-emitting layer or the second electrode may coincide with each other, and the first inorganic insulating film may include silicon oxide, and the second inorganic insulating film may include silicon nitride.

[0007] The first inorganic insulating film can be continuously formed in the above open area.

[0008] The above peripheral area may include a first peripheral area including the open area and a second peripheral area where a bypass portion is located, through which a data line formed on the insulating layer bypasses and extends.

[0009] The opening area, through which a display panel is penetrated, is located on the inner side of the first peripheral area, and may further include a camera disposed in the opening area.

[0010] The first surrounding area includes at least one dam, and the dam may have a ring shape.

[0011] The open areas may be located on each side of the dam.

[0012] A display device according to one embodiment comprises: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a semiconductor layer located on the substrate and overlapping with the display region and including a channel; a gate electrode overlapping with the channel of the semiconductor layer; an insulating layer located on the gate electrode and including a first inorganic insulating film and a second inorganic insulating film located on the first inorganic insulating film; a first electrode located on the insulating layer; a light-emitting layer located on the first electrode; and a second electrode located on the light-emitting layer, wherein in the peripheral region, the second inorganic film is also broken in an open region where the light-emitting layer and the second electrode are broken, and the step difference occurring when the second inorganic insulating film, the light-emitting layer, and the second electrode are broken in the open region is 300 nm or more and 500 nm or less.

[0013] The first inorganic insulating film comprises silicon oxide, and the second inorganic insulating film may comprise silicon nitride.

[0014] The first inorganic insulating film can be continuously formed in the above open area.

[0015] The thickness of the second inorganic insulating film may be 20 nm or more and 100 nm or less.

[0016] The opening area, through which a display panel is penetrated, is located on the inner side of the first peripheral area, and may further include a camera disposed in the opening area.

[0017] The above peripheral area may include a first peripheral area including the open area and a second peripheral area where a bypass portion is located, through which a data line formed on the insulating layer bypasses and extends.

[0018] The first surrounding area includes at least one dam, the dam has a ring shape, and the open area may be located on each side of the dam.

[0019] A method for manufacturing a display device according to one embodiment comprises: a method for manufacturing a display device including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region, wherein the peripheral region comprises the steps of: forming an insulating layer on a substrate; forming a first data conductive layer on the insulating layer, the first layer, a second layer located on the first layer, and a third layer located on the second layer; stacking a material for a second data conductive layer on the first data conductive layer; removing the material for the second data conductive layer while removing all of the third layer, a part of the second layer, and a part of the insulating layer of the first data conductive layer together; stacking a material for a first electrode; removing the material for the first electrode while removing all of the remaining second layer together to complete a sacrificial layer; sequentially stacking a functional layer and a second electrode on the sacrificial layer; and irradiating a laser onto the sacrificial layer to remove the sacrificial layer, the functional layer adjacent to the sacrificial layer, and the second electrode together. The method includes the step of forming the opening region penetrating the display panel, wherein the first electrode, the functional layer, and the second electrode constitute a light-emitting element.

[0020] The step of removing the material for the second data conductive layer can use a wet etching method.

[0021] The first layer and the third layer of the first data conductive layer may comprise titanium, and the second layer may comprise aluminum.

[0022] The above sacrificial layer may include aluminum.

[0023] The material for the second data conductive layer has a triple-layer structure comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, wherein the first layer and the third layer of the material for the second data conductive layer comprise titanium, and the second layer may comprise aluminum.

[0024] The first electrode material has a triple-layer structure comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, wherein the first layer and the third layer of the first electrode material comprise indium tin oxide, and the second layer may comprise silver. Effects of the invention

[0025] According to the embodiments, by positioning the aperture area corresponding to the camera within the display area, the surrounding area where the image is not displayed can be reduced, and the display area where the image is displayed can be secured more widely. Brief explanation of the drawing

[0026] FIG. 1 is an exploded perspective view of a display device according to one embodiment. FIG. 2 is a schematic cross-sectional view of a display device according to one embodiment. FIG. 3 is a plan view illustrating some components of a display panel according to one embodiment. Figure 4 is an enlarged plan view of area A of Figures 1 and 3. FIG. 5 is a circuit diagram of a pixel according to one embodiment. FIG. 6 is a cross-sectional view of a pixel included in a display area of ​​a display panel according to one embodiment. FIG. 7 is a cross-sectional view of a display panel in which a peripheral area and an opening area are located among a display panel according to one embodiment. FIG. 8 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment in which the functional layer and the second electrode have been removed. FIG. 9 is a flowchart schematically illustrating the manufacturing process of a display panel according to one embodiment. FIG. 10 is a diagram sequentially illustrating the steps of forming a sacrificial layer during the manufacturing process of a display panel according to one embodiment. FIG. 11 is a diagram illustrating the step of removing a sacrificial layer and its surrounding layers through laser irradiation during the manufacturing process of a display panel according to one embodiment. FIG. 12 is a drawing of a sacrificial layer and its surroundings taken before irradiating a laser on a display panel according to one embodiment. FIG. 13 is a drawing taken after removing the sacrificial layer and the surrounding layer of a display panel according to one embodiment through laser irradiation. FIG. 14 is a cross-section of the sacrificial layer and its surroundings that has been removed after the display panel is completed according to one embodiment. FIG. 15 is a cross-sectional view of the surrounding area before the sacrificial layer is completed during the manufacture of a display panel according to one embodiment. FIG. 16 is a drawing sequentially illustrating the steps of forming a sacrificial layer of a display panel according to a comparative example. Figure 17 is a cross-section of the sacrificial layer and its surroundings that was removed after the display panel was completed according to the comparative example of Figure 16. FIG. 18 is a circuit diagram of a pixel according to another embodiment. FIG. 19 is a flowchart schematically illustrating the manufacturing process of a display panel according to another embodiment. FIG. 20 is an enlarged cross-sectional view of a portion of a display panel from which a sacrificial layer has been removed according to another embodiment. FIG. 21 is a cross-sectional view of a pixel included in the display area of ​​a display panel according to the embodiment of FIG. 18. FIG. 22 is a cross-sectional view of a display panel in which the peripheral area and the opening area are located among the display panels according to another embodiment. Specific details for implementing the invention

[0027] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0028] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0029] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0030] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity.

[0031] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0032] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0033] Below, a display device according to one embodiment is schematically described through FIGS. 1 and FIGS. 2.

[0034] FIG. 1 is an exploded perspective view of a display device according to one embodiment, and FIG. 2 is a schematic cross-sectional view of a display device according to one embodiment.

[0035] Referring to FIGS. 1 and 2, a display device (1000) displays an image toward a third direction (DR3) on a plane defined by a first direction (DR1) and a second direction (DR2). The front (or top) and back (or bottom) surfaces of each member are distinguished by the third direction (DR3). The directions indicated by the first to third directions (DR1, DR2, DR3) can be converted to other directions in a relative sense.

[0036] The display device (1000) includes a cover window (WU), a display panel (DP), and a housing member (HM). In this embodiment, the cover window (WU), the display panel (DP), and the housing member (HM) may be combined to form the display device (1000). Additionally, the display device (1000) may include an electronic module (ES), such as a camera or a sensor.

[0037] A cover window (WU) is placed on a display panel (DP) to protect the front surface of the display panel (DP). The cover window (WU) may include a transparent area (TA) and a blocking area (BA). The transparent area (TA) is an optically transparent area and may transmit incident light. The blocking area (BA) may be an area with a relatively lower light transmittance compared to the transparent area (TA). The blocking area (BA) defines the shape of the transparent area (TA) and may surround the transparent area (TA). The blocking area (BA) may display a predetermined color. The blocking area (BA) may overlap with a non-display area (PA) of the display panel (DP) to block the non-display area (PA) from being visible from the outside.

[0038] The cover window (WU) may include a first hole area (HA1) and a second hole area (HA2). Each of the first hole area (HA1) and the second hole area (HA2) may overlap with an electronic module (ES) described later. The electronic module (ES) may photograph an external object or detect or receive external light through the first hole area (HA1) and the second hole area (HA2).

[0039] According to one embodiment, the first hole region (HA1) may be located in the transmission region (TA), and the second hole region (HA2) may be located in the blocking region (BA). However, this is merely an example, and the first hole region (HA1) and the second hole region (HA2) may be located in opposite regions, both may be located in the transmission region (TA), or both may be located in the blocking region (BA). The first hole region (HA1) and the second hole region (HA2) may have different shapes. The first hole region (HA1) may have a circular shape in a planar plane, and the second hole region (HA2) may have an elliptical shape with a major axis extended along the first direction (DR1) in a planar plane. However, the shapes of the first hole region (HA1) and the second hole region (HA2) are not limited thereto, and their size or shape may be varied.

[0040] The display panel (DP) may be a flat rigid display panel or a flexible display panel. A display panel according to one embodiment of the present invention is a light-emitting display panel. For example, the display panel may be an organic light-emitting display panel or a quantum dot light-emitting display panel. An intermediate layer of an organic light-emitting display panel may include a functional layer and a light-emitting layer, and the light-emitting layer may include an organic light-emitting material. An intermediate layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Depending on the embodiment, it may be an inorganic light-emitting display pattern including an inorganic light-emitting diode. Hereinafter, the display panel (DP) is described using an organic light-emitting display panel.

[0041] The display panel (DP) displays an image on its front surface. The front surface of the display panel (DP) includes a display area (DA) and a non-display area (PA). The image is displayed in the display area (DA). The non-display area (PA) may surround the display area (DA).

[0042] A display panel (DP) may include a plurality of pixels (PX) located in a display area (DA). The pixels (PX) may emit light in response to an electrical signal. The light emitted by the pixels (PX) may be combined to form an image. A single pixel (PX) includes a pixel circuit comprising a plurality of transistors and a light-emitting diode that emits light by receiving current from the pixel circuit. The pixel circuit may further include a capacitor. The number of transistors and capacitors included in a single pixel (PX), as well as their connection relationships, can be varied in many ways.

[0043] A display panel (DP) according to one embodiment may include an aperture area (DTA) penetrating the display panel (DP). The display panel (DP) is not formed within the aperture area (DTA). Referring to FIG. 2, a first electronic module (ES1), which is one of the electronic modules (ES), may be located within the aperture area (DTA). The first electronic module (ES1) may be a camera capable of taking photos or videos. The aperture area (DTA) may overlap with the first hole area (HA1) of the cover window (WU). The aperture area (DTA) is located within the planar display area (DA) and is surrounded by the display area (DA). Some of the plurality of pixels (PX) may be arranged surrounding the aperture area (DTA). Thus, an image may also be displayed in an area adjacent to the aperture area (DTA). Referring to the embodiment of FIG. 1, the aperture area (DTA) is located on the upper left side when the display area (DA) is viewed from the front. However, the aperture area (DTA) may be located in the upper right corner or in the center of the display area (DA), that is, at a location where the distance from the aperture area (DTA) to the left and right ends of the display area (DA) is equal. The position of the aperture area (DTA) within the display area (DA) may vary depending on the embodiment. Through Figure 4, which will be described later, we will examine in detail the area A where the aperture area (DTA) is located.

[0044] The display panel (DP) includes a non-display area (PA) that extends from the display area (DA) and is located therein, where a plurality of signal lines and pad portions are located. A data driving portion (50) may be located in the non-display area (PA). According to one embodiment, the pad portion of the non-display area (PA) may be electrically connected to a printed circuit board (PCB) including a driving chip (80), which will be explained in more detail below in FIG. 3.

[0045] As illustrated in FIG. 2, an adhesive layer (AD) that bonds the display panel (DP) and the cover window (WU) may be located between the display panel (DP) and the cover window (WU). The adhesive layer (AD) may not be located in the aperture area (DTA) where the display panel (DP) is not formed. This is because light loss may occur if the adhesive layer (AD) is located when light is incident on a first electronic module (ES1), such as a camera, so the adhesive layer (AD) may be omitted in the part corresponding to the aperture area (DTA).

[0046] Meanwhile, the display panel (DP) may further include a touch sensor capable of detecting a user's touch. The touch sensor may be located on the front of a pixel (PX) and may include at least one touch electrode. Various methods may be applied to the touch sensor included in this embodiment, such as a resistive method or a capacitive method. A capacitive touch sensor may detect a touch using a single touch electrode (self-capacitance method) or detect a touch using a pair of touch electrodes (mutual-capacitance method).

[0047] The electronic module (ES) includes various functional modules for operating the display device (1000). The electronic module (ES) may be electrically connected to the display panel (DP) through connectors not shown, etc. For example, the electronic module (ES) may be a camera, a speaker, or a sensing sensor such as light or heat.

[0048] The electronic module (ES) may include a first electronic module (ES1) and a second electronic module (ES2).

[0049] The first electronic module (ES1) may be a camera that captures an external subject received through the aperture area (DTA) and / or the first hole area (HA1). Information captured by the first electronic module (ES1) may be stored in a storage unit (not shown). According to an embodiment, the first electronic module (ES1) may receive an external input transmitted through the aperture area (DTA) and the first hole area (HA1) or provide an output through the aperture area (DTA) and the first hole area (HA1). Referring to FIG. 2, the first electronic module (ES1) may be located within the aperture area (DTA) penetrating the display panel (DP) and is positioned to capture the front of the display device (1000) through the cover window (WU).

[0050] The second electronic module (ES2) may include, for example, one or more of a light-emitting module, a light-sensing module, and an acoustic output module. The second electronic module (ES2) may include a light-emitting module that outputs infrared light or a CMOS sensor for infrared detection, or a receiver that provides the other party's voice during a call. Depending on the embodiment, it may also include an acoustic input module such as a microphone. However, this is illustrated as an example, and the electronic module (ES) may be composed of a single module, may include a larger number of additional electronic modules, may be arranged in various configurations, and is not limited to any one embodiment.

[0051] A housing member (HM) is positioned below a display panel (DP). The housing member (HM) is combined with a cover window (WU) to form the exterior of a display device (1000). The housing member (HM) may include a material having relatively high rigidity. For example, the housing member (HM) may include a plurality of frames and / or plates made of glass, plastic, or metal. The housing member (HM) provides a predetermined receiving space. The display panel (DP) can be received within the receiving space and protected from external impact.

[0052] Below, the structure of a display panel (DP) including an opening area (DTA) is examined in detail through Fig. 3.

[0053] FIG. 3 is a plan view illustrating some components of a display panel according to one embodiment.

[0054] Referring to FIG. 3, the display panel (DP) can be divided into a display area (DA) and a non-display area (PA), and the non-display area (PA) can be defined along the border of the display area (DA). An opening area (DTA) is located within the display area (DA).

[0055] A display panel (DP) includes a plurality of pixels (PX). The plurality of pixels (PX) may be arranged within a display area (DA). Each pixel (PX) includes a light-emitting element and a pixel circuit connected thereto. Each pixel (PX) emits, for example, red, green, blue, or white light and may include, as an example, an organic light-emitting diode.

[0056] The display panel (DP) may include a plurality of signal lines and pad portions. The plurality of signal lines may include a scan line (SL) extended in a first direction (DR1), a data line (DL) extended in a second direction (DR2), and a driving voltage line (PL), etc.

[0057] Scan driving units (20) are located on the left and right sides of the display area (DA) and generate and transmit scan signals to each pixel (PX) through scan lines (SL). Referring to FIG. 4, pixels (PX) other than those located on the left and right sides of the aperture area (DTA) along the first direction (DR1) can receive scan signals together from two scan driving units (20) located on the left and right sides. Meanwhile, pixels (PX) located on the left and right sides of the aperture area (DTA) can receive scan signals only from the scan driving unit (20) located on one side. The connection relationship between the pixels (PX) and the scan lines (SL) can be examined in more detail as follows. The scan lines (SL) of the pixels (PX) other than those located on the left and right sides of the aperture area (DTA) can be electrically connected to both scan driving units (20) located on both sides. In contrast, the scan lines (SL) of the pixels (PX) located on the left and right sides of the aperture area (DTA) are electrically connected only to the scan drive unit (20) on one side. The scan lines (SL) connected to the pixels (PX) located on the left and right sides of the aperture area (DTA) are disconnected on the left and right sides with respect to the aperture area (DTA). That is, the scan lines (SL) connected to the pixel (PX) located on the left side of the aperture area (DTA) and the scan lines (SL) connected to the pixel (PX) located on the right side of the aperture area (DTA) are electrically disconnected from each other in the aperture area (DTA). As a result, the scan line (SL) of the pixel (PX) located to the left of the aperture area (DTA) is electrically connected only to the scan drive unit (20) located to the left of the display area (DA), and the scan line (SL) of the pixel (PX) located to the right of the aperture area (DTA) is electrically connected only to the scan drive unit (20) located to the right of the display area (DA).

[0058] The pad portion (PAD) is positioned at one end of the display panel (DP) and includes a plurality of terminals (P1, P2, P3, P4). The pad portion (PAD) is exposed without being covered by an insulating layer and can be electrically connected to a printed circuit board (PCB). The pad portion (PAD) can be electrically connected to a pad portion (PCB_P) of the printed circuit board (PCB). The printed circuit board (PCB) can transmit a signal or power of an IC driver chip (80) to the pad portion (PAD).

[0059] The control unit converts multiple video signals transmitted from the outside into multiple video data signals and transmits the converted signals to the data driving unit (50) through terminal (P1). Additionally, the control unit receives a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generates a control signal to control the operation of the scan driving unit (20) and the data driving unit (50), and transmits it to each through terminals (P3, P1). The control unit transmits a driving voltage (ELVDD) to the driving voltage supply wiring (60) through terminal (P2). Additionally, the control unit transmits a common voltage (ELVSS) to each of the common voltage supply wirings (70) through terminal (P4).

[0060] The data driving unit (50) is positioned on the non-display area (PA) and generates a data voltage (DATA) to be applied to each pixel (PX) and transmits it to each data line (DL). The data driving unit (50) may be positioned on one side of the display panel (DP), for example, between the pad unit (PAD) and the display area (DA). Referring to FIG. 4, the data lines (DL) connected to the remaining pixels (PX), excluding the pixels (PX) located on the upper and lower sides of the aperture area (DTA) along the second direction (DR2), may have a straight structure extending along the second direction (DR2). In contrast, the data lines (DL) connected to the pixels (PX) located on the upper and lower sides of the aperture area (DTA) extend along the second direction (DR2), but may include a portion (refer to RDL in FIG. 4) that extends along the periphery of the aperture area (DTA).

[0061] The driving voltage supply wiring (60) is positioned on the non-display area (PA). For example, the driving voltage supply wiring (60) may be positioned between the data driving unit (50) and the display area (DA). The driving voltage supply wiring (60) provides a driving voltage (ELVDD) to the pixels (PX). The driving voltage supply wiring (60) is positioned in a first direction (DR1) and may be connected to a plurality of driving voltage lines (PL) positioned in a second direction (DR2).

[0062] The common voltage supply wiring (70) is placed on the non-display area (PA). The common voltage supply wiring (70) may have a shape that surrounds the substrate (SUB). The common voltage supply wiring (70) delivers a common voltage (ELVSS) to one electrode (e.g., a second electrode) of the light-emitting element containing the pixel (PX).

[0063] Below, the area A including the opening area (DTA) shown in FIG. 3 will be described in detail with reference to FIG. 4.

[0064] Figure 4 is an enlarged plan view of area A of Figures 1 and 3.

[0065] Referring to FIG. 4, the display panel (DP) includes a plurality of signal lines (SL, DL) and a plurality of pixels (PX) located on a substrate. Each of the plurality of pixels (PX) can be connected to a plurality of signal lines (SL, DL). Although FIG. 4 briefly illustrates that one pixel (PX) is connected to one scan line (SL), the actual pixel (PX) can be connected to a plurality of scan lines (SL).

[0066] The hole area (HA) included in the display panel (DP) includes an aperture area (DTA) and a surrounding area (LA) encircling the aperture area (DTA). A pixel (PX) is located outside the hole area (HA) and corresponds to the display area (DA).

[0067] The periphery area (LA) is an area that encloses the outer edge of the opening area (DTA) and is an intermediate area between the marked area (DA) and the opening area (DTA). The periphery area (LA) includes a first periphery area (LA1) and a second periphery area (LA2). In FIG. 4, the dotted circle indicates the boundary of the hole area (HA) and the boundary separating the first periphery area (LA1) and the second periphery area (LA2).

[0068] The first peripheral area (LA1) includes an area where a laser is irradiated to remove a portion of the layer, and also includes the dams (D1, D2). The laser is irradiated on the dams (D1, D2) and their surroundings. The first peripheral area (LA1) is a part that prevents damage to the components and wiring located in the display area (DA) even if the laser is irradiated and the process of cutting the aperture area (DTA) is subsequently carried out.

[0069] The second peripheral area (LA2) is an area where a portion (RDL; hereinafter also referred to as a bypass portion) is placed, which is extended along the periphery of the aperture area (DTA) by the data line (DL). As a result, even if the data line (DL) cannot have a straight structure due to the aperture area (DTA), multiple pixels (PX) located above and below the aperture area (DTA) are connected by a single data line (DL) due to the portion (RDL) that is bent along the periphery of the aperture area (DTA).

[0070] The first peripheral area (LA1) is located closer to the opening area (DTA) than the second peripheral area (LA2), and the second peripheral area (LA2) is located closer to the display area (DA) than the first peripheral area (LA1).

[0071] Meanwhile, in this embodiment, the scan line (SL) is not formed in the second peripheral area (LA2) and therefore does not include a bypass structure. That is, the scan line (SL) connected to the pixels (PX) located to the left and right of the aperture area (DTA) is disconnected on the left and right sides with the aperture area (DTA) as the center. However, depending on the embodiment, the scan line (SL) may also form a bypass portion in the second peripheral area (LA2) while the left and right scan lines (SL) are connected to each other.

[0072] Below, we will examine the circuit structure of a pixel according to one embodiment through FIG. 5.

[0073] FIG. 5 is a circuit diagram of a pixel according to one embodiment.

[0074] A single pixel (PX) includes a pixel circuit unit comprising a plurality of transistors and a capacitor, and a light-emitting diode that receives current from the pixel circuit unit and emits light.

[0075] As illustrated in FIG. 5, one pixel (PX) of a display device according to one embodiment includes a plurality of transistors (T1, T2, T3, T4, T5, T6, T7), a holding capacitor (Cst), a boost capacitor (Cbt), and a light-emitting diode (LED) connected to multiple wires (127, 151, 152, 153, 154, 155, 171, 172, 741).

[0076] A plurality of wires (127, 151, 152, 153, 154, 155, 171, 172, 741) are connected to a single pixel (PX). The plurality of wires includes a first initialization voltage line (127), a first scan signal line (151), a second scan signal line (152), an initialization control line (153), a bypass control line (154), a light emission control line (155), a data line (171), a driving voltage line (172), and a common voltage line (741).

[0077] The wiring briefly illustrated as a scan line (SL) in FIGS. 3 and 4 is specifically divided and illustrated in FIG. 5 as a first initialization voltage line (127), a first scan signal line (151), a second scan signal line (152), an initialization control line (153), a bypass control line (154), and a light emission control line (155).

[0078] The first scan signal line (151) is connected to the scan driver and transmits the first scan signal (GW) to the second transistor (T2). The second scan signal line (152) may have the same wiring as the first scan signal line (151) and transmits the second scan signal (GC), which is the same scan signal as the first scan signal (GW), to the third transistor (T3).

[0079] The initialization control line (153) transmits an initialization control signal (GI) to the fourth transistor (T4). The bypass control line (154) transmits a bypass signal (GB) to the seventh transistor (T7). The bypass control line (154) may be composed of the first scan signal line (151) of the preceding stage. The light emission control line (155) transmits a light emission control signal (EM) to the fifth transistor (T5) and the sixth transistor (T6).

[0080] The data line (171) corresponds to the data line (DL) of FIGS. 3 and FIGS. 4, and is a wiring that transmits the data voltage (DATA) generated by the data driving unit (50), and the brightness of the light-emitting diode (LED) changes according to the data voltage (DATA) applied to the pixel (PX).

[0081] The driving voltage line (172) corresponds to the driving voltage line (PL) of FIG. 3 and applies a driving voltage (ELVDD). The first initialization voltage line (127) transmits a first initialization voltage (VINT). The common voltage line (741) applies a common voltage (ELVSS) to the cathode electrode of the light-emitting diode (LED). In this embodiment, the voltages applied to the driving voltage line (172), the first initialization voltage line (127), and the common voltage line (741) may each be constant voltages.

[0082] A plurality of transistors included in the pixel circuit may include a driving transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). A plurality of transistors may include polycrystalline silicon semiconductors.

[0083] The second transistor (T2) is a transistor that transmits data voltage (DATA) into the pixel (PX), the fourth transistor (T4) is a transistor that initializes the voltage of the gate electrode of the driving transistor (T1) to the first initialization voltage (VINT), and the seventh transistor (T7) is a transistor that initializes the anode voltage of the light-emitting diode (LED) to the first initialization voltage (VINT).

[0084] The fifth transistor (T5) transmits the driving voltage (ELVDD) to the driving transistor (T1), and the sixth transistor (T6) transmits the output current of the driving transistor (T1) to the light-emitting diode (LED), and the section in which the fifth transistor (T5) and the sixth transistor (T6) are turned on may be the light-emitting section.

[0085] The third transistor (T3) connects the gate electrode and the output electrode of the driving transistor (T1) to each other, so that the data voltage (DATA) passes through the driving transistor (T1) and is stored in the holding capacitor (Cst) connected to the gate electrode of the driving transistor (T1). At this time, the voltage finally stored in the holding capacitor (Cst) can be a voltage value in which the threshold voltage of the driving transistor (T1) is compensated.

[0086] The driving transistor (T1) generates and outputs an output current based on the voltage stored in the holding capacitor (Cst).

[0087] The boost capacitor (Cbt) performs the function of lowering the voltage of the gate electrode of the driving transistor (T1) when the first scan signal (GW) applied to the first scan signal line (151) changes to a low voltage and turns on the second transistor (T2). As a result, the driving transistor (T1) can reliably maintain the turned-on state.

[0088] Although it has been described above that one pixel (PX) includes seven transistors (T1 to T7), one holding capacitor (Cst), and one boost capacitor (Cbt), it is not limited thereto, and the number of transistors, the number of capacitors, and their connection relationships can be varied. In particular, according to the embodiment, transistors such as the third transistor (T3), the fourth transistor (T4), and / or the seventh transistor (T7) may include an oxide semiconductor having N-MOS characteristics as a semiconductor layer and may be turned on when a high-level voltage is delivered to the gate electrode.

[0089] Below, we will examine the cross-sectional structure of the display panel through Figures 6 to 8.

[0090] FIG. 6 is a cross-sectional view of a pixel included in a display area of ​​a display panel according to one embodiment, FIG. 7 is a cross-sectional view of a display panel where a peripheral area and an aperture area are located of a display panel according to one embodiment, and FIG. 8 is an enlarged cross-sectional view of a portion of a display panel according to one embodiment where a functional layer and a second electrode have been removed.

[0091] First, regarding the cross-sectional structure of the display panel, we examine the cross-sectional structure of the display area (DA) through Fig. 6.

[0092] A substrate (SUB) according to one embodiment may include an inorganic insulating material such as glass or an organic insulating material such as plastic such as polyimide (PI). The substrate (SUB) may be a single layer or a multilayer. The substrate (SUB) may have a structure in which at least one base layer comprising a sequentially stacked polymer resin and at least one inorganic layer are alternately stacked.

[0093] The substrate (SUB) can have varying degrees of flexibility. The substrate (SUB) can be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc.

[0094] A buffer layer (BF) may be located on the substrate (SUB). The buffer layer (BF) can prevent the transfer of impurities from the substrate (SUB) to the upper layer of the buffer layer (BF), particularly the semiconductor layer (SC), thereby preventing the degradation of the semiconductor layer (SC)'s characteristics and relieving stress. The buffer layer (BF) may include an inorganic insulating material, such as silicon nitride or silicon oxide, or an organic insulating material. Part or all of the buffer layer (BF) may be omitted. Depending on the embodiment, a metal layer (not shown) may be formed between the substrate (SUB) and the buffer layer (BF). The metal layer may be formed to maintain the characteristics of the semiconductor layer (SC).

[0095] A semiconductor layer (SC) is located on a buffer layer (BF). The semiconductor layer (SC) may include polycrystalline silicon. The semiconductor layer (SC) includes a channel region (C), a first region (S), and a second region (D). The first region (S) and the second region (D) are each positioned on either side of the channel region (C). The channel region (C) is a semiconductor region that is doped with a small amount of impurities or is not doped with impurities compared to the first region (S) and the second region (D), and the first region (S) and the second region (D) are semiconductor regions that are doped with a large amount of impurities compared to the channel region (C).

[0096] A first inorganic insulating layer (IL1) is located on the semiconductor layer (SC). The first inorganic insulating layer (IL1) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may have a single-layer or multi-layered structure including at least one of ).

[0097] A first gate conductive layer (GAT1) comprising a gate electrode (GE) and a first capacitor electrode (CE1) is located on the first inorganic insulating layer (IL1). The first gate conductive layer (GAT1) may be a single layer or a multilayer film in which a metal film comprising any one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, titanium (Ti), and titanium alloy is stacked. The gate electrode (GE) may overlap with the channel region (C) of the planar semiconductor layer (SC).

[0098] A second inorganic insulating layer (IL2) is located on the first gate conductive layer (GAT1) and the first inorganic insulating layer (IL1). The second inorganic insulating layer (IL2) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0099] A second gate conductive layer (GAT2) comprising an upper electrode (AE) and a second capacitor electrode (CE2) is positioned on the second inorganic insulating layer (IL2). The second capacitor electrode (CE2) and the upper electrode (AE) may be different parts of a single conductive pattern. The second capacitor electrode (CE2) and the upper electrode (AE) may be electrically connected. The second gate conductive layer (GAT2) may be a single layer or a multilayer film in which a metal film comprising any one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, titanium (Ti), and titanium alloy is stacked.

[0100] The first capacitor electrode (CE1) and the second capacitor electrode (CE2) overlap to form a holding capacitor (Cst).

[0101] A third inorganic insulating layer (IL3) is located on the second gate conductive layer (GAT2) and the second inorganic insulating layer (IL2). The third inorganic insulating layer (IL3) is silicon oxide (SiO₂).x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0102] A first data conductive layer (SD1) comprising a source electrode (SE) and a drain electrode (DE) is positioned on a third inorganic insulating layer (IL3). The source electrode (SE) and the drain electrode (DE) can be electrically connected to the first region (S) and the second region (D) of the semiconductor layer (SC), respectively, through contact holes formed in the third inorganic insulating layer (IL3) and the first and second inorganic insulating layers (IL1, IL2). According to an embodiment, the semiconductor layer (SC) can be directly extended without the source electrode (SE) and the drain electrode (DE) and can be electrically connected to an adjacent pixel. The first data conductive layer (SD1) may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or a multilayer structure including the above. The first data conductive layer (SD1) of the present embodiment has a triple-layer structure in which aluminum (Al) is disposed between two layers of titanium (Ti), and the following description focuses on the triple-layer structure of Ti / Al / Ti.

[0103] A first organic insulating layer (IL4) and a second organic insulating layer (IL5) are sequentially positioned on the third inorganic insulating layer (IL3) and the first data conductive layer (SD1). The first organic insulating layer (IL4) and the second organic insulating layer (IL5) may include organic insulating materials such as general-purpose polymers like polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide, acrylic polymers, siloxane polymers, etc.

[0104] A connecting member (CE) may be located between the first organic insulating layer (IL4) and the second organic insulating layer (IL5). The connecting member (CE) constitutes the second data conductive layer (SD2) and can connect the drain electrode (DE) and the first electrode (E1). The second data conductive layer (SD2) may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multilayer structure containing these. The second data conductive layer (SD2) of this embodiment has a triple-layer structure in which aluminum (Al) is disposed between two layers of titanium (Ti), similar to the first data conductive layer (SD1), and the following description will focus on the Ti / Al / Ti triple-layer structure.

[0105] A first electrode (E1; hereinafter also referred to as a pixel electrode or anode electrode) is positioned on the second organic insulating layer (IL5). The first electrode (E1) forms a pixel electrode layer (PXL) and is connected to a connecting member (CE) through a contact hole in the second organic insulating layer (IL5). The first electrode (E1) is electrically connected to a drain electrode (DE). The first electrode (E1) may include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), and gold (Au), and may also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The first electrode (E1) may be composed of a single layer containing a metal material or a transparent conductive oxide, or a multilayer containing these. The first electrode (E1) in this embodiment may have a triple film structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO), and the structure of ITO / Ag / ITO will be described below.

[0106] The gate electrode (GE) and the semiconductor layer (SC) constitute a transistor, and depending on the transistor, it may include a source electrode (SE) and a drain electrode (DE) that are electrically connected to the first region (S) and the second region (D) of the semiconductor layer (SC). Depending on the transistor, the transistor may be composed only of the gate electrode (GE) and the semiconductor layer (SC) without the source electrode (SE) and the drain electrode (DE). The transistor (the sixth transistor (T6) in FIG. 5) is connected to the first electrode (E1) to supply current to a light-emitting element (LED).

[0107] A pixel defining film (IL6) and a spacer (IL7) are located on top of the second organic insulating layer (IL5) and the first electrode (E1).

[0108] The pixel defining film (IL6) has an opening that overlaps with at least a portion of the first electrode (E1) and defines a light-emitting region. The opening may have a planar shape similar to the first electrode (E1). The opening may have a planar rhombus or an octagonal shape similar to a rhombus, but is not limited thereto and may have any shape such as a square, polygon, circle, or ellipse.

[0109] The pixel definition film (IL6) and spacer (IL7) may include organic insulating materials such as general-purpose polymers like polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide, acrylic polymers, and siloxane polymers.

[0110] An intermediate layer (EL) is located on the pixel defining film (IL6), spacer (IL7), and first electrode (E1). The intermediate layer (EL) may include an emitting layer (EML) and a functional layer (FL). The emitting layer (EML) of the intermediate layer (EL) may generate a predetermined colored light. The emitting layer (EML) may include organic materials and / or inorganic materials. In this embodiment, the emitting layer (EML) is formed only within the opening of the pixel defining film (IL6).

[0111] Meanwhile, the functional layer (FL) among the intermediate layer (EL) may include at least one of a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL). The functional layer (FL) may be divided into a first functional layer (FL1) located between the first electrode (E1) and the light-emitting layer, and a second functional layer (FL2) located between the light-emitting layer and the second electrode (E2). Each functional layer (FL) may have a shape that overlaps with the front surface of the substrate (SUB). The functional layer (FL) may be arranged across a plurality of pixels.

[0112] A second electrode (E2) is located on the intermediate layer (EL). The second electrode (E2) may include a reflective metal including calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), etc., or a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0113] The first electrode (E1), the intermediate layer (EL), and the second electrode (E2) can constitute a light-emitting element (LED). Here, the first electrode (E1) may be an anode, which is a hole injection electrode, and the second electrode (E2) may be a cathode, which is an electron injection electrode. However, the embodiments are not necessarily limited thereto, and depending on the driving method of the light-emitting display device, the first electrode (E1) may be a cathode and the second electrode (E2) may be an anode.

[0114] Holes and electrons are injected into the intermediate layer (EL) from the first electrode (E1) and the second electrode (E2), respectively, and light emission occurs when the exciton formed by the combination of the injected holes and electrons falls from the excited state to the ground state.

[0115] An encapsulation layer (ENC) is positioned on the second electrode (E2). The encapsulation layer (ENC) can cover and seal not only the top surface but also the sides of the light-emitting element (LED). Since the light-emitting element is very vulnerable to moisture and oxygen, the encapsulation layer (ENC) seals the light-emitting element (LED) to block the ingress of external moisture and oxygen.

[0116] The encapsulation layer (ENC) may include multiple layers, and may be formed as a composite membrane including both an inorganic layer and an organic layer, and as an example, may be formed as a triple layer in which a first encapsulation inorganic layer (EIL1), an encapsulation organic layer (EOL), and a second encapsulation inorganic layer (EIL2) are formed sequentially.

[0117] The first encapsulating inorganic layer (EIL1) can cover the second electrode (E2). The first encapsulating inorganic layer (EIL1) can prevent external moisture or oxygen from penetrating into the light-emitting element (LED). For example, the first encapsulating inorganic layer (EIL1) may include silicon nitride, silicon oxide, or a compound combining these. The first encapsulating inorganic layer (EIL1) can be formed through a deposition process.

[0118] The encapsulating organic layer (EOL) is disposed on the first encapsulating inorganic layer (EIL1) and can come into contact with the first encapsulating inorganic layer (EIL1). Curvatures formed on the upper surface of the first encapsulating inorganic layer (EIL1) or particles present on the first encapsulating inorganic layer (EIL1) are covered by the encapsulating organic layer (EOL), thereby blocking the influence of the surface condition of the upper surface of the first encapsulating inorganic layer (EIL1) on the components formed on the encapsulating organic layer (EOL). Additionally, the encapsulating organic layer (EOL) can relieve stress between the contacting layers. The encapsulating organic layer (EOL) may contain organic material and can be formed through solution processes such as spin coating, slit coating, or inkjet processes.

[0119] The second encapsulating inorganic layer (EIL2) is placed on the encapsulating organic layer (EOL) to cover the encapsulating organic layer (EOL). The second encapsulating inorganic layer (EIL2) can be stably formed on a relatively flat surface compared to the one placed on the first encapsulating inorganic layer (EIL1). The second encapsulating inorganic layer (EIL2) encapsulates moisture, etc. released from the encapsulating organic layer (EOL) to prevent it from entering to the outside. The second encapsulating inorganic layer (EIL2) may include silicon nitride, silicon oxide, or a compound combining these. The second encapsulating inorganic layer (EIL2) can be formed through a deposition process.

[0120] Although not illustrated in this specification, a capping layer located between the second electrode (E2) and the encapsulation layer (ENC) may be further included. The capping layer may include an organic material. The capping layer protects the second electrode (E2) from a subsequent process, such as a sputtering process, and improves the light emission efficiency of the light-emitting element (LED). The capping layer may have a higher refractive index than the first encapsulation inorganic layer (EIL1).

[0121] Although only one transistor is shown in Fig. 6, each actual pixel may include multiple transistors as shown in Fig. 5.

[0122] The cross-sectional structure of the display area (DA) as described above can have a cross-sectional structure as shown in Fig. 7 as it extends to the surrounding area (LA) and the opening area (DTA).

[0123] FIG. 7 further illustrates additional insulating layers (additional overcoat layer (YOC), additional inorganic insulating layer (YILD), and additional planarization layer (YPVX)) covering the surrounding area (LA) and display area (DA), while clearly showing that nothing is formed in the opening area (DTA). Depending on the embodiment, at least some of the additional insulating layers may be omitted, and with reference to FIG. 22, the structure may have only the additional planarization layer (YPVX) formed as an additional insulating layer without the additional overcoat layer (YOC) and the additional inorganic insulating layer (YILD). Depending on the embodiment, a touch electrode may be additionally formed between the encapsulation layer (ENC) and the additional planarization layer (YPVX) in the display area (DA) to detect touch.

[0124] The surrounding area (LA) is divided into a first surrounding area (LA1) and a second surrounding area (LA2). In FIG. 7, the width of the first surrounding area (LA1) is depicted as being narrower than that of the second surrounding area (LA2), but depending on the embodiment, it may be formed with various widths and is not limited thereto.

[0125] The first peripheral region (LA1) includes a dam (D1, D2) and includes a region where the functional layer (FL) and the second electrode (E2) are removed (first open region (R1), second open region (R2), and third open region (R3)). Additionally, the first peripheral region (LA1) also includes a region where a laser is irradiated onto a sacrificial layer (SFL; see FIG. 10 and FIG. 11) to form the region where the functional layer (FL) and the second electrode (E2) are removed (first open region (R1), second open region (R2), and third open region (R3)). The laser may be irradiated across the dam (D1, D2) and the region where the functional layer (FL) and the second electrode (E2) are removed (first open region (R1), second open region (R2), and third open region (R3)). The first peripheral region (LA1) is a part that prevents damage to the components and wiring located in the display area (DA) even when a laser is irradiated and a process of cutting the aperture area (DTA) is subsequently performed.

[0126] The second peripheral region (LA2) is an area where a bypass section (RDL) is placed, which extends along the periphery of the aperture region (DTA) along the data line (DL). As a result, even if the data line (DL) cannot have a straight structure due to the aperture region (DTA), multiple pixels (PX) located above and below the aperture region (DTA) are connected by a single data line (DL) due to the bypass section (RDL) that bypasses along the periphery of the aperture region (DTA). In the embodiment of FIG. 7, the bypass section is located on the first data conductive layer (SD1) and is positioned above the third inorganic insulating layer (IL3).

[0127] In the peripheral region (LA), a buffer layer (BF), a first inorganic insulating layer (IL1), and a second inorganic insulating layer (IL2) are continuously extended from the display region (DA) on the substrate (SUB). Additionally, the third inorganic insulating layer (IL3) also has a form that is continuously extended from the display region (DA), but in the first peripheral region (LA1), the functional layer (FL) and the second electrode (E2) are removed in the region (first open region (R1), second open region (R2), and third open region (R3)), the thickness is reduced. This structure is because when forming the first open region (R1), second open region (R2), and third open region (R3), the functional layer (FL) and the second electrode (E2) are removed along with the sacrificial layer (SFL) formed of metal, and a portion of the third inorganic insulating layer (IL3) located underneath them is also removed. According to the embodiment, the third inorganic insulating layer (IL3) is made of silicon oxide (SiO2). x A third-1 inorganic insulating layer (IL3-1) formed of ) and silicon nitride (SiN) located thereon x It may have a double-layer structure including a third-2 inorganic insulating layer (IL3-2) formed by ). Referring to FIG. 8, in the third inorganic insulating layer (IL3) of the double-layer structure, the third-2 inorganic insulating layer (IL3-2) is removed in the first open region (R1), the second open region (R2), and the third open region (R3) of the first peripheral region (LA1), and only the third-1 inorganic insulating layer (IL3-1) may remain.

[0128] In the second peripheral region (LA2), a bypass layer (RDL) is located on top of the third inorganic insulating layer (IL3), and a first organic insulating layer (IL4), a second organic insulating layer (IL5), a pixel defining layer (IL6), a spacer (IL7), a functional layer (FL), a second electrode (E2), and an encapsulation layer (ENC) are formed continuously thereon. Additionally, an additional insulating layer, an additional overcoat layer (YOC), an additional inorganic insulating layer (YILD), and an additional planarization layer (YPVX) may be further formed on top of the encapsulation layer (ENC).

[0129] Meanwhile, the first surrounding area (LA1) has a different layered structure in the area where the dam (D1, D2) is located and in the area where the functional layer (FL) and the second electrode (E2) are removed (first open area (R1), second open area (R2) and third open area (R3)).

[0130] First, the layered structure of the areas where the functional layer (FL) and the second electrode (E2) have been removed (first open area (R1), second open area (R2) and third open area (R3)) is as follows.

[0131] In the first open region (R1), the second open region (R2), and the third open region (R3), a substrate (SUB), a buffer layer (BF), a first inorganic insulating layer (IL1), a second inorganic insulating layer (IL2), a third inorganic insulating layer (IL3), a first encapsulating inorganic layer (EIL1), and a second encapsulating inorganic layer (EIL2) are sequentially stacked. However, in the first open region (R1) located close to the display region (DA), an encapsulating organic layer (EOL) is further formed between the first encapsulating inorganic layer (EIL1) and the second encapsulating inorganic layer (EIL2). Depending on the embodiment, an encapsulating organic layer (EOL) may be further formed up to the second open region (R2) or the third open region (R3). However, since it is suitable for blocking moisture and oxygen for the organic bag layer (EOL) among the bag layers (ENC) to be formed so as not to be exposed to the outside, the ends of the organic bag layer (EOL) can be formed in a structure that is covered by the first inorganic bag layer (EIL1) and the second inorganic bag layer (EIL2) so as not to be exposed to the outside. In the embodiment of FIG. 7, the first inorganic bag layer (EIL1) and the second inorganic bag layer (EIL2) are in contact with each other above the first dam (D1). However, the location where the first inorganic bag layer (EIL1) and the second inorganic bag layer (EIL2) are in contact may be located near the second dam (D2).

[0132] The functional layer (FL) and the second electrode (E2) in the layered structure of the first open region (R1), the second open region (R2), and the third open region (R3) as described above have a structure that is open and broken in the first open region (R1), the second open region (R2), and the third open region (R3).

[0133] In the first open region (R1), the second open region (R2), and the third open region (R3), the structure has a reduced thickness of the third inorganic insulating layer (IL3). This structure may be formed when the first open region (R1), the second open region (R2), and the third open region (R3) are formed, by removing the functional layer (FL) and the second electrode (E2) along with the sacrificial layer formed of metal, and by removing a portion of the third inorganic insulating layer (IL3) located underneath. Additionally, according to the embodiment, the third inorganic insulating layer (IL3) may be silicon oxide (SiO₂). x A layer formed of ) (3-1 inorganic insulating layer (IL3-1)) and silicon nitride (SiN) on the same x In the case where the double layer structure of the layer formed by ) (3-2 inorganic insulating layer (IL3-2)) is present, as shown in FIG. 8, silicon nitride (SiN x The third-2 inorganic insulating layer (IL3-2) formed by ) is removed, and only the third-1 inorganic insulating layer (IL3-1) may remain.

[0134] The layered structure of the area where the dams (D1, D2) are located in the first surrounding area (LA1) is as follows.

[0135] At least two dams (D1, D2) may be located in the first surrounding area (LA1). For example, the first dam (D1) and the second dam (D2) may be located in order of proximity to the display area (DA). The first dam (D1) and the second dam (D2) are formed on a substrate (SUB), a buffer layer (BF), a first inorganic insulating layer (IL1), a second inorganic insulating layer (IL2), and a third inorganic insulating layer (IL3). The structure of each dam (D1, D2) located on the third inorganic insulating layer (IL3) is examined in detail as follows.

[0136] The first dam (D1) may include a first-1 subdam (D1-a), a first-2 subdam (D1-b), and a first-3 subdam (D1-c). The first-1 subdam (D1-a) may be located in the same layer as the second organic insulating layer (IL5) located in the display area (DA) and may contain the same material. The first-1 subdam (D1-a) may be formed in the same process as the second organic insulating layer (IL5) located in the display area (DA). The first-2 subdam (D1-b) may be located in the same layer as the pixel defining film (IL6) located in the display area (DA) and may contain the same material. The first-2 subdam (D1-b) may be formed in the same process as the pixel defining film (IL6) located in the display area (DA). The first-3rd subdam (D1-c) may be located in the same layer as the spacer (IL7) located in the marked area (DA) and may contain the same material. The first-3rd subdam (D1-c) may be formed in the same process as the spacer (IL7) located in the marked area (DA).

[0137] The second dam (D1) may include a second-1 subdam (D2-a), a second-2 subdam (D2-b), a second-3 subdam (D2-c), and a second-4 subdam (D2-d). The second-1 subdam (D2-a) may be located in the same layer as the first organic insulating layer (IL4) located in the display area (DA) and may contain the same material. The second-1 subdam (D2-a) may be formed in the same process as the first organic insulating layer (IL4) located in the display area (DA). The second-2 subdam (D2-b) may be located in the same layer as the second organic insulating layer (IL5) located in the display area (DA) and may contain the same material. The second-2 subdam (D2-b) may be formed in the same process as the second organic insulating layer (IL5) located in the display area (DA). The second-third subdam (D2-c) may be located in the same layer as the pixel defining film (IL6) located in the display area (DA) and may contain the same material. The second-third subdam (D2-c) may be formed in the same process as the pixel defining film (IL6) located in the display area (DA). The second-fourth subdam (D2-d) may be located in the same layer as the spacer (IL7) located in the display area (DA) and may contain the same material. The second-fourth subdam (D2-d) may be formed in the same process as the spacer (IL7) located in the display area (DA).

[0138] The present specification illustrates an embodiment in which the first dam (D1) is formed with a triple-layer structure and the second dam (D2) is formed with a quadruple-layer structure. However, it is not limited thereto, and the positions may be changed such that the first dam (D1) is formed with a quadruple-layer structure and the second dam (D2) is formed with a triple-layer structure, or both the first dam (D1) and the second dam (D2) may be formed with a triple-layer structure, or both the first dam (D1) and the second dam (D2) may be formed with a quadruple-layer structure. It is also obvious that a double-layer structure dam comprising only a part of the aforementioned sub-dam may be provided. Furthermore, although the present specification illustrates an embodiment in which two dams (D1, D2) are located in a surrounding area (LA), it is not limited to this number, and two or more dams may be located in the surrounding area (LA). Additionally, referring to FIG. 7, areas where the functional layer (FL) and the second electrode (E2) have been removed may be located on both sides of a single dam, but areas where the functional layer (FL) and the second electrode (E2) have been removed may be formed only on one side. As the number of dams changes, the number of areas where the functional layer (FL) and the second electrode (E2) have been removed may also change.

[0139] Meanwhile, the dams (D1, D2) described in this specification may have a ring shape that encloses the planar opening region (DTA) as shown in FIG. 4. Additionally, the regions from which the functional layer (FL) and the second electrode (E2) have been removed (first open region (R1), second open region (R2), and third open region (R3)) may also have a ring shape located on the planar dams (D1, D2). However, this is an exemplary form and may be provided with a polygon, an ellipse, or a closed line shape including at least some curves instead of a ring shape, or a shape including a plurality of partially disconnected patterns, and is not limited to any one embodiment.

[0140] A first-1 layer (FL-1) may be located on the first dam (D1). A first-2 layer (FL-2) may be located on the second dam (D2). A first-3 layer (FL-3) may be located between the second dam (D2) and the opening region (DTA). The first-1 layer (FL-1), the first-2 layer (FL-2), and the first-3 layer (FL-3) contain the same material as the functional layer (FL) and may be formed in the same process.

[0141] A second-1 layer (E2-1), a second-2 layer (E2-2), and a second-3 layer (E2-3) may be located on top of each of the first-1 layer (FL-1), the first-2 layer (FL-2), and the first-3 layer (FL-3). The second-1 layer (E2-1), the second-2 layer (E2-2), and the second-3 layer (E2-3) may contain the same material as the second electrode (E2) and may be formed in the same process.

[0142] A second open region (R2) is located between the continuously stacked first-1 layer (FL-1) and second-1 layer (E2-1) and the continuously stacked first-2 layer (FL-2) and second-2 layer (E2-2), and a third open region (R3) is located between the continuously stacked first-2 layer (FL-2) and second-2 layer (E2-2) and the continuously stacked first-3 layer (FL-3) and second-3 layer (E2-3). Additionally, the continuously stacked first-1 layer (FL-1) and second-1 layer (E2-1) are separated from the functional layer (FL) and the second electrode (E2) by the first open region (R1).

[0143] A first encapsulation inorganic layer (EIL1) extending from a display area (DA) may be located in the surrounding area (LA). Additionally, an end of an encapsulation organic layer (EOL) extending from the display area (DA) may be located therein. The first dam (D1) can control the spreading of the material during the process of forming the encapsulation organic layer (EOL). The encapsulation organic layer (EOL) may have a shape that fills the space between the end of the display area (DA) and the first dam (D1). A second encapsulation inorganic layer (EIL2) overlapping with the front surface of the substrate (SUB) may be located on the encapsulation organic layer (EOL).

[0144] In the first open region (R1), a first encapsulating inorganic layer (EIL1), an encapsulating organic layer (EOL), and a second encapsulating inorganic layer (EIL2) may be located on the first inorganic insulating layer (IL1). Additionally, in the second open region (R2), a first encapsulating inorganic layer (EIL1) and a second encapsulating inorganic layer (EIL2) may be located on the first inorganic insulating layer (IL1). Additionally, in the third open region (R3), a first encapsulating inorganic layer (EIL1) and a second encapsulating inorganic layer (EIL2) may be located on the first inorganic insulating layer (IL1).

[0145] The first electronic module described above can be inserted into the opening region (DTA) as shown in FIG. 2. The inner surface of the opening region (DTA) can be defined by the ends of a substrate (SUB), a buffer layer (BF), a first inorganic insulating layer (IL1), a second inorganic insulating layer (IL2), a third inorganic insulating layer (IL3), a first-third layer (FL-3), a second-first layer (E2-1), a first encapsulating inorganic layer (EIL1), a second encapsulating inorganic layer (EIL2), an additional overcoat layer (YOC), an additional inorganic insulating layer (YILD), and an additional planarization layer (YPVX). The substrate (SUB), buffer layer (BF), first inorganic insulating layer (IL1), second inorganic insulating layer (IL2), third inorganic insulating layer (IL3), first-third layer (FL-3), second-first layer (E2-1), first encapsulating inorganic layer (EIL1), second encapsulating inorganic layer (EIL2), additional overcoat layer (YOC), additional inorganic insulating layer (YILD), and additional planarization layer (YPVX) are cut together so that the ends of each layer are aligned with each other. However, this is not limited thereto, and it is understood that some of the aforementioned components may be omitted or added to form the inner surface of the opening region (DTA).

[0146] Below, through FIG. 8, we will examine in detail the first open region (R1), which is one of the regions where the functional layer (FL) and the second electrode (E2) have been removed, and its surroundings.

[0147] As illustrated in FIG. 8, the first open region (R1) is sequentially stacked with a substrate (SUB), a buffer layer (BF), a first inorganic insulating layer (IL1), a second inorganic insulating layer (IL2), a third inorganic insulating layer (IL3), a first encapsulating inorganic layer (EIL1), and an encapsulating organic layer (EOL). Referring to FIG. 7, a second encapsulating inorganic layer (EIL2) is also stacked on top of the encapsulating organic layer (EOL).

[0148] In the first open area (R1), only insulating layers are laminated, and some of the various insulating layers (first organic insulating layer (IL4), second organic insulating layer (IL5), pixel defining film (IL6), and spacer (IL7)) located above the third inorganic insulating layer (IL3) in the display area (DA) are removed. That is, when forming each insulating layer (IL4, IL5, IL6, IL7), the corresponding insulating layer (IL4, IL5, IL6, IL7) is removed in the open areas (R1, R2, R3).

[0149] The functional layer (FL) and the second electrode (E2) located on the spacer (IL7) are formed together with the same material as the first-1 layer (FL-1) and the second-1 layer (E2-1), but are separated while forming a first open region (R1), and are separated from each other based on the first open region (R1). The first-2 layer (FL-2), first-3 layer (FL-3), second-2 layer (E2-2), and second-3 layer (E2-3), each formed with the same material as the functional layer (FL) and the second electrode (E2), are also separated based on the second open region (R2) and the third open region (R3), respectively.

[0150] The first encapsulated inorganic layer (EIL1) located above the second electrode (E2) is formed continuously on both sides of the first open region (R1).

[0151] Below, we will examine the manufacturing sequence of the display panel through FIGS. 9 to 11.

[0152] FIG. 9 is a flowchart schematically illustrating a manufacturing process of a display panel according to one embodiment, FIG. 10 is a diagram sequentially illustrating a step of forming a sacrificial layer during a manufacturing process of a display panel according to one embodiment, and FIG. 11 is a diagram illustrating a step of removing a sacrificial layer and its surrounding layer through laser irradiation during a manufacturing process of a display panel according to one embodiment.

[0153] First, through FIG. 9, we briefly examine the stacking structure of the surrounding area (LA), focusing on the step of stacking each layer of the display area (DA) of the display panel. Each step (S10 to S100) illustrated in FIG. 9 corresponds to an etching process using a mask, and will be explained below with reference to FIG. 6.

[0154] After forming a buffer layer (BF) on the substrate (SUB), a semiconductor layer material is deposited, and the semiconductor layer (SC) is completed (S10) by etching using a mask. In this embodiment, the semiconductor layer (SC) can be formed as a polycrystalline semiconductor including polycrystalline silicon, and the final semiconductor layer (SC) can be formed by forming amorphous silicon entirely, changing it to polycrystalline silicon through a crystallization process, and then patterning it using a mask.

[0155] After forming a first inorganic insulating layer (IL1) on the buffer layer (BF) and semiconductor layer (SC), a material for a first gate conductive layer is stacked, and etched using a mask to complete a first gate conductive layer (GAT1) including a gate electrode (GE) and a first capacitor electrode (CE1) (S20).

[0156] After forming a second inorganic insulating layer (IL2) on top of the first inorganic insulating layer (IL1) and the first gate conductive layer (GAT1), a material for the second gate conductive layer is stacked and etched using a mask to complete the second gate conductive layer (GAT2) including the second capacitor electrode (CE2) (S30).

[0157] After forming the third inorganic insulating layer (IL3) entirely on the second inorganic insulating layer (IL2) and the second gate conductive layer (GAT2), an opening (CNT) is formed (S40) using a mask to expose the semiconductor layer (SC) in the first inorganic insulating layer (IL1), the second inorganic insulating layer (IL2), and the third inorganic insulating layer (IL3).

[0158] A material for the first data conductive layer is deposited on the third inorganic insulating layer (IL3), and the first data conductive layer (SD1) including the source electrode (SE) and the drain electrode (DE) is completed (S50) by etching using a mask. At this time, a pattern of the first data conductive layer (SD1) is formed in the first peripheral region (LA1), and the sacrificial layer (SFL) is completed through a subsequent process. The manufacturing step of the sacrificial layer (SFL) is examined in detail through FIG. 10.

[0159] After forming the first organic insulating layer (IL4) entirely on the third inorganic insulating layer (IL3) and the first data conductive layer (SD1), a mask is used to form the pattern of the first organic insulating layer (IL4) in the opening of the display area (DA) and the surrounding area (LA) (S60). The pattern of the first organic insulating layer (IL4) in the surrounding area (LA) includes the 2-1 subdam (D2-a), and the pattern of the first organic insulating layer (IL4) may not be formed in the other surrounding area (LA).

[0160] A material for a second data conductive layer is laminated on the first organic insulating layer (IL4), and a second data conductive layer (SD2) including a connecting member (CE) is completed (S70) by etching using a mask.

[0161] After forming the second organic insulating layer (IL5) entirely on the first organic insulating layer (IL4) and the second data conductive layer (SD2), a mask is used to form the pattern of the second organic insulating layer (IL5) in the opening of the display area (DA) and the surrounding area (LA) (S80). The pattern of the second organic insulating layer (IL5) in the surrounding area (LA) includes the first-1 subdam (D1-a) and the second-2 subdam (D2-b), and the pattern of the second organic insulating layer (IL5) may not be formed in the other surrounding area (LA).

[0162] A material for a pixel electrode layer is laminated on top of the second organic insulating layer (IL5), and a pixel electrode layer (PXL) including the first electrode (E1) is completed (S90) by etching using a mask.

[0163] After the material forming the pixel defining film (IL6) and spacer (IL7) on the second organic insulating layer (IL5) and the pixel electrode layer (PXL) is sequentially stacked as a whole, a pixel defining film (IL6) and spacer (IL7) pattern in the surrounding area (LA) is formed (S100) with an opening defining a light-emitting region that overlaps at least a portion of the first electrode (E1) in the display area (DA) and is formed using a mask. The pixel defining film (IL6) and spacer (IL7) pattern includes a first-2 subdam (D1-b), a first-3 subdam (D1-c), a second-3 subdam (D2-c), and a second-4 subdam (D2-d), and the pixel defining film (IL6) and spacer (IL7) pattern may not be formed in the other surrounding area (LA).

[0164] An intermediate layer (EL) and a second electrode (E2) are sequentially stacked over the pixel defining film (IL6) and the spacer (IL7). Among the intermediate layers (EL), the light-emitting layer (EML) is formed only within the opening of the pixel defining film (IL6), and the functional layer (FL) is formed over the entire substrate. As a result, the functional layer (FL) and the second electrode (E2) are formed in the surrounding area (LA) as well, and as shown in FIG. 11, through a laser irradiation step (S120), the functional layer (FL) and the second electrode (E2) have a structure that is disconnected from the first open area (R1), the second open area (R2), and the third open area (R3).

[0165] Before describing the laser irradiation step, we examine the step in which the sacrificial layer (SFL) of the first peripheral region (LA1) is completed through steps S50 to S90 through FIG. 10. The part illustrated in FIG. 10 corresponds to one of the first open region (R1), the second open region (R2), and the third open region (R3).

[0166] In FIG. 10, the third inorganic insulating layer (IL3) is silicon oxide (SiO₂). x A third-1 inorganic insulating layer (IL3-1) formed of ) and silicon nitride (SiN) located thereon x It is illustrated in detail as a double-layer structure including a third-second inorganic insulating layer (IL3-2) formed by ).

[0167] First, as shown in FIG. 10(a), in step S50, a first data conductive layer (SD1) pattern is formed on the third inorganic insulating layer (IL3) of the first peripheral region (LA1) using the same material as the first data conductive layer (SD1). The first data conductive layer (SD1) pattern has a triple-layer structure and consists of a first-1 data conductive layer (SD1-1), a first-2 data conductive layer (SD1-2), and a first-3 data conductive layer (SD1-3). In this embodiment, the first-1 data conductive layer (SD1-1) and the first-3 data conductive layer (SD1-3) contain titanium (Ti), and the first-2 data conductive layer (SD1-2) has a triple-layer structure containing aluminum (Al).

[0168] Referring to FIG. 10(a), while dry etching to form a pattern of a first data conductive layer (SD1), a third inorganic insulating layer (IL3) located beneath the pattern of the first data conductive layer (SD1) is partially etched, and its thickness is reduced by gd1. Here, the value of gd1 can be approximately 50 nm or more and 90 nm or less. Additionally, the third inorganic insulating layer (IL3) being etched is silicon nitride (SiN x The 3-2 inorganic insulating layer (IL3-2) is formed of ), and silicon oxide (SiO₂). x The third-1 inorganic insulating layer (IL3-1) formed by ) is not etched.

[0169] After that, through step S60, a first organic insulating layer (IL4) is formed in the display area (DA), but in the open areas (R1, R2, R3) of the surrounding area (LA), the first organic insulating layer (IL4) is removed after being laminated and is not formed.

[0170] In FIG. 10, the step of completing the second data conductive layer (S70) is divided into two steps to explain it more clearly. As shown in FIG. 10, the step of completing the second data conductive layer (S70) consists of a step of stacking a material for the second data conductive layer (S70-1) and a process of etching the material for the second data conductive layer (S70-2).

[0171] As shown in FIG. 10(b), a material for a second data conductive layer is laminated (S70-1) on a pattern of a first data conductive layer (SD1) of a triple layer located in an open area (R1, R2, R3). The material for the second data conductive layer forms a triple layer and consists of a second-1 data conductive layer (SD2-1), a second-2 data conductive layer (SD2-2), and a second-3 data conductive layer (SD2-3). In this embodiment, the second-1 data conductive layer (SD2-1) and the second-3 data conductive layer (SD2-3) include titanium (Ti), and the second-2 data conductive layer (SD2-2) has a triple layer structure including aluminum (Al), thus having the same triple layer structure as the first data conductive layer (SD1).

[0172] Subsequently, as shown in FIG. 10(c), a process (S70-2) for etching the material for the second data conductive layer in the display area (DA) is performed. At this time, the material for the second data conductive layer located in the open area (R1, R2, R3) is also dry-etched. In the open area (R1, R2, R3), as the stacked material for the second data conductive layer is dry-etched, the first-third data conductive layer (SD1-3), which is located at the top of the triple-layer first data conductive layer (SD1) pattern located underneath, is also removed, and the thickness of the first-second data conductive layer (SD1-2) is reduced. In addition, the third inorganic insulating layer (IL3) exposed during such dry etching is also partially etched, and its thickness is reduced by a total of gd2. Here, the value of gd2 can be approximately 100 nm or more and 180 nm or less. Furthermore, the third inorganic insulating layer (IL3) being etched is silicon nitride (SiN x The 3-2 inorganic insulating layer (IL3-2) is formed of ), and silicon oxide (SiO₂). x The third-1 inorganic insulating layer (IL3-1) formed by ) is not etched.

[0173] After that, through step S80, a second organic insulating layer (IL5) is formed in the display area (DA), but in the open areas (R1, R2, R3) of the surrounding area (LA), the second organic insulating layer (IL5) is removed after being laminated and is not formed.

[0174] After that, as shown in FIG. 10(d), when a pixel electrode layer (PXL) including a first electrode (E1) is completed (S90) by stacking a material for the pixel electrode layer in the display area (DA) and wet etching, the pixel electrode layer material is stacked in the open area (R1, R2, R3) of the surrounding area (LA) and then removed by wet etching, and the first-2 data conductive layer (SD1-2) remaining in the first data conductive layer (SD1) pattern is etched as the thickness decreases, thereby completing the final sacrificial layer (SFL). The sacrificial layer is the same layer as the first-1 data conductive layer (SD1-1) of the first data conductive layer (SD1) pattern and contains titanium (Ti). The sacrificial layer (SFL) is also called a dummy metal pattern, is not electrically connected to other components and is floating, and can have a shape similar to the shape of a dam in a plan view (e.g., a ring shape).

[0175] When the sacrificial layer (SFL) is completed in FIG. 10(d), the thickness of the exposed third inorganic insulating layer (IL3) may be the same as in FIG. 10(c), and the final thickness of the third inorganic insulating layer (IL3) may have a value reduced by about 180 nm or less from the thickness of the initially formed third inorganic insulating layer (IL3). The third-2 inorganic insulating layer (IL3-2) remaining in the first peripheral region (LA1) has a reduced thickness of about 100 nm or more and 180 nm or less, and may have a thickness of about 20 nm or more and 100 nm or less. In addition, the lower third-1 inorganic insulating layer (IL3-1) of the third inorganic insulating layer (IL3) is not etched, so its thickness is constant in the display region (DA) and the peripheral region (LA).

[0176] As described above, the step of partially removing the functional layer (FL) and the second electrode (E2) using the completed sacrificial layer (SFL) in the open area (R1, R2, R3) of the surrounding area (LA) is examined in detail through FIG. 11.

[0177] Step S100 of Fig. 9 is performed on the completed sacrificial layer (SFL) as shown in Fig. 10. That is, the material forming the pixel definition film (IL6) and spacer (IL7) on the sacrificial layer (SFL) is sequentially stacked as a whole and then etched and removed.

[0178] After that, the functional layer (FL) and the second electrode (E2) are sequentially stacked throughout, so that the functional layer (FL) and the second electrode (E2) are also formed on top of the sacrificial layer (SFL).

[0179] In the formed state, a laser (S110) is irradiated from below the substrate (SUB) as shown in FIG. 11(a). The laser is applied only to a portion of the surrounding region (LA) (the first surrounding region (LA1)). As shown in FIG. 11(b), the irradiated laser reacts with the sacrificial layer (SFL) formed of metal, causing the sacrificial layer (SFL) and the surrounding layers to detach. At this time, the functional layer (FL) and the second electrode (E2) detach together with the sacrificial layer (SFL), resulting in a structure separated around the open regions (R1, R2, R3). Additionally, as the sacrificial layer (SFL) detaches, a portion of the third inorganic insulating layer (IL3) located beneath it also detaches. If the third inorganic insulating layer (IL3) has a double-layer structure, only the upper third-2 inorganic insulating layer (IL3-2) may detach when the sacrificial layer (SFL) detaches. This is because silicon nitride (SiN x ) and silicon oxide (SiO x It may be detaching as it separates at the interface between them. As a result, as illustrated in Fig. 11(b), silicon oxide (SiO₂) in the open regions (R1, R2, R3) x Only the 3-1 inorganic insulating layer (IL3-1) formed of ) remains, and silicon nitride (SiN x The third-2 inorganic insulating layer (IL3-2) formed by ) can be removed.

[0180] Referring to FIG. 11, the open region (R1, R2, R3) is formed to be lower than the adjacent first peripheral region (LA1) by the thickness of the third-second inorganic insulating layer (IL3-2), the functional layer (FL), and the second electrode (E2). The thickness difference (gd3) between the open region (R1, R2, R3) and the adjacent first peripheral region (LA1) may be approximately 300 nm or more and 500 nm or less.

[0181] Since the laser being irradiated reacts with metal, it should not be irradiated into the marked area (DA), and it can also be prevented from being irradiated into the second surrounding area (LA2) due to the bypass area (RDL). The laser is irradiated in correspondence with a plurality of sacrificial layers (SFL) in the first surrounding area (LA1), and can also be irradiated into the dam (D1, D2) portion.

[0182] In order for the sacrificial layer (SFL) to react with the laser, it needs to be formed with a thickness greater than a certain amount, and if formed of titanium (Ti), the sacrificial layer (SFL) can have a thickness of about 20 nm or more.

[0183] According to the embodiments, lasers having different energy densities (ED) may be irradiated to the irradiated area. For example, a laser with a high energy density may be irradiated to the area where the sacrificial layer (SFL) is located, while a laser with a low energy density may be irradiated to other areas. The laser may be irradiated in a direction from the display area (DA) toward the area where the aperture area (DTA) is to be formed. Meanwhile, if the laser energy density is strong, the surrounding insulating layer may carbonize, approximately 1000 mJ / cm² 2 Lasers can be irradiated with the following energy densities.

[0184] Although FIGS. 10 and 11 illustrate and describe only one sacrificial layer (SFL), since one sacrificial layer (SFL) forms one opening area within the first surrounding area (LA1), it can be seen that in the embodiment of FIG. 7, a total of three sacrificial layers (SFL) are formed and then removed, resulting in a structure in which a total of three open areas (R1, R2, R3) are formed. Additionally, the sacrificial layers (SFL) and the open areas (R1, R2, R3) are formed at locations that do not overlap with the dams (D1, D2) and may be located between the dams (D1, D2).

[0185] After the process as shown in FIG. 11 is performed, referring to FIG. 7, a first encapsulating inorganic layer (EIL1) can be formed on the front surface of the substrate (SUB). Additionally, an encapsulating organic layer (EOL) can be formed to be located in a part of the surrounding area (LA) while overlapping with the display area (DA). In the process of forming the encapsulating organic layer (EOL), the liquid organic material can be prevented from spreading by dams (D1, D2). The encapsulating organic layer (EOL) can be formed by an inkjet method of applying the liquid organic material onto the first encapsulating inorganic layer (EIL1). At this time, the dams (D1, D2) set the boundary of the area where the liquid organic material is applied and prevent the liquid organic material from overflowing outside the dams (D1, D2).

[0186] Subsequently, a second encapsulating inorganic layer (EIL2) may be formed on the encapsulating organic layer (EOL) to overlap with the front surface of the substrate (SUB). The first encapsulating inorganic layer (EIL1) and the second encapsulating inorganic layer (EIL2) may come into contact with each other in the surrounding area (LA).

[0187] An additional overcoat layer (YOC) and an additional inorganic insulating layer (YILD) may be sequentially laminated on top of the second encapsulating inorganic layer (EIL2), in a part of the display area (DA), and in the surrounding area (LA). Additionally, an additional planarization layer (YPVX) may be laminated over the entire display panel. According to an embodiment, a touch electrode may be additionally formed between the encapsulating layer (ENC) and the additional planarization layer (YPVX) in the display area (DA) to detect touch.

[0188] After the display panel is completed in this manner, a process is performed to form an aperture area (DTA) for placing a first electronic module (ES1), such as a camera. The aperture area (DTA) can be formed by penetrating the display panel. The aperture area (DTA) can be formed by a laser or drilling process.

[0189] Below, we examine the planar and cross-sectional structures of the surrounding area (LA) through FIGS. 12 to 15.

[0190] First, let's examine the planar structure of the surrounding area (LA) through Figures 12 and 13.

[0191] FIG. 12 is a drawing of a sacrificial layer and its surroundings before laser irradiation in a display panel according to one embodiment, and FIG. 13 is a drawing of a display panel according to one embodiment after removing the sacrificial layer and its surrounding layers through laser irradiation.

[0192] In Figure 12, the parts labeled as Hole layer 1, Hole layer 2, and Hole layer 3 are the sacrificial layer (SFL), and it can be seen that they are formed of a metallic material and have a bright color.

[0193] After that, the sacrificial layer (SFL) and the surrounding layers are removed by irradiating with a laser, as shown in Fig. 13.

[0194] Referring to Fig. 13, it can be seen that a dark line (refer to the arrow in Fig. 13) is visible in the area where the sacrificial layer (SFL) has been removed. In Fig. 13, the dark line is not clearly visible in the Hole layer 1 portion of Fig. 12, but it is clearly visible in the Hole layer 2 and Hole layer 3 portions. This dark line may be visible due to the height difference (step difference) between the open area (R1, R2, R3) and the adjacent first surrounding area (LA1), and it may also be visible as the surrounding area reacts to laser irradiation.

[0195] The step difference between the open area (R1, R2, R3) and the adjacent first peripheral area (LA1) is examined through FIGS. 14 and 15.

[0196] FIG. 14 is a cross-section of the sacrificial layer and its surroundings after the display panel is completed according to one embodiment, and FIG. 15 is a cross-section of the surroundings before the sacrificial layer is completed during the manufacturing of the display panel according to one embodiment.

[0197] First, through Fig. 14, we examine the relationship of the thickness of the layers after the sacrificial layer is removed by finally irradiating with a laser.

[0198] FIG. 14 is divided into a portion where the functional layer (FL) and the second electrode (E2) are located and a portion where the functional layer (FL) and the second electrode (E2) are not located, and the portion where the functional layer (FL) and the second electrode (E2) are not located corresponds to an open area (R1, R2, R3).

[0199] In Fig. 14, the sum of the measured thicknesses of each layer (SUB, BF, IL1, IL2, IL3-1) in the open region (R1, R2, R3) is 1454 nm (534.3 + 71.6 + 225.8 + 159.7 + 154.2 + 308.4).

[0200] Meanwhile, the total thickness up to the third-second inorganic insulating layer (IL3-2) located below the functional layer (FL), where the functional layer (FL) and the second electrode (E2) are located, is measured to be 1542 nm.

[0201] Based on this, the thickness of the third-2 inorganic insulating layer (IL3-2) is 88 nm, and the thickness of gd3 in FIG. 11 is 363.4 nm. Therefore, in the display panel of the final completed embodiment, the height difference between the open area (R1, R2, R3) and its surroundings in the first peripheral area (LA1) is 363.4 nm, and depending on the embodiment, a thickness difference of about 300 nm or more and 500 nm or less may occur. Meanwhile, the thickness of the third-2 inorganic insulating layer (IL3-2) finally remaining in the first peripheral area (LA1) may be 20 nm or more and 100 nm or less.

[0202] In the following, through FIG. 15, we examine the cross-section of the surrounding area before the sacrificial layer is completed. FIG. 15 is a cross-sectional structure captured at step 10(d), showing a state in which a portion of the first-second data conductive layer (SD1-2) containing aluminum (Al) remains due to wet etching. However, since it is scheduled to be removed along with the sacrificial layer in a subsequent laser process, there is no problem even if a portion of the first-second data conductive layer (SD1-2) remains.

[0203] According to FIG. 15, the first-1 data conductive layer (SD1-1) constituting the sacrificial layer (SFL) has a thickness of 65.41 nm, the thickness of the third-2 inorganic insulating layer (IL3-2) located below the first-1 data conductive layer (SD1-1) is 189.3 nm, and the thickness of the exposed third-2 inorganic insulating layer (IL3-2) was measured to be 48.19 nm. In this case, the gd2 value in FIG. 10(c) is 141.11 nm.

[0204] After that, when the functional layer (FL) and the second electrode (E2) are laminated on the exposed third-2 inorganic insulating layer (IL3-2), a layered structure as shown in Fig. 11(a) is formed.

[0205] Through the above, we have examined a display panel that forms a sacrificial layer (SFL) according to one embodiment and removes it by irradiating it with a laser.

[0206] For structural and methodological comparison, FIGS. 16 and 17 examine the manufacturing method and single-layer structure according to the comparative example.

[0207] First, we examine the formation steps of the sacrificial layer according to the comparative example through Fig. 16.

[0208] FIG. 16 is a drawing sequentially illustrating the steps of forming a sacrificial layer of a display panel according to a comparative example.

[0209] In Fig. 16, the structure below the third inorganic insulating layer (IL3) is excluded.

[0210] In FIG. 16, the third inorganic insulating layer (IL3) is silicon oxide (SiO₂). x A third-1 inorganic insulating layer (IL3-1) formed of ) and silicon nitride (SiN) located thereon x It is illustrated as a double-layer structure including a third-second inorganic insulating layer (IL3-2) formed by ).

[0211] In FIG. 16(a), through the S50p step corresponding to the S50 step of FIG. 9, a material for the first data conductive layer is deposited on the third inorganic insulating layer (IL3) in the display area (DA), and the first data conductive layer (SD1) including the source electrode (SE) and the drain electrode (DE) is completed by etching using a mask. At this time, in the comparative example, the pattern of the first data conductive layer (SD1) is not formed in the peripheral area (LA). As a result, while etching the material for the first data conductive layer, the third-2 inorganic insulating layer (IL3-2) located underneath is dry-etched, and its height is reduced to 90 nm or less.

[0212] After that, the first organic insulating layer (IL4) is deposited on the third-second inorganic insulating layer (IL3-2) in the portion of the surrounding area (LA) where the sacrificial layer (SFL) is formed, and then etched away.

[0213] After that, in FIG. 16(b), a material for the second data conductive layer is deposited in the display area (DA) and etched through the S70p step corresponding to the S70 step of FIG. 9 to complete the second data conductive layer (SD2). At this time, in the comparative example, the pattern of the second data conductive layer (SD2) is not formed in the surrounding area (LA). As a result, while etching the material for the second data conductive layer, the third-2 inorganic insulating layer (IL3-2) located underneath is additionally dry-etched, and its height is reduced by 90 nm or less.

[0214] After that, in the comparative example, the process up to step S100 of FIG. 9 is performed. Then, a step (S105p) of forming a sacrificial layer (SFL) using a separate mask is performed as shown in FIG. 16(c). That is, a metal material for the sacrificial layer is deposited in the surrounding area (LA), and the sacrificial layer (SFL) is completed by etching using a mask. At this time, as shown in FIG. 16(c), the third-2 inorganic insulating layer (IL3-2) is completely etched, and the third-1 inorganic insulating layer (IL3-1) is exposed.

[0215] After that, the functional layer (FL) and the second electrode (E2) are sequentially stacked, and a laser is irradiated (S110p) from below the substrate (SUB) as shown in FIG. 16(d). The irradiated laser reacts with the sacrificial layer (SFL) formed of metal, causing the sacrificial layer (SFL) and the surrounding layers to detach.

[0216] As a result, the comparative example has a final cross-sectional structure as shown in Fig. 16(e).

[0217] When comparing the cross-sectional structure of the comparative example in Fig. 16(e) with the cross-sectional structure according to the present embodiment in Fig. 11(b), the cross-sectional structure of the open region (R1, R2, R3) from which the sacrificial layer (SFL) has fallen off is the same, but there is a difference in the presence or absence of the third-second inorganic insulating layer (IL3-2) located around it.

[0218] Below, we will examine in detail the cross-section of a comparative example actually manufactured by the manufacturing method of Fig. 16 through Fig. 17.

[0219] Figure 17 is a cross-section of the sacrificial layer and its surroundings that was removed after the display panel was completed according to the comparative example of Figure 16.

[0220] In FIG. 17, the functional layer (FL) and the second electrode (E2) are located in a portion and the functional layer (FL) and the second electrode (E2) are not located in a portion, and the portion where the functional layer (FL) and the second electrode (E2) are not located corresponds to an opening region.

[0221] In Fig. 17, the total thickness below the functional layer (FL) in the portion where the functional layer (FL) is located is 1520 nm, and the total thickness of the aperture region where the functional layer (FL) is not located is measured to be 1514.9 nm (589.3 + 490.5 + 132.2 + 302.9). When comparing the two thicknesses, there is a difference of about 5 nm, but considering measurement error and process error, this is substantially the same height.

[0222] In addition, in FIG. 17, the third-2 inorganic insulating layer (IL3-2) is not visible below the functional layer (FL), and only the third-1 inorganic insulating layer (IL3-1) is consistently positioned, so it can be confirmed that there is a difference in the height of the functional layer (FL) and the second electrode (E2) when compared to the structure of the embodiment of the present invention. That is, in the comparative example, the third-2 inorganic insulating layer (IL3-2) is not formed around the opening region, but in the present embodiment of FIG. 11(b), the third-2 inorganic insulating layer (IL3-2) with reduced thickness is located around the open region (R1, R2, R3). Here, the thickness of the third-2 inorganic insulating layer (IL3-2) with reduced height may be 20 nm or more and 100 nm or less. As a result, compared to the comparative example, in the embodiment of the present invention, the depth of the portion where the functional layer (FL) and the second electrode (E2) are short-circuited is deeper by the thickness (20 nm or more and 100 nm or less) of the third-2 inorganic insulating layer (IL3-2), and the functional layer (FL) and the second electrode (E2) are located further from the substrate (SUB) by the thickness (20 nm or more and 100 nm or less) of the third-2 inorganic insulating layer (IL3-2).

[0223] Hereinafter, another embodiment of the present invention will be examined through FIGS. 18 to 21.

[0224] Another embodiment of the present invention is an embodiment in which the semiconductor layer included in the pixel (PX) includes an oxide semiconductor layer in addition to a polycrystalline semiconductor layer.

[0225] First, let's look at the circuit structure of a pixel (PX) according to another embodiment through FIG. 18.

[0226] FIG. 18 is a circuit diagram of a pixel according to another embodiment.

[0227] Unlike the pixel (PX) of FIG. 5, the pixel (PX) of FIG. 18 includes oxide semiconductors for the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7). As a result, the second transistor (T2) and the third transistor (T3) receive different scan signals (GW, GC). Meanwhile, in the embodiment of FIG. 18, the fourth transistor (T4) and the seventh transistor (T7) receive different initialization voltages (VINT, AINT).

[0228] As illustrated in FIG. 18, one pixel (PX) of a display device according to one embodiment includes a plurality of transistors (T1, T2, T3, T4, T5, T6, T7), a holding capacitor (Cst), a boost capacitor (Cbt), and a light-emitting diode (LED) connected to multiple wires (127, 128, 151, 152, 153, 154, 155, 171, 172, 741).

[0229] A plurality of wires (127, 128, 151, 152, 153, 154, 155, 171, 172, 741) are connected to a single pixel (PX). The plurality of wires includes a first initialization voltage line (127), a second initialization voltage line (128), a first scan signal line (151), a second scan signal line (152), an initialization control line (153), a bypass control line (154), a light emission control line (155), a data line (171), a driving voltage line (172), and a common voltage line (741).

[0230] The first scan signal line (151) is connected to a scan driver to transmit the first scan signal (GW) to the second transistor (T2). The second scan signal line (152) may have a voltage of opposite polarity to the voltage applied to the first scan signal line (151) at the same timing as the signal of the first scan signal line (151). For example, when a negative voltage is applied to the first scan signal line (151), a positive voltage may be applied to the second scan signal line (152). The second scan signal line (152) transmits the second scan signal (GC) to the third transistor (T3).

[0231] The initialization control line (153) transmits an initialization control signal (GI) to the fourth transistor (T4). The bypass control line (154) transmits a bypass signal (GB) to the seventh transistor (T7). The bypass control line (154) may be composed of the first scan signal line (151) of the preceding stage. The light emission control line (155) transmits a light emission control signal (EM) to the fifth transistor (T5) and the sixth transistor (T6).

[0232] The data line (171) is a wiring that transmits data voltage (DATA) generated by a data driving unit (not shown), and the brightness of the light-emitting diode (LED) changes according to the data voltage (DATA) applied to the pixel (PX).

[0233] The driving voltage line (172) applies a driving voltage (ELVDD). The first initialization voltage line (127) transmits a first initialization voltage (VINT), and the second initialization voltage line (128) transmits a second initialization voltage (AINT). The common voltage line (741) applies a common voltage (ELVSS) to the cathode electrode of the light-emitting diode (LED). In this embodiment, the voltages applied to the driving voltage line (172), the first and second initialization voltage lines (127, 128), and the common voltage line (741) may each be constant voltages.

[0234] A plurality of transistors may include a driving transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). A plurality of transistors may include oxide transistors comprising oxide semiconductors and silicon transistors comprising polycrystalline silicon semiconductors. In the embodiment of FIG. 18, the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) may be made of oxide transistors, and the driving transistor (T1), the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may be made of silicon transistors. However, this is not limited thereto, and a plurality of transistors may all be made of silicon transistors and / or oxide transistors.

[0235] The second transistor (T2) is a transistor that transmits data voltage (DATA) into the pixel (PX), the fourth transistor (T4) is a transistor that initializes the voltage of the gate electrode of the driving transistor (T1) to the first initialization voltage (VINT), and the seventh transistor (T7) is a transistor that initializes the anode voltage of the light-emitting diode (LED) to the second initialization voltage (AINT).

[0236] The fifth transistor (T5) transmits the driving voltage (ELVDD) to the driving transistor (T1), and the sixth transistor (T6) transmits the output current of the driving transistor (T1) to the light-emitting diode (LED), and the section in which the fifth transistor (T5) and the sixth transistor (T6) are turned on may be the light-emitting section.

[0237] The third transistor (T3) connects the gate electrode and the output electrode of the driving transistor (T1) to each other, so that the data voltage (DATA) passes through the driving transistor (T1) and is stored in the holding capacitor (Cst) connected to the gate electrode of the driving transistor (T1). At this time, the voltage finally stored in the holding capacitor (Cst) can be a voltage value in which the threshold voltage of the driving transistor (T1) is compensated.

[0238] The driving transistor (T1) generates and outputs an output current based on the voltage stored in the holding capacitor (Cst).

[0239] The boost capacitor (Cbt) performs the function of lowering the voltage of the gate electrode of the driving transistor (T1) when the first scan signal (GW) applied to the first scan signal line (151) changes to a low voltage and turns on the second transistor (T2). As a result, the driving transistor (T1) can reliably maintain the turned-on state.

[0240] Although it has been described above that one pixel (PX) includes seven transistors (T1 to T7), one holding capacitor (Cst), and one boost capacitor (Cbt), it is not limited thereto, and the number of transistors, the number of capacitors, and their connection relationships can be varied.

[0241] Below, we will briefly examine the manufacturing process of a display panel according to another embodiment through FIG. 19.

[0242] FIG. 19 is a flowchart schematically illustrating the manufacturing process of a display panel according to another embodiment.

[0243] Compared to FIG. 9, FIG. 19 further includes the step of forming an oxide semiconductor layer (OSC) (S31) and the step of forming a third gate conductive layer (GAT3) (S32). Additionally, in the embodiment of FIG. 9, the opening formation step is included as two steps (S40-1, S40-2).

[0244] The steps are as follows.

[0245] After forming a buffer layer (BF) on the substrate (SUB), a semiconductor layer material is deposited, and the semiconductor layer (SC) is completed (S10) by etching using a mask. In this embodiment, the semiconductor layer (SC) can be formed as a polycrystalline semiconductor including polycrystalline silicon, and the final semiconductor layer (SC) can be formed by forming amorphous silicon entirely, changing it to polycrystalline silicon through a crystallization process, and then patterning it using a mask.

[0246] After forming a first inorganic insulating layer (IL1) on the buffer layer (BF) and semiconductor layer (SC), a material for a first gate conductive layer is stacked, and etched using a mask to complete a first gate conductive layer (GAT1) including a gate electrode (GE) and a first capacitor electrode (CE1) (S20).

[0247] After forming a second inorganic insulating layer (IL2) on top of the first inorganic insulating layer (IL1) and the first gate conductive layer (GAT1), a material for the second gate conductive layer is stacked and etched using a mask to complete the second gate conductive layer (GAT2) including the second capacitor electrode (CE2) and the overlapping electrode (OBML) (S30).

[0248] After forming the second-1 inorganic insulating layer (IL2-1) on the second inorganic insulating layer (IL2) and the second gate conductive layer (GAT2), an oxide semiconductor layer (OSC) is completed (S31) using a mask thereon.

[0249] A second-2 inorganic insulating layer (IL2-2) covering a second-1 inorganic insulating layer (IL2-1) and an oxide semiconductor layer (OSC) is laminated as a whole. A material for a third gate conductive layer is laminated on top of the second-2 inorganic insulating layer (IL2-2), and a third gate conductive layer (GAT3) including an oxide gate electrode (OGE) that overlaps with the oxide semiconductor layer (OSC) is completed (S32). According to the embodiment, a connecting member electrically connected to the overlap electrode (OBML) may be additionally formed on the third gate conductive layer (GAT3).

[0250] After forming the third inorganic insulating layer (IL3) entirely on the second-2 inorganic insulating layer (IL2-2) and the third gate conductive layer (GAT3), a first opening (P-CNT) is formed (S40-1) using a mask to expose a semiconductor layer (SC) to the first inorganic insulating layer (IL1), the second inorganic insulating layer (IL2), the second-1 inorganic insulating layer (IL2-1), the second-2 inorganic insulating layer (IL2-2), and the third inorganic insulating layer (IL3). Here, the first opening (P-CNT) may be an opening for exposing a semiconductor layer (SC) formed of a polycrystalline semiconductor.

[0251] Subsequently, a second opening (O-CNT) is formed (S40-2) using an additional mask to expose an oxide semiconductor layer (OSC) to the second-2 inorganic insulating layer (IL2-2) and the third inorganic insulating layer (IL3). Here, the second opening (O-CNT) may be an opening for exposing an oxide semiconductor layer (OSC) formed from an oxide semiconductor. Depending on the embodiment, the process of forming the opening may be performed with a single mask or formed through a single process, but is not limited thereto.

[0252] A material for a first data conductive layer is deposited on top of a third inorganic insulating layer (IL3), and a first data conductive layer (SD1) including a source electrode (SE) and a drain electrode (DE) is completed (S50). At this time, a pattern of the first data conductive layer (SD1) is formed in the first peripheral region (LA1), and a sacrificial layer (SFL) is completed through a subsequent process (see FIG. 10).

[0253] After forming the first organic insulating layer (IL4) entirely on the third inorganic insulating layer (IL3) and the first data conductive layer (SD1), a mask is used to form the pattern of the first organic insulating layer (IL4) in the opening of the display area (DA) and the surrounding area (LA) (S60). The pattern of the first organic insulating layer (IL4) in the surrounding area (LA) includes the 2-1 subdam (D2-a), and the pattern of the first organic insulating layer (IL4) may not be formed in the other surrounding area (LA).

[0254] A material for a second data conductive layer is laminated on the first organic insulating layer (IL4), and a second data conductive layer (SD2) including a connecting member (CE) is completed (S70) by etching using a mask.

[0255] After forming the second organic insulating layer (IL5) entirely on the first organic insulating layer (IL4) and the second data conductive layer (SD2), a mask is used to form the pattern of the second organic insulating layer (IL5) in the opening of the display area (DA) and the surrounding area (LA) (S80). The pattern of the second organic insulating layer (IL5) in the surrounding area (LA) includes the first-1 subdam (D1-a) and the second-2 subdam (D2-b), and the pattern of the second organic insulating layer (IL5) may not be formed in the other surrounding area (LA).

[0256] A material for a pixel electrode layer is laminated on top of the second organic insulating layer (IL5), and a pixel electrode layer (PXL) including the first electrode (E1) is completed (S90) by etching using a mask.

[0257] After the material forming the pixel defining film (IL6) and spacer (IL7) on the second organic insulating layer (IL5) and the pixel electrode layer (PXL) is sequentially stacked as a whole, a pixel defining film (IL6) and spacer (IL7) pattern in the surrounding area (LA) is formed (S100) with an opening defining a light-emitting region that overlaps at least a portion of the first electrode (E1) in the display area (DA) and is formed using a mask. The pixel defining film (IL6) and spacer (IL7) pattern includes a first-2 subdam (D1-b), a first-3 subdam (D1-c), a second-3 subdam (D2-c), and a second-4 subdam (D2-d), and the pixel defining film (IL6) and spacer (IL7) pattern may not be formed in the other surrounding area (LA).

[0258] On the pixel definition film (IL6) and spacer (IL7), an intermediate layer (EL; FL+EML) and a second electrode (E2) are sequentially stacked. As a result, the functional layer (FL) and the second electrode (E2) are connected in the surrounding area (LA) as well, and as shown in FIG. 11, through a laser irradiation step (S120), the functional layer (FL) and the second electrode (E2) are disconnected in the first open area (R1), the second open area (R2), and the third open area (R3).

[0259] In the embodiment of FIG. 19, although there is a difference in the layered structure of the display area (DA), since there is a difference in the lower structure of the third inorganic insulating layer (IL3), the upper structure of the third inorganic insulating layer (IL3) may be substantially the same as FIG. 10 and FIG. 11.

[0260] That is, when forming the pattern of the first data conductive layer (SD1) as in FIG. 10(a), the third inorganic insulating layer (IL3) is partially etched so that its thickness is reduced by gd1. Here, the value of gd1 can be approximately 50 nm or more and 90 nm or less. Additionally, in the subsequent process (S70-2) of etching the material for the second data conductive layer, the exposed third inorganic insulating layer (IL3) is further partially etched so that its thickness is reduced by a total of gd2. Here, the value of gd2 can be approximately 100 nm or more and 180 nm or less.

[0261] When the sacrificial layer (SFL) is completed in FIG. 10(d), the thickness of the exposed third inorganic insulating layer (IL3) may be the same as in FIG. 10(c), and the final thickness of the third inorganic insulating layer (IL3) may have a value reduced by about 180 nm or less from the thickness of the first formed third inorganic insulating layer (IL3). The third-2 inorganic insulating layer (IL3-2) remaining in the first peripheral region (LA1) has a thickness reduced by about 100 nm or more and 180 nm or less, and may have a thickness of about 20 nm or more and 100 nm or less.

[0262] And as shown in FIG. 11, when an open region (R1, R2, R3) is formed through laser irradiation, the open region (R1, R2, R3) is formed to be lower than the adjacent first peripheral region (LA1) by the thickness of the third-second inorganic insulating layer (IL3-2), the functional layer (FL), and the second electrode (E2). The thickness difference (gd3) between the open region (R1, R2, R3) and the adjacent first peripheral region (LA1) can be approximately 300 nm or more and 500 nm or less.

[0263] After that, a laser or drilling process may be further performed to form a digital opening (DTA) that penetrates the display panel.

[0264] Below, we examine the cross-sectional structure of the open region (R1, R2, R3) formed as the sacrificial layer is removed through FIG. 20.

[0265] FIG. 20 is an enlarged cross-sectional view of a portion of a display panel from which a sacrificial layer has been removed according to another embodiment.

[0266] Figure 20 is similar to Figure 8, with the only difference being that two additional insulating layers (2-1 inorganic insulating layer (IL2-1) and 2-2 inorganic insulating layer (IL2-2)) are located between the second inorganic insulating layer (IL2) and the third inorganic insulating layer (IL3).

[0267] In FIG. 20 as well, the functional layer (FL) and the second electrode (E2) are separated from the first-1 layer (FL-1) and the second-1 layer (E2-1) based on the open regions (R1, R2, R3). Meanwhile, the first encapsulated inorganic layer (EIL1) located above the second electrode (E2) is formed continuously on both sides based on the first open region (R1).

[0268] Below, we will examine in more detail the cross-sectional structure in the display area of ​​a pixel (PX) having the same structure as in Fig. 18 through Fig. 21.

[0269] FIG. 21 is a cross-sectional view of a pixel included in the display area of ​​a display panel according to the embodiment of FIG. 18.

[0270] The substrate (SUB) may have various degrees of flexibility. The substrate (SUB) may be a flexible substrate formed of multiple insulating layers that allows bending, folding, rolling, etc.

[0271] A buffer layer (BF) may be located on the substrate (SUB), but may be excluded as in the embodiment of FIG. 21.

[0272] A semiconductor layer (SC) is located on a substrate (SUB). The semiconductor layer (SC) may include polycrystalline silicon. The semiconductor layer (SC) includes a channel region that overlaps with a gate electrode (GE) located on the top, and a first region and a second region located on both sides thereof. The channel region is a semiconductor region that is doped with a small amount of impurities or is not doped with impurities compared to the first region and the second region, and the first region and the second region are semiconductor regions that are doped with a large amount of impurities compared to the channel region.

[0273] A first inorganic insulating layer (IL1) is located on the semiconductor layer (SC). The first inorganic insulating layer (IL1) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may have a single-layer or multi-layered structure including at least one of ).

[0274] A first gate conductive layer (GAT1) comprising a gate electrode (GE) and a first capacitor electrode (CE1) is located on the first inorganic insulating layer (IL1). The first gate conductive layer (GAT1) may be a single layer or a multilayer film in which a metal film comprising any one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, titanium (Ti), and titanium alloy is stacked. The gate electrode (GE) may overlap with the channel region of the planar semiconductor layer (SC).

[0275] A second inorganic insulating layer (IL2) is located on the first gate conductive layer (GAT1) and the first inorganic insulating layer (IL1). The second inorganic insulating layer (IL2) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0276] A second gate conductive layer (GAT2) comprising a second capacitor electrode (CE2) and an overlapping electrode (OBML) is positioned on a second inorganic insulating layer (IL2). The second capacitor electrode (CE2) and the overlapping electrode (OBML) may be different parts of a single conductive pattern. The second capacitor electrode (CE2) overlaps with the first capacitor electrode (CE1) to form a retaining capacitor (Cst). The overlapping electrode (OBML) has a structure that overlaps with the channel of a subsequent oxide semiconductor layer (OSC). The second gate conductive layer (GAT2) may be a single layer or a multilayer film in which a metal film comprising any one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, titanium (Ti), and titanium alloy is stacked.

[0277] A second-1 inorganic insulating layer (IL2-1) is located on the second gate conductive layer (GAT2) and the second inorganic insulating layer (IL2). The second-1 inorganic insulating layer (IL2-1) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0278] An oxide semiconductor layer (OSC) is located on top of the second-1 inorganic insulating layer (IL2-1). The oxide semiconductor layer (OSC) includes a channel region that overlaps with the gate electrode (GE) located on top, and first and second regions located on both sides thereof. The channel region is a semiconductor region that is doped with a small amount of impurities or is not doped with impurities compared to the first and second regions, and the first and second regions are semiconductor regions that are doped with a large amount of impurities compared to the channel region.

[0279] A second-2 inorganic insulating layer (IL2-2) is formed on top of the second-1 inorganic insulating layer (IL2-1) and the oxide semiconductor layer (OSC). The second-2 inorganic insulating layer (IL2-2) is silicon oxide (SiO₂).x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0280] A third gate conductive layer (GAT3) comprising an oxide gate electrode (OGE) is located on top of the second-2 inorganic insulating layer (IL2-2). The oxide gate electrode (OGE) overlaps planarly with the channel of the oxide semiconductor layer (OSC). The third gate conductive layer (GAT3) may be a single layer or a multilayer film in which a metal film comprising any one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, titanium (Ti), and titanium alloy is stacked.

[0281] A third inorganic insulating layer (IL3) is located on top of the second-second inorganic insulating layer (IL2-2) and the third gate conductive layer (GAT3). The third inorganic insulating layer (IL3) is silicon oxide (SiO₂). x ), silicon nitride (SiN x ) and silicon nitrate (SiO₂ x N y It may be a single layer or a multilayer including at least one of ).

[0282] A first data conductive layer (SD1) comprising a source electrode (SE) and a drain electrode (DE) is positioned on a third inorganic insulating layer (IL3). The source electrode (SE) and the drain electrode (DE) can be electrically connected to the first region (S) and the second region (D) of the semiconductor layer (SC), respectively, through contact holes formed in the third inorganic insulating layer (IL3) and the first and second inorganic insulating layers (IL1, IL2). According to an embodiment, the semiconductor layer (SC) can be directly extended without the source electrode (SE) and the drain electrode (DE) and electrically connected to an adjacent pixel. The first data conductive layer (SD1) may include aluminum (Al), silver (Ag), magnesium (Mg), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or a multilayer structure including the same. The first data conductive layer (SD1) of the present embodiment has a triple-layer structure in which aluminum (Al) is disposed between two layers of titanium (Ti), and the following description focuses on the triple-layer structure of Ti / Al / Ti.

[0283] A first organic insulating layer (IL4) and a second organic insulating layer (IL5) are sequentially positioned on the third inorganic insulating layer (IL3) and the first data conductive layer (SD1). The first organic insulating layer (IL4) and the second organic insulating layer (IL5) may include organic insulating materials such as general-purpose polymers like polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide, acrylic polymers, siloxane polymers, etc.

[0284] A connecting member (CE) may be located between the first organic insulating layer (IL4) and the second organic insulating layer (IL5). The connecting member (CE) constitutes the second data conductive layer (SD2) and may connect the drain electrode (DE) and the first electrode (E1), or connect the first capacitor electrode (CE1) or the gate electrode of the driving transistor (T1) to other components. The second data conductive layer (SD2) may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multilayer structure including the same. The second data conductive layer (SD2) of the present embodiment has a triple layer structure in which aluminum (Al) is disposed between two layers of titanium (Ti), similar to the first data conductive layer (SD1), and the following description focuses on the triple layer structure of Ti / Al / Ti.

[0285] A first electrode (E1) is located on the second organic insulating layer (IL5). The first electrode (E1) forms a pixel electrode layer (PXL) and is connected to a connecting member (CE) through a contact hole in the second organic insulating layer (IL5). The first electrode (E1) is electrically connected to a drain electrode (DE). The first electrode (E1) may include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), and gold (Au), and may also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) and indium zinc oxide (IZO). The first electrode (E1) may be composed of a single layer containing a metal material or a transparent conductive oxide, or a multilayer containing these. In this embodiment, the first electrode (E1) may have a triple-layer structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO), and the following description focuses on the structure of ITO / Ag / ITO.

[0286] The gate electrode (GE) and the semiconductor layer (SC) constitute a polycrystalline transistor, and the oxide gate electrode (OGE) and the oxide semiconductor layer (OSC) constitute an oxide transistor. Depending on the transistor, a source electrode (SE) and a drain electrode (DE) may be included that are electrically connected to the first and second regions of the semiconductor layer (SC, OSC). Depending on the transistor, the transistor may be formed using only the gate electrode (GE) and the semiconductor layer (SC, OSC) without the source electrode (SE) and the drain electrode (DE). The transistor (the sixth transistor (T6)) is connected to the first electrode (E1) to supply current to the light-emitting element (LED).

[0287] A pixel defining film (IL6) and a spacer (IL7) are located on top of the second organic insulating layer (IL5) and the first electrode (E1).

[0288] The pixel defining film (IL6) has an opening that overlaps with at least a portion of the first electrode (E1) and defines a light-emitting region. The opening may have a planar shape similar to the first electrode (E1). The opening may have a planar rhombus or an octagonal shape similar to a rhombus, but is not limited thereto and may have any shape such as a square, polygon, circle, or ellipse.

[0289] The pixel definition film (IL6) and spacer (IL7) may include organic insulating materials such as general-purpose polymers like polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, polyimide, acrylic polymers, and siloxane polymers.

[0290] An intermediate layer (EL) is positioned on the pixel defining layer (IL6), spacer (IL7), and first electrode (E1). Referring to FIG. 6, the intermediate layer (EL) may include an emitting layer (EML) and a functional layer (FL). The emitting layer (EML) of the intermediate layer (EL) may generate a predetermined colored light. The emitting layer (EML) may include an organic material and / or an inorganic material. In this embodiment, the emitting layer (EML) is formed only within the opening of the pixel defining layer (IL6). Additionally, the functional layer (FL) may include at least one of a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL). The functional layer (FL) can be divided into a first functional layer (FL1) located between the first electrode (E1) and the light-emitting layer, and a second functional layer (FL2) located between the light-emitting layer and the second electrode (E2). The functional layer may have a shape that overlaps with the front surface of the substrate (SUB). The functional layer may be arranged across multiple pixels.

[0291] A second electrode (E2) is located on the intermediate layer (EL). The second electrode (E2) may include a reflective metal including calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), etc., or a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0292] The first electrode (E1), the intermediate layer (EL), and the second electrode (E2) can constitute a light-emitting element (LED). Here, the first electrode (E1) may be an anode, which is a hole injection electrode, and the second electrode (E2) may be a cathode, which is an electron injection electrode. However, the embodiments are not necessarily limited thereto, and depending on the driving method of the light-emitting display device, the first electrode (E1) may be a cathode and the second electrode (E2) may be an anode.

[0293] Holes and electrons are injected into the organic intermediate layer (EL) from the first electrode (E1) and the second electrode (E2), respectively, and light emission occurs when the exciton formed by the combination of the injected holes and electrons falls from the excited state to the ground state.

[0294] Although not illustrated in FIG. 21, an encapsulation layer (ENC) is positioned on the second electrode (E2) as in FIG. 6 and FIG. 7. The encapsulation layer (ENC) can cover and seal not only the upper surface but also the side surface of the light-emitting element (LED). Since the light-emitting element is very susceptible to moisture and oxygen, the encapsulation layer (ENC) seals the light-emitting element (LED) to block the inflow of external moisture and oxygen. The encapsulation layer (ENC) may include a plurality of layers, and among them, it may be formed as a composite film including both an inorganic layer and an organic layer, and as an example, it may be formed as a triple layer in which a first encapsulation inorganic layer (EIL1), an encapsulation organic layer (EOL), and a second encapsulation inorganic layer (EIL2) are formed sequentially.

[0295] The above description is based on embodiments having the pixel structures of FIGS. 5 and 6 and embodiments having the pixel structures of FIGS. 18 and 21. However, the present invention can be applied to various other embodiments as well.

[0296] Below, a modified embodiment of FIG. 7 is examined through FIG. 22.

[0297] FIG. 22 is a cross-sectional view of a display panel in which the peripheral area and the opening area are located among the display panels according to another embodiment.

[0298] In Fig. 22, unlike Fig. 7, only an additional planarization layer (YPVX) is formed as an additional insulating film.

[0299] That is, the additional insulating film covering the peripheral region (LA) and the display region (DA) is formed solely of an additional planarization layer (YPVX) to have an overall flat characteristic. Depending on the embodiment, a touch electrode may be additionally formed between the encapsulation layer (ENC) and the additional planarization layer (YPVX) in the display region (DA) to detect touch.

[0300] In the embodiment of FIG. 22, the inner surface of the opening region (DTA) can be defined by the ends of the substrate (SUB), buffer layer (BF), first inorganic insulating layer (IL1), second inorganic insulating layer (IL2), third inorganic insulating layer (IL3), first-third layer (FL-3), second-first layer (E2-1), first encapsulating inorganic layer (EIL1), second encapsulating inorganic layer (EIL2), and additional flattening layer (YPVX). The substrate (SUB), buffer layer (BF), first inorganic insulating layer (IL1), second inorganic insulating layer (IL2), third inorganic insulating layer (IL3), first-third layer (FL-3), second-first layer (E2-1), first encapsulating inorganic layer (EIL1), second encapsulating inorganic layer (EIL2), and additional flattening layer (YPVX) are cut together so that the ends of each layer are aligned with each other.

[0301] However, this is not limited to this, and it goes without saying that some of the aforementioned components may be omitted or added to form the inner surface of the opening area (DTA).

[0302] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0303] 1000: Display device DP: Display panel WU: Cover window HM: Housing member ES: Electronic Module DTA: Aperture Area LA, LA1, LA2: Surrounding areas HA, HA1, HA2: Hole areas TA: Transmittance area BA: Blocking area DA: Display area R1, R2, R3: Open area D1, D2: Dam EL: Intermediate layer EML: Emissive layer FL, FL1, FL2: Functional layer E1: First electrode E2: Second electrode RDL: Bypass SFL: Sacrifice Layer LED: Light Emitting Diode PX: Pixel T1, T2, T3, T4, T5, T6, T7: Transistors Cbt: Boost capacitor Cst: Holding capacitor SL: Scan line 151: 1st scan signal line 152: 2nd scan signal line 153: Initialization control line 154: Bypass control line 155: Light emission control line 171, DL: Data line 172, PL: Driving voltage line 127, 128: Initialization voltage line 60: Driving voltage supply wiring 70: Common voltage supply wiring 741: Common voltage line 20: Scan driver 50: Data driver 80: Driver chip SC, OSC: Semiconductor layer GAT1, GAT2, GAT3: Gate conductive layer SD1, SD2: Data conductive layer PXL: Pixel electrode layer SUB: Substrate BF: Buffer layer IL1: First inorganic insulating layer IL2: Second inorganic insulating layer IL3: Third inorganic insulating layer IL4: First organic insulating layer IL5: Second organic insulating layer IL6: Pixel defining layer IL7: Spacer ENC: Encapsulation layer EIL1, EIL2: Inorganic layer of bag EOL: Organic layer of bag YILD: Additional inorganic insulation layer YOC: Additional overcoat layer YPVX: Additional planarization layer AD: Adhesion layer GE. OGE: Gate electrode SE: Source electrode DE: Drain electrode CE1, CE2: Capacitor electrodes AE: Upper electrode CE: Connecting member C: Channel region OBML: Overlapping electrodes CNT, P-CNT, O-CNT: Opening

Claims

Claim 1 A display device comprising: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a semiconductor layer located on the substrate and overlapping with the display region and including a channel; an inorganic insulating layer located on the semiconductor layer; a gate electrode located on the inorganic insulating layer and overlapping with the channel of the semiconductor layer; an insulating layer located on the gate electrode and including a first inorganic insulating film and a second inorganic insulating film located on the first inorganic insulating film; a first electrode located on the insulating layer; a light-emitting layer located on the first electrode; and a second electrode located on the light-emitting layer, wherein in the peripheral region, the light-emitting layer and the second electrode are separated in an open region, and the second inorganic insulating film is also separated, and in the open region, the first inorganic insulating film, the inorganic insulating layer, and the substrate are continuously formed. Claim 2 A display device according to claim 1, wherein the severed end of the second inorganic insulating film and the severed end of the light-emitting layer or the second electrode coincide with each other, and the first inorganic insulating film comprises silicon oxide, and the second inorganic insulating film comprises silicon nitride. Claim 3 delete Claim 4 A display device according to claim 1, wherein the surrounding area comprises a first surrounding area including the open area and a second surrounding area where a bypass portion is located on which a data line formed on the insulating layer is bypassed and extended. Claim 5 A display device according to claim 4, wherein the opening area through which a display panel is penetrated is located on the inner side of the first peripheral area, and further comprising a camera disposed in the opening area. Claim 6 In paragraph 4, the first peripheral area includes at least one dam, and the dam is a ring-shaped display device. Claim 7 In paragraph 6, a display device in which the open area is located on each side of the dam. Claim 8 A display device comprising: a substrate including an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region; a semiconductor layer located on the substrate and overlapping with the display region and including a channel; an inorganic insulating layer located on the semiconductor layer; a gate electrode located on the inorganic insulating layer and overlapping with the channel of the semiconductor layer; an insulating layer located on the gate electrode and including a first inorganic insulating film and a second inorganic insulating film located on the first inorganic insulating film; a first electrode located on the insulating layer; a light-emitting layer located on the first electrode; and a second electrode located on the light-emitting layer, wherein in the peripheral region, the second inorganic insulating film is also interrupted in an open region where the light-emitting layer and the second electrode are interrupted, and the step difference occurring where the second inorganic insulating film, the light-emitting layer, and the second electrode are interrupted in the open region is 300 nm or more and 500 nm or less, and the first inorganic insulating film, the inorganic insulating layer, and the substrate are continuously formed in the open region. Claim 9 A display device according to claim 8, wherein the first inorganic insulating film comprises silicon oxide and the second inorganic insulating film comprises silicon nitride. Claim 10 In claim 9, the first inorganic insulating film is continuously formed in the open region of the display device. Claim 11 A display device according to claim 10, wherein the thickness of the second inorganic insulating film is 20 nm or more and 100 nm or less. Claim 12 A display device according to claim 11, wherein the opening area through which a display panel is penetrated is located on the inner side of the surrounding area, and further comprising a camera disposed in the opening area. Claim 13 In claim 11, the above-mentioned peripheral area comprises a first peripheral area including the open area and a second peripheral area where a bypass portion is located on which a data line formed on the insulating layer bypasses and extends. Claim 14 In paragraph 13, the first peripheral area comprises at least one dam, the dam has a ring shape, and the open area is located on each side of the dam, respectively, forming a display device. Claim 15 A method for manufacturing a display device comprising an opening region, a surrounding region surrounding the opening region, and a display region surrounding the surrounding region, wherein the surrounding region comprises the steps of: forming an insulating layer on a substrate; forming a first data conductive layer on the insulating layer, the first layer, a second layer located on the first layer, and a third layer located on the second layer; stacking a material for a second data conductive layer on the first data conductive layer; removing the material for the second data conductive layer while simultaneously removing the entire third layer, a part of the second layer, and a part of the insulating layer from the first data conductive layer; stacking a material for a first electrode; removing the material for the first electrode while simultaneously removing the entire remaining second layer to complete a sacrificial layer; sequentially stacking a functional layer and a second electrode on the sacrificial layer; and irradiating a laser onto the sacrificial layer to remove the sacrificial layer, the functional layer adjacent to the sacrificial layer, and the second electrode together. A method for manufacturing a display device comprising the step of forming an opening region penetrating a display panel, wherein the first electrode, the functional layer, and the second electrode constitute a light-emitting element. Claim 16 In claim 15, the step of removing the material for the second data conductive layer is a method for manufacturing a display device using a wet etching method. Claim 17 A method for manufacturing a display device according to claim 16, wherein the first layer and the third layer of the first data conductive layer comprise titanium, and the second layer comprises aluminum. Claim 18 In paragraph 17, the above sacrificial layer is a method for manufacturing a display device comprising aluminum. Claim 19 In claim 17, the material for the second data conductive layer has a triple-layer structure comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, wherein the first layer and the third layer of the material for the second data conductive layer comprise titanium, and the second layer comprises aluminum. Claim 20 A method for manufacturing a display device according to claim 19, wherein the first electrode material has a triple-layer structure comprising a first layer, a second layer located above the first layer, and a third layer located above the second layer, wherein the first layer and the third layer of the first electrode material comprise indium tin oxide, and the second layer comprises silver.

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