Display device

Abstract

According to one embodiment of the present invention, a display device comprising a display area and a non-display area, wherein the display device comprises: a pixel disposed within the display area; a driving control unit disposed within the non-display area and controlling the driving of the pixel; and a wiring unit, wherein at least a portion thereof is disposed within the non-display area and electrically connects the pixel and the driving control unit; wherein the non-display area includes a fan-out area located between the display area and the driving control unit, and the wiring unit includes a first power line, a second power line, and a fan-out line, each having at least a portion disposed within the fan-out area, and the first power line and the second power line are separated by a separation area in which at least a portion thereof extends in a diagonal direction when viewed on a plane, and the diagonal direction is non-parallel to one side of the display device in which the driving control unit is disposed adjacently.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] With the recent rise in interest in information displays, research and development on display devices is continuously being carried out. The problem to be solved

[0003] One objective of the present invention is to provide a display device in which the resistance variation of the wirings at different locations is reduced and short-circuit defects between electrode configurations are prevented.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0005] According to one embodiment of the present invention, a display device comprising a display area and a non-display area, wherein the display device comprises: a pixel disposed within the display area; a driving control unit disposed within the non-display area and controlling the driving of the pixel; and a wiring unit, wherein at least a portion thereof is disposed within the non-display area and electrically connects the pixel and the driving control unit; wherein the non-display area includes a fan-out area located between the display area and the driving control unit, and the wiring unit includes a first power line, a second power line, and a fan-out line, each having at least a portion disposed within the fan-out area, and the first power line and the second power line are separated by a separation area in which at least a portion thereof extends in a diagonal direction when viewed on a plane, and the diagonal direction is non-parallel to one side of the display device in which the driving control unit is disposed adjacently.

[0006] According to an embodiment, a display device may be provided in which the first power line and the second power line have a plate shape when viewed in a planar view, the first power line includes a first adjacent line adjacent to the second power line, the second power line includes a second adjacent line adjacent to the second power line, and the first power line and the second power line do not overlap each other when viewed in a planar view.

[0007] According to an embodiment, a display device may be provided in which the first adjacent line and the second adjacent line are parallel to each other.

[0008] According to an embodiment, a display device may be provided in which the first adjacent line and the second adjacent line are formed such that the drive control unit is offset from one side of the display device adjacent to it.

[0009] According to an embodiment, a display device may be provided in which the first adjacent line and the second adjacent line have a stepped shape.

[0010] According to an embodiment, a display device may be provided in which the first power line and the second power line are placed on the same layer, and the fan-out line is placed on a different layer from the first power line and the second power line.

[0011] According to an embodiment, a display device may be provided that further comprises a transistor electrically connected to the driving control unit and including a first transistor electrode and a second transistor electrode, wherein the first transistor electrode and the second transistor electrode are disposed on the same layer as the first power line and the second power line.

[0012] According to an embodiment, a display device may be provided that further comprises a barrier electrode layer that overlaps with at least a portion of the transistor when viewed in a planar view, wherein the barrier electrode layer is disposed on the same layer as the fan-out line.

[0013] According to an embodiment, a display device may be provided in which at least a portion of the fan-out line overlaps with the spacing area when viewed on a plane.

[0014] According to an embodiment, a display device may be provided in which the fan-out line includes a first fan-out line, a second fan-out line, and a third fan-out line, wherein the first fan-out line, the second fan-out line, and the third fan-out line are spaced apart in a first direction, and at least a portion of each of the first fan-out line, the second fan-out line, and the third fan-out line extends in a second direction.

[0015] According to an embodiment, a display device may be provided in which the fan-out area includes a first area, a second area, and a third area, and the first area, the second area, and the third area are spaced apart from each other in the second direction when viewed on a plane, and the first area is positioned between the second area and the second area.

[0016] According to an embodiment, a display device may be provided in which the second direction is a direction from the drive control unit toward the display area.

[0017] According to an embodiment, a display device may be provided in which the fan-out area includes a first overlapping area and a second overlapping area, the first power line overlaps with the fan-out line within the first overlapping area, and the second power line overlaps with the fan-out line within the second overlapping area.

[0018] According to an embodiment, a display device may be provided in which the first fan-out line overlaps with the separation area within the first area when viewed on a plane, and the second fan-out line and the third fan-out line do not overlap with the separation area within the first area when viewed on a plane.

[0019] According to an embodiment, a display device may be provided in which the second fan-out line overlaps with the spacing area within the second area when viewed on a plane, and the first fan-out line and the third fan-out line do not overlap with the spacing area within the second area when viewed on a plane.

[0020] According to an embodiment, a display device may be provided in which the third fan-out line overlaps with the spacing area within the third area when viewed on a plane, and the first fan-out line and the second fan-out line do not overlap with the spacing area within the third area when viewed on a plane.

[0021] According to an embodiment, a display device may be provided in which, when viewed on a plane within the first region, the second fan-out line overlaps with the second overlapping region and the third fan-out line overlaps with the first overlapping region; when viewed on a plane within the second region, the first fan-out line overlaps with the first overlapping region and the third fan-out line overlaps with the first overlapping region; and when viewed on a plane within the third region, the first fan-out line overlaps with the second overlapping region and the second fan-out line overlaps with the second overlapping region.

[0022] According to an embodiment, a display device may be provided in which the driving control unit includes a scan driving unit, a data driving unit, and a compensation unit for driving the pixel, and the scan driving unit, the data driving unit, and the compensation unit are disposed on one side of the display area.

[0023] According to an embodiment, a display device may be provided in which the width of the fan-out area widens as it moves from the drive control unit toward the display area.

[0024] According to an embodiment, a display device may be provided in which the fan-out line comprises at least one of a scan line, a data line, and a sensing line electrically connected to the pixel.

[0025] The means for solving the problem of the present invention are not limited to the means for solving the problem described above, and unmentioned means for solving the problem will be clearly understood by those skilled in the art from this specification and the attached drawings. Effects of the invention

[0026] According to one embodiment of the present invention, a display device can be provided in which the resistance deviation of the wirings at different locations is reduced and short-circuit defects between electrode configurations are prevented.

[0027] The effects of the present invention are not limited to the effects described above, and unmentioned effects will be clearly understood by those skilled in the art from this specification and the accompanying drawings. Brief explanation of the drawing

[0028] FIGS. 1 and FIGS. 2 are a perspective view and a cross-sectional view showing a light-emitting element according to one embodiment. FIG. 3 is a block diagram showing a display device according to an embodiment. FIG. 4 is a plan view showing a display device according to an embodiment. FIG. 5 is a circuit diagram showing a pixel circuit included in a pixel according to an embodiment. FIG. 6 is a drawing for explaining a stacked structure included in a display device according to an embodiment. Figure 7 is a cross-sectional view according to I~I' of Figure 4. Figures 8 and 9 are enlarged views of the EA1 area of ​​Figure 4. Figure 10 is an enlarged view of the EA2 area of ​​Figure 8. FIG. 11 is a cross-sectional view according to II to II' of FIG. 10. FIG. 12 is a cross-sectional view according to III to III' of FIG. 10. FIG. 13 is a cross-sectional view according to Ⅳ~Ⅳ' of FIG. 10. Specific details for implementing the invention

[0029] The embodiments described in this specification are intended to clearly explain the concept of the invention to those skilled in the art to which the invention pertains; therefore, the invention is not limited by the embodiments described in this specification, and the scope of the invention should be interpreted to include modifications or variations that do not depart from the concept of the invention.

[0030] The terms used in this specification have been selected to be as widely used as possible, taking into account their functions in the present invention; however, they may vary depending on the intent, custom, or emergence of new technologies of those skilled in the art to which the present invention pertains. However, if a specific term is defined and used with an arbitrary meaning, the meaning of that term will be described separately. Accordingly, the terms used in this specification should be interpreted based on their actual meaning and the content throughout this specification, rather than merely their names.

[0031] The drawings attached to this specification are intended to facilitate the explanation of the present invention. Since the shapes depicted in the drawings may be exaggerated as necessary to aid in understanding the present invention, the present invention is not limited by the drawings.

[0032] In cases where it is determined that a specific description of known configurations or functions related to the present invention in this specification may obscure the essence of the present invention, such detailed description will be omitted as necessary.

[0033] The present invention relates to a display device. Hereinafter, a display device according to an embodiment will be described with reference to FIGS. 1 to 13.

[0034] FIGS. 1 and 2 illustrate a light-emitting element (LD) included in a display device (see '100' in FIG. 3) according to an embodiment. FIGS. 1 and 2 are a perspective view and a cross-sectional view showing a light-emitting element according to one embodiment. FIGS. 1 and 2 illustrate a columnar light-emitting element (LD), but the type and / or shape of the light-emitting element (LD) is not limited thereto.

[0035] Referring to FIGS. 1 and 2, the light-emitting element (LD) may include a first semiconductor layer (11) and a second semiconductor layer (13), and an active layer (12) interposed between the first and second semiconductor layers (11, 13). For example, if the extension direction of the light-emitting element (LD) is the length (L) direction, the light-emitting element (LD) may include a first semiconductor layer (11), an active layer (12), and a second semiconductor layer (13) that are sequentially stacked along the length (L) direction.

[0036] The light-emitting element (LD) may be provided in a columnar shape extending along one direction. The light-emitting element (LD) may have a first end (EP1) and a second end (EP2). One of the first and second semiconductor layers (11, 13) may be adjacent to the first end (EP1) of the light-emitting element (LD). The other of the first and second semiconductor layers (11, 13) may be adjacent to the second end (EP2) of the light-emitting element (LD).

[0037] According to the embodiments, the light-emitting element (LD) may be a light-emitting element manufactured into a pillar shape through an etching method or the like. In this specification, the term "pillar shape" encompasses a rod-like shape or a bar-like shape that is long in the length (L) direction (i.e., the aspect ratio is greater than 1), such as a cylindrical column or a polygonal column, and the shape of the cross-section is not particularly limited. For example, the length (L) of the light-emitting element (LD) may be larger than its diameter (D) (or the width of the cross-section).

[0038] According to the embodiments, the light-emitting element (LD) may have a size ranging from nanoscale to microscale. For example, the diameter (D) and / or length (L) of the light-emitting element (LD) may have a size ranging from nanoscale to microscale. The size of the light-emitting element (LD) is not limited thereto.

[0039] The first semiconductor layer (11) may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer (11) may include an N-type semiconductor layer. As an example, the first semiconductor layer (11) may include any one of the semiconductor materials of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an N-type semiconductor layer doped with a first conductivity type dopant such as Si, Ge, Sn, etc. However, the material constituting the first semiconductor layer (11) is not limited thereto, and the first semiconductor layer (11) may be composed of various other materials.

[0040] The active layer (12) is disposed on the first semiconductor layer (11) and can be formed as a single-quantum well or multi-quantum well structure. The position of the active layer (12) can be varied depending on the type of light-emitting element (LD).

[0041] According to an embodiment, a clad layer (not shown) doped with a conductive dopant may be further formed on the upper and / or lower portion of the active layer (12). For example, the clad layer may be formed as an AlGaN layer or an InAlGaN layer. According to an embodiment, materials such as AlGaN and InAlGaN may be used to form the active layer (12), and various other materials may also constitute the active layer (12).

[0042] The second semiconductor layer (13) is disposed on the active layer (12) and may include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include a P-type semiconductor layer. As an example, the second semiconductor layer (13) may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a second conductivity type dopant such as Mg. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may also constitute the second semiconductor layer (13).

[0043] When a voltage greater than the threshold voltage is applied to both ends of the light-emitting element (LD), electron-hole pairs combine in the active layer (12), causing the light-emitting element (LD) to emit light. By controlling the light emission of the light-emitting element (LD) using this principle, the light-emitting element (LD) can be used as a light source for various light-emitting devices, including pixels of a display device.

[0044] According to an embodiment, the light-emitting element (LD) may further include an insulating film (INF) provided on its surface. The insulating film (INF) may be formed on the surface of the light-emitting element (LD) to surround at least the outer surface of the active layer (12), and may also further surround a portion of the first and second semiconductor layers (11, 13). The insulating film (INF) may be formed as a single film or a double film, but is not limited thereto and may be composed of a plurality of films. As an example, the insulating film (INF) may include a first insulating film comprising a first material and a second insulating film comprising a second material different from the first material.

[0045] According to an embodiment, the insulating film (INF) may expose both ends of a light-emitting element (LD) having different polarities. For example, the insulating film (INF) may expose one end of each of the first and second semiconductor layers (11, 13) located at the first and second ends (EP1, EP2) of the light-emitting element (LD). In another embodiment, the insulating film (INF) may expose the sides of the first and second semiconductor layers (11, 13) adjacent to the first and second ends (EP1, EP2) of the light-emitting element (LD) having different polarities.

[0046] According to an embodiment, the insulating film (INF) may be composed of a single layer or multiple layers comprising at least one insulating material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and titanium oxide (TiOx), but is not limited thereto. For example, according to another embodiment, the insulating film (INF) may be omitted.

[0047] According to the embodiment, the insulating film (INF) can ensure electrical stability of the light-emitting element (LD) and minimize surface defects of the light-emitting element (LD), thereby improving lifespan and efficiency.

[0048] According to an embodiment, the light-emitting element (LD) may additionally include one or more phosphor layers, active layers, semiconductor layers, and / or electrode layers disposed on one side of the first semiconductor layer (11), active layer (12), and / or second semiconductor layer (13). As an example, a contact electrode layer may be further disposed at the first and second ends (EP1, EP2) of the light-emitting element (LD), respectively. However, the structure of the light-emitting element (LD) is not limited to the example described above.

[0049] FIG. 3 is a block diagram showing a display device according to an embodiment.

[0050] The display device (100) may refer to a device configured to output optical data. The display device (100) may be an electronic device that uses the light-emitting element (LD) described above with reference to FIGS. 1 and FIGS. 2 as a light source. According to one embodiment, the display device (100) may be a tablet PC, a television, a smartphone, or a laptop, but is not limited to specific examples.

[0051] According to an embodiment, the display device (100) may include a pixel unit (110) and a driving control unit (D-IC). According to one example, the driving control unit (D-IC) may include a scan driving unit (120), a data driving unit (130), a compensation unit (140), and a control unit (150).

[0052] The pixel section (110) may include a pixel (see 'PX' in FIG. 4). The pixel section (110) may include a plurality of subpixels (SPX) connected to a scan line (SL) and a data line (DL).

[0053] According to an embodiment, at least one of the subpixels (SPX) can form a pixel (PX). The subpixels (SPX) can form a single pixel (PX). For example, the subpixels (SPX) may include a first subpixel capable of emitting red light, a second subpixel capable of emitting green light, and a third subpixel capable of emitting blue light. However, the color and composition of the light emitted by each subpixel (SPX) are not limited thereto.

[0054] A scan drive unit (120) may be positioned on one side of a pixel unit (110). The scan drive unit (120) may receive a first control signal (SCS) from a control unit (150). The scan drive unit (120) may supply a scan signal to scan lines (SL) in response to the first control signal (SCS).

[0055] According to an embodiment, the first control signal (SCS) may be a signal for controlling the driving timing of the scan driving unit (120). The first control signal (SCS) may include a scan start signal and a plurality of clock signals for the scan signal. The scan signal may be set to a gate-on level corresponding to the type of transistor to which the scan signal is supplied (for example, first to third transistors (see 'T1~T3' in FIG. 5)).

[0056] The data driving unit (130) may be positioned on one side of the pixel unit (110). The data driving unit (130) may receive a second control signal (DCS) from the control unit (150). The data driving unit (130) may supply a data signal to the data line (DL) in response to the second control signal (DCS).

[0057] According to the embodiment, the second control signal (DCS) may be a signal for controlling the driving timing of the data driving unit (130).

[0058] The compensation unit (140) may be positioned on one side of the pixel unit (110). The compensation unit (140) may receive a sensing value (current or voltage information) extracted from a subpixel (SPX) through a sensing line (SENL). Based on the sensing value, the compensation unit (140) may generate a compensation value that compensates for the degradation of the subpixel (SPX). For example, the compensation unit (140) may obtain information regarding changes in the characteristics of the first transistor (see 'T1' in FIG. 5) and / or the light-emitting element (LD) (for example, changes in the threshold voltage, mobility, and other characteristics of the first transistor (T1)). Based on the information regarding the changes in characteristics, the compensation unit (140) may calculate a compensation value that compensates for a data signal and provide it to the control unit (150) or the data driving unit (130).

[0059] According to an embodiment, the compensation unit (140) can receive a third control signal (CCS) from the control unit (150). The compensation unit (140) can supply a sensing signal to a subpixel (SPX) in response to the third control signal (CCS).

[0060] According to an embodiment, the third control signal (CCS) may be a signal for controlling the operation of a compensation unit (140) for sensing and degradation compensation of subpixels (SPX).

[0061] The control unit (150) can acquire a first control signal (SCS), a second control signal (DCS), and a third control signal (CCS). The control unit (150) can generate the first control signal (SCS) and the second control signal (DCS) and provide them to the scan drive unit (120) and the data drive unit (130), respectively. The control unit (150) can generate the third control signal (CCS) and provide it to the compensation unit (140).

[0062] According to an embodiment, a single-side driving structure may be provided in which a scan driving unit (120), a data driving unit (130), and a compensation unit (140) are disposed on one side of a pixel unit (110). Hereinafter, for convenience of explanation, a display device (100) including a single-side driving structure will be described.

[0063] According to an embodiment, to apply a short-range driving structure to a display device (100), the scan line (SL) may include a main scan line (SML) and a sub-scan line (SSL).

[0064] A main scan line (SML) can be connected to at least one sub-scan line (SSL). For example, as shown in FIG. 3, two sub-scan lines (SSL) can be electrically connected to one main scan line (SML).

[0065] The main scan line (SML) is extended in a first direction (DR1) and can be connected to a subpixel (SPX) of the corresponding pixel row. The main scan line (SML) can supply a scan signal to the subpixel (SPX).

[0066] The sub-scan line (SSL) is extended in a second direction (DR2) and can be connected to the main scan line (SML) at the contact part (CP). The sub-scan line (SSL) can electrically connect the scan drive part (120) and the main scan line (SML).

[0067] According to an embodiment, in a single-sided drive structure, the scan drive unit (120) and the data drive unit (130) are positioned on the same side, so that the data lines (DL) and sub-scan lines (SSL) can be extended in the same direction (for example, a second direction (DR2)).

[0068] The pixel row direction is horizontal and may refer to the first direction (DR1). The pixel column direction is vertical and may refer to the second direction (DR2). The pixel row and pixel column may be defined by the arrangement of subpixels (SPX). The pixel row may be defined by the main scan line (SML).

[0069] The data line (DL) can be extended along a pixel column (e.g., a second direction (DR2)) and connected to a subpixel (SPX). The data line (DL) can supply a data signal to the connected subpixel (SPX).

[0070] In FIG. 3, the scan driving unit (120), data driving unit (130), compensation unit (140), and control unit (150) are shown separately, but at least some of the scan driving unit (120), data driving unit (130), compensation unit (140), and control unit (150) may be integrated into a single module or IC chip (integrated circuit chip). For example, at least some of the configuration and / or functions of the control unit (150) may be included in the data driving unit (130).

[0071] Although not illustrated in the drawings, according to an embodiment, the scan driving unit (120) may be composed of a plurality of scan driving units (e.g., a plurality of scan driving chips or scan driving circuits) each responsible for driving a portion of the pixel unit (110). The data driving unit (130) may be composed of a plurality of data driving units (e.g., a plurality of data driving chips or data driving circuits) each responsible for driving a portion of the pixel unit (110).

[0072] FIG. 4 is a plan view showing a display device according to an embodiment.

[0073] Referring to FIG. 4, the display device (100) may include a base layer (BSL) and a pixel (PX) including a light-emitting element (LD). According to one embodiment, the display device (100) may include a display area (DA) and a non-display area (NDA). The display device (100) may include a driving control unit (D-IC) and a wiring unit (LP).

[0074] The base layer (BSL) may constitute a base member of the display device (100). According to one example, the base layer (BSL) may be a rigid or flexible substrate or film, but is not limited to specific examples.

[0075] A pixel portion (110) may be placed within the display area (DA). The display area (DA) may refer to an area where a pixel (PX) is placed. Light may be emitted from the display area (DA). The non-display area (NDA) may refer to an area where a pixel (PX) is not placed. The non-display area (NDA) may refer to an area outside the display area (DA). For example, the non-display area (NDA) may be provided in a form that surrounds at least a portion of the display area (DA).

[0076] According to an embodiment, a driving control unit (D-IC) and a wiring unit (LP) may be disposed in a non-display area (NDA). Although not shown in the drawing, according to one example, a pad portion electrically connecting the driving control unit (D-IC) and the wiring unit (LP) may be further disposed in the non-display area (NDA).

[0077] Pixels (PX) may be placed within a display area (DA). Pixels (PX) may be arranged regularly according to a stripe or Pentile™ array structure, etc. However, the array structure of the pixels (PX) is not limited to these.

[0078] According to an embodiment, a pixel (PX) may be connected to a driving control unit (D-IC) through a wiring unit (LP). The wiring unit (LP) may include a fan-out line (see '320' in FIG. 8), a first power line (see 'VDD' in FIG. 5), and a second power line (see 'VSS' in FIG. 5). The fan-out line (320) may include a scan line (SL), a data line (DL), and a sensing line (SENL).

[0079] The driving control unit (D-IC) can provide a predetermined signal and a predetermined power to the pixel (PX). The pixel (PX) can be driven based on the predetermined signal and the predetermined power. The signal and power applied from the driving control unit (D-IC) can be applied to the pixel (PX) via the wiring unit (LP). According to one embodiment, the pixel (PX) can be driven based on electrical signals provided from the scan line (SL), data line (DL), sensing line (SENL), first power line (VDD), and second power line (VSS).

[0080] The wiring section (LP) may be placed within the non-display area (NDA). The wiring section (LP) may surround at least a portion of the display area (DA). According to one example, at least a portion of the wiring section (LP) may be placed between the display area (DA) and the driving control section (D-IC). In FIG. 4, the wiring section (LP) is shown placed only between the display area (DA) and the driving control section (D-IC), but is not limited thereto. According to an embodiment, the wiring section (LP) may be placed at a location adjacent to the display area (DA).

[0081] According to an embodiment, the wiring section (LP) can electrically connect the driving control section (D-IC) and the pixel (PX). According to one example, the wiring section (LP) may include at least a portion of each of the scan line (SL), the data line (DL), the first power line (VDD), and / or the second power line (VSS).

[0082] According to an embodiment, the wiring section (LP) may include a fan-out area (300). The wiring section (LP) may include a fan-out line (320) placed within the fan-out area (300). The fan-out area (300) may be placed between the display area (DA) and the driving control section (D-IC) when viewed in a planar view.

[0083] According to one example, the fan-out line (320) may include at least a portion of each of the scan line (SL), data line (DL), and sensing line (SENL), as wirings arranged within the fan-out area (300) when viewed in a plane.

[0084] According to an embodiment, at least a portion of each of the first power line (VDD) and the second power line (VSS) may be placed within the fan-out area (300).

[0085] According to the embodiment, the fan-out area (300) may have a shape that widens as it moves in one direction. The fan-out area (300) may have different widths depending on the second direction (DR2). For example, the width of the fan-out area (300) may widen as it moves from the driving control unit (D-IC) toward the display area (DA).

[0086] FIG. 5 is a circuit diagram showing a pixel circuit included in a pixel according to an embodiment.

[0087] The subpixel (SPXij) illustrated in FIG. 5 may be any one of the subpixels (SPX) described above with reference to FIG. 3, and may refer to a subpixel (SPX) connected to the i-th scan line (SLi), the j-th data line (DLj), the i-th sensing signal line (SELi), and the j-th sensing line (SENLj). (Here, i and j are natural numbers.)

[0088] Referring to FIG. 5, the subpixel (SPXij) may include a light-emitting element (LD) and a pixel circuit (PXC).

[0089] A light-emitting element (LD) can be connected between a first power line (VDD) and a second power line (VSS). One end of the light-emitting element (LD) (e.g., a P-type semiconductor) is connected to the first power line (VDD) via a pixel circuit (PXC), and the other end of the light-emitting element (LD) (e.g., an N-type semiconductor) can be connected to the second power line (VSS) via a power line (PL).

[0090] According to an embodiment, when a driving current is supplied through a pixel circuit (PXC), the light-emitting element (LD) can emit light of a brightness corresponding to the driving current.

[0091] According to an embodiment, light-emitting elements (LDs) can be connected to each other through various connection structures between a first power line (VDD) and a second power line (VSS). For example, the light-emitting elements (LDs) may be connected only in parallel or only in series. Alternatively, the light-emitting elements (LDs) may be connected in a mixed series / parallel structure.

[0092] The first power line (VDD) and the second power line (VSS) may have different potentials so that the light-emitting elements (LDs) can emit light. For example, the first power line (VDD) may be set to a higher potential than the second power line (VSS). According to an embodiment, the first power line (VDD) and the second power line (VSS) may have a potential difference sufficient to allow light to be emitted during the light emission period of the subpixel (SPXij).

[0093] The pixel circuit (PXC) can connect the first power line (VDD) and the light-emitting element (LD). The pixel circuit (PXC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a storage capacitor (Cst).

[0094] One electrode of the first transistor (T1) is connected to the first power line (VDD), and the other electrode can be connected to one electrode of the light-emitting element (LD) (for example, the anode electrode). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) can control the current flowing through the light-emitting element (LD) in response to the voltage applied through the first node (N1).

[0095] One electrode of the second transistor (T2) may be connected to the j-th data line (DLj), and the other electrode may be connected to the first node (N1). The gate electrode of the second transistor (T2) may be connected to the i-th scan line (SLi). The second transistor (T2) is turned on when a scan signal is supplied from the i-th scan line (SLi), and at this time, the data signal provided from the j-th data line (DLj) may be transmitted to the first node (N1).

[0096] One electrode of the third transistor (T3) may be connected to the j-th sensing line (SENLj), and the other electrode may be connected to the second node (N2). The gate electrode of the third transistor (T3) may be connected to the i-th sensing signal line (SELi). When the third transistor (T3) is turned on in response to a sensing signal provided from the i-th sensing signal line (SELi), a reference voltage may be provided to the second node (N2) through the j-th sensing line (SENLj).

[0097] According to an embodiment, the reference voltage may serve to set or initialize the voltage of the electrode of the first transistor (T1) connected to the light-emitting element (LD) (for example, the source electrode of the first transistor (T1)) to a constant value. According to an example, the reference voltage may be set to a voltage lower than or equal to that of the second power line (VSS).

[0098] According to an embodiment, when the third transistor (T3) is turned on in response to a sensing signal provided from the i-th sensing signal line (SELi), it can transmit a sensing current to the j-th sensing line (SENLj).

[0099] According to an embodiment, the sensing current may be provided to a compensation unit (140). The sensing current may be used to calculate the mobility of the first transistor (T1) and the amount of change in the threshold voltage.

[0100] A storage capacitor (Cst) can be connected between a first node (N1) (or the gate electrode of the first transistor (T1)) and a second node (N2) (or the other electrode of the first transistor (T1)). The storage capacitor (Cst) can store information regarding the difference between the voltage of the first node (N1) and the voltage of the second node (N2).

[0101] Meanwhile, the structure of the pixel circuit (PXC) is not limited to the structure shown in FIG. 5, and various types of structures can be implemented.

[0102] FIG. 6 is a drawing for explaining a stacked structure included in a display device according to an embodiment.

[0103] Referring to FIG. 6, the stacked structure included in the display device according to the embodiment may have a structure in which at least a portion is patterned in a structure in which a base layer (BSL), a barrier electrode layer (BML), a buffer layer (BFL), an active layer (ACT), a gate insulating layer (GI), a gate electrode layer (GE), an interlayer insulating layer (ILD), a source / drain electrode layer (SDL), a protection layer (PSV), and an alignment electrode layer (ELT) are sequentially stacked.

[0104] The base layer (BSL) constitutes the base member of the display device (100) and may mean a rigid or flexible substrate or film.

[0105] A buffer layer (BFL) may be disposed on a base layer (BSL). The buffer layer (BFL) may refer to a layer for preventing the diffusion of impurities or moisture penetration into an active layer (ACT) containing a semiconductor. According to one example, the buffer layer (BFL) may include at least one metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), etc.

[0106] The active layer (ACT) may be a layer containing a semiconductor. For example, the active layer (ACT) may include at least one of polysilicon, amorphous silicon, and an oxide semiconductor. According to one embodiment, the active layer (ACT) may form the channel of each transistor (T1 to T3), and the portion in contact with the source / drain electrode layer (SDL) may be doped with impurities.

[0107] The barrier electrode layer (BML), gate electrode layer (GE), source / drain electrode layer (SDL), and alignment electrode layer (ELT) may be layers containing a conductor. Each of the barrier electrode layer (BML), gate electrode layer (GE), and source / drain electrode layer (SDL) may be composed of a single layer or multiple layers. According to one embodiment, each of the barrier electrode layer (BML), gate electrode layer (GE), and source / drain electrode layer (SDL) may include any one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt), but is not limited thereto.

[0108] A gate insulating layer (GI), an interlayer insulating layer (ILD), and a protective layer (PSV) may be interposed between each layer to electrically isolate the active layer (ACT), the gate electrode layer (GE), the source / drain electrode layer (SDL), and the alignment electrode layer (ELT) from one another. According to an embodiment, the required electrode patterns may be electrically connected to each other through contact holes formed in the gate insulating layer (GI), the interlayer insulating layer (ILD), and the protective layer (PSV).

[0109] According to an embodiment, the gate insulating layer (GI), the interlayer insulating layer (ILD), and the protective layer (PSV) may comprise at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). According to an embodiment, the gate insulating layer (GI), the interlayer insulating layer (ILD), and the protective layer (PSV) may comprise an organic material and may be composed of a single or multiple layers.

[0110] Hereinafter, with reference to FIG. 7, the structure of a pixel (PX) according to an embodiment will be described.

[0111] Figure 7 is a cross-sectional view according to I~I' of Figure 4.

[0112] Referring to FIG. 7, the pixel (PX) may include a base layer (BSL), a pixel circuit (PCL), and a display element (DPL). For convenience of explanation, the following description will focus on the first transistor (T1) among the first to third transistors (T1 to T3). Additionally, configurations identical to those described above are referred to by the same reference numerals, and any content that may be duplicated is omitted or briefly explained.

[0113] As described above, the base layer (BSL) can constitute the base surface of the pixel (PX). The base layer (BSL) may refer to a rigid or flexible substrate or film, but is not limited thereto.

[0114] A pixel circuit (PCL) may be disposed on a base layer (BSL). The pixel circuit (PCL) may include a buffer layer (BFL), a first transistor (T1), a gate insulating layer (GI), an interlayer insulating layer (ILD), a first contact hole (CH1), a second contact hole (CH2), and a protection layer (PSV).

[0115] The base electrode layer (BML) can be placed on the base layer (BSL).

[0116] The first transistor (T1) may be a driving transistor. The first transistor (T1) may include an active layer (ACT), a gate electrode layer (GE), a first transistor electrode (TE1), and a second transistor electrode (TE2).

[0117] The active layer (ACT) may be located on the buffer layer (BFL). The active layer (ACT) may include at least one of polysilicon, amorphous silicon, and oxide semiconductor.

[0118] The active layer (ACT) may include a first contact region in contact with a first transistor electrode (TE1) and a second contact region in contact with a second transistor electrode (TE2). The first contact region and the second contact region may be semiconductor patterns doped with impurities. The region between the first contact region and the second contact region may be a channel region. The channel region may be an intrinsic semiconductor pattern not doped with impurities.

[0119] The gate insulating layer (GI) can be placed on the active layer (ACT).

[0120] The gate electrode layer (GE) can be disposed on the gate insulating layer (GI). The location of the gate electrode layer (GE) can correspond to the location of the channel region of the active layer (ACT). For example, the gate electrode layer (GE) can be disposed on the channel region of the active layer (ACT) with the gate insulating layer (GI) in between.

[0121] An interlayer insulating layer (ILD) can be placed on the gate electrode layer (GE).

[0122] The first transistor electrode (TE1) and the second transistor electrode (TE2) may be located on the interlayer insulating layer (ILD). The first transistor electrode (TE1) may penetrate the interlayer insulating layer (ILD) and the gate insulating layer (GI) to contact the first contact region of the active layer (ACT), and the second transistor electrode (TE2) may penetrate the interlayer insulating layer (ILD) and the gate insulating layer (GI) to contact the second contact region of the active layer (ACT).

[0123] According to an embodiment, the first transistor electrode (TE1) can be electrically connected to the first connecting wire (CNL1) through a first contact hole (CH1) penetrating the protective layer (PSV). According to one example, the first transistor electrode (TE1) may be a source electrode and the second transistor electrode (TE2) may be a drain electrode.

[0124] The power line (PL) may be placed on the interlayer insulation layer (ILD). The power line (PL) may be electrically connected to the second connecting wire (CNL2) through a second contact hole (CH2) penetrating the protective layer (PSV). According to one embodiment, an electrical signal may be provided to the power line (PL) from the second power line (VSS).

[0125] The protective layer (PSV) may be located on the interlayer insulating layer (ILD). The protective layer (PSV) may cover the first transistor electrode (TE1), the second transistor electrode (TE2), and the power line (PL).

[0126] The display element section (DPL) may be placed on the pixel circuit section (PCL). The display element section (DPL) may include a bank pattern (BNP), a first electrode (ELT1), a second electrode (ELT2), a first insulating film (INS1), a light-emitting element (LD), a first contact electrode (CNE1), a second contact electrode (CNE2), a second insulating film (INS2), a bank (BNK), and a third insulating film (INS3).

[0127] The bank pattern (BNP) may have a shape protruding in an upward direction. According to one example, the upward direction may refer to the display direction and / or third direction (DR3) where light is emitted from the light-emitting element (LD). A first electrode (ELT1) and a second electrode (ELT2) may be arranged on the bank pattern (BNP) to form a reflective barrier.

[0128] The first electrode (ELT1) may be placed on a protective layer (PSV) or a bank pattern (BNP). The first electrode (ELT1) may be a path through which an electrical signal applied via the first connecting wire (CNL1) is provided. According to one example, power supplied from the first power line (VDD) may be provided to a light-emitting element (LD) via the first connecting wire (CNL1) and the first electrode (ELT1).

[0129] The second electrode (ELT2) may be placed on the protective layer (PSV) or the bank pattern (BNP). The second electrode (ELT2) may be a path through which an electrical signal applied via the second connecting wire (CNL2) is provided. According to one example, power supplied from the second power line (VSS) may be provided to the light-emitting element (LD) via the power line (PL), the second connecting wire (CNL2), and the second electrode (ELT2).

[0130] According to the embodiment, the first electrode (ELT1) and the second electrode (ELT2) can be formed in the same process as the alignment electrode layer (ELT) described above with reference to FIG. 6.

[0131] A light-emitting element (LD) may be disposed on the first insulating layer (INS1). The first insulating layer (INS1) may be disposed on a protective layer (PSV). The first insulating layer (INS1) may be disposed on the first electrode (ELT1) and / or the second electrode (ELT2). The first insulating layer (INS1) can stabilize the connection between the electrode configurations and reduce external influences. According to one example, the first insulating layer (INS1) may comprise at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0132] A light-emitting element (LD) may be disposed on a first insulating film (INS1) between a first electrode (ELT1) and a second electrode (ELT2). The light-emitting element (LD) may be the light-emitting element (LD) described above with reference to FIGS. 1 and FIGS. 2.

[0133] The second insulating film (INS2) may be disposed on the light-emitting element (LD). The second insulating film (INS2) may cover the active layer (12) of the light-emitting element (LD). The second insulating film (INS2) may include either an organic material or an inorganic material. According to one embodiment, the second insulating film (INS2) may fill a groove provided on the back surface of the light-emitting element (LD).

[0134] The first contact electrode (CNE1) and the second contact electrode (CNE2) may be disposed on the first insulating film (INS1). The first contact electrode (CNE1) and the second contact electrode (CNE2) may each be electrically connected to the first electrode (ELT1) and the second electrode (ELT2) through a contact hole formed in the first insulating film (INS1).

[0135] According to an embodiment, the first contact electrode (CNE1) and the second contact electrode (CNE2) may include a conductive material. According to one example, the first contact electrode (CNE1) and the second contact electrode (CNE2) may include a transparent conductive material including ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ITZO (Indium Tin Zinc Oxide).

[0136] According to an embodiment, the light-emitting element (LD) can emit light based on electrical signals provided from the first contact electrode (CNE1) and the second contact electrode (CNE2).

[0137] A bank (BNK) may be a structure that defines the light-emitting region of a pixel (PX). The light-emitting region may refer to an area where light is emitted from a light-emitting element (LD). For example, a bank (BNK) may be placed at the boundary between adjacent pixels (PX).

[0138] The third insulating film (INS3) may be arranged on the bank (BNK), the first contact electrode (CNE1), the second contact electrode (CNE2), and the second insulating film (INS2). The third insulating film (INS3) may include either an organic material or an inorganic material. The third insulating film (INS3) can protect the display element part (DPL) from external influences.

[0139] The arrangement relationship regarding the light-emitting element (LD) and electrode configuration, etc., is not limited to the example described above with reference to FIG. 7, and arrangement relationships according to various modifiable embodiments may be implemented.

[0141] Hereinafter, with reference to FIGS. 8 to 13, an electrode structure within a non-display area (NDA) according to an embodiment will be described. As an example, the description will focus on the fan-out area (300) within the non-display area (NDA).

[0142] FIGS. 8 and FIGS. 9 are enlarged views of the EA1 area of ​​FIGS. 4. FIGS. 8 is a plan view showing a portion of the fan-out area (300) according to one embodiment. FIGS. 9 is a plan view showing a portion of the fan-out area (300) according to another embodiment.

[0143] Referring to FIG. 8, a first power line (VDD), a second power line (VSS), and a fan-out line (320) may be arranged within the fan-out area (300).

[0144] According to an embodiment, the first power line (VDD) and the second power line (VSS) may be placed on the same layer. For example, the first power line (VDD) and the second power line (VSS) may be placed on the same layer as the source / drain electrode layer (SDL). The first power line (VDD) and the second power line (VSS) may be formed within the same process.

[0145] According to an embodiment, the fan-out line (320) may be placed on a different layer from the first power line (VDD) and the second power line (VSS). For example, the fan-out line (320) may be placed on the same layer as the barrier electrode layer (BML). The fan-out line (320) may be formed in the same process as the barrier electrode layer (BML).

[0146] According to an embodiment, the first power line (VDD) and the second power line (VSS) may each have a plate shape. Accordingly, the first power line (VDD) and the second power line (VSS) having plate shapes are separated into multiple wires, and the separated multiple wires may be connected to each pixel (PX) within the display area (DA).

[0147] For example, a first power line (VDD) is electrically connected to wiring provided to a display area (DA) through a predetermined contact hole, and an electrical signal provided from the first power line (VDD) can be applied to a light-emitting element (LD). A second power line (VSS) is electrically connected to wiring provided to a display area (DA) through a predetermined contact hole, and an electrical signal provided from the second power line (VSS) can be applied to a light-emitting element (LD).

[0148] According to the embodiment, the first power line (VDD) and the second power line (VSS) may not overlap within the fan-out area (300) when viewed in a plane.

[0149] For example, the fan-out area (300) may include a first overlapping area (422), a second overlapping area (424), and a separation area (426). In this case, the first overlapping area (422) may refer to an area where the first power line (VDD) and the fan-out line (320) overlap when viewed on a plane. The second overlapping area (424) may refer to an area where the second power line (VSS) and the fan-out line (320) overlap when viewed on a plane. The separation area (426) may refer to an area where the first power line (VDD) and the second power line (VSS) are not placed.

[0150] Experimentally, when the first power line (VDD) and the second power line (VSS) overlap, there may be a risk of a short circuit defect occurring during the manufacturing process. However, according to the present embodiment, the first power line (VDD) and the second power line (VSS) are formed on the same layer but spaced apart by a predetermined distance, so that the risk of a short circuit defect can be reduced.

[0151] According to an embodiment, the fan-out line (320) may be positioned within a first overlapping area (422), a second overlapping area (424), and / or a spaced-out area (426) when viewed in a planar view. In FIG. 8, for convenience of explanation, the fan-out line (320) is shown arranged on the front of the fan-out area (300), but according to an embodiment, the fan-out line (320) may include a plurality of wires spaced apart from each other. For example, referring to FIG. 10, the fan-out line (320) may be composed of a plurality of wires spaced apart along a first direction (DR1) and at least a portion of which extends along a second direction (DR2).

[0152] However, it is not limited thereto, and various arrangement forms may be implemented to configure the fan-out area (300). For example, at least a portion of the fan-out line (320) within the fan-out area (300) may extend in a first direction (DR1), and at least another portion may extend in a second direction (DR2).

[0153] According to the embodiment, the first overlapping area (422) and the second overlapping area (424) may not overlap each other when viewed in a plane. The first power line (VDD) and the second power line (VSS) may be separated from each other with a separation area (426) in between.

[0154] According to an embodiment, the first power line (VDD) and the second power line (VSS) may be spaced apart from each other. For example, the first power line (VDD) may include a first adjacent line (432) positioned adjacent to the second power line (VSS), and the second power line (VSS) may include a second adjacent line (434) positioned adjacent to the first power line (VDD).

[0155] According to an embodiment, the first adjacent line (432) and the second adjacent line (434) may not overlap when viewed in a plane. According to one example, the first adjacent line (432) and the second adjacent line (434) may be formed parallel to each other.

[0156] According to an embodiment, the separation area (426) may be extended diagonally. The separation area (426) may be defined by a first power line (VDD) and a second power line (VSS). For example, the shape of the separation area (426) may be defined by a first adjacent line (432) of the first power line (VDD) and a second adjacent line (434) of the second power line (VSS). According to one example, at least a portion of the separation area (426) may be extended in a diagonal direction, and the diagonal direction may be non-parallel to one side of the display device (100). Referring to FIG. 4 in conjunction with FIG. 8, one side of the display device (100) to which the driving control unit (D-IC) is placed adjacently may be extended in a first direction (DR1), and the diagonal direction may be formed to be at least offset from the first direction (DR1). The first adjacent line (432) and the second adjacent line (434) can be at least parallel to the first direction (DR1).

[0157] However, the shapes of the first power line (VDD) and the second power line (VSS) are not limited thereto. With reference to FIG. 9, the shapes of the first power line (VDD) and the second power line (VSS) according to another embodiment will be described.

[0158] According to the embodiment, the first power line (VDD) and the second power line (VSS) may have a stepped shape. For example, the first adjacent line (432) and the second adjacent line (434) may be implemented in a stepped shape.

[0159] According to the embodiment, the first adjacent line (432) and the second adjacent line (434) may be extended unevenly. The first adjacent line (432) and the second adjacent line (434) may not have the shape of a uniformly extended line.

[0160] For example, the first adjacent line (432) may include a first-1 protrusion and a first-2 protrusion that is different from the first-1 protrusion. Likewise, the second adjacent line (434) may include a second-1 protrusion and a second-2 protrusion that is different from the second-1 protrusion.

[0161] Hereinafter, with reference to FIGS. 10 to 13, the first power line (VDD), the second power line (VSS), and the fan-out line (320) according to the embodiment will be described in more detail.

[0162] FIG. 10 is an enlarged view of the EA2 region of FIG. 8. FIG. 11 is a cross-sectional view according to II to II' of FIG. 10. FIG. 12 is a cross-sectional view according to III to III' of FIG. 10. FIG. 13 is a cross-sectional view according to IV to IV' of FIG. 10.

[0163] Referring to FIGS. 10 to 13, the spacing area (426) may overlap with at least a portion of the fan-out line (320). At this time, the fan-out line (320) may be provided in multiple numbers, and each of the multiple fan-out lines (320) may have different positions overlapping with the spacing area (426).

[0164] According to the embodiment, the fan-out lines (320) may be any one of a scan line (SL), a data line (DL), and a sensing line (SENL), but are not limited thereto. As an example, the fan-out lines (320) may correspond to at least one of the lines that provide an electrical signal applied to a pixel (PX) within a display area (DA).

[0165] Hereinafter, the fan-out line (320) is described based on an embodiment in which the fan-out line (320) includes a first fan-out line (322), a second fan-out line (324), a third fan-out line (326), a fourth fan-out line (328), and a fifth fan-out line (329).

[0166] According to an embodiment, the first fan-out line (322), the second fan-out line (324), the third fan-out line (326), the fourth fan-out line (328), and the fifth fan-out line (329) may be spaced apart from each other in a first direction (DR1) and may have a shape that extends in a second direction (DR2). At least a portion of each of the first fan-out line (322), the second fan-out line (324), the third fan-out line (326), the fourth fan-out line (328), and the fifth fan-out line (329) may have a shape that extends in the second direction (DR2).

[0167] The fan-out area (300) may include a first area (352), a second area (354), and a third area (356). The first area (352), the second area (354), and the third area (356) may be separated along the direction of electrical signal transmission of the fan-out line (320). For example, the first area (352), the second area (354), and the third area (356) may be separated along a second direction (DR2). In this case, the second direction (DR2) may mean the direction from the driving control unit (D-IC) toward the display area (DA) when referring to FIG. 4.

[0168] FIG. 11 is a cross-sectional view centered on the first region (352) of the fan-out region (300). FIG. 12 is a cross-sectional view centered on the second region (354) of the fan-out region (300). FIG. 13 is a cross-sectional view centered on the third region (356) of the fan-out region (300).

[0169] Referring to FIGS. 10 and 11, within the first region (352), the separation region (426) may overlap with the first fan-out line (322) when viewed in a plane.

[0170] According to an embodiment, within the first region (352), the spaced region (426) may not overlap with the second fan-out line (324), the third fan-out line (326), the fourth fan-out line (328), and the fifth fan-out line (329).

[0171] According to an embodiment, within the first region (352), the first overlapping region (422) may overlap with the third fan-out line (326) and the fifth fan-out line (329) when viewed in a plane.

[0172] According to an embodiment, within the first region (352), the second overlapping region (424) may overlap with the second fan-out line (324) and the fourth fan-out line (328) when viewed in a plane.

[0173] Referring to FIGS. 10 and FIGS. 12, within the second region (354), the separation region (426) may overlap with the second fan-out line (324) when viewed in a plane.

[0174] According to an embodiment, within the second region (354), the spaced region (426) may not overlap with the first fan-out line (322), the third fan-out line (326), the fourth fan-out line (328), and the fifth fan-out line (329).

[0175] According to the embodiment, within the second region (354), the first overlapping region (422) may overlap with the first fan-out line (322), the third fan-out line (326), and the fifth fan-out line (329) when viewed in a plane.

[0176] According to the embodiment, within the second region (354), the second overlapping region (424) may overlap with the fourth fan-out line (328) when viewed in a plane.

[0177] Referring to FIG. 10 and FIG. 13, within the third region (356), the separation region (426) may overlap with the third fan-out line (326) when viewed in a plane.

[0178] According to an embodiment, within the third region (356), the spaced region (426) may not overlap with the first fan-out line (322), the second fan-out line (324), the fourth fan-out line (328), and the fifth fan-out line (329).

[0179] According to the embodiment, within the third region (356), the first overlapping region (422) may overlap with the fifth fan-out line (329) when viewed in a plane.

[0180] According to the embodiment, within the third region (356), the second overlapping region (424) may overlap with the first fan-out line (322), the second fan-out line (324), and the fourth fan-out line (328) when viewed in a plane.

[0181] According to the embodiment, the fan-out line (320) overlapping with the separation area (426) may not be covered by the first power line (VDD) and / or the second power line (VSS).

[0182] Experimentally, physical data of the fan-out line (320) may be provided differently depending on the range of the area overlapping with the separation area (426). For example, if a first line, which is one of the fan-out lines (320), overlaps with the separation area (426) by a first range, it may have a first resistance, and if the first line overlaps with the separation area (426) by a second range different from the first range, it may have a second resistance different from the first resistance. In this case, there is a possibility that distortion of the electrical signal passing through the fan-out line (320) may occur, and thus there may be a risk of image quality variation of the display device (100).

[0183] However, according to an embodiment of the present invention, the type of target wiring overlapping with the separation area (426) may differ depending on the location of the fan-out area (300) (e.g., first area (352), second area (354), and third area (356)). As a result, the difference in physical data (e.g., resistance) caused by the separation area (426) can be distributed across the plurality of fan-out lines (320). Consequently, distortion of the electrical signal passing through the fan-out line (320) can be prevented, and the image quality variation of the display device (100) can be improved.

[0185] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments of the present invention described above may be implemented separately or in combination.

[0186] Accordingly, the embodiments disclosed in this invention are intended to illustrate, not limit, the technical concept of the invention, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of this invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of this invention. Explanation of the symbols

[0187] LD: Light-emitting element BML: Barrier electrode layer D-IC: Driving Control Unit ACT: Active Layer 100: Display device GE: Gate electrode layer 110: Pixel section SDL: Source / drain electrode layer 120: Scan driver ELT: Alignment electrode layer 130: Data driver PCL: Pixel circuit 140: Compensation section DPL: Display element section 150: Control unit 422: First overlapping area PX: Pixel 424: Second overlapping area SPX: Subpixel 426: Separation area SL: Scan line VDD: 1st power line DL: Data line VSS: Second power line SENL: Sensing Line 320: Fan-out Line BSL: Base Layer 352: Region 1 DA: Display area 354: Second area NDA: Non-display area 356: Third area LP: Wiring Section 300: Fan-out Area

Claims

Claim 1 A display device comprising a display area and a non-display area, wherein a pixel disposed within the display area; a driving control unit disposed within the non-display area and controlling the driving of the pixel; and a wiring unit, at least a portion of which is disposed within the non-display area and electrically connects the pixel and the driving control unit. A display device comprising, wherein the non-display area includes a fan-out area formed on one side of the display area and located between the display area and the drive control unit, and the wiring unit includes a first power line, a second power line, and a fan-out line—the fan-out line being a line separate from the first power line and the second power line—each having at least a portion disposed within the fan-out area, and within the fan-out area, the first power line and the second power line are separated by a separation area in which at least a portion extends in a diagonal direction when viewed in a planar view, and one side of the display device adjacent to the drive control unit extends in a first direction, and the first direction and the diagonal direction are non-parallel to each other, and the first power line and the second power line have a plate shape to cover an area extending in the first direction and a second direction perpendicular to the first direction when viewed in a planar view. Claim 2 A display device according to claim 1, wherein the first power line includes a first adjacent line adjacent to the second power line, the second power line includes a second adjacent line adjacent to the second power line, and the first power line and the second power line do not overlap each other when viewed in a plane, and the first adjacent line and the second adjacent line are parallel to each other. Claim 3 A display device according to claim 1, further comprising: an interlayer insulating layer disposed on a substrate—the first power line and the second power line are disposed on the interlayer insulating layer—; and a protective layer that directly covers the upper surface of each of the first power line and the second power line, at least a portion of which is disposed within the spaced-apart area, and is directly adjacent to the portion of the interlayer insulating layer exposed by the first power line and the second power line. Claim 4 In claim 2, the first adjacent line and the second adjacent line are formed such that the drive control unit is offset from one side of the display device adjacent to it. Claim 5 In claim 2, the first adjacent line and the second adjacent line are a display device having a stepped shape. Claim 6 A display device according to claim 1, wherein the first power line and the second power line are disposed on the same layer, and the fan-out line is disposed on a different layer from the first power line and the second power line. Claim 7 A display device according to claim 6, further comprising a transistor electrically connected to the driving control unit and including a first transistor electrode and a second transistor electrode, wherein the first transistor electrode and the second transistor electrode are disposed on the same layer as the first power line and the second power line. Claim 8 A display device according to claim 7, further comprising a barrier electrode layer that overlaps with at least a portion of the transistor when viewed in a planar view, wherein the barrier electrode layer is disposed on the same layer as the fan-out line. Claim 9 A display device according to claim 1, wherein at least a portion of the fan-out line overlaps with the spacing area when viewed in a plane. Claim 10 A display device according to claim 2, wherein the fan-out line comprises a first fan-out line, a second fan-out line, and a third fan-out line, wherein the first fan-out line, the second fan-out line, and the third fan-out line are spaced apart in the first direction, and at least a portion of each of the first fan-out line, the second fan-out line, and the third fan-out line extends in the second direction, and wherein the first direction is a horizontal direction and the second direction is a vertical direction. Claim 11 A display device according to claim 10, wherein the fan-out area comprises a first area, a second area, and a third area, wherein the first area, the second area, and the third area are spaced apart from each other in the second direction when viewed in a plane, and the first area is positioned between the second area and the third area. Claim 12 In claim 10, the display device wherein the second direction is a direction from the drive control unit toward the display area. Claim 13 A display device according to claim 11, wherein the fan-out area includes a first overlapping area and a second overlapping area, the first power line overlaps with the fan-out line within the first overlapping area, and the second power line overlaps with the fan-out line within the second overlapping area. Claim 14 A display device according to claim 13, wherein the first fan-out line overlaps with the spacing area within the first area when viewed in a plane, and the second fan-out line and the third fan-out line do not overlap with the spacing area within the first area when viewed in a plane. Claim 15 A display device according to claim 14, wherein the second fan-out line overlaps with the spacing area within the second area when viewed in a plane, and the first fan-out line and the third fan-out line do not overlap with the spacing area within the second area when viewed in a plane. Claim 16 A display device according to claim 15, wherein the third fan-out line overlaps with the spacing area within the third area when viewed in a planar view, and the first fan-out line and the second fan-out line do not overlap with the spacing area within the third area when viewed in a planar view. Claim 17 A display device according to claim 13, wherein, when viewed in a plane within the first region, the second fan-out line overlaps with the second overlapping region and the third fan-out line overlaps with the first overlapping region; when viewed in a plane within the second region, the first fan-out line overlaps with the first overlapping region and the third fan-out line overlaps with the first overlapping region; and when viewed in a plane within the third region, the first fan-out line overlaps with the second overlapping region and the second fan-out line overlaps with the second overlapping region. Claim 18 A display device according to claim 1, wherein the driving control unit comprises a scan driving unit for driving the pixel, a data driving unit, and a compensation unit, and wherein the scan driving unit, the data driving unit, and the compensation unit are disposed on one side of the display area. Claim 19 A display device in which, in claim 1, the width of the fan-out area widens as it moves from the drive control unit toward the display area. Claim 20 A display device according to claim 1, wherein the fan-out line comprises at least one of a scan line, a data line, and a sensing line electrically connected to the pixel.

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