Image sensor

Abstract

An image sensor according to the concept of the present invention comprises: a first substrate having a first surface and a second surface facing each other, wherein the first substrate includes unit pixel regions and impurity regions disposed adjacent to the first surface, and a device isolation pattern provided on the first surface of the first substrate and defining the impurity regions; and a first wiring layer covering the first surface of the first substrate, wherein the first wiring layer includes a first insulating layer covering the first surface of the first substrate, wirings on the first insulating layer, and a first penetration structure penetrating the first insulating layer, wherein the first penetration structure comprises: a first pattern connected to any one of the impurity regions of the first substrate and in contact with at least a portion of the device isolation pattern; a second pattern provided on the first pattern and in contact with the wirings; and a third pattern provided between the first pattern and the second pattern, wherein the upper surface of the first pattern may be provided at a higher level than the upper surface of the device isolation pattern.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to a CMOS image sensor. Background Technology

[0002] Image sensors convert optical images into electrical signals. Recently, with the development of the computer and telecommunications industries, the demand for high-performance image sensors is increasing in various fields such as digital cameras, camcorders, PCS (Personal Communication System), gaming devices, security cameras, and medical micro cameras.

[0003] Image sensors include Charge Coupled Devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors offer a simple driving method and allow for the integration of signal processing circuits onto a single chip, enabling product miniaturization. CMOS image sensors also consume very little power, making them suitable for products with limited battery capacity. Furthermore, CMOS image sensors can utilize compatible CMOS process technologies, which helps reduce manufacturing costs. Consequently, the use of CMOS image sensors is rapidly increasing as technological advancements enable the realization of high resolutions. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide an image sensor having improved electrical characteristics.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] An image sensor according to the concept of the present invention comprises: a first substrate having a first surface and a second surface facing each other, wherein the first substrate includes unit pixel regions and impurity regions disposed adjacent to the first surface, and a device isolation pattern provided on the first surface of the first substrate and defining the impurity regions; and a first wiring layer covering the first surface of the first substrate, wherein the first wiring layer includes a first insulating layer covering the first surface of the first substrate, wirings on the first insulating layer, and a first penetration structure penetrating the first insulating layer, wherein the first penetration structure comprises: a first pattern connected to any one of the impurity regions of the first substrate and in contact with at least a portion of the device isolation pattern; a second pattern provided on the first pattern and in contact with the wirings; and a third pattern provided between the first pattern and the second pattern, wherein the upper surface of the first pattern may be provided at a higher level than the upper surface of the device isolation pattern.

[0007] An image sensor according to the concept of the present invention comprises: a first substrate having a first surface and a second surface facing each other, wherein the first substrate includes unit pixel regions and impurity regions disposed adjacent to the first surface, and a device isolation pattern provided on the first surface of the first substrate and defining the impurity regions; and a first wiring layer covering the first surface of the first substrate, wherein the first wiring layer includes a first insulating layer covering the first surface of the first substrate, wirings on the first insulating layer, and a first penetration structure penetrating the first insulating layer, wherein the first penetration structure includes: a first pattern connected to the impurity regions of the first substrate and vertically overlapping with at least a portion of the device isolation pattern; a second pattern in contact with the wirings; and a third pattern covering the upper surface of the first pattern, wherein the first pattern and the second pattern may be vertically spaced apart with the third pattern in between.

[0008] An image sensor according to the concept of the present invention comprises: a first substrate having a first surface and a second surface facing each other; the first substrate including a pixel array region, an optical black region, and a pad region, wherein the pixel array region includes unit pixel regions and impurity regions disposed adjacent to the first surface; a device isolation pattern provided on the first surface of the first substrate and defining the impurity regions; a pixel isolation pattern provided inside the first substrate defining the unit pixel regions; gate patterns provided on the first surface of the first substrate; an anti-reflection film provided on the second surface of the first substrate; color filters and microlenses provided on the anti-reflection film; and a grid pattern provided between the color filters. and a first wiring layer covering the first surface and the gate patterns of the first substrate, the first wiring layer includes a first insulating layer covering the first surface of the first substrate, wirings on the first insulating layer, and a first penetration structure and a second penetration structure penetrating the first insulating layer, wherein the first penetration structure includes: a first pattern connected to the impurity regions of the first substrate and in contact with at least a portion of the device isolation pattern; a second pattern provided on the first pattern and in contact with the wirings; and a third pattern provided between the first pattern and the second pattern, and the upper surface of the first pattern may be provided at a higher level than the upper surface of the device isolation pattern. Effects of the invention

[0009] An image sensor according to the present invention may include a through-structure comprising first to third patterns containing different materials. The through-structure may be spaced apart from the gate patterns and may be vertically overlapped with adjacent device isolation patterns and a substrate, respectively. Accordingly, the size of the gate patterns can be designed to be larger, thereby providing an image sensor with improved electrical characteristics. Brief explanation of the drawing

[0010] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention. FIG. 2 is a plan view of an image sensor according to embodiments. Figure 3 is a cross-section taken along the line I-I' of Figure 2. Figure 4 is a plan view showing an enlarged view of area A of Figure 2. Figure 5 is a cross-section taken along the line II-II' of Figure 4. Figure 6 is an enlarged view of area B of Figure 5. FIG. 7 is a drawing for explaining an image sensor according to embodiments and corresponds to area B of FIG. 5. FIG. 8 is a plan view of an image sensor according to embodiments, corresponding to area A of FIG. 2. Figure 9 is a cross-section taken along the line III-III' of Figure 8. Figure 10 is an enlarged view of area C of Figure 9. FIGS. 11 to 20 are drawings for explaining a method of manufacturing an image sensor according to embodiments, corresponding to a cross-section cut along line II-II' of FIG. 4. Specific details for implementing the invention

[0011] In this specification, the same reference numerals throughout the text may refer to the same components. An image sensor according to embodiments of the present invention is described.

[0012] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention.

[0013] Referring to FIG. 1, the unit pixel regions of the image sensor may include photoelectric conversion regions (PD1, PD2, PD3, PD4), transfer transistors (TX), source follower transistors (SX), reset transistors (RX), dual conversion transistors (DCX), and select transistors (AX). The transfer transistors (TX), source follower transistors (SX), reset transistors (RX), dual conversion transistors (DCX), and select transistors (AX) may each include a transfer gate (TG), a source follower gate (SF), a reset gate (RG), a dual conversion gate (DCG), and a select gate (SEL).

[0014] The photoelectric conversion regions (PD1, PD2, PD3, PD4) may be photodiodes containing n-type impurity regions and p-type impurity regions. The floating diffusion region (FD) may function as the drain of the transfer transistors (TX). The floating diffusion region (FD) may function as the source of the dual conversion transistor (DCX). The floating diffusion region (FD) may be electrically connected to the source follower gate (SF) of the source follower transistor (SX). The source follower transistor (SX) may be connected to the selection transistor (AX).

[0015] The operation of the image sensor is explained as follows with reference to FIG. 1. First, with light blocked, a power supply voltage (V) is applied to the drain of the reset transistor (RX) and the drain of the source follower transistor (SX). DD) is applied and the reset transistor (RX) and dual conversion transistor (DCX) are turned on to release the charges remaining in the floating diffusion region (FD). Then, the reset transistor (RX) is turned off, and external light is incident on the photoelectric conversion regions (PD1, PD2, PD3, PD4), generating electron-hole pairs in each of the photoelectric conversion regions (PD1, PD2, PD3, PD4). Holes move to the P-type impurity region of the photoelectric conversion regions (PD1, PD2, PD3, PD4), and electrons move to the n-type impurity region and accumulate. When the transfer transistors (TX) are turned on, charges such as these electrons and holes are transferred to the floating diffusion region (FD) and accumulated. The gate bias of the source follower transistor (SX) changes in proportion to the amount of accumulated charge, causing a change in the source potential of the source follower transistor (SX). At this time, when the selector transistor (AX) is turned ON, a signal due to charge is read through the column line.

[0016] The wiring line may be electrically connected to at least one of the transmission gate (TG), source follower gate (SF), dual conversion gate (DCG), reset gate (RG), and select gate (SEL). The wiring line is connected to the drain of the reset transistor (RX) or the drain of the source follower transistor (SX) with a power supply voltage (V DD It can be configured to apply ). The wiring line may include a column line connected to a select transistor (AX). The wiring line may be the wirings described below.

[0017] Although FIG. 1 illustrates a form in which photoelectric conversion regions (PD1, PD2, PD3, PD4) electrically share a single floating diffusion region (FD), embodiments of the present invention are not limited thereto. For example, a single unit pixel region may be provided with any one of the photoelectric conversion regions (PD1, PD2, PD3, PD4), a floating diffusion region (FD), and four transistors (TX RX, AX, SX), and the reset transistor (RX), source follower transistor (SX), or select transistor (AX) may be shared by neighboring unit pixel regions. Accordingly, the integration density of the image sensor may be improved.

[0018] FIG. 2 is a plan view of an image sensor according to embodiments. FIG. 3 is a cross-sectional view taken along the line I-I' of FIG. 2.

[0019] Referring to FIGS. 2 and 3, an image sensor according to embodiments may include a sensor chip (1000) and a circuit chip (2000). The sensor chip (1000) may include a photoelectric conversion layer (10), a first wiring layer (20), and a light transmission layer (30). The photoelectric conversion layer (10) may include a first substrate (100), a device isolation pattern (130), a pixel isolation pattern (150), and gate patterns (171, 173).

[0020] The first substrate (100) may include a pixel array region (AR), an optical black region (OB), and a pad region (PAD). The pixel array region (AR) may be positioned in the center portion of the first substrate (100) in a planar view. The pixel array region (AR) may include a plurality of unit pixel regions (PX). The unit pixel regions (PX) may output a photoelectric signal from incident light. The unit pixel regions (PX) may form columns and rows and may be arranged two-dimensionally. The columns may be parallel to a first direction (D1). The rows may be parallel to a second direction (D2). In this specification, the first direction (D1) may be parallel to a first surface (100a) of the first substrate (100), and the second direction (D2) may be parallel to a first surface (100a) of the first substrate (100) and intersect with the first direction (D1). For example, the second direction (D2) may be substantially perpendicular to the first direction (D1). The third direction (D3) may be perpendicular to the first direction (D1) and the second direction (D3), respectively. Below, the pixel array area (AR) of the image sensor will be described in more detail, and the optical black area (OB), pad area (PAD), and circuit chip (2000) will be described later.

[0021] FIG. 4 is a plan view showing an enlarged view of area A of FIG. 2. FIG. 5 is a cross-section taken along the line II-II' of FIG. 4.

[0022] Referring to FIGS. 4 and 5, an image sensor according to embodiments may include a first substrate (100), an element isolation pattern (130), a pixel isolation pattern (150), gate patterns (171, 173), and a first wiring layer (20). The first wiring layer (20) may include insulating layers (221, 223), wirings (222, 224), and first and second through-structures (210, 230).

[0023] The first substrate (100) may have a first surface (100a; or front) and a second surface (100b; or rear) facing each other. Light may be incident on the second surface (100b) of the first substrate (100). A first wiring layer (20) may be disposed on the first surface (100a) of the first substrate (100), and a light-transmitting layer (30) may be disposed on the second surface (100b) of the first substrate (100). The first substrate (100) may be a semiconductor first substrate or a Silicon on Insulator (SOI) first substrate. The semiconductor first substrate may include, for example, a silicon first substrate, a germanium first substrate, or a silicon-germanium first substrate. The first substrate (100) may include impurities of a first conductivity type. For example, the first type of impurity may include p-type impurities such as aluminum (Al), boron (B), indium (In) and / or gallium (Ga).

[0024] The first substrate (100) may include a plurality of unit pixel regions (PX) defined by a pixel separation pattern (150). The plurality of unit pixel regions (PX) may be arranged in a matrix form along a first direction (D1) and a second direction (D2) that intersect each other. The first substrate (100) may include photoelectric conversion regions (110). The photoelectric conversion regions (110) may be provided to each of the unit pixel regions (PX) within the first substrate (100). The photoelectric conversion regions (110) may perform the same function and role as the photoelectric conversion regions (PD1, PD2, PD3, PD4) of FIG. 1. The photoelectric conversion regions (110) may be regions doped with impurities of a second conductivity type within the first substrate (100). The impurities of the second conductivity type may have a conductivity type opposite to that of the impurities of the first conductivity type. The second type of impurity may include n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb). The photoelectric conversion regions (110) may be adjacent to the first surface (100a) of the first substrate (100). That is, the photoelectric conversion regions (110) may be positioned closer to the first surface (100a) than to the second surface (100b). For example, each photoelectric conversion region (110) may include a first region adjacent to the first surface (100a) and a second region adjacent to the second surface (100b). There may be a difference in impurity concentration between the first region and the second region of the photoelectric conversion region (110). Accordingly, the photoelectric conversion region (110) may have a potential gradient between the first surface (100a) and the second surface (100b) of the first substrate (100). As another example, the photoelectric conversion region (110) may not have a potential slope between the first surface (100a) and the second surface (100b) of the first substrate (100).

[0025] The first substrate (100) and the photoelectric conversion regions (110) can form a photodiode. That is, the photodiode can be formed by a pn junction of the first substrate (100) of the first conductivity type and the photoelectric conversion regions (110) of the second conductivity type. The photoelectric conversion regions (110) forming the photodiode can generate and accumulate photocharges in proportion to the intensity of incident light.

[0026] The pixel separation pattern (150) A pixel separation pattern (150) may be provided within the first substrate (100) and may define unit pixel regions (PX). For example, a pixel separation pattern (150) may be provided between the unit pixel regions (PX) of the first substrate (100). In a planar view, the pixel separation pattern (150) may have a grid structure. In a planar view, the pixel separation pattern (150) may completely surround each of the unit pixel regions (PX). The pixel separation pattern (150) may be provided within a first trench (TR1), and the first trench (TR1) may be recessed from the first surface (100a) of the first substrate (100). The pixel separation pattern (150) may extend from the first surface (100a) of the first substrate (100) toward the second surface (100b). For example, the width of the pixel isolation pattern (150) may gradually decrease from the first surface (100a) to the second surface (100b) of the first substrate (100). The pixel isolation pattern (150) may be a deep trench isolation film. The pixel isolation pattern (150) may penetrate the first substrate (100). The vertical height of the pixel isolation pattern (150) may be substantially the same as the vertical thickness of the first substrate (100).

[0027] The pixel separation pattern (150) may include a first separation pattern (151), a second separation pattern (153), and a capping pattern (155). The first separation pattern (151) may be provided along the sidewall of the first trench (TR1). The first separation pattern (151) may, for example, include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). For another example, the first separation pattern (151) may include a plurality of layers, and said layers may include different materials. The first separation pattern (151) may have a lower refractive index than the first substrate (100). Accordingly, crosstalk between unit pixel regions (PX) of the first substrate (100) may be prevented or reduced.

[0028] A second separation pattern (153) may be provided inside the first trench (TR1). The second separation pattern (153) may fill the interior of the first trench (TR1). The side walls of the second separation pattern (153) may be surrounded by the first separation pattern (151). The first separation pattern (151) may be interposed between the second separation pattern (153) and the first substrate (100). Accordingly, the second separation pattern (153) may be separated from the first substrate (100) by the first separation pattern (151). When the image sensor is operated, the second separation pattern (153) may be electrically separated from the first substrate (100) by the first separation pattern (151). The second separation pattern (153) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon containing impurities, polycrystalline silicon without impurities, amorphous silicon, and / or a metallic material. In one example, if the second separation pattern (153) is silicon containing impurities, the impurities may include n-type or p-type impurities. In another example, if the second separation pattern (153) is a metallic material, the metallic material may include tungsten.

[0029] A capping pattern (155) may be provided on the upper surface of a second separation pattern (153). The capping pattern (155) may be positioned adjacent to a first surface (100a) of a first substrate (100). The upper surface of the capping pattern (155) may be coplanar with the first surface (100a) of the first substrate (100). The lower surface of the capping pattern (155) may be substantially the same as the upper surface of the second separation pattern (153). The capping pattern (155) may include a non-conductive material. For example, the capping pattern (155) may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). Accordingly, the pixel separation pattern (150) can prevent photocharges generated by incident light incident on each of the unit pixel regions (PX) from being incident on adjacent unit pixel regions (PX) by random drift. That is, the pixel separation pattern (150) can prevent crosstalk between unit pixel regions (PX).

[0030] A device isolation pattern (130) may be provided within the first substrate (100). For example, the device isolation pattern (130) may be provided within a second trench (TR2), and the second trench (TR2) may be recessed from the first surface (100a) of the first substrate (100). The device isolation pattern (130) may be a shallow device isolation (STI) film. The device isolation pattern (130) may expose the first surface (100a) of the first substrate (100). The device isolation pattern (130) may define a location where impurity regions (120) provided on the upper surface of the first substrate (100) are disposed. The lower surface (130b) of the device isolation pattern (130) may be provided within the first substrate (100). The width of the device isolation pattern (130) may gradually decrease from the first surface (100a) to the second surface (100b) of the first substrate (100). The lower surface (130b) of the device isolation pattern (130) may be spaced apart from the photoelectric conversion regions (110). At least a portion of the device isolation pattern (130) is placed on the upper sidewall of the pixel isolation pattern (150) and may be connected to the upper sidewall of the pixel isolation pattern (150). The side and lower surface (130b) of the device isolation pattern (130) and the sidewall of the pixel isolation pattern (150) may have a stepped structure. The height of the device isolation pattern (130) in the third direction (D3) may be smaller than the height of the pixel isolation pattern (150) in the third direction (D3). The device isolation pattern (130) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0031] Gate patterns (171, 173) may be provided on a first surface (100a) of a first substrate (100). The gate patterns (171, 173) may include first gate patterns (171) having a buried structure and second gate patterns (173) having a planar structure. In a planar view, the gate patterns (171, 173) may be disposed on each unit pixel region (PX). For example, one first gate pattern (171) and at least one second gate pattern (173) may be disposed on each unit pixel region (PX). The gate patterns (171, 173) may not overlap with the pixel separation pattern (150) in a planar view. The gate patterns (171, 173) can function as gate electrodes for the transfer transistor (TX), source follower transistor (SX), reset transistor (RX), dual conversion transistor (DCX), and select transistor (AX) described above in FIG. 1. For example, the gate patterns (171, 173) may include a transfer gate (TG), a source follower gate (SF), a reset gate (RG), a dual conversion gate (DCG), and a select gate (SEL).

[0032] The first wiring layer (20) may include insulating layers (221, 223), through-structures (210, 230), wiring (222), and vias (224). The insulating layers (221, 223) may include a first insulating layer (221) and second insulating layers (223). The first insulating layer (221) may cover a first surface (100a) of the first substrate (100). The first insulating layer (221) may be provided between the wiring (222) and the first surface (100a) of the first substrate (100) to cover gate patterns (171, 173). The second insulating layers (223) may be laminated on the first insulating layer (221). The first and second insulating layers (212, 223) may include a non-conductive material. For example, the first and second insulating layers (212, 223) may include silicon-based insulating materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0033] Wiring (222)This can be provided on the first insulating layer (221). More specifically, the wiring (222) can be disposed within the second insulating layers (223) laminated on the first surface (100a) of the first substrate (100). The wiring (222) can be electrically connected to the gate patterns (171, 173) through vias (224). The electrical signal converted in the photoelectric conversion regions (110) can be signal processed in the first wiring layer (20). In embodiments of the present invention, the arrangement of the wiring (222) can be arranged independently of the arrangement of the photoelectric conversion regions (110). That is, the wiring (222) may cross the top of the photoelectric conversion regions (110). The lowest wiring (222) of the wiring (222) may come into direct contact with the upper surfaces (210a, 230a) of the through structures (210, 230). The wiring (222) and vias (224) may comprise a material different from that of the through structures (210, 230). The wiring (222) and vias (224) may comprise a metallic material, for example, copper (Cu). The wiring (222) and vias (224) may be electrically connected to the through structures (210, 230). Details regarding the through structures (210, 230) will be described later.

[0034] Light-transmitting layer (30) It may include an anti-reflective film (311), first and second rear insulating layers (313, 315), color filters (320), a grid pattern insulating layer (331), a grid pattern (333), and micro-lenses (340). The light-transmitting layer (30) may collect and filter light incident from the outside and provide the light to the photoelectric conversion layer (10).

[0035] Specifically, color filters (320) and micro lenses (340) may be provided on the second surface (100b) of the first substrate (100). The color filters (320) may each be placed on the unit pixel regions (PX). Micro lenses (340) may each be placed on the color filters (320). An anti-reflection film (131) and a first rear insulating layer (313) may be provided between the second surface (100b) of the first substrate (100) and the color filters (320). The anti-reflection film (131) may prevent light reflection so that light incident on the second surface (100b) of the first substrate (100) can smoothly reach the photoelectric conversion regions (110). A second rear insulating layer (315) may be provided between the color filters (320) and the micro lenses (340). The first rear insulating layer (313) and the second rear insulating layer (315) may include at least one of a fixed charge layer, an adhesive layer, and a protective layer. Each of the first rear insulating layer (313) and the second rear insulating layer (315) may include a plurality of layers as not illustrated, and may include a metal oxide (e.g., aluminum oxide or hafnium oxide) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0036] Color filters (320) may be arranged corresponding to each of a plurality of unit pixel regions. The color filters (320) may include primary color filters. The color filters (303) may include first to third color filters that transmit different colors. For example, the first to third color filters may each transmit green, red, and blue light. The first to third color filters may be arranged in a Bayer pattern. For another example, the first to third color filters may transmit other colors such as cyan, magenta, or yellow.

[0037] Micro-lenses (340) may each be placed on the lower surface of the color filters (320). Micro-lenses (340) may each overlap vertically with the photoelectric conversion regions (110). Micro-lenses (340) may be connected to each other, as shown in the illustration. Micro-lenses (340) may be transparent so as to transmit light. Micro-lenses (340) may have a convex shape so as to concentrate light incident on unit pixel regions (PX). Micro-lenses (340) may include an organic material. For example, micro-lenses (340) may include a photoresist material or a thermosetting resin.

[0038] FIG. 6 is an enlarged view of area B of FIG. 5. Hereinafter, the gate patterns (171, 173) and through structures (210, 230) will be described in more detail.

[0039] Referring to FIG. 6 together with FIG. 5, the first gate patterns (171) may include a first portion (171T) and a second portion (171U). The first portion (171T) of each of the first gate patterns (171) may be disposed on a first surface (100a) of the first substrate (100). The first portion (171T) may extend in a direction parallel to the first surface (100a) of the first substrate (100). The second portion (171U) of each of the first gate patterns (171) may protrude into the first substrate (100). The second portion (171U) may be connected to the first portion (171T). The first gate patterns (171) may include transmission gates (TG). The first gate patterns (171) may include a metallic material, a metal silicide material, polysilicon, and combinations thereof.

[0040] As shown in FIG. 5, each of the second gate patterns (173) may be disposed on the first surface (100a) of the first substrate (100). Each of the second gate patterns (173) may extend in a direction parallel to the first surface (100a) of the first substrate (100). Each of the second gate patterns (173) may be rectangular in a planar view. The second gate patterns (173) may include a source follower gate (SF), a reset gate (RG), a dual conversion gate (DCG), and a select gate (SEL).

[0041] A gate insulating pattern (175) may be interposed between each of the gate patterns (171, 173) and the first substrate (100). The gate insulating pattern (175) may include, for example, a silicon-based insulating material and / or a high dielectric material. A gate spacer (177) may cover the sidewalls of the first portion (171T) of each of the first gate patterns (171) and the sidewalls of each of the second gate patterns (173) on the first surface (100a) of the first substrate (100). The gate spacer (177) may include a semiconductor nitride, for example, silicon nitride, silicon carbide nitride, or silicon oxide nitride.

[0042] Through-hole structures (210, 230) may be provided on a first surface (100a) of a first substrate (100). Through-hole structures (210, 230) may be provided inside a first insulating layer (221). Through-hole structures (210, 230) may be disposed between the first substrate (100) and wirings (222). Through-hole structures (210, 230) may include first through-hole structures (210) and second through-hole structures (230). The first through-hole structures (210) may be connected to the first substrate (100), and the second through-hole structures (230) may be connected to gate patterns (171, 173).

[0043] First through-structures (210) may be provided between the first substrate (100) and the wiring (222). The first through-structures (210) may extend vertically to connect the impurity regions (120) of the first substrate (100) and the wiring (222). The first through-structures (210) may be provided inside the third trenches (TR3). The first through-structures (210) may fill the interior of the third trenches (TR3). The third trenches (TR3) may penetrate the first insulating layer (221) and penetrate at least a portion of the upper part of the first substrate (100). The first through-structures (210) may be spaced apart from adjacent gate patterns (171, 173). Each of the first through-hole structures (210) may include a first pattern (211) connected to the first substrate (100), a second pattern (213) provided on the first pattern (211), and a third pattern (215) connected to the wiring (222). The first pattern (211), the second pattern (213), and the third pattern (215) may be vertically aligned. The first pattern (211), the second pattern (213), and the third pattern (215) may include different materials. For the sake of simplicity of description, a single first through-hole structure (210) is described below.

[0044] A first pattern (211) may be provided on an impurity region (120) of a first substrate (100). The first pattern (211) may fill the lower part of a third trench (TR3). The first pattern (211) may be connected to the impurity region (120) of the first substrate (100). The first pattern (211) may include the same material as the first substrate (100). The first pattern (211) may include, for example, polycrystalline silicon containing impurities. The impurities may include impurities of a second conductivity type, and the impurities of the second conductivity type may include n-type impurities such as, for example, phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb). The interface (S1) between the first pattern (211) and the first substrate (100) may not be distinct.

[0045] According to embodiments, the first pattern (211) may be perpendicularly overlapped with the adjacent device isolation pattern (130) and the impurity region (120) of the adjacent first substrate (100), respectively. For example, the first pattern (211) may be placed at the boundary where the device isolation pattern (130) and the impurity region (120) of the first substrate (100) meet. The first pattern (211) may be in contact with at least a portion of the adjacent device isolation pattern (130). More specifically, the side (211c) and bottom (210b) of the first pattern (211) may be in contact with the device isolation pattern (130). For another example, the first pattern (211) may be connected to the impurity region (120) of the first substrate (100) and spaced apart from the device isolation pattern (130).

[0046] The lower surface (210b) of the first pattern (211) may be the lower surface (210b) of the first through-structure (210). The lower surface (210b) of the first pattern (211) may be provided at a level between the first surface (100a) of the first substrate (100) and the lower surface of the device isolation pattern (130). The upper surface (211a) of the first pattern (211) may be provided at a level between the upper surfaces (171a, 173a) of adjacent gate patterns (171, 173) and the first surface (100a) of the first substrate (100). The distance (H1) in the third direction (D3) from the first surface (100a) of the first substrate (100) to the upper surface (211a) of the first pattern (211) may be 100 Å or more and 1800 Å or less.

[0047] A second pattern (213) of the first penetrating structure (210) may be provided on the upper surface (211a) of the first pattern (211). The second pattern (213) may be provided between the first pattern (211) and the third pattern (215) of the first penetrating structure (210). The second pattern (213) may cover the upper surface (211a) of the first pattern (211). Accordingly, the first pattern (211) and the third pattern (215) of the first penetrating structure (210) may be spaced apart vertically. The thickness of the second pattern (213) in the third direction (D3) may be 50 Å or more and 200 Å or less. The second pattern (213) may include a metal silicide material, for example, cobalt silicide (CoSix) and / or nickel silicide (NiSix). The second pattern (213) can electrically connect the first pattern (211) and the third pattern (215). The electrical connection characteristics between the first pattern (211) and the third pattern (215) can be improved by the second pattern (213).

[0048] When a metal silicide material is interposed between the contact surface of a semiconductor material and a metal material, the transfer of charge between the semiconductor material and the metal material can be made smoother. However, as the metal silicide material is closer to the photoelectric conversion region (110), the photoelectric conversion characteristics of the photoelectric conversion region (110) may be degraded. According to the embodiments, the first through-structure (210) may include a second pattern (213) containing a metal silicide material between a first pattern (211) containing silicon and a third pattern (215) containing a metal material. The second pattern (213) can facilitate the transfer of charge between the first pattern (211) and the third pattern (215). The second pattern (213) may be provided at a higher level than the first surface (100a) of the first substrate (100) and may not be adjacent to the photoelectric conversion region (110). Accordingly, an image sensor with improved photoelectric conversion characteristics may be provided.

[0049] A third pattern (215) of the first through structure (210) may be provided between the second pattern (213) and the wiring (222). The third pattern (215) may fill the upper part of the third trench (TR3). The upper surface of the third pattern (215) may be in contact with the lower surface (222b) of the lowest wiring (222) among the wirings (222), and the lower surface of the third pattern (215) may be in contact with the upper surface of the second pattern (213). The upper surface of the third pattern (215) may be the upper surface (210a) of the first through structure (210). The upper surface of the third pattern (215) may be coplanar with the upper surface of the first insulating layer (221). The third pattern (215) may include a metallic material, for example, tungsten, copper, aluminum and / or an alloy thereof. The third pattern (215) may include a different metal material than the wiring (222). For example, the third pattern (215) may include tungsten, and the wiring (222) may include copper.

[0050] Second through-structures (230) may be provided between the gate patterns (171, 173) and the wiring (222). The second through-structures (230) may extend vertically to connect the gate patterns (171, 173) and the wiring (222). The second through-structures (230) may be provided inside the fourth trenches (TR4). The second through-structures (230) may fill the interior of the fourth trenches (TR4). The fourth trenches (TR4) may penetrate the first insulating layer (221) to expose the upper surface of each of the gate patterns (171, 173). The second through-structures (230) may be vertically overlapped with adjacent gate patterns (171, 173), respectively. Each of the second through-structures (230) may include a first pattern (233) connected to the gate patterns (171, 173) and a second pattern (235) provided on the first pattern (233). The first pattern (233) and the second pattern (235) may be vertically aligned. The first pattern (233) and the second pattern (235) may include different materials.

[0051] First patterns (233) of the second through-structures (230) may be provided on the upper surfaces of the gate patterns (171, 173), respectively. The first patterns (233) may be in contact with the upper surfaces of the corresponding gate patterns (171, 173), respectively. The thickness of each of the first patterns (233) in the third direction (D3) may be 50 Å or more and 200 Å or less. The first patterns (233) may comprise a metal silicide material, for example, cobalt silicide (CoSix) and / or nickel silicide (NiSix). The first patterns (232) may electrically connect the second patterns (235) and the gate patterns (171, 173), respectively.

[0052] Second patterns (235) of the second penetration structures (230) may each be provided on the first patterns (233). The second patterns (235) of the second penetration structures (230) may each fill the interior of the fourth trenches (TR4). The second patterns (235) may each be aligned vertically with the first patterns (233). The second patterns (235) may each connect the first patterns (233) and the lowest wiring (222) of the wiring (222). The second patterns (235) may include a different metal material than the first patterns (233) and the wiring (222). For example, the second patterns (235) may include tungsten.

[0053] Referring further to FIG. 6, a second through-hole structure (230) may be disposed between a pair of first through-hole structures (210). For example, one of the first through-hole structures (210) may be spaced horizontally apart from the first gate pattern (171) and may overlap vertically with the device isolation pattern (130) and the impurity region (120), respectively. The other of the first through-hole structures (210) may be spaced apart from the first gate pattern (171) and the adjacent device isolation pattern (130), respectively. The other of the first through-hole structures (210) may not overlap vertically with the device isolation pattern (130) and may be connected to the impurity region (120). The second patterns (213) of the first through-hole structures (210) and the first pattern (233) of the second through-hole structure (230) may be provided at different levels. For example, the first pattern (233) of the second penetrating structure (230) may be provided at a higher level than the second patterns (213) of the first penetrating structures (210).

[0054] Referring again to FIG. 4, a plurality of first penetrating structures (210) and second penetrating structures (230) may be provided within a single unit pixel area (PX). For example, a single first gate pattern (171) and at least one second gate pattern (173) may be disposed within the unit pixel area (PX). In a planar view, the first penetrating structures (210) may not overlap with the gate patterns (171, 173), and the second penetrating structures (230) may overlap with the gate patterns (171, 173). Depending on the planar arrangement of the first through-structures (210) and the second through-structures (230), the capacitance value between the transmission gates (TG1, TG2, TG3, TG4) and the source follower gate (SF) described in FIG. 1, or the capacitance value between the transmission gates (TG1, TG2, TG3, TG4) and the dual conversion gate (DCG) can be adjusted. According to embodiments, any one of the first through-structures (210) may be arranged to overlap with an adjacent device isolation pattern (130) and an impurity region (120) of the first substrate (100) exposed by the device isolation pattern (130), respectively. Accordingly, the space between any one of the first through-structures (210) and the nearest gate pattern may be widened, and it may be possible to design the area of ​​the gate patterns (171, 173) to be larger. If the area of ​​the gate patterns (171, 173) increases, the electrical characteristics of the image sensor can be improved.

[0055] FIG. 7 is a drawing for explaining an image sensor according to embodiments and corresponds to area B of FIG. 5. Hereinafter, redundant descriptions are omitted and differences are described in detail.

[0056] Referring to FIG. 7, an image sensor according to embodiments may include a first substrate (100), a device isolation pattern (130), a pixel isolation pattern (150), gate patterns (171, 173), and a first wiring layer (20). The first wiring layer (20) may include insulating layers (221, 223), wirings (222, 224), and first and second through-structures (210, 230).

[0057] The first substrate (100), device isolation pattern (130), pixel isolation pattern (150), gate patterns (171, 173), insulating layers (221, 223) and wirings (222, 224) may be substantially the same as described in FIGS. 1 to 6.

[0058] First through-structures (210) may be provided between the first substrate (100) and the wiring (222). The first through-structures (210) may extend vertically to connect the impurity regions (120) of the first substrate (100) and the wiring (222). Third trenches (TR3) may penetrate the first insulating layer (221) and penetrate at least a portion of the upper surface of the first substrate (100). The first through-structures (210) may be spaced apart from adjacent gate patterns (171, 173). Each of the first through-structures (210) may include a first pattern (211) connected to the first substrate (100), a second pattern (213) provided on the first pattern (211), and a third pattern (215) connected to the wiring (222).

[0059] A first pattern (211) may be provided on an impurity region (120) of a first substrate (100). The first pattern (211) may be connected to the impurity region (120) of the first substrate (100). An upper surface (211a) of the first pattern (211) may be provided at a higher level than the upper surface (171a) of the first gate pattern (171). For example, the upper surface (211a) of the first pattern (211) may be provided at a level between the upper surface (171a) of the first gate pattern (171) and the lower surfaces (222b) of the lowest wiring (222).

[0060] A second pattern (213) may be provided on the first pattern (211). The second pattern (213) may be substantially identical to the second pattern (213) of the first penetration structure (210) described in FIGS. 5 and 6. A third pattern (215) may be provided on the second pattern (213). The third pattern (215) may be substantially identical to the third pattern (215) described in FIGS. 5 and 6.

[0061] A second through-hole structure (230) may be provided between the first gate pattern (171) and the wiring (222). The second through-hole structure (230) may further include a third pattern (231). More specifically, the second through-hole structure (230) may include a third pattern (231) in contact with the first gate pattern (171), a second pattern (235) provided on the third pattern (231), and a first pattern (233) provided between the second pattern (235) and the third pattern (231). The first pattern (233) and the second pattern (235) may be substantially identical to the first pattern (233) and the second pattern (235) of the second through-hole structure (230) described in FIGS. 5 and 6.

[0062] The third pattern (231) may include the same material as the first substrate (100). More specifically, the third pattern (231) may include polycrystalline silicon containing impurities. The impurities may include impurities of the second conductivity type, and the impurities of the second conductivity type may include n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb), for example. The third pattern (231) may electrically connect the first gate pattern (171) and the first pattern (233).

[0063] The second pattern (213) of the first penetration structure (210) and the first pattern (233) of the second penetration structure (230) may be provided at the same level. More specifically, the distance at which the second pattern (213) of the first penetration structure (210) is vertically spaced from the lower surface (222b) of the lowest wiring (222) may be equal to the distance at which the first pattern (233) of the second penetration structure (230) is vertically spaced from the lower surface (222b) of the lowest wiring (222).

[0064] FIG. 8 is a plan view of an image sensor according to embodiments, corresponding to area A of FIG. 2. FIG. 9 is a cross-section cut along line III-III' of FIG. 8. FIG. 10 is an enlarged view of area C of FIG. 9.

[0065] Referring to FIGS. 8 and 9, an image sensor according to embodiments may include a first substrate (100), an element isolation pattern (130), a pixel isolation pattern (150), gate patterns (171, 173), and a first wiring layer (20). The first wiring layer (20) may include insulating layers (221, 223), wirings (222, 224), and first and second through-structures (210, 230). The first substrate (100), the element isolation pattern (130), the pixel isolation pattern (150), the insulating layers (221, 223), and the wirings (222, 224) may be substantially the same as those described in FIGS. 4 and 5. Hereinafter, details that overlap with previously described content will be omitted, and differences will be described in detail.

[0066] Referring to FIGS. 8 and FIGS. 9 together, gate patterns (171, 173) may be provided on a first surface (100a) of a first substrate (100). The gate patterns (171, 173) may include first gate patterns (171) having a buried structure and second gate patterns (173) having a planar structure. In a planar view, each unit pixel region (PX) may include a single first gate pattern (171) and a single second gate pattern (173). The first gate pattern (171) and the second gate pattern (173) may be spaced apart from each other. Four adjacent unit pixel regions (PX) may form a pixel region group. Each of the four adjacent unit pixel regions (PX) may have a structure symmetric to the adjacent unit pixel regions (PX) in a first direction (D1) or a second direction (D2). For example, the second gate patterns (173) and the first gate patterns (171) placed inside each of a pair of unit pixel regions (PX) aligned in the second direction (D2) may each be aligned in the second direction (D2). The gate insulation pattern (175) and the gate spacer (177) may be substantially the same as those described in FIGS. 4 and FIGS. 5. For the sake of simplicity of description, the following description is based on a single unit pixel region (PX).

[0067] Referring to FIG. 9 and FIG. 10 together, through-hole structures (210, 230) may be provided on a first surface (100a) of a first substrate (100). Through-hole structures (210, 230) may be provided inside a first insulating layer (221). Through-hole structures (210, 230) may be disposed between the first substrate (100) and wirings (222). Through-hole structures (210, 230) may include a pair of first through-hole structures (210) and a second through-hole structure (230). A pair of first through-hole structures (210) may be connected to the first substrate (100), and the second through-hole structures (230) may be connected to a second gate pattern (173).

[0068] A pair of first through-structures (210) may be provided between the first substrate (100) and the wiring (222). The first through-structures (210) may extend vertically to connect the impurity regions (120) of the first substrate (100) and the wiring (222). The first through-structures (210) may be provided inside the third trenches (TR3). The first through-structures (210) may be arranged horizontally spaced apart with the second gate pattern (173) in between. The first through-structures (210) may fill the interior of the third trenches (TR3). The first through-structures (210) may penetrate at least a portion of the upper part of the first substrate (100) and the upper part of the adjacent device isolation patterns (130). Each of the first through-structures (210) may include a first pattern (211) connected to the first substrate (100), a second pattern (213) provided on the first pattern (211), and a third pattern (215) connected to the wiring (222). The first pattern (211), the second pattern (213), and the third pattern (215) may be vertically aligned. The first pattern (211), the second pattern (213), and the third pattern (215) may include different materials. The first to third patterns (211, 213, 215) may be substantially the same as those described in FIG. 6.

[0069] A second through-hole structure (230) may be provided on gate patterns (171, 173), for example, on the second gate pattern (173). The second through-hole structure (230) may extend vertically to connect the second gate pattern (173) and the wiring (222). The second through-hole structure (230) may be provided inside the fourth trench (TR4). The second through-hole structure (230) may fill the interior of the fourth trench (TR4). The fourth trench (TR4) may penetrate the first insulating layer (221) to expose the upper surface of the second gate pattern (173). The second through-hole structure (230) may be vertically overlapped with each adjacent second gate pattern (173). The second through-structure (230) may include a first pattern (233) connected to the second gate pattern (173) and a second pattern (235) provided on the first pattern (233). The first pattern (233) and the second pattern (235) may be vertically aligned. The first pattern (233) and the second pattern (235) may include different materials. Although not illustrated, as another example, the second through-structure (230) may further include a third pattern (235) interposed between the first pattern (233) and the upper surface (173a) of the second gate pattern (173).

[0070] A second through-structure (230) may be disposed between a pair of first through-structures (210). The first through-structures (210) and the second through-structure (230) may be arranged in alignment in one direction. The upper surface of each of the first through-structures (210) and the upper surface of the second through-structure (230) may be provided at the same level. The second patterns (213) of the first through-structures (210) and the first pattern (233) of the second through-structure (230) may be provided at different levels. However, not limited thereto, the second patterns (213) of the first through-structures (210) and the first pattern (233) of the second through-structure (230) may be provided at the same level. According to the embodiments, a pair of first through-structures (210) may be further away from the outer region of the unit pixel area (PX) centered on the second through-structure (230). Accordingly, each of the pair of first through-structures (210) may overlap with the impurity region (120) of the adjacent first substrate (100) and the adjacent device isolation pattern (130). Accordingly, the second gate pattern (173) connected to the second through-structure (230) can be designed to be wider. More specifically, the width (W1) of the second gate pattern (173) in the second direction (D) may be larger. For example, the width (W1) of the second gate pattern (173) in the second direction (D2) for the width (W2) of the first surface (100a) of the first substrate (100) exposed by the device isolation pattern (130) in the second direction (D2) may be 0.5 or more and 0.7 or less.

[0071] Below, the optical black region (OB) and pad region (PAD) of the first substrate (100) of the image sensor will be described in more detail.

[0072] An optical black area (OB) may be placed between the pixel array area (AR) and the pad area (PAD) of the first substrate (100). The optical black area (OB) may surround the pixel array area (AR) in a planar view. A first contact plug (70), a first protective film (71), a light-blocking pattern (73), a first conductive pattern (75), a first capping pattern (77), and a first embedding pattern (79) may be provided on the optical black area (OB).

[0073] A first contact plug (70) may be provided on a second surface (100b) of the substrate (100) or inside the substrate (100). A first contact trench may be formed on the second surface (100b) of the first substrate (100), and the first contact plug (70) may be provided within the first contact trench. The first contact plug (70) may comprise a metallic material, for example, aluminum. The first contact plug (70) may be electrically connected to a pixel separation pattern (150), more specifically to a second separation pattern (153).

[0074] A first conductive pattern (75) may be provided on a second surface (100b) of a substrate (100). The first conductive pattern (75) may cover a first rear insulating layer (313) on the second surface (100b) of the first substrate (100), conformally covering the inner wall of a first through hole and a first contact trench. The first conductive pattern (75) may penetrate a portion of the photoelectric conversion layer (10), the first wiring layer (20), and the circuit chip (2000). More specifically, the first conductive pattern (750) may be electrically connected by contacting the wiring (222) and pixel separation patterns (150) within the first wiring layer (20). The first conductive pattern (750) may be electrically connected to the lower wiring (55) within the circuit chip (2000). The first conductive pattern (75) may include a metallic material, for example, tungsten.

[0075] A first embedded pattern (79) is provided on the first conductive pattern (75) to fill the remaining portion of the first through-hole. The first embedded pattern (79) can penetrate the photoelectric conversion layer (10) and the first wiring layer (20). A first capping pattern (77) may be provided on the first embedded pattern (79). A first capping pattern (77) may be provided on the first embedded pattern (53). The first capping pattern (77) may include an insulating material containing silicon, for example, silicon oxide, silicon nitride, silicon oxynitride and / or a combination thereof.

[0076] A light-blocking pattern (73) may be provided on the first contact plug (70), the first conductive pattern (75), and the first embedded pattern (79). The light-blocking pattern (73) may block light incident on the optical black area (OB). A first protective film (71) may be provided on the light-blocking pattern (73) to cover the light-blocking pattern (73).

[0077] A photoelectric conversion region (111) and a dummy region (112) may be provided in the optical black region (OB) of the first substrate (100). The photoelectric conversion region (111) may be doped with, for example, an impurity of a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, n-type. Unlike the photoelectric conversion region (110) described in FIGS. 4 and 5, the photoelectric conversion region (111) may not perform the operation of receiving light and generating an electrical signal. The dummy region (112) may be a region that is not doped with impurities. The signals generated in the photoelectric conversion region (111) and the dummy region (112) may be used as information to remove process noise later.

[0078] A pad area (PAD) is provided on the edge portion of the first substrate (100) and can surround a pixel array area (AR) in a planar view. In the pad area (PAD), a second conductive pattern (85), a second embedded pattern (89), a second capping pattern (87), a second cone pack plug (80), and a second protective film (81) may be provided on the first substrate (100).

[0079] A second contact plug (80) may be provided on a pad area (PAD). More specifically, the second contact plug (80) may be provided on a second surface (100b) of the first substrate (100) or inside the first substrate (100). A second contact trench may be formed on the second surface (100b) of the first substrate (100), and the second contact plug (80) may be provided within the second contact trench. The second contact plug (80) may serve as an electrical connection passage between the image sensor element and the outside. More specifically, the second contact plug (80) may output an electrical signal generated in unit pixel areas (PX) to the outside. Alternatively, an external electrical signal applied to the second contact plug (80) may be applied, for example, to a pixel separation pattern (150).

[0080] A second conductive pattern (85) may be provided on the second surface (100b) of the first substrate (100) or inside the first substrate (100). The second conductive pattern (85) may cover the first rear insulating layer (313) on the second surface (100b) of the first substrate (100) and conformally cover the inner wall of the second through hole and the second contact trench. The second conductive pattern (85) may penetrate the photoelectric conversion layer (10), the first wiring layer (20), and a portion of the circuit chip (2000). More specifically, the second conductive pattern (85) may be electrically connected to the lower wiring (55) within the second wiring layer (50) of the circuit chip (2000). The second conductive pattern (85) may include a metallic material, for example, tungsten.

[0081] A second embedded pattern (89) may be provided on the second conductive pattern (85) to fill the remaining portion of the second through-hole. The second embedded pattern (89) may penetrate the photoelectric conversion layer (10) and the first wiring layer (20). A second capping pattern (87) may be provided on the second embedded pattern (89). The second capping pattern (87) may include an insulating material containing silicon, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a combination thereof. A second protective film (81) may be provided on the second conductive pattern (85) and the second capping pattern (87). The second protective film (81) may cover the second conductive pattern (85) and the second capping pattern (87) but may not cover the first contact plug (80).

[0082] The image sensor may include a circuit chip (2000). The circuit chip (2000) may be laminated on the sensor chip (1000). The circuit chip (2000) may include a second substrate (40) and a second wiring layer (50). The second wiring layer (50) may be interposed between the first wiring layer (20) and the second substrate (40). Integrated circuits (TR) may be disposed on the upper surface of the second substrate (40) or within the second substrate (40). The integrated circuits (TR) may include logic circuits, memory circuits, or a combination thereof. The integrated circuits (TR) may include, for example, transistors. The second wiring layer (1800) may include lower insulating layers and lower wiring (55). The lower wiring (55) may be provided within the lower insulating layers. The lower wiring (55) may be electrically connected to the integrated circuits (TR).

[0084] FIGS. 11 to 20 are drawings for explaining a method of manufacturing an image sensor according to embodiments, corresponding to a cross-section cut along line II-II' of FIG. 4.

[0085] Referring to FIG. 11, a first substrate (100) having a first surface (100a) and a second surface (100b) facing each other may be prepared. The first substrate (100) may contain impurities of a first conductivity type (e.g., p-type). In one example, the first substrate (100) may be a first substrate having a first conductivity type epitaxial layer formed on a first conductivity type bulk silicon first substrate. In another example, the first substrate (100) may be a bulk first substrate including a well of the first conductivity type.

[0086] A second trench (TR2) can be formed on a first surface (100a) of a first substrate (100). Forming the second trench (TR2) may include forming a first mask pattern (MK) on the first surface (100a) of the first substrate (100) and performing an etching process on the first surface (100a) using the first mask pattern (MK).

[0087] Referring to FIG. 12, a second preliminary separation pattern (130p) can be formed on a first surface (100a) of a first substrate (100). The second preliminary separation pattern (130p) can be formed by performing a deposition process on the first surface (100a) of the first substrate (100). The second preliminary separation pattern (130p) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The second preliminary separation pattern (130p) can completely fill the interior of the second trench (TR2) and cover the first mask pattern (MK). The upper surface of the second preliminary separation pattern (130p) can be formed at a higher level than the first surface (100a) of the first substrate (100). A mask (not shown) can be formed on the second preliminary separation pattern (130p), and the second preliminary separation pattern (130p) and the first substrate (100) can be anisotropically etched to form a first trench (TR1). The bottom surface of the first trench (TR1) can be located at a higher level than the second surface (100b) of the first substrate (100).

[0088] After the formation of the first trench (TR1), a first preliminary separation pattern (151p) that conformally covers the inner wall of the first trench (TR1) may be formed. The first preliminary separation pattern (151p) may cover the inner wall of the first trench (TR1) and the upper surface of the second preliminary separation pattern (130p). The first preliminary separation pattern (151p) may be formed by depositing an insulating material on the first substrate (100) on which the first trench (TR1) is formed. The first preliminary separation pattern (151p) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0089] A second preliminary separation pattern (153p) can be formed on the first preliminary separation pattern (151p). The second preliminary separation pattern (153p) can be formed by performing a deposition process on the first substrate (100) on which the first preliminary separation pattern (151p) is formed. The second preliminary separation pattern (153p) can cover the first preliminary separation pattern (151p) on the inner wall of the first trench (TR1) and can cover the upper surface of the second preliminary separation pattern (130p). The second preliminary separation pattern (153p) may include, for example, polysilicon.

[0090] Referring to FIG. 13, an etching process can be performed on the second preliminary separation pattern (153p). In the etching process, the upper portion of the second preliminary separation pattern (153p) can be removed to form the second separation pattern (153). Accordingly, a portion of the first preliminary separation pattern (151p) may be exposed to the outside. The etching process can be performed until the second separation pattern (153) is positioned at a level lower than the lower portion of the second preliminary separation pattern (103p).

[0091] According to one embodiment, after the etching process is performed, a doping process may be performed on the second separation pattern (153). The doping process may be, for example, a beam line ion implantation process or a plasma doping process (PLAD). In the case of a plasma doping process, a source material may be supplied into a process chamber in a gaseous state. After plasma ionizing the source material, a high-voltage bias may be applied to an electrostatic chuck (not shown) on which the first substrate (100) is loaded, so that the ionized source material may be injected into the second separation pattern (153). Plasma doping can achieve uniform doping even at relatively very deep locations and can improve the doping process speed. In the case of a beam line ion implantation process, because the width of the first trench (TR1) is relatively deep and narrow, it may be difficult to dope uniformly along the vertical depth on the second separation pattern (153). Accordingly, when the doping process is performed by a beam line ion implantation process, the second separation pattern (153) may have an impurity concentration that varies with vertical depth. In an image sensor element, if a negative voltage is applied to the second separation pattern (153), the dark current characteristics of the image sensor may be improved.

[0092] A preliminary capping film (155p) may be formed on the first preliminary separation pattern (151p) and the second separation pattern (153). Forming the preliminary capping film (155p) may include performing a deposition process on the first surface (100a) of the first substrate (100). The preliminary capping film (155p) may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0093] Referring to FIG. 14, a first separation pattern (151), a capping pattern (155), and a device separation pattern (130) can be formed. Forming the capping pattern (155) and the device separation pattern (103) may include performing a planarization process on the first surface (100a) of the first substrate (100). In the planarization process, the upper portion of the first preliminary separation pattern (151p), the upper portion of the preliminary device separation pattern (130p), and the upper portion of the preliminary capping film (155p) may be removed. According to one example, the first mask pattern (MK) may be removed after the planarization process, thereby preventing damage to the first surface (100a) of the first substrate (100). Accordingly, the first surface (100a) of the first substrate (100), the upper surface (130a) of the device separation pattern (130), the upper surface of the capping pattern (155), and the upper surface of the first pixel separation pattern (151) may form a co-plane.

[0094] Referring to FIG. 15, photoelectric conversion regions (110) can be formed by doping impurities within unit pixel regions (PX). The photoelectric conversion regions (110) may have a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type). The vertical thickness of the first substrate (100) can be reduced by performing a thinning process that removes a portion of the first substrate (100). The thinning process may include grinding or polishing the second surface (100b) of the first substrate (100) and performing anisotropic or isotropic etching. To thin the first substrate (100), the top and bottom of the first substrate (100) may be inverted. A portion of the first substrate (100) may be removed by a grinding or polishing process, and subsequently, an anisotropic or isotropic etching process may be performed to remove remaining surface defects of the first substrate (100).

[0095] As a thin film process is performed on the second surface (100b) of the first substrate (100), the lower surfaces of the first separation pattern (151) and the second separation pattern (153) may be exposed. The lower surfaces of the first separation pattern (151) and the second separation pattern (153) may co-plane with the second surface (100b) of the first substrate (100). Subsequently, transistors may be formed on the first surface (100a) of the first substrate (100). Forming the transistors may include forming gate patterns (171, 173) and forming impurity regions (120) by doping impurities on the first surface (100a) of the first substrate (100). The impurity regions (120) may include n-type or p-type impurities.

[0096] Referring further to FIG. 15, a first insulating layer (221) can be formed on a first surface (100a) of a first substrate (100). The first insulating layer (221) can be formed to cover gate electrodes (171, 173), device isolation pattern (130), and the first surface (100a) of the first substrate (100) formed on the first surface (100a) of the first substrate (100). The first insulating layer (221) can be formed by performing a process of depositing an insulating material on the first surface (100a) of the first substrate (100). The first insulating layer (221) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0097] A second mask (MK2) can be formed to form third trenches (TR3) and fourth trenches (TR4) by performing a photolithography process on the upper surface of the first insulating layer (221). The second mask (MK2) can define the locations where the third trenches (TR3) and fourth trenches (TR4) are formed. A first etching process can be performed on the first insulating layer (221) using the second mask (MK2) as an etching mask. During the first etching process, the second mask (MK2) may be damaged, and the thickness of the second mask (MK2) may be reduced. The first etching process may be, for example, a dry etching process or an anisotropic etching process. A portion of the first insulating layer (221) may be removed to form the third trenches (TR3) and fourth trenches (TR4). The third trenches (TR3) may expose the impurity regions (120) of the first substrate (100) and / or the upper surface (130a) of the device isolation pattern (130). More specifically, the third trenches (TR3) may be formed on the boundary region where the impurity region (120) of the first substrate (100) and the device isolation pattern (130) meet, or may be formed on the impurity region (120) of the first substrate (100). The fourth trenches (TR4) may be formed on the first gate pattern (171) and the second gate pattern (173). The fourth trenches (TR4) may expose the upper surface (171a) of the first gate pattern (171) and the upper surface (173a) of the second gate pattern (173).

[0098] Referring to FIG. 16, a second etching process can be performed on the first substrate (100) and the device isolation pattern (130) exposed by the third trenches (TR3) and the fourth trenches (TR4). The second etching process can be performed using the remaining second mask (MK2) and the first insulating layer (221) as etching masks. In the second etching process, a portion of the upper surface of the first substrate (100) and / or a portion of the upper surface of the device isolation pattern (130) may be removed. At this time, a plurality of source materials used as etching gases may be mixed to control the etching of the first substrate (100) and the device isolation pattern (130) simultaneously without etching selectivity. By the second etching process, the depth of the third trenches (TR3) and the fourth trenches (TR4) may be increased. The bottom surface of each of the third trenches (TR3) and the fourth trenches (TR4) can be placed at a lower level than the first surface (100a) of the first substrate (100).

[0099] Referring to FIG. 17, first patterns (211) of a first through-structure can be formed to fill a portion of the interior of the third trenches (TR3) and the fourth trenches (TR4). For example, forming the first patterns (211) may include performing a deposition process to deposit a polycrystalline silicon film on the first insulating layer (221) and performing an etching process to remove a portion of the deposited polycrystalline silicon film.

[0100] When a polycrystalline silicon film is deposited on the first insulating layer (221), the polycrystalline silicon film may cover the upper surface of the first insulating layer (221) and fill the interiors of the third trenches (TR3) and the fourth trenches (TR4). The polycrystalline silicon film may be connected to the impurity regions (120) of the first substrate (100) exposed by the third trenches (TR3), and the boundary may not be distinct. The polycrystalline silicon film may be in contact with at least a portion of the device isolation pattern (130) exposed by the third trenches (TR3).

[0101] When performing an etching process on a polycrystalline silicon film, the upper portion of the polycrystalline silicon film can be removed to form first patterns (211). The etching process can be performed until the upper surfaces (211a) of the first patterns (211) are positioned at a lower level than the upper surface (171a) of the first gate pattern (171) and the upper surface of the second gate pattern (173). Accordingly, the polycrystalline silicon film filling the interior of the fourth trenches (TR4) is completely removed, so that the upper surface (171a) of the first gate pattern (171) and the upper surface (173a) of the second gate pattern (173) can be exposed. However, unlike what is illustrated, the etching process may be performed until the upper surfaces (211a) of the first patterns (211) are positioned at a higher level than the upper surface (171a) of the first gate pattern (171) and the upper surface of the second gate pattern (173). In this case, as shown in FIG. 7, the second through-structure (230) may further include a third pattern (231).

[0102] As another example, forming the first patterns (211) may include performing a selective epitaxial growth process (SEG; hereinafter referred to as the epi process) on a substrate (100). When performing the epi process, the first patterns (211) can be formed by growing them using the substrate (100) as a seed.

[0103] After forming the first patterns (211), a heat treatment process and an impurity implantation process may be performed. Through the heat treatment process, the first patterns (211) may be integrally connected to the substrate (100). The boundary between the first patterns (211) and the substrate (100) may or may not be distinguished. The conductivity type of the impurity implanted in the impurity implantation process may be the same as the conductivity type of the impurity in the impurity region (120) to which each of the first patterns (211) is connected.

[0104] Referring to FIG. 18, second patterns (213) of first through-structures and first patterns (233) of second through-structures can be formed inside the third trenches (TR3) and the fourth trenches (TR4). Forming the second patterns (213) of the first through-structures and the first patterns (233) of the second through-structures may include depositing a metal silicide material to form a metal silicide film and performing an etching process on the metal silicide film.

[0105] A metal silicide film can be formed by depositing a metal silicide material on the upper surface of the first insulating layer (221) and inside the third trenches (TR3) and the fourth trenches (TR4). The metal silicide material may include, for example, cobalt silicide (CoSix), nickel silicide (NiSix), titanium silicide (TiSix), and / or alloys thereof. The metal silicide film may cover the upper surface of the first insulating layer (221), the inner walls of the third trenches (TR3), the upper surfaces of the first patterns (213), the inner walls of the fourth trenches (TR4), the upper surface (171a) of the first gate pattern (171), and the upper surface of the second gate pattern (173). An etching process may be performed on the metal silicide film to remove a portion of the metal silicide film. The above etching process can be performed until the thickness of each of the second patterns (213) of the first through-structures and the first patterns (233) of the second through-structures is 50 Å or more and 200 Å or less. Accordingly, the second patterns (213) of the first through-structures and the first patterns (233) of the second through-structures can be formed.

[0106] Referring to FIG. 19, third patterns (214) of first through-structures and second patterns (235) of second through-structures can be formed to fill the interiors of third trenches (TR3) and fourth trenches (TR4). A polishing process may be performed on the upper surface of the first insulating layer (221). By the polishing process, the upper surface of the third patterns (214) and the upper surface of the second patterns (235) may form a co-plane with the upper surface (221a) of the first insulating layer (221). The second patterns (235) and the third patterns (214) may include a conductive material, for example, tungsten. Accordingly, a first penetrating structure (210) including first to third patterns (211, 213, 215) and a second penetrating structure (230) including first and second patterns (233, 235) may be formed.

[0107] Referring to FIG. 20, second insulating layers (223) can be sequentially formed on the upper surface of a first insulating layer (221), a first through-structure (210), and a second through-structure (230). Wiring (222) and vias (224) can be formed within the second insulating layers (223). The wiring (222) can be connected to the first through-structure (210) and the second through-structure (230), respectively.

[0108] Referring again to FIG. 5, a reflection-preventing film (311) and a first rear insulating layer (313) can be formed on the second surface (100b) of the first substrate (100). A grid pattern insulating layer (331) and a grid pattern (333) can be formed on the first rear insulating layer (313). The grid pattern insulating layer (331) and the grid pattern (333) can be formed as a grid structure in a planar view.

[0109] Color filters (320) can be formed on the first rear insulating layer (313). The color filters (320) can each be formed on unit pixel regions (PX). Micro lenses (340) can each be formed on the color filters (320). Accordingly, an image sensor according to embodiments of the present invention can be manufactured.

[0111] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A first substrate having a first surface and a second surface facing each other, wherein the first substrate includes unit pixel regions and impurity regions disposed adjacent to the first surface, and a device isolation pattern provided on the first surface of the first substrate and defining the impurity regions; a first wiring layer covering the first surface of the first substrate, wherein the first wiring layer includes a first insulating layer covering the first surface of the first substrate, wirings on the first insulating layer, and a first penetration structure penetrating the first insulating layer; a first gate pattern provided on the first surface of the first substrate and adjacent to the first penetration structure; and a second penetration structure penetrating the first insulating layer, wherein the first penetration structure includes: a first pattern penetrating a portion of the first substrate; a second pattern provided on the first pattern and in contact with the wirings; and a third pattern provided between the first pattern and the second pattern, and the second penetration structure includes: a fourth pattern in contact with the upper surface of the first gate pattern; An image sensor comprising a fifth pattern provided on the fourth pattern and in contact with the wirings, wherein the first pattern is perpendicularly superimposed with any one of the impurity regions and the device isolation pattern, the upper surface of the first pattern is provided at a higher level than the upper surface of the device isolation pattern, the third pattern and the fourth pattern comprise the same material, and the fourth pattern is located at a higher level than the third pattern. Claim 2 In claim 1, the third pattern and the fourth pattern are image sensors comprising a metal silicide material. Claim 3 delete Claim 4 In claim 1, the upper surface of the first pattern of the first through structure is provided at a level between the first surface of the first substrate and the upper surface of the first gate pattern. Claim 5 delete Claim 6 In claim 1, the lower surface of the first pattern of the first through-structure is an image sensor provided at a level between the upper surface of the element isolation pattern and the lower surface of the element isolation pattern. Claim 7 An image sensor according to claim 1, wherein the vertical distance from the upper surface of the element isolation pattern to the upper surface of the first pattern is 100 Å or more and 1800 Å or less. Claim 8 delete Claim 9 delete Claim 10 In claim 1, the second pattern of the first penetrating structure and the wiring comprise different materials in an image sensor.

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