Semiconductor logic circuit including non-volatile memory cells

Abstract

A phase change memory (PCM) device comprising a bottom electrode, a bottom heater above the bottom electrode, a bottom buffer layer above the bottom heater, a PCM region above the bottom buffer layer, an upper buffer layer above the PCM region, an upper heater above the upper buffer layer, and a top electrode above the upper heater.

Description

Technology Field

[0001] The present invention generally relates to semiconductor logic circuits. More specifically, the invention relates to exclusive OR (XOR) and exclusive NOR (XNOR) circuits comprising a single non-volatile memory cell. Background Technology

[0002] Phase Change Memory (PCM) devices are non-volatile memory devices capable of maintaining the state of memory elements for days to decades without consuming power. Examples of volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM); where DRAM requires the memory elements to be continuously refreshed, SRAM requires a continuous supply of energy to maintain the state of the memory elements.

[0003] In the case of phase change memory, information is stored in materials that can be manipulated into different phases. Each of these phases exhibits different electrical properties and can be used to store information. The amorphous phase and the crystalline phase are the two phases (0 and 1) typically used for bit storage because there is a detectable difference in electrical resistance. Specifically, the amorphous phase has higher resistance than the crystalline phase.

[0004] Chalcogenides are a group of materials commonly used as phase change materials. This group of materials contains chalcogens (Group 16 of the periodic table / VIA) and other elements. Selenium (Se) and tellurium (Te) are the two most common semiconductors in this group used to create chalcogenides when making phase change memory cells. Examples of these include Ge2Sb2Te5 (GST-225), SbTe, and In2Se3.

[0005] Phase-change memory cell design also seeks to minimize the area of ​​each cell to maximize the density of memory cell arrays, thereby reducing the overall die space of the associated circuits. Reducing the number of circuit components required for a logic device can also reduce the overall logic circuit die space. means of solving the problem

[0006] The following is a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or important components or to explain the scope of specific embodiments or claims. Its sole purpose is to present concepts in a simplified form as an introduction to the more detailed description to be presented later. In one or more embodiments described herein, devices, systems, computer implementation methods, apparatuses and / or computer program products enable computer logic circuits having fewer components and reduced die space.

[0007] Aspects of the present invention include a semiconductor device comprising a bottom electrode, a bottom heater above the bottom electrode, a bottom buffer layer above the bottom heater, a PCM region above the bottom buffer layer, an upper buffer layer above the PCM region, an upper heater above the upper buffer layer, and a top electrode above the upper heater.

[0008] Aspects of the present invention disclose methods, systems, and computer logic circuits related to a semiconductor logic circuit comprising a nonvolatile memory cell arranged in series between a first node and a second node—the first node is configured to receive a first write pulse, the second node is configured to receive a second write pulse, and the circuit is configured to receive a read pulse across the first node and the second node. The method comprises the steps of: simultaneously applying the first write pulse and the second write pulse to the nonvolatile memory cell prior to a logical write operation; simultaneously writing a first logic state of the first node to the nonvolatile memory and writing a second logic state of the second node to the nonvolatile memory; applying a read pulse across the first node and the second node; and interpreting the logic state of the circuit according to a response associated with the read pulse. Brief explanation of the drawing

[0009] The above and other objects, features, and advantages of the present invention will become more apparent through a more detailed description of some embodiments of the present invention in the attached drawings, wherein the same reference generally refers to the same components in the embodiments of the present invention.

[0010] FIG. 1 provides a cross-sectional view of a semiconductor device during manufacturing according to an embodiment of the present invention.

[0011] FIG. 2 provides a cross-sectional view of a semiconductor device during manufacturing according to an embodiment of the present invention.

[0012] FIG. 3 provides a cross-sectional view of a semiconductor device during manufacturing according to an embodiment of the present invention.

[0013] FIG. 4 provides a cross-sectional view of a semiconductor device during manufacturing according to an embodiment of the present invention.

[0014] FIG. 5 provides a graphic depiction of the input voltage and device state according to an embodiment of the present invention.

[0015] FIG. 6 provides a schematic diagram of a logic circuit component according to an embodiment of the present invention.

[0016] FIG. 7 provides a schematic diagram of a logic circuit control record and read signal according to an embodiment of the present invention.

[0017] FIG. 8 provides a device logic state change for a device receiving signals illustrated in FIG. 7, according to an embodiment of the present invention.

[0018] FIG. 9 provides a flowchart showing the sequence of operations according to an embodiment of the present invention. Specific details for implementing the invention

[0019] Various embodiments of the present invention are described herein with reference to the relevant drawings. Other embodiments may be devised without departing from the scope of the invention. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) between components are presented in the following description and drawings. Such connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this regard. Accordingly, the combination of entities may imply a direct or indirect combination, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, the reference in this description to forming layer “A” on layer “B” includes a situation in which one or more intermediate layers (e.g., layer “C”) are located between layer “A” and layer “B,” provided that the relevant characteristics and functions of layer “A” and layer “B” are not substantially altered by the intermediate layer(s).

[0020] The following definitions and abbreviations are intended for use in interpreting the claims and the specification. As used herein, the terms “comprising,” “comprising,” “to be included,” “included,” “having,” “having,” “containing,” or any other variations thereof are used with the intent to encompass non-exclusive inclusion. For example, a composition, mixture, process, method, product, or device comprising a list of components is not necessarily limited to such components and may include other components not expressly listed or inherent in such composition, mixture, process, method, product, or device.

[0021] Additionally, the term “exemplary” is used herein to mean “provided as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not be interpreted as being more desirable or advantageous than any other embodiment or design. The terms “at least one” and “one or more” are understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term “a plurality” is understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term “connection” may include indirect “connections” and direct “connections.”

[0022] References to “one embodiment,” “an embodiment,” “an exemplary embodiment,” etc., in the specification indicate that the described embodiment may include specific features, structures, or properties, but not all embodiments may include or exclude said specific features, structures, or properties. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when describing specific features, structures, or properties in relation to an embodiment, it should be noted that it is within the knowledge of a person skilled in the art to have such features, structures, or properties in relation to other embodiments, whether or not explicitly described.

[0023] For the purposes of the following description, the terms “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives relate to the structures and methods described when indicating directions in the drawings. The terms “lying on,” “on,” “on top,” “located on,” or “located on” mean that a first component, such as a first structure, exists on a second component, such as a second structure, and that intermediate components, such as an interface structure, may exist between the first component and the second component. The term “direct contact” means that the first component, such as a first structure, and the second component, such as a second structure, are connected at the boundary surface of the two components without any intermediate conductive, insulating, or semiconductor layer. It should be noted that the term “selective to,” such as “first component selective to second component,” implies that the first component may be etched and the second component may act as an etching stop.

[0024] For the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various operations and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will be mentioned only briefly herein or will be omitted entirely without providing well-known process details.

[0025] However, as background art, a more general description of a semiconductor device manufacturing process that may be used to implement one or more embodiments of the present invention will now be provided. While specific manufacturing operations used to implement one or more embodiments of the present invention may be known individually, the described combination of operations and / or resulting structures of the present invention is unique. Accordingly, the unique combination of operations described in connection with the manufacture of a semiconductor device according to the present invention utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0026] PCM materials utilize the large resistance difference between the amorphous and crystalline states. The amorphous phase has high electrical resistivity, while the crystalline phase has low resistivity. Often, the difference in resistivity is on the order of three to four orders of magnitude. Consequently, the variation in read current is very large, providing opportunities for multiple analog levels required for multi-level cell technology operations.

[0027] By applying a current sufficient to raise the temperature of the PCM material above the critical temperature required for crystallizing the amorphous phase, the PCM material can be set from the high-resistivity amorphous phase to the low-resistivity crystalline phase. Then, by applying a sufficient current to raise the temperature of the PCM material above its melting temperature and melting the crystals, the PCM material can be reset. The molten material is then quenched by rapidly removing the current. When the PCM material is quenched, the material returns to the amorphous glass phase.

[0028] Efforts to reduce the size of computer processors focus on shrinking individual circuit components and reducing the number of required circuit components. The disclosed embodiments enable the reduction of die space for Exclusive OR (XOR) and Negative Exclusive OR (XNOR) circuits by reducing the number of required circuit components. The disclosed circuits include a single non-volatile phase-change memory cell for each of the XOR and XNOR variants.

[0029] The embodiments may include a design for an integrated circuit chip that can be created in a graphical computer programming language and stored on a computer storage medium (disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not manufacture the chip or the photolithography mask used for manufacturing the chip, the designer may transmit the resulting design directly or indirectly to such entities by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photolithography mask, which generally contains multiple copies of the corresponding chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0030] Methods such as those described herein may be used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of unprocessed wafers (i.e., as a single wafer containing multiple unpackaged chips), as bare dies, or in packaged forms. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnects or embedded interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product, such as a motherboard, or (b) a final product. The final product may be any product containing the integrated circuit chip, ranging from toys to displays, keyboards, or other input devices, and high-end computer products with central processors.

[0031] FIG. 1 illustrates a semiconductor device (100) during manufacturing according to one embodiment of the present invention. As illustrated in the drawing, the device (100) includes a bottom electrode (130) disposed on a dielectric layer such as a SiO2 layer (120), which is ultimately disposed on a substrate (110). Each layer may be formed by sputtering or chemical vapor deposition (CVD) with a metal, for example, forming the bottom electrode (130), typically tungsten or titanium nitride.

[0032] The semiconductor substrate (110) may include any semiconductor material, for example, silicon. The substrate may include circuits such as logic circuits and memory circuits that can be connected to the device described by the present invention. The term “semiconductor material” is used throughout this application to denote a material having semiconductor properties. In addition to silicon, semiconductor materials include modified Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V semiconductor materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CaSe (cadmium selenide), CaS (cadmium sulfide), CaTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. “III-V semiconductor materials” means that the semiconductor material comprises at least one element from Group IIIA (i.e., Group 13) of the periodic table and at least one element from Group VA (i.e., Group 15) of the periodic table.

[0033] FIG. 1 further illustrates a device (100) after the formation of a bottom heater layer (140), and exemplary bottom heater (140) materials include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), and electrically similar materials. Typically, the choice of bottom heater (140) material is a material that does not react or mix with the top buffer layer (150) at an elevated operating temperature as described below.

[0034] FIG. 1 further illustrates a device after deposition of a bottom buffer layer (150), a PCM region layer (160), a top buffer layer (170), and a top heater layer (180). Exemplary top and bottom buffer layer materials include carbon (C), TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. The PCM region (160) material includes germanium telluride (GeTe), antimony telluride (Sb2Te3), gallium antimonide (GaSb), aluminum antimonide (AlSb), germanium antimony telluride (Ge2Sb2Te5), or GST. Other compositions of Ge(x)Sb(y)Te(z) may be used, where x, y, and z are integers defining the chemical composition. For example, for Ge2Sb2Te5, x=2, y=2, and z=5. An exemplary top heater (180) material includes the material described for the bottom heater (140). CMP can be performed after the deposition of each layer and before the deposition of the next layer.

[0035] In one embodiment, the PCM region (160) has a thickness of about 100 nm. In one embodiment, the PCM region has a thickness of about 20 nm. In one embodiment, the PCM region (160) has a thickness of about 20 nm to 100 nm. The PCM device switching speed is related to the PCM region thickness. For a given fixed energy application rate in the PCM region, the thicker the layer, the longer the heating time required to change the phase and switch the logic state. A thinner PCM region thickness requires less total energy and a shorter time to change the phase and logic state.

[0036] FIG. 2 illustrates a device after forming PCM pillars from layers (140, 150, 160, 170, and 180) using reactive ion etching or other suitable etching methods. After the formation of the PCM pillars, a layer (310) of an isolation layer dielectric (ILD) material is deposited. Examples of ILD materials include SiN and low dielectric constant dielectrics. The ILD supports, protects, and passivates the PCM pillar structure as shown in FIG. 3. CMP is used to flatten the structure and expose the top heater (180).

[0037] FIG. 4 illustrates a device after the addition of ILD material (420), etching of vias for the top electrode (430), and deposition of a top electrode material similar to that described for the bottom electrode (130). FIG. 4 further illustrates the etching of vias for the upper portion of the bottom electrode (130) through ILD material (310) and deposition of the bottom electrode (130) material.

[0038] In one embodiment, one or more components of the system may use hardware and / or software to solve problems that are inherently very technical (e.g., applying a simultaneous write pulse to a non-volatile memory cell, reading the state of a non-volatile memory cell, interpreting the logic state of a circuit, etc.). These solutions are not abstract and cannot be performed by a series of human mental actions, for example, due to the processing functions required to facilitate computer logic interpretation. Additionally, some of the processes performed may be carried out by a specialized computer to perform defined tasks related to logic circuit operations. For example, a specialized computer may be used to perform tasks related to computer logic, etc.

[0039] In one embodiment, the disclosed logic circuits reduce the processing cycle required to utilize the XOR circuit. In this embodiment, the present method resets the XOR circuits in a first clock cycle by simultaneously applying first and second write pulses to the PCM memory cell. During the second clock cycle, the present method writes the logic state of each of the two nodes, X1 and X2, to the XOR circuit memory cell. In a third clock cycle, the present method reads the state of the XOR circuit by applying a READ voltage across the PCM memory cell.

[0040] Table 1 provides a logical truth table for an XOR circuit. As shown in the table, an XOR circuit with inputs X1 and X2 and an output Y provides a logical “0” output for matching input values ​​where both input values ​​are logical “0” or logical “1”, and a logical “1” output for non-matching input values ​​where one input is logical “0” and the other is logical “1”. X1 X2 Y 0 0 0 0 1 1 1 0 1 1 1 0 Table 1, XOR Logical Truth Table

[0041] Table 2 provides a logical truth table for an XNOR circuit. As shown in the table, an XNOR circuit with inputs X1 and X2 and an output Y provides a logical “1” output for matching input values ​​where both input values ​​are logical “0” or logical “1”, and a logical “0” output for non-matching input values ​​where one input is logical “0” and the other is logical “1”. X1 X2 Y 0 0 1 0 1 0 1 0 0 1 1 1 Table 2, XNOR Logical Truth Table

[0042] Phase Change Memory (PCM) cells, such as PCMs using chalcogenide materials, transition between logical “0” and logical “1” by changing the material phase of the constituent chalcogenide material between amorphous glass, which has relatively high resistance, and a crystalline lattice, which has relatively low resistance. As illustrated in the graph (800) of FIG. 5, to write or set the initial logical “0” state of the PCM to a logical “1” state, it is necessary to apply a voltage set pulse (510) across the PCM material such that the associated current across the PCM material is high enough to raise the temperature of the material above the glass-crystal transition temperature (515). If the material is maintained at that voltage (temperature) for a sufficiently long time, the material may crystallize. To reset the PCM from logical “1” to logical “0”, a higher reset voltage pulse (520) and an associated higher current must be applied to the material. The higher the voltage / current, the higher the temperature exceeding the crystal melting temperature (525) of the material, causing the crystal to melt. If this voltage is quickly removed, the material is reset from a molten state to an amorphous glass state of logical “0”. To read the logic state of the PCM, a READ voltage pulse (530) must be applied to the PCM material and the resistance and / or current associated with the known READ voltage must be measured. As shown in FIG. 5, the READ voltage (530) is below the glass-to-crystallization threshold (515). Reading the logic state of the PCM cell does not set or reset the PCM cell material because the electrical signal applied to the PCM cell to read the state of the PCM cell does not raise the temperature of the PCM cell sufficiently to crystallize or melt the PCM material.

[0043] The schematic diagram (600) of FIG. 6 illustrates the components of a semiconductor logic circuit. As illustrated in the drawing, the illustrated circuit portion includes a PCM cell (610) connected in series with a first node X1 and a second node X2. In one embodiment, the first node X1 is connected to a word line and one or more voltage pulse generators, as well as peripheral switching elements that enable control of the signal passing through X1 and the PCM cell (610). Similarly, the second node X2 is connected to a bit line and at least one voltage pulse generator. The bit line also connects the second node X2 to switching elements that enable control of the signal passing through X2 and the PCM cell (610). In this embodiment, the voltage pulse generator connected to X1 and the voltage pulse generator connected to X2 have opposite polarities. In this embodiment, the READ circuit is connected to X1 and X2 to enable the measurement of the resistance of the PCM using a known READ voltage through the application of a low level of READ voltage across X1, the PCM cell (610), X2, and a series of components and the generated current.

[0044] FIG. 7 provides a set of timelines (700) illustrating signals applied to an XOR gate of an embodiment of the present invention for a series of clock pulses (710). In one embodiment, prior to every logic write and logic operand read cycle, a higher device including the logic circuit disclosed in FIG. 6 simultaneously applies write pulses to the PCM cell (610) from each of the X1 and X2 nodes. As illustrated in FIG. 7, during a high clock pulse, the present method applies two write pulses (720) to the PCM. These two pulses may overlap completely or only partially when applied across the PCM cell (610). These two pulses originate from voltage pulse generators having opposite polarities and are combined into a single pulse (not shown) having a voltage amplitude equal to the sum of the two individual voltage amplitudes. In this embodiment, when the sum of the two write pulse voltages exceeds the PCM cell (610) material melting voltage threshold, the corresponding current passes through, raising the temperature of the PCM cell (610). The elevated temperature melts the material. Rapid removal of the voltage / current quenches the material into an amorphous glass phase, resetting the PCM cell (610) to a high-resistance amorphous glass state. After a low clock pulse is intervened, during the next high clock pulse, the method writes the logic state of each of the two basic logic registers to X1 and X2, respectively. As provided in the drawing, Scenario 7A illustrates the absence of pulses in X1 and X2 associated with the logic states of X1=0 and X2=0. Scenario 7B illustrates a single X1 write pulse for X1=1 and X2=0. Scenario 7C illustrates a single X2 write pulse for X1=0 and X2=1. Scenario 7D illustrates simultaneous X1 and X2 write pulses for X1=1 and X2=1.In each scenario, the present method applies a READ pulse (330) to the PCM cell (610) to determine the current physical state (current and resistance levels) of the PCM cell (610) to be used to interpret the current logic state of the XOR or XNOR logic gate.

[0045] Each write pulse applied to the PCM cell (610) from X1 or X2 has a voltage amplitude that is high enough to raise the temperature of the PCM cell (610) above the glass-crystal threshold of the PCM cell (610), but not high enough to raise the temperature above the melting threshold of the PCM cell (610). Each pulse itself changes the PCM state from glass to crystal. The two signals combine to raise the PCM temperature above the melting threshold, thereby resetting the PCM to the glass state.

[0046] FIG. 8 illustrates a change in the logic state of a PCM cell (610) as the signals of FIG. 7 are applied. As illustrated in the figure, for each scenario, the present method resets the logic state (810) of the PCM from an initial logic state value “1” to a logic value “0”. As the present method applies combined pre-logic operation pulses (320) to the PCM cell (610) of FIG. 9, the logic state is reset to “0”. In other cases not illustrated, the initial logic value “0” will remain “0” when and after combined write pulses are applied to the PCM material. The non-volatile PCM cell maintains this state until the application of a “set” pulse occurs. Regardless of the initial logic state of the circuit, the logic state is reset to “0” after the application of simultaneous pulses (320).

[0047] In the case of Scenario 8A corresponding to the signals of Scenario 7A, no pulse is applied because the current logic state of X1 and X2, respectively, is “0”. The PCM state remains the same, and this method reads the PCM logic state as high resistance, low current, or logic “0”.

[0048] In the case of Scenario 8B, the present method applies a single “set” voltage pulse to X1 corresponding to X1=1. The present method does not apply a pulse to X2 because X2=0. The application of a single X1 “set” pulse changes the PCM cell (610) from amorphous glass to a lower resistance crystal lattice. Then, the present method reads the logic state of the PCM cell (610) as low resistance, high current, or logic “1”.

[0049] Similarly, in the case of scenario 8C, the present method applies a single write pulse to the PCM cell (610) from node X2 because X2=1. The present method does not apply a pulse to X1 because X1=0. The application of a single X2 “set” pulse changes the PCM cell (610) from amorphous glass to a crystalline lattice again, and the present method reads the current logic state of low resistance, high current, or logic “1” again.

[0050] In Scenario 8D, the present method simultaneously applies write pulses from X1 and X2, corresponding to X1=1 and X2=1. Simultaneously applying two write pulses raises the temperature of the PCM cell (610) above the crystal melting point and converts the state of the PCM cell (610) to a high-resistance amorphous state. The present method reads the logic state of the PCM cell (610) as high resistance, low current, or logic “0”.

[0051] In the illustrated embodiments, the application of a reverse polarity voltage pulse may result in an excessive PCM cell (610) current exceeding the PCM melting current threshold. In this embodiment, the addition of a resistor of appropriate size connected in series between the PCM cell (610) and node X2, or a voltage pulse generator for the node X2 write pulse, enables write pulses at node X2 while reducing the risk of excessive write pulse current from the X2 write pulses. In some embodiments, a resistor may be placed in series between X1 and the PCM cell (610) to similarly limit the current applied to the PCM cell (610) during the write pulse from X1.

[0052] In one embodiment, the method interprets the logical reads in terms of the measured current. High current corresponds to a logical “1” and low current corresponds to a logical “0”. In this embodiment, the logical reads correspond to an XOR gate having the inputs and corresponding outputs listed in Table 1. In one embodiment, the method interprets the logical reads in terms of the PCM cell (610) resistance. In this embodiment, high resistance corresponds to a logical “1” and low resistance corresponds to a logical “0”. In one embodiment, the method uses the opposite polarity of the X1 and X2 nodes and shifts the amplitude of the voltage sensor from an a:0>1 scale to an a:-1>0 scale. For these embodiments, the method interprets the circuit as a logical XNOR gate having the inputs and outputs listed in Table 2.

[0053] In one embodiment, the present method utilizes the opposite polarities of nodes X1 and X2 to interpret the circuit as an XNOR rather than an XOR circuit.

[0054] FIG. 9 provides a flowchart (900) illustrating exemplary activities related to the implementation of the disclosed embodiments. After the program starts, a method of the logic circuit control program in block (910) applies simultaneous write pulses to the PCM cell (610) from nodes X1 and X2, respectively, referenced in FIG. 8 above. The time at which these two pulses are applied to the PCM overlaps. The pulses may be applied simultaneously or at least partially overlap. The simultaneous application of two write voltage pulses from voltage pulse generators having opposite polarity generates a combined voltage pulse having an amplitude equal to the sum of the amplitudes of the voltages of the two base voltage pulses. This single write pulse has a voltage amplitude high enough to exceed the melting voltage threshold of the PCM cell (610), raise the temperature of the PCM cell (610) above the melting temperature, and reset the PCM cell (610) to a high-resistance amorphous state.

[0055] In block (920), the method of the logic circuit control program applies write pulses to the PCM cell (610) through nodes X1 and X2 according to the current logic state of the registers associated with X1 and X2. Write pulses are transmitted for a logic state of “1”, and no pulses are transmitted for a logic state of “0”. Each individual write pulse has a voltage amplitude that is high enough to transition the PCM cell (610) from glass to crystal and set the logic value of the PCM cell (610) from “0” to “1”, but not high enough to transition the PCM material to an amorphous state. When combined, the voltage amplitudes of the two write pulses combine to exceed the melting voltage threshold of the PCM material. The combined pulses melt the PCM and transition it to a reset high-resistance amorphous state.

[0056] In this embodiment, for the logic state X1=0, X2=0, no pulse is applied, and the PCM maintains a glass state granted by the application of two simultaneous write pulses prior to the logical write. For the logic state X1=1, X2=0 or X1=0, X2=1, a single write pulse is applied to the PCM cell (610). This single pulse has a voltage amplitude sufficient to transition the PCM from the remaining glass state to the set crystalline state. For the logic condition X1=1, X2=1, two write pulses are applied to the PCM again. The PCM cell (610) transitions from the reset glass state to the molten state and then returns to the high-resistance glass state.

[0057] In block (930), the method of the logic circuit control program applies a low read voltage pulse across X1, the PCM cell (610), X2, and a series of circuit elements. The method reads the current and the associated resistance level across the elements, where high current indicates low resistance and low current indicates high resistance. The read pulse voltage has an amplitude smaller than the set voltage threshold of the PCM material.

[0058] In block (940), the method of the logic circuit control program interprets the results of the logical read operations performed in block (930). In the case of an XOR gate operation, the method interprets high current as a logical “1” and low current as a logical “0”. In the case of an XNOR operation, the method interprets high current (low resistance) as a logical “0” and low current (high resistance) as a logical “0”.

[0059] The disclosed circuit embodiments can be manufactured using standard CMOS (complementary metal-oxide semiconductor) manufacturing technology. Phase change memory cell structures may include mushroom cells, closed cells, pillar cells, pore cells, structures, etc.

[0060] The present invention may be a system, method, and / or computer program product at all possible technical detail levels of integration. The present invention may be advantageously practiced in any single or parallel system processing an instruction stream. A computer program product may comprise a computer-readable storage medium and has computer-readable program instructions on the medium that enable a processor to perform aspects of the present invention.

[0061] A computer-readable storage medium may be a tangible device capable of holding and storing instructions to be used by an instruction execution device. A computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoings, but is not limited thereto. A non-comprehensive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), eraseable and programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multi-purpose disc (DVD), memory sticks, floppy disks, punched cards, or mechanically encoded devices such as raised structures in grooves on which instructions are written, and any suitable combination of the foregoings. The computer-readable storage media or computer-readable storage devices used herein are not interpreted as transitory signals in themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses transmitted through fiber optic cables), or electrical signals transmitted through wires.

[0062] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a communication network (network), for example, the Internet, a local area network, a wide area network and / or a wireless network. The communication network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transmits the computer-readable program instructions to be stored on a computer-readable storage medium within each computing / processing device.

[0063] Computer-readable program instructions for executing the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written by combining one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++ or similar languages, and conventional procedural programming languages ​​such as the “C” programming language or similar languages. Computer-readable program instructions may be executed entirely on the user’s computer, partially on the user’s computer, as a stand-alone software package, partially on the user’s computer and partially on a remote computer, or entirely on a remote computer or server. In the last case above, the remote computer may be connected to the user’s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or this connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to customize the electronic circuit to perform the embodiments of the present invention.

[0064] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowcharts and / or block diagrams and combinations of blocks within the flowcharts and / or block diagrams may be implemented by computer-readable program instructions.

[0065] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to create a machine, and thus the instructions may be executed through the processor of said computer or other programmable data processing device to create means for implementing the functions / operations specified in the blocks or blocks of said flowchart and / or block diagram. These computer-readable program instructions may also be stored on a computer-readable storage medium and may instruct a computer, a programmable data processing device and / or other devices to function in a specific way so that said computer-readable storage medium, on which the instructions are collectively stored, includes an article of manufacture comprising instructions that implement the modes of function / operation specified in the blocks or blocks of said flowchart and / or block diagram.

[0066] Computer-readable program instructions are also loaded into a computer, other programmable data processing device, or other device to create a computer-implemented process by causing a series of operation steps to be performed on said computer, other programmable device, or other device, so that instructions executed on said computer, other programmable device, or other device can implement functions / operations specified in blocks or blocks of a flowchart and / or block diagram.

[0067] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein for convenience of description to explain the relationship of one component or feature to another component(s) or feature(s) as exemplified in the drawings. It will be understood that the spatially relative terms are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if the device in the drawings is inverted, components described as “below” or “below” other components or features will be oriented “above” other components or features. Therefore, the term “below” may include both upper and lower orientations. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0068] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with the measurement of a specific amount based on equipment available at the time of application. For example, “about” may include a range of ±8% or 5% or 2% of a given value.

[0069] For example, a phrase “selective to” such as “selective to the first component” means that the first component can be etched and the second component can act as an etching stop.

[0070] The term “conformal” (e.g., conformal layer) means that the thickness of the layer is substantially the same on all surfaces or that the thickness variation is less than 15% of the layer’s nominal thickness.

[0071] As previously mentioned herein, for the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, as background art, a more general description of semiconductor device manufacturing processes that may be used to implement one or more embodiments of the present invention will now be provided. While specific manufacturing operations used to implement one or more embodiments of the present invention may be known individually, the described combination of operations and / or resulting structures of the present invention is unique. Accordingly, the unique combination of operations described in connection with the manufacture of a semiconductor device according to the present invention utilizes various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0072] Generally, the various processes used to form microchips to be packaged into ICs are divided into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring materials onto a wafer. Available technologies include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Electrochemical Deposition (ECD), Molecular Beam Epitaxy (MBE), and, more recently, Atomic Layer Deposition (ALD). Removal / etching is any process of removing materials from a wafer. Examples include etching processes (wet or dry) and Chemical Mechanical Planarization (CMP). For example, Reactive Ion Etching (RIE) is a type of dry etching that uses a chemically reactive plasma to expose materials to ion bombardment, which removes a portion of the material from an exposed surface to remove materials such as masked patterns on semiconductor materials. This plasma is generated at low pressure (vacuum) by an electromagnetic field. Semiconductor doping generally involves modifying electrical properties by doping, for example, transistor sources and drains, through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices.Semiconductor lithography is the process of forming three-dimensional relief images or patterns on a semiconductor substrate for subsequent transfer. In semiconductor lithography, patterns are formed by a photosensitive polymer called photoresist. To construct the complex structures that make up a transistor and the many wires connecting the millions of transistors in a circuit, the lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with previously formed patterns, and conductors, insulators, and selectively doped regions are slowly built to form the final device.

[0073] The flowcharts and block diagrams in the drawings illustrate possible implementations of manufacturing and / or operating methods according to various embodiments of the present invention. Various functions / operations of the method are indicated as blocks in the flowcharts. In some alternative implementations, the functions mentioned in the blocks may occur in a different order than those mentioned in the drawings. For example, two blocks shown consecutively may actually be executed simultaneously, or these two blocks may sometimes be executed in reverse order depending on the related functions.

[0074] The description of various embodiments of the present invention is provided for illustrative purposes only and is not intended to be complete or limiting to the described embodiments. It will be apparent to those skilled in the art that many modifications and variations may be made without departing from the scope of the invention. The terms used herein are chosen to best describe the principles of the embodiments, substantial applications of the technology found in the market, or technical improvements, or to enable those skilled in the art to understand the embodiments described herein.

Claims

Claim 1 As a phase change memory (PCM) device, the PCM device comprises: a semiconductor substrate; a dielectric layer on the semiconductor substrate; a bottom electrode on the dielectric layer; a bottom heater on a portion of the bottom electrode; a bottom buffer layer on the bottom heater; a PCM region on the bottom buffer layer; a top buffer layer on the PCM region; and a top heater on the top buffer layer. A PCM device comprising: a top electrode on the top heater; a PCM column is formed from the bottom heater to the top heater; a layer of an isolating dielectric (ILD) material is provided on both sides of the PCM column; a layer of an isolating dielectric (ILD) material is provided on both sides of the top electrode; one end of the top electrode contacts a portion of the upper surface of the ILD material layer on one side of the PCM column; the other end of the top electrode contacts a portion of the upper surface of the ILD material layer on the other side of the PCM column; a via is provided on the bottom electrode and penetrates the ILD material layer on one side of the PCM column; the via extends to the upper surface of the ILD material layer disposed on one side of the top electrode; and the same material as the bottom electrode is formed within the via. Claim 2 A PCM device according to claim 1, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. Claim 3 In claim 1, the PCM device wherein the lower heater comprises titanium nitride or tantalum nitride. Claim 4 A PCM device according to claim 1, wherein the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z), and In(x)Se(y), where x, y, and z are integers. Claim 5 A PCM device according to claim 1, wherein the PCM region comprises a thickness of less than 100 nm. Claim 6 A PCM device according to claim 1, wherein the PCM region comprises a thickness of less than 20 nm. Claim 7 A PCM device according to claim 1, wherein the PCM region comprises a thickness of 1 to 100 nm; and the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z), and In(x)Se(y), wherein x, y, and z are integers. Claim 8 A method for manufacturing a semiconductor device comprises: forming a dielectric layer on a semiconductor substrate; forming a bottom electrode on the dielectric layer; forming a bottom heater on the bottom electrode; forming a bottom buffer layer on the bottom heater; forming a PCM region on the bottom buffer layer; forming a top buffer layer on the PCM region; forming a top heater on the top buffer layer; etching from the bottom heater to the top heater to form a PCM pillar from the bottom heater to the top heater; and depositing a layer of an isolation layer dielectric (ILD) material on both sides of the PCM pillar. A method comprising the steps of forming an upper electrode on the upper heater and forming layers of an isolation layer dielectric (ILD) material on both sides of the upper electrode, wherein one end of the upper electrode contacts a portion of the upper surface of the ILD material layer on one side of the PCM column, and the other end of the upper electrode contacts a portion of the upper surface of the ILD material layer on the other side of the PCM column, and vias are provided on the lower electrode and penetrate the ILD material layer on one side of the PCM column, and vias extend to the upper surface of the ILD material layer disposed on one side of the upper electrode, and the same material as the lower electrode is formed within the vias. Claim 9 A method according to claim 8, wherein the lower buffer layer comprises a material selected from the group consisting of C, TiN, TaN, TiC, TaC, TiAlN, TaAlN, TiAlC, TaAlC, HfN, and WN. Claim 10 In claim 8, the method wherein the buffer layer comprises germanium telluride. Claim 11 In claim 8, the method wherein the lower heater comprises tantalum nitride. Claim 12 In claim 8, the PCM region comprises a material selected from the group consisting of Sb(x)Te(y), Ge(x)Sb(y)Te(z), and In(x)Se(y), wherein x, y, and z are integers. Claim 13 In claim 8, the method wherein the PCM region has a thickness of less than 100 nm. Claim 14 In claim 8, the method wherein the PCM region has a thickness of less than 20 nm. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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