Integration of display drivers and spread-spectrum video transmission

Abstract

A video display includes a display panel having a gate driver and a source driver. Each of the source drivers is arranged to receive a discrete-time continuous-amplitude signal representing a video stream through a transmission medium and to decode the signal using demodulation to generate a plurality of samples to be output on the output of the source driver. At least one of the source drivers is arranged to extract a gate driver timing control signal from the signal and output a gate driver control signal to the gate driver so as to synchronize the output of the source driver with the gate driver, thereby displaying the video stream on the display panel of the display unit.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims priority to U.S. provisional patent application No. 63 / 240,630 (file number HYFYP009P1), filed September 3, 2021, the entirety of which is incorporated herein by reference; No. 63 / 280,017 (file number HYFYP009P2), filed November 16, 2021; No. 63 / 317,336 (file number HYFYP014P), filed March 7, 2022; and No. 63 / 346,064 (file number HYFYP014P2), filed May 26, 2022.

[0003] The present application also includes U.S. Application No. 15 / 925,123 filed on March 19, 2018 (File No. HYFYP001), U.S. Application No. 16 / 494,901 filed on September 17, 2019 (File No. HYFYP002), U.S. Application No. 17 / 879,499 filed on August 2, 2022 (File No. HYFYP003), U.S. Application No. 17 / 686,790 filed on March 4, 2022 (File No. HYFYP004AX1), U.S. Application No. 17 / 887,849 filed on August 15, 2022 (File No. HYFYP006), and U.S. Application No. 17 / 851,821 filed on June 28, 2022 (File No. HYFYP007), Includes, by reference, U.S. application no. 63 / 398,460 (file number HYFYP008P) filed on August 16, 2022, and U.S. application no. 63 / 391,226 (file number HYFYP013P3) filed on July 21, 2022.

[0004] Field of invention

[0005] The present invention generally relates to displaying video on a display panel of a display unit. More specifically, the present invention relates to a source driver for decoding an analog signal to be displayed. Background Technology

[0006] Image sensors, display panels, and video processors are constantly competing to achieve larger formats, higher color depth, higher frame rates, and higher resolutions. Local-site video transmission involves performance scaling bottlenecks that limit throughput and degrade performance while consuming more cost and power. Eliminating these bottlenecks can yield benefits.

[0007] For example, as display resolution increases, the data rate of video information transmitted from a video source to a display screen is increasing exponentially, from 3Gbps for Full HD a decade ago to 160Gbps for new 8K screens. Generally, a display with 4K resolution requires a bandwidth of about 18Gbps at 60Hz and 36Gbps at 120Hz. And an 8K display requires 72Gbps at 60Hz and 144Gbps at 120Hz.

[0008] Until now, data has been transmitted digitally using various Low Voltage Differential Signaling (LVDS) data transmission schemes that use a bit rate of 16 Gbps per signal pair and parallelize pairs to achieve the required total bit rate. Due to a wiring delay of 5 ns / m, the wavelength of every bit in the digital connection is 12 mm, which is close to the limit of this type of connection and requires extensive data synchronization to obtain useful data. This digital information then needs to be converted into analog pixel information on the fly using ultra-fast digital-to-analog (D / A) conversion in the display's source driver.

[0009] Today, DA converters use 8 bits, but soon DA conversion may require 10 bits or even 12 bits, at which point it will be very difficult to convert accurately at a sufficiently fast data rate. Therefore, displays must perform DA conversion within a very short time, and as the time available for conversion becomes increasingly shorter, stabilizing DA conversion is also becoming a problem.

[0010] Therefore, new devices and technologies are needed to eliminate the need for DA conversion in the source driver of the display, increase bandwidth, and utilize analog video signals generated outside or inside the display unit. means of solving the problem

[0011] To achieve the above, and according to the purpose of the present invention, a source driver of a display panel within a display unit that decodes an analog signal into a voltage expected by the display panel is disclosed.

[0012] A video signal is a list of brightness values. Precisely maintaining fixed bit-width (i.e., digital) brightness values ​​is inefficient for video transmission, and analog voltage provides a much larger dynamic range because there is no need to accurately reproduce these brightness values ​​at the bit level. Therefore, the present invention proposes transmitting the video signal of a display panel as an analog signal rather than a digital signal.

[0013] Advantages include reduced power consumption. In conventional technology, power consumption significantly limits system performance, but using the present invention reduces power consumption by up to 60%. Additionally, the embodiments provide noise immunity and EM stealth in that EMI / RFI emissions from the display panel are much lower than specified limits. Furthermore, the transmission range of the new analog signal is much wider than that of existing Ethernet or HDBaseT signals. Moreover, while conventional transmission uses expensive mixed-signal processing for high-speed digital circuits, embodiments of the present invention use fully degraded analog processing for greater flexibility and lower production costs.

[0014] In addition, using a new analog spread-spectrum video transport (SSVT) signal for data transmission between the display controller and the source driver of the display panel significantly reduces the cost and complexity of the silicon chip. For example, for 4K 60Hz panels and 8K 120Hz panels, chip area is saved by 3:1 and 10:1, respectively, when comparing the existing transmission between the signal source (via LVDS or Vx1 transmitter) and the source driver receiver (including a DA converter) with the equivalent function implemented using transmission between the new SSVT transmitter and the new SSVT receiver.

[0015] The present invention relates to a circuit for decoding analog video data transmitted between a video source and a video sink using a technique derived from Spread Spectrum Direct Sequence (SSDS) modulation-based Code Division Multiple Access (CDMA) channel sharing. As described in more detail below, the number and content of input video samples received from the video source depend on the color space in which the source operates. Regardless of which color space is used, each video sample represents the amount of light detected or measured in the specified color space.

[0016] As a stream of input digital video samples is received by the encoder, the input digital video samples are (1) repeatedly distributed by assigning input video samples to encoder input vectors according to a specified permutation, and (2) encoded by applying SSDS-based modulation with orthogonal codes to each of the multiple encoder input vectors, thereby generating multiple composite EM signals having noise-like properties. The analog EM signals are transmitted through a transmission medium (3). At the receiving end, (4) the incoming analog EM signals are decoded by applying SSDS-based demodulation using the same orthogonal codes, so that the samples can be reconstructed into output vectors, and (5) the output vectors are displayed on a display as voltages. Consequently, the original stream of time-aligned video samples containing color and pixel-related information is transmitted from the video source to the video sink.

[0017] Once captured and converted from a video source, the digital video data can be encoded and transmitted to a video display for near real-time viewing. The captured video data may also be stored for later viewing in a time-shifted mode. In either case, an analog SSVT signal is used to transmit the digital video data received from the video source (or storage device) to the video sink for display (or storage). The SSVT signal can originate from a computer or other processor and be transmitted to the display unit (video sink); it may originate outside the display unit, or the SSVT signal may be generated within the display unit or the display panel itself. Brief explanation of the drawing

[0018] The present invention is best understood by referring to the following description together with the accompanying drawings, along with additional advantages of the present invention. FIG. 1 illustrates a conventional technology for transmitting a digital signal to a display panel within a display unit. FIG. 2 illustrates a conventional display driver architecture for a display, such as a display panel. Figure 3 illustrates the transmission of an analog video signal to a display panel using conversion near the SoC of a display unit. Figure 4 illustrates the transmission of an analog video signal to a display unit using conversion near the digital video processor of a local-site video system. FIG. 5 illustrates the transmission of an SSVT analog video signal to a display panel using conversion and encoding within a display unit. Figure 6 illustrates an example of a display source driver. FIG. 7 illustrates a more detailed drawing of a decoding unit and its output. Figure 8 shows a source driver that buffers and then amplifies a sample. FIG. 9 is a block diagram of one of the decoders (656) of FIG. 8. Figure 10 is a block diagram of the collector of Figure 8. FIG. 11 illustrates a GPU-to-the-Glass platform, which is a custom printed circuit board that includes a current generation GPU as well as an SSVT transmitter. FIG. 12 illustrates a GPU-to-glass system-on-module (SoM) that includes a current generation GPU as well as an SSVT transmitter. FIG. 13 illustrates an enhanced GPU-to-glass system including an SSVT transmitter with an enhanced GPU fully integrated. Figure 14 illustrates an example showing how a signal sample, in this case an analog value, is encoded within an encoder and then transmitted through an electromagnetic path. FIG. 15 illustrates a novel encoding technique that can be applied to signal samples that are digital values. Figure 16 shows the decoding of an analog input level encoded using the encoder of Figure 14. FIG. 17a illustrates the use of an analog encoder and a corresponding analog decoder. Figure 17b shows the use of a digital encoder and a corresponding analog decoder. FIG. 17c illustrates the use of a digital decoder to decode an encoded analog signal that arrives via an electromagnetic path. Figure 18 shows a simulation of the SSVT waveform transmitted through the electromagnetic path. Figure 19 is a logic diagram for one of the four decoders. Figure 20 is a diagram of a typical decoder track circuit. Specific details for implementing the invention

[0019] In a video display system, the conversion of incident light into a signal is typically performed by a source assembly, and a designated conversion will determine the format of a payload to be transmitted to a sink assembly, which may be a display or video processor, that receives a designated format from the source assembly via one or more electromagnetic paths and converts the received payload into a signal used with an appropriate output device to generate emitted light suitable for human viewing.

[0020] After the digitization of the video signal occurs at the system's signal source (often the GPU), the digital signal is transmitted to the display source driver, typically using a combination of high-performance wiring systems, where the digital signal is converted back into an analog signal and loaded into the display pixels. Therefore, the sole purpose of digitization is to transmit data from the video source to the display pixels. Consequently, we recognize that it is far more beneficial to avoid digitization entirely whenever possible and transmit analog data directly from the video source to the display driver. This can be achieved using the novel SSVT encoding of the present application, which allows the source driver to decode the accurate analog voltage. Since analog data is highly accurate, high bit depth is not required. This implies that additional bandwidth remains for expansion, as the sampling rate is at least 10 times lower than that of digital transmission.

[0021] Furthermore, it is recognized that it is much easier to perform DA conversion at a point requiring less power than the final point where the display panel actually needs to be driven. Therefore, instead of transmitting digital signals continuously from the video source to the location where the analog signal needs to be generated, we generally transmit analog signals to the display at a sampling rate much lower than when digitizing. In other words, instead of transmitting gigabits per second over multiple lines, we can perform this with only a few megasamples per second for analog signals, thus reducing the bandwidth of the channels that need to be used. Additionally, in the case of prior technology digital transmission, every bit occupies only about 1.25 cm (considering that cable propagation is about 0.2 m / ns, 16 Gbps means 1 / 16 ns / bit, so 1 bit is 0.2 / 16 meters), whereas transmitting analog data increases the available space tenfold, which means that additional bandwidth can be utilized.

[0022] Furthermore, the bits of the digital data must be well-defined. Since this definition is highly sensitive to errors and noise, it must be possible to detect highs and lows with great accuracy. On the other hand, the proposed analog transmission is much less sensitive. This means that the quality of the cable (e.g., the cable extending from one end of the display to the other) does not need to be high.

[0023] The present invention is particularly applicable to high-resolution, high-dynamic-range displays used in computer systems, televisions, monitors, machine vision, automotive displays, virtual or augmented reality displays, etc.

[0024] Pre-transmission (digital) of video information to the display panel

[0025] FIG. 1 illustrates a prior art known as “display connectivity” that transmits digital signals to a display panel within a display unit (100). For the purposes of this disclosure, “display panel” refers to an internal part of a display that implements pixels that generate light for viewing, whereas “display unit” refers to an entire (generally) rectangular enclosure comprising a display panel, a panel assembly, a frame, a driver, cables, and associated electronic components for generating a video image. Generally, a mass-produced display panel comprising O(N^2) pixels is controlled by O(N) voltages, and each voltage is updated O(N) times (the inverse of the frame rate) per display interval.

[0026] The input of a digital video signal (112) to a display unit via an HDMI connector (such as an RJ45 connector) to a system-on-chip (SoC) (110) of a display unit is illustrated. The SoC (110) transmits the digital signal to a timing controller (120) (TCON) via a V-by-One HS standard (116), and the timing controller then transmits the signal to any number of digital-to-analog converters (DACs) (122) within the source driver of the display panel (118) using bit serial transmission (121) (e.g., SerDes, LVDS, or CEDS) to convert the digital signal into an analog signal to be input to the pixels of the display panel. Digital transmission may also use MLVDS, DDI, etc. Control signals (114) provide video framing flags (Vsync, Hsync, etc.), configuration parameters, gate driver control signals, FRC grayscale, driver parameter settings, backlight control, contrast control, etc.

[0027] In addition to the disadvantages mentioned above, this digital transmission of display connectivity leads to higher EMI / RFI issues due to its reliance on high-speed digital circuits, requires high power, is difficult to synchronize, and must be implemented using relatively expensive integrated circuit processes. Furthermore, for example, 8K V-by-One HS requires 48 wire pairs at 3.5Gbps.

[0028] Furthermore, these disadvantages of display connectivity also exist in local-site video connectivity. For example, a computer's GPU generates a video signal that is transmitted digitally to a display unit (via V-by-One HS, MLVDS, DDI, etc.), where a DAC within the source driver converts the signal into analog. Generally, the GPU chip is located as close as possible to the microprocessor on the system / microprocessor board.

[0029] Therefore, converting the digital video signal from digital to analog as close as possible to the SoC, GPU, or digital video processor not only eliminates the need for a DAC within the display panel's source driver but also enables the realization of the above advantages when transmitting an analog signal instead of a digital signal within or to the display unit.

[0030] FIG. 2 illustrates a conventional display source driver architecture for a display such as a display panel (118). A source driver (200) having 900 to 1,000 outputs is generally shown. Multiple instances of this source driver exist within every display, cascaded together through the top row so that DIO1 and DIO2 connect any two of the series (via a shift register (220)). Thus, the drivers are extended horizontally, and a typical display unit contains between 1 and 20 of these drivers. The data in 210 is serialized digital data coming from the timing controller of the SoC. Each source driver generally has a digital part (202) and an analog part (204) including a DAC (230). Outputs (240-244) are output directly to the display column, i.e., the display glass, to drive the source of each pixel, as is well known in the art.

[0031] The source driver (200) requires that most of the driver area be used by digital electronic devices that require a data rate 10 times higher than the associated signal provided to the column line of the display. This is disadvantageous because the total power consumed in all (digital or analog) circuits depends linearly on the switching frequency (typically the clock frequency).

[0032] Display connectivity

[0033] FIG. 3 illustrates the transmission of an analog video signal to a display panel (318) using a conversion at or near the SoC (110) of the display unit (300). In this embodiment, the conversion and encoding of the digital video signal into an analog SSVT signal occurs within the display unit itself (or even within the panel assembly) to improve display connectivity. Input of a digital video signal (312) to a system-on-chip (310) via an HDMI connector (or an RJ45 connector, etc., when the present invention works with content streamed over the Internet) is illustrated. The digital signal is transmitted via V-by-One (or other bit serial transmission) to an SSVT transmitter (315) (which may be implemented in an integrated circuit, e.g., a chip), where the SSVT transmitter converts the digital video signal into a spread-spectrum video transmission (SSVT) signal (316) transmitted to the display panel (318) via a novel SSVT source driver (320). A timing controller (TCON) located between the SoC (310) and the SSVT transmitter (315) is not shown. In one embodiment, the SSVT transmitter (315) is implemented within its own integrated circuit and the SoC and TCON are separated; in another embodiment, both the SSVT transmitter (315) and TCON are combined within a single integrated circuit; and in yet another embodiment, the transmitter (315), TCON, and SoC are all combined within a single integrated circuit. Although not shown in this drawing, if the TCON is separated, it is located between the SoC (310) and the SSVT transmitter (315).

[0034] The control signal (314) may also provide, as previously mentioned, a gate driver control signal, FRC gradation, driver parameter setting, backlight control, contrast control, etc., but is not mandatory. The display panel (318) is associated with any number of SSVT source drivers (320) (implemented by any number of chips) that decode the analog SSVT signal (316) into the analog voltage expected by the display panel, as described in more detail below. The display panel driver chipset is considered to include integrated circuits (315 and 320).

[0035] The display panel or the new source driver described below does not require a DAC (digital-to-analog converter). Preferably, the display unit (300) can be implemented in a mature IC process, EMI / RFI emissions are much lower than the specified limits, only half the power is required, it is easier to synchronize, and an 8K display would require only 8 wire pairs at 1.6 GHz or 18 wire pairs at 680 MHz. In contrast, the conventional transmission of digital video signals within the display unit from a system-on-a-chip (SoC) must be implemented in a relatively expensive IC process, EMI / RFI emissions are problematic because they rely on high-speed digital circuitry, and an 8K / 60 Hz display requires 8 wire pairs at 16 Gbps or 36 wire pairs at 3.5 Gbps.

[0036] Local site video connectivity

[0037] FIG. 4 illustrates the delivery (400) of an analog video signal to a display panel using conversion near a digital video processor of a local-site video system. In this embodiment, the conversion and encoding of the digital video signal into an analog SSVT (spread-spectrum video transport) signal occurs outside the display unit (401) or the display panel. Thus, the input to the display unit (401) is an analog SSVT signal. A core AI / ML GPU (410) that generates the digital video signal is shown, and an SSVT transmitter (414) encodes the digital signal into an analog spread-spectrum video transport (SSVT) signal (416), which is transmitted to the display unit, and thus to the display panel (418). The display unit includes any number of SSVT source drivers (420) that decode the SSVT signal into an analog voltage expected by the display panel, as described in more detail below. A DAC (digital-to-analog converter) is not required within the display unit, the display panel, or the drivers.

[0038] The GPU (410) where the video data is processed may be located within a computer. Once converted and encoded by the SSVT transmitter (414), the analog signal (416) is transmitted to a display unit (401). The display unit may be nearby, 10 meters away, or further away. Thus, the information path from the graphics or video processor, which is effectively a computer, passes through multiple transmission connections directly to the display unit without being digitized at any point along the data path. Originally, the video signal may originate from a camera or similar device shown in FIG. 4, which is transmitted to the GPU (410). The video signal may also originate from a camera, video processor, or internet modem at a location where it can be converted to SSVT using the transmitter (414).

[0039] Preferably, the further upstream the display unit is from which DA conversion and encoding into SSVT signals are performed (i.e., conversion and encoding are not performed within the display unit itself), the greater the advantage. There is no need to perform compression to transmit the compressed digital video signal through the HDMI cable. In this particular embodiment, full-resolution display information is processed at the GPU, then conversion and encoding are performed at the GPU chip, and subsequently, all transmission is carried out via a relatively low-frequency SSVT signal until the signal reaches the display unit. In this case, the full display resolution was processed at full frame rate from the GPU source to the display unit endpoint without internal compression.

[0040] Display connectivity details

[0041] FIG. 5 illustrates the transmission of an SSVT analog video signal to a display panel (550) of a display unit (500) using conversion and encoding within the display unit. In this embodiment, the conversion and encoding of the digital video signal into an analog SSVT signal occurs within the display unit (500) itself to improve display connectivity. The SoC and TCON of the display unit are not illustrated. As previously mentioned, three or more commercial embodiments may exist: a discrete embodiment in which the SSVT transmitter is implemented as a mixed-signal integrated circuit and the TCON and SoC are discrete components (an SSVT transmitter "adapter chip" is inserted between the legacy TCON and the novel source driver described herein - the SSVT transmitter converts the TCON output signal into an SSVT signal); a mixed embodiment in which the SSVT transmitter is integrated with the TCON in a single IC and the SoC is discrete; and a fully integrated embodiment in which as many possible functions are integrated into a custom mixed-signal integrated circuit (the SSVT transmitter is integrated with the TCON and SoC).

[0042] In a demo system (not shown), the SoC digital functions are implemented on an FPGA carrier board that implements TCON digital functions and communicates via HDMI 2.0 with a custom mixed-signal PCB that implements an SSVT transmitter within the analog subsystem. While SoC functions (e.g., decompression of compressed digital video signals) are performed in software on the GPU, TCON functions (e.g., generation of timing signals for gate and source drivers) are performed in software and soft circuitry on the FPGA.

[0043] In this example of FIG. 5, the display panel (550) is located within a panel frame (551) within a 55-inch HDR 4K60 display unit as illustrated. As illustrated, both the SSVT transmitter (540) and the panel frame (551) are located within the display unit (500). The display panel (550) may be a display panel of any size, may be a display or displays within a VR headset, and may be a head-up display (HUD) where the display is projected onto a windshield, a screen of a visor, etc.

[0044] Even if the input signal is not SSVT—that is, a digital video signal—using an SSVT signal within the display unit offers significant advantages. In conventional display units, the HDMI signal must be decompressed to obtain full-bitrate digital data that must be transmitted from the receiving end of the display unit to every location within the unit. For 64-inch or 80-inch displays, this connection can be quite long, requiring the transmission of digital data from one end of the input device to the other end where the final display source driver is located. Therefore, there is an advantage in internally converting the digital signal to SSVT and then sending the resulting SSVT signal to every location within the display unit where the source driver is located. Specifically, this offers the advantages of using lower frequencies and lower EMI signals, as well as the benefits of embedded synchronization and low-latency initialization.

[0045] Also illustrated in FIG. 5 is an SSVT transmitter (540) that generates an SSVT signal (592) for a source driver (586) as well as power and control signals (590) for a gate driver (560). It includes individual flexible PCBs (584) and rigid PCBs (582) each having a source driver (586) that generates a source voltage for a display panel. As described in more detail below, the signal (608) optionally provides information regarding the display panel back to the transmitter (540) to assist in the encoding of the SSVT signal. The generation of the gate driver control signal (590) can be performed by a timing controller (or other specific hardware) based on synchronization information from the source driver.

[0046] Generally, the SSVT transmitter and the SSVT receiver (in this case, the source driver (586)) are connected via a transmission medium. In various embodiments, the transmission medium may be a cable (e.g., HDMI, flat cable, fiber optic cable, metal cable, non-metallic carbon track flex cable) or wireless. The transmission medium may have numerous EM paths with one path per encoder. The SSVT transmitter includes a splitter and multiple encoders. The SSVT receiver will include multiple decoders, equal in number to the encoders. The number of paths in the transmission medium may vary from one to more than one. In this example, the medium is a combination of cables, traces on a PCB, internal connections within an IC, and other media used by a person of ordinary skill.

[0047] During operation, a stream of time-aligned video samples containing color values ​​and pixel-related information is received from the video source of the display unit (500) and transmitted to the SSVT transmitter (540) via the SoC and TCON (processing by the SoC may be performed as is known in the art). The number and content of the input video samples received from the video source depend on the color space in which the source operates (the samples may be black and white). Regardless of which color space is used, each video sample represents the amount of light detected or measured in the specified color space.

[0048] As a stream of input digital video samples is received at the SSVT transmitter, the input digital video samples are (1) repeatedly distributed by assigning video samples to encoder input vectors according to a specified permutation (one vector per encoder), and (2) encoded by applying SSDS-based modulation using orthogonal codes to each of the multiple encoder input vectors, thereby generating multiple composite EM signals (one analog signal from each encoder) having noise-like properties. Then, the analog EM signals are transmitted as one signal per path through a transmission medium (3).

[0049] For illustrative purposes, one possible permutation implemented by the divider to construct the four vectors V0, V1, V2, and V3 is a permutation in which each vector contains N color information samples. In this example, the color information exposed for the sample set is "RGB", respectively. In this example, the exposed RGB samples of the sample set are assigned to the vectors V0, V1, V2, and V3 from left to right. That is, the "R", "G", and "B" values ​​of the leftmost sample and the "R" signal of the next set of samples are assigned to vector V0, while the next (left to right) "G", "B", "R", and "G" values ​​of the next samples are assigned to vector V1, the next (left to right) "B", "R", "G", and "B" values ​​are assigned to vector V2, and the next (left to right) "R", "G", "R", and "R" values ​​are assigned to vector V3. Once a signal is assigned to the fourth vector V3, the process is repeated until each of the four vectors V0, V1, V2, and V3 has N samples. In various embodiments, the number of N samples can vary widely.

[0050] For example, let us consider an example where N = 60. In this case, the total number of N samples contained in the four vectors V0, V1, V2, and V3 is 240 (60 x 4 = 240). When fully constructed, the four encoder input vectors V0, V1, V2, and V3 contain samples (where S = 3) for 80 individual sample sets (240 / 3 = 80). In other words:

[0051] · Vector V0 is samples P0, N0 to P0, N N-1 Including;

[0052] · Vector V1 is samples P1, N0 to P1, N N-1 Includes;

[0053] · Vector V2 is samples P2, N0 to P2, N N-1 Includes,

[0054] · Vector V3 is samples P3, N0 to P3, N N-1 Includes

[0055] It must be understood that the above example is merely illustrative and should not be interpreted as a limitation. The number of samples N may be greater than or less than 60. Additionally, it must be understood that the color information exposed for each set of samples may be arbitrary color information (e.g., Y, C, Cr, Cb, etc.) and is not limited to RGB. The number of EM paths through the transmission medium can also vary widely. Therefore, the number of vectors V and the number of encoders can also vary widely from 1 to any number greater than 1. Furthermore, it must be understood that the permutation scheme used to construct the vectors is arbitrary regardless of the number. Any permutation method may be used, and the restriction is that the permutation method used at the transmitting end is also used at the receiving end.

[0056] Then, each vector of N samples is encoded by a corresponding encoder and L output levels are generated in parallel using the encoding scheme described herein and particularly shown in FIG. 14-17. Preferably, L >= N >= 2. As described, the encoding can be analog (a DAC is placed before the encoder) or digital (the L levels are converted to analog by a DAC before being transmitted). Then, the L analog output levels are transmitted through an EM path to an SSVT receiver (in this case, a source driver (586)) as part of a spread-spectrum video transport (SSVT) signal. Since the SSVT signal is an analog signal, there is an advantage that no DAC is required in the source driver.

[0057] Although not shown in FIG. 5, the SSVT transmitter (540) may be located outside the display unit.

[0058] Display panel source driver

[0059] FIG. 6 illustrates a display source driver (586). As illustrated, a plurality of source drivers are cascaded as is known in the art, and these plurality of source drivers drive a display panel. As illustrated, the source driver (586) does not require a DAC (in the signal path for converting digital samples to analog samples for display) as is required in source drivers of the prior art. The input to the decoding unit (610) of each source driver is an analog SSVT signal (592) encoded upstream from within the display unit itself or from outside the display unit, as described herein. As shown, the SSVT signal (592) is daisy-chained between the source drivers. In an alternative embodiment, each source driver has its own SSVT signal, and TCON provides timing information to each source driver chip.

[0060] The decoding unit (610) may have any number (P) of decoders, or it may have only a single decoder. The unit (610) decodes the SSVT signal or signals (described in more detail below) and outputs numerous reconstructed analog sample streams (612), i.e., analog voltages (number of samples corresponding to the number of outputs of the source driver). Since these analog outputs (612) may not be within the voltage range required by the display panel, scaling may be required, and they may be input to a level shifter (620) that uses analog conversion to shift the voltage to a voltage range for driving the display panel. Any suitable level shifter known in the art, such as a latch type or an inverter type, may be used. The level shifter is also called an amplifier.

[0061] For example, the voltage range from the decoding unit may be 0 to 1V, and the voltage range from the level shifter may be -8 to a maximum of +8V (an inversion signal (622) can be used to tell the level shifter to invert the voltage every other frame, i.e., the range will be -8 to 0V for one frame and then 0V to +8V for the next frame). In this way, the SSVT signal does not need to invert its own voltage every frame, the decoding unit provides a positive voltage range (e.g.), and the level shifter inverts the voltage every other frame as expected by the display panel. The decoding unit can also implement line inversion and dot inversion. The inversion signal tells the level shifter which voltage to switch. Some display panels, such as OLEDs, do not require this voltage to be inverted every other frame, in which case an inversion signal is not needed and the level shifter will not invert the voltage every other frame. Display panels such as LCDs require this voltage inversion. The inverted signal (622) is restored from the decoding unit as described below.

[0062] Additionally, inputs to the level shifter (620) may be gain and gamma values, where the gain determines the degree to which amplification is applied and the gamma curve associates the light flux with the perceived brightness, which linearizes the human optical light flux perception. Generally, in a source driver of the prior art, both gain and gamma are set values ​​determined by the manufacturing characteristics of the display panel. In an analog level shifter (620), gain and gamma can be implemented as follows. In one embodiment, gamma is implemented in the digital part of the system, and level shifting and gain are implemented in the driver by setting the output stage amplification. In the case of gamma, it can also be implemented in the output driver by implementing non-linear amplification characteristics. Once shifted, the sample is output to an output (634) used to drive the source electrode in the corresponding column of the display panel, as is known in the art.

[0063] Various physical characteristics or properties of a specific display panel are required by the GPU (or any other display controller) or any entity performing SSVT encoding to properly encode the SSVT signal for final display on that specific display panel (whether encoded within the display unit itself or further upstream outside of that display unit). These physical characteristics are labeled (608) and include, in particular, resolution, tessellation, backlight layout, color profile, aspect ratio, and gamma curve. Resolution is constant for a specific display panel; tessellation refers to the method of dividing the plane of the panel into multiple regions in a constant and predetermined manner, in pixel units; backlight layout indicates the resolution and diffusion characteristics of the backlight panel; color profile is the accurate luminance response of all primary colors, providing accurate colors in the image; and the aspect ratio of the display panel will have an individual known value.

[0064] These physical characteristics of a specific display panel may be transmitted, wired, or provided to a specific display controller in various ways. In one example illustrated in FIG. 5, the signal (608) transmits the values ​​for these physical characteristics directly from the display panel (or other location within the display unit) to the SSVT transmitter (540). Alternatively, the SSVT transmitter (540) embedded within the specific display unit is provided with these values ​​hardcoded within the transmitter. Or, the specific display controller is configured to be used only with a specific type of display panel, and the corresponding characteristic values ​​are hardcoded into the display controller.

[0065] The input to the display panel may also be a backlight signal (604) that directs the LEDs of the backlight, namely when to switch on and at what level. That is, this is a low-resolution representation of an image, meaning that the backlight LEDs are turned on where the display should be bright and turned off where the display should be dark. The backlight signal is a monochrome signal that may be included within the SSVT signal, that is, another parallel and independent video signal that travels along with other parallel video signals R, G, and B (e.g.), and may be low or high resolution.

[0066] The output from the decoding unit (610) is a gate driver control signal (606) that shares timing control information with the gate driver (560) located at the left edge of the display panel to synchronize the gate driver with the source driver. Typically, each decoding unit includes a timing acquisition circuit that obtains the same timing control information for the gate driver, and one or more source driver flex foils (typically the leftmost and / or rightmost source driver) transmit the corresponding timing control information to the gate driver. The timing control information for the gate driver is embedded within the SSVT signal and is recovered from the corresponding signal using established spread spectrum techniques.

[0067] Generally, conventional display drivers are connected directly to the glass using a "COF (Chip-on-Flex or Chip-on-Foil)" IC package, although existing COG (Chip-on-Glass) is also possible but not common in large displays. Existing display panels can be converted into SSVT-supported panels by replacing these drivers with the new source drivers of FIGS. 6 and 7. The inputs of these ICs are typically connected together via a PCBA to provide input signals for the video source and timing controller. They may be located close to or far from the display panel and can transmit video and control signals via inexpensive wires.

[0068] Details of SSVT Decoding and Source Driver Integration

[0069] At the receiving end, the decoder of each source driver is responsible for re-decoding the stream of differential EM level signals received through the transmission medium into a format suitable for display. Once converted to the appropriate format, the video content contained in the samples can be displayed on the video display frame by frame. Consequently, video captured from all video sources can be recreated into a video sink. Alternatively, the decoded video information can be stored for later display in time-shift mode.

[0070] FIG. 7 illustrates a more detailed diagram of the decoding unit (610) of the source driver. P represents the number of input electromagnetic pairs, each pair carrying an independent SSVT signal except that it is an isochronous signal known to be closely generated by the encoder on the transmitting side. The source driver includes P decoders (780) and collectors (blocks (782, 786)). The decoders (780) perform the inverse transformation of the paired encoders on the transmitting side and reconstruct the input differential EM level signal into an output vector of N reconstructed samples (a single-ended input may be used instead of a differential input). The collector assigns the decoder output vector samples (or "reconstructed samples") to designated locations in the source driver inputs (612). The source driver inputs (612) contain S reconstructed samples corresponding to the driven column groups of the display panel. A retimer function is included within the collector.

[0071] P decoders (780) (labeled 0 to P-1) each have a differential EM level signal Level 0 to Level P-1 (702-704) are arranged to receive. In response, each decoder (780) is configured to receive N differential pairs of reconstructed samples (Sample0 to Sample N-1) is generated. If there are 4 decoders (780) (P=4), 4 vectors V0, V1, V2, and V3 are each constructed. The number of samples N is exactly the same as the number of orthogonal codes used in the previous encoding, that is, N orthogonal codes were used, which means N codes from the codebook.

[0072] The reconstruction bank (782) has N reconstructed samples (Sample0 to Sample) for each of the four decoder output vectors V0, V1, V2 and V3 at the end of each decoding interval. N-1 Samples and retains each differential pair of ). These received differential voltage signal pairs are samples for each of the four vectors V0, V1, V2, and V3 respectively (Sample N-1 It is output to Sample0). Basically, each reconstruction bank is reconstructed with a single voltage in a differential pair. The staging bank (786) outputs all reconstructed samples (N) for each of the four decoder output vectors V0, V1, V2, and V3. n-1 It receives (or N0) and acts as an analog output buffer, which is described in more detail below. When a sample is moved to the staging bank (786), it is triggered by a latch signal (632) derived from the decoded SSVT signal. The latch signals can be daisy-chained between source drivers. When a sample is emitted from the staging bank, it is sent to the level shifter (620).

[0073] The decoding unit (610) also includes a channel aligner (787) and a staging controller (789) that receive framing information and aperture information from each decoder (780). In response, the staging controller (789) adjusts the timing of the staging bank (786) to ensure that all samples of the level signal come from a common time interval transmitted by the SSVT transmitter. Consequently, individual channels of the transmission medium do not necessarily have to be the same length, as the channel aligner (787) and the staging controller (789) compensate for any timing difference. The gate driver control signal (606) provides timing information to the gate driver (or intermediate circuit), which in turn provides the correct timing and control signal to the gate driver, and may originate from the channel aligner (787).

[0074] FIG. 7 discloses a decoder that buffers samples of a staging bank (786) and then shifts (amplifies) the level, and it is also possible to buffer samples for output after shifting the level.

[0075] Display panel source driver array

[0076] FIG. 8 illustrates an alternative embodiment for implementing an array of source drivers. The array (650) is suitable for use with a display panel having 8K resolution and a 144Hz refresh rate, i.e., an "8K144" panel. FIG. 8 shows that in this embodiment, each source driver includes a single decoder (i.e., a decoding unit of a single decoder) and a corresponding collector and amplifier, whereas FIG. 6 and 7 show that each source driver may have many decoders within the decoding unit of the source driver. Either method may be used.

[0077] Twenty-four 720 MHz SSVT signals (652–654) are shown, each being a twisted pair from the SSVT transmitter (540), i.e., each twisted pair originating from the transmitter’s encoder. Each pair is input to one of the decoders (656–658), and each decoder outputs 64 analog samples at a frequency of 11.25 MHz. These samples are input to one of the 24 collectors (662–664), and each collector collects 15 sets of these samples before updating the output at 15 decoding intervals, as shown in more detail below. As previously mentioned, each collector consists of a reconstruction bank and a staging bank (not explicitly shown in this drawing). In turn, these 960 analog samples from each collector are input to one of the amplifiers (666-668) at a frequency of 750 kHz for amplification before being output to the display column of the display panel at a frequency of 750 kHz (11.25 MHz x 64 / 960) as an amplified analog level (670). For clarity, the signals (604, 606, 608, 622, 632) shown in FIGS. 6 and 7 are not shown.

[0078] Theoretically, amplifiers or level shifters can be omitted if the encoded SSVT signal is at a higher voltage and the decoded signal generates the sample voltage required for the display. However, since SSVT signals are typically at a lower voltage (and displays require a higher voltage output), amplification is necessary.

[0079] FIG. 8 discloses a decoder that buffers a sample in a collector (664) and then amplifies it, and it is also possible to amplify the sample to be output and then collect (buffer) it. Any embodiment may be used.

[0080] FIG. 9 is a block diagram of one of the decoders (656) of FIG. 8. One of the SSVT signals (652) input to the decoder is shown. The decoder includes a chip counter (680), a codebook (682) typically stored in RAM containing orthogonal codes used for encoding and decoding, as well as a block diagram (684) for each decoding circuit for each of the 64 output analog samples (688). Each group of 64 analog samples is output as "effective" once per L cycle at 11.25 MHz. Decoding is described in more detail below with specific circuit diagrams.

[0081] FIG. 10 is a block diagram of the collector of FIG. 8 and shows the staging bank (786) of FIG. 7 in more detail. Basically, individual collectors perform serial-to-parallel conversion with split line buffers. The input shown for each collector (662-664) is a set of 64 analog samples (690-692) from each decoder at a frequency of 11.25 MHz (reconstruction bank (782) is not shown). As shown, during each decoding interval, a new set of incoming 64 reconstructed samples is stored in the collector, and each collector is filled once every 15 decoding intervals. After each 15 decoding interval, 960 stored samples (698) from each collector are output to the corresponding amplifier (666-668) before being delivered to the corresponding column of the display panel as shown.

[0082] In one particular embodiment, each of the source drivers of FIG. 8 (e.g., decoder (658), collector (664) and amplifier (668)) is implemented in an integrated circuit, and each of these integrated circuits can be mounted on a flexible PCB (584) as shown in FIG. 5.

[0083] Specific display panel examples

[0084] In a first specific embodiment, the present invention may be implemented in a TFT LCD panel frame assembly having characteristics such as a large-area display panel (LDP), e.g., 8K144 resolution / frame rate, at least 10-bit sub-pixel color depth, and is suitable for use in a display of 65 inches or larger. In this embodiment, the SSVT transmitter (540) is implemented in a single integrated circuit and there are 24 source drivers (586), each implemented in a single integrated circuit. The transmitter (540) each has a maximum f of 780 Msps. SSVT Outputs 24 wire pairs (592) (SSVT signals) having, and each input of each source driver is f of up to 780 Msps SSVT It is a single SSVT signal wire pair having. The optical characteristics of this embodiment are equivalent to those of a conventional LDP, such as color reproduction, brightness, contrast, and response time.

[0085] In a second specific embodiment, the present invention may be implemented in an LCD panel frame assembly having characteristics such as a large-area display panel (LDP), e.g., 8K240 resolution / frame rate and at least 10-bit sub-pixel color depth, and is suitable for use in a display of 65 inches or larger. In this embodiment, the SSVT transmitter (540) is implemented in a single integrated circuit and there are 24 source drivers (586), each implemented in a single integrated circuit. Input to the transmitter (540) is made via CEDS (Clock Embedded Differential Signaling), and each has f up to 1,300 Msps. SSVT It outputs 24 wire pairs (592) (SSVT signals) having, and each input of each source driver is f with a maximum of 1,300 Msps. SSVT It is a single SSVT signal wire pair having, and each source driver outputs 960 columns. The optical characteristics of this embodiment are equivalent to those of a conventional LDP, such as color reproduction, brightness, contrast, and response time.

[0086] SSVT Transmitter Integration Example

[0087] Below are various embodiments illustrating different levels of integration between a GPU and an SSVT transmitter. These embodiments provide the advantages described above for various use cases, such as gameplay, home theaters, retail signage, outdoor signage, public displays, and television. In each of these embodiments below, the SSVT signal is generated outside the display unit and then transmitted to the source driver of the corresponding display unit to display video data on a display panel within the display unit. Compared to conventional digital video transmission technology, these embodiments provide up to 10 times the reach, 100 times the noise immunity, and use less power (depending on the level of integration).

[0088] FIG. 11 illustrates a GPU-to-the-Glass platform embodiment (800) in which the platform is a custom printed circuit board (802) that includes a current generation (or "legacy") GPU IC (804) as well as an SSVT transmitter IC (806). In this embodiment, the SSVT transmitter is not integrated within the GPU. Video data is received from a storage, camera, the Internet, etc. (808), processed by the GPU (804), and then converted and encoded into an SSVT signal (810) by the SSVT transmitter (806). This signal is then transmitted to a display unit (819) via an appropriate EM path (physical wire, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers (812-818), decoded, and displayed on a display panel as described above. The display unit may include any large format, high dynamic range, high frame rate, high resolution display as described above. This PCB-level integrated embodiment uses 20% less power compared to existing technology.

[0089] FIG. 12 illustrates a GPU-to-glass system-on-module (SoM) embodiment (820) in which the SoM (822) includes a current generation GPU IC (824) as well as an SSVT transmitter IC (826), and the IC may be a Known Good Die (KGD). In this embodiment, the SSVT transmitter is not integrated within the GPU. Video data is received from a storage, camera, the Internet, etc. (828) and processed by the GPU (824) before being converted and encoded into an SSVT signal (830) by the SSVT transmitter (826). This signal is then transmitted to a display unit (839) via any suitable EM path (physical wire, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers (832-838), then decoded as previously described, and displayed on a display panel. The display unit may include any large format, high dynamic range, high frame rate, high resolution display as described above. This higher level of integration embodiment uses 50% less power compared to existing technology.

[0090] FIG. 13 illustrates an enhanced GPU-to-the-glass embodiment (840) comprising an enhanced GPU (844) and an SSVT transmitter (846) fully integrated within the GPU die. Video data is received from a storage, camera, the Internet, etc. (848), processed by the GPU (844), and then converted and encoded into an SSVT signal (850) by the SSVT transmitter (846). This signal is then transmitted to a display unit (859) via any suitable EM path (physical wire, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers (852-858), decoded as previously described, and displayed on a display panel. The display unit may include any large format, high dynamic range, high frame rate, high resolution display as described above. This highest level of integration embodiment uses 60% less power than conventional technology. Additionally, the GPU has an SSVT transmitter integrated within the same silicon piece. Therefore, since all digital transmission takes place within a very short distance, the high data rate of a single chip is not very important.

[0091] SSVT Signal, Encoding and Decoding

[0092] As previously mentioned, various embodiments of the present invention disclose that an analog SSVT signal is used to transmit video information within (or to) a display unit, among other things, to eliminate the need for a DAC within a source driver. Techniques for encoding and decoding said signal are described below.

[0093] For the purposes of this disclosure, an electromagnetic signal (EM signal) is a variable represented as electromagnetic energy whose amplitude changes over time. An EM signal propagates from a transmitter terminal to a receiver terminal through an EM path, e.g., a pair of wires (or cables), free space (or wireless), and optical or waveguides (fiber). An EM signal can be characterized as either continuous or discrete in each of the two dimensions of time and amplitude. A "pure analog" signal is a continuous-time, continuous-amplitude EM signal, a "digital" signal is a discrete-time, discrete-amplitude EM signal, and a "sampled analog" signal is a discrete-time, continuous-amplitude EM signal. This disclosure discloses a new discrete-time, continuous-amplitude EM signal called a "spread-spectrum video transport (SSVT)" signal, which is an improvement over existing SSDS-CDMA signals. SSVT means transmitting electromagnetic signals through an EM path or a path using enhanced Spread-Spectrum Direct Sequence (SSDS) based modulation.

[0094] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies, including cellular phones. CDMA is an example of multiple access, allowing multiple transmitters to simultaneously transmit information over a single communication channel. In communication applications, the use of CDMA enables multiple users to share a specific frequency band without interference from other users. CDMA utilizes Spread Spectrum Direct Sequence (SSDS) encoding, which encodes each user's data using a unique code. By using unique codes, the transmissions of multiple users can be combined and transmitted without interference between users. At the receiving end, the same unique code is used for each user to demodulate the transmission and recover the data for each user individually.

[0095] SSVT signals differ from CDMA. When a stream of input video samples (e.g.) is received by an encoder, it is encoded by applying SSDS-based modulation to each of the multiple encoder input vectors to generate an SSVT signal. The SSVT signal is then transmitted through the transmission medium. At the receiving end, the incoming SSVT signal is decoded by applying corresponding SSDS-based demodulation to reconstruct the encoded samples. Consequently, unlike CDMA, which transmits data from multiple users to multiple receivers, the original stream of video samples, arranged in chronological order and containing color and pixel-related information, is transmitted from a single video source to a single video sink.

[0096] FIG. 14 illustrates a simplified example showing how signal samples, in this case analog values, are encoded within an encoder and then transmitted via an electromagnetic path. An input vector of N analog values ​​(902–908) representing the voltage of individual pixels within a video frame is shown. These voltages may represent the luminance of a monochrome image or the luminous intensity of a specific color value of a pixel, such as the R, G, or B color value of the pixel; that is, each value represents the amount of light detected or measured in a specified color space. Although pixel voltages were used in this example, this encoding technique can be used with voltages representing any of the various signals from sensors, such as LIDAR values, sound values, haptic values, aerosol values, etc., and the analog values ​​may represent other samples, such as current. Signal samples that are digital values ​​can also be encoded, and this digital encoding is described below. Additionally, although a single encoder and a single EM path are illustrated, embodiments of the present invention work well with multiple encoders, each transmitting via an EM path.

[0097] Preferably, the start signal sample voltage is generally higher than the encoded voltage of the SSVT signal. After encoding, the voltage range is generally 0 to 1V for efficiency, but other ranges are also possible. A lower voltage means lower power consumption and can be used in the future.

[0098] These voltages are typically taken from pixels in a specific order within a row of a frame, but other rules may be used to select and align these pixels. Regardless of which rules are used to select these pixels and order them for encoding, the same rules are used at the receiving end of the decoder to decode these voltages in the same order and then place those voltages into the resulting frame to which they belong. Similarly, if the frame is color and uses RGB, the rules at this encoder may be to encode all R pixel voltages first, followed by the G and B voltages, or for voltages (902-906) to represent the RGB values ​​of one pixel in the row and the next three voltages (908-912) to represent the RGB values ​​of the next pixel. Again, the same rules that this encoder uses to align and encode the voltages are used at the receiving end of the decoder. As long as the decoder uses the same rules, any specific rule (color value, row, etc.) may be used to order the analog values ​​(902-908). As described, any N analog values ​​(902-908) can be presented to be encoded at once using the codebook (920), which is limited only by the number of entries in the codebook.

[0099] As mentioned, the codebook (920) has N codes (932-938), and in this simple example, the codebook has 4 codes, which means that 4 analog values ​​(902-908) are encoded at once. A larger number of codes, e.g. 127 codes, 255 codes, etc., may be used, but for practical reasons such as circuit complexity, it is preferable to use a smaller number of codes. As is known in the art, the codebook (920) contains N mutually orthogonal codes, each of which has a length L, and in this example, L = 4. Generally, each code is an SSDS code, but as discussed herein, it does not necessarily have to be a diffusion code. As indicated, each code is divided into L time intervals (also called "chips"), and each time interval contains a binary value for the corresponding code. As illustrated in code representation (942), the code (934) can be represented in the traditional binary form "1100", but the same code can also be represented as "1 1 -1 -1" as shown in code representation (944) to make it easier to use when modulating values ​​as described below. The codes (932 and 936-938) can also be represented as (942 or 944). Each code of length L is not associated with another computing device (such as a telephone), another person, or another transmitter as is done in CDMA.

[0100] Accordingly, the following technique is used to transmit four analog values ​​(902-908) to a receiver (using the corresponding decoder) through a transmission medium (34). Each analog value is to be modulated by each chip within its corresponding code representation (944), for example, the value (902), i.e., .3, is modulated (948) sequentially over time by each chip within the code representation (944) of the code (932). The modulation (948) may be a multiplication operator. Thus, modulating .3 with the code (932) yields the series ".3, .3, .3, .3". When .7 is modulated with code (934), it becomes ".7, .7, -.7, -.7", the value "0" becomes "0, 0, 0, 0", and the value "1" becomes "1, -1, 1, -1". Generally, the first chip of each code modulates its corresponding analog value and then the next chip of each code modulates its analog value, but in the implementation, a specific analog value may be modulated by all chips of the code before moving to the next analog value.

[0101] For each time interval, the modulated analog values ​​are summed at (951) (recognized as vertical in this figure) to obtain analog output levels (952-958), for example, summing the modulated values ​​for these time intervals yields output levels of 2, 0, 0.6, and -1.4. These analog output levels (952-958) may be further normalized or amplified to match the voltage limit of the transmission line and may be transmitted sequentially over time when generated through the electromagnetic path (e.g., differential twisted pair) of the transmission medium (34). The receiver then receives the output levels (952-958) in that order and decodes them using the same codebook (920) using the inverse of the encoding scheme shown here. The resulting pixel voltages (902-908) may be displayed on the display frame of the receiver according to the rules used. Accordingly, the analog values ​​(902-908) are effectively synchronously encoded and transmitted through a single electromagnetic path in a sequential series (952-958) of L analog output levels. As illustrated and described herein, numerous encoders and electromagnetic paths may also be used. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0102] Preferably, even if using robust SSDS technology (e.g., spread code) causes a significant drop in bandwidth, the use of mutually orthogonal code, modulation of each sample by the corresponding code chip, summing, and parallel transmission of N samples using L output levels yields a significant bandwidth gain. Unlike traditional CDMA technology, which encodes binary numbers serially and then sums them, the present invention first modulates the entire sample (i.e., the entire analog or digital value rather than a single bit) at each chip of the corresponding code, and then sums these modulations at each time interval of the code to obtain the resulting analog voltage level for each specific time interval and utilizes the amplitude of the resulting waveform. It is these analog output levels that are transmitted through the transmission medium, rather than the binary representation. Furthermore, unlike CDMA technology, which allows multiple access by different people, different devices, or different sources and transmits to multiple sinks, the present invention facilitates the transmission of analog voltage from one video source to another video sink—that is, from endpoint to endpoint. Additionally, compression is not required to transmit the sample values.

[0103] FIG. 15 illustrates this new encoding technique applicable to signal samples that are digital values. Here, the digital values ​​(902'-908') are digital representations of voltages. Using different examples of voltages, the value (902') is "1101", the value (904') is "0011", the value (906') is "0001", and the value (908') is "1000". Each digital value is modulated (digitally multiplied) by "1" or "-1" according to the representation (944) of each code, that is, the chip of the code corresponding to the digital value to be modulated. Considering only the first time interval (940) of each code and adding the sign bit, the most significant bit (MSB), modulating "1101" results in "01101" (MSB "0" signifies a positive value), modulating "0011" generates "00011", modulating "0001" generates "00001", and modulating "1000" generates "01000". These modulated values ​​are indicated in the comments of the first time interval. (Although not indicated, modulating with a -1 chip generates a negative value that can be expressed in binary using a binary representation suitable for negative values.)

[0104] When summed digitally, these modulated values ​​in the first time interval generate the digital value 952' "011001" (again, the MSB is the sign bit), and the other digital value (954'-958') is calculated in the same way, although it is not shown in this example. Considering this summing of decimals, it can be confirmed that the sum of the modulated values ​​13, 3, 1, and 8 is 25. Although not shown in this example, additional MSBs are available for the resulting level (952'-958'), given that a sum can generally require more than 5 bits. For example, if the value (902'-908') is represented using 4 bits, the level (952'-958') can be represented using up to 10 bits if there are 64 codes (64 bits added log2). Alternatively, if 32 modulated values ​​are summed, 5 more bits will be added. The number of bits required for the output level will vary depending on the number of codes.

[0105] The output level (950') can first be normalized to the input requirements of the DAC and then sequentially fed to the DAC (959) to convert each digital value into a corresponding analog value for transmission through the EM path. The DAC (959) may be a MAX5857 RF DAC (including a clock that multiplies the PLL / VCO and a 14-bit RF DAC core, and may bypass the complex path to directly access the RF DAC core), and the bandpass filter and variable gain amplifier (VGA) are not shown. In some situations, the number of bits used for the level (950') is greater than the number allowed by the DAC (959); for example, the level (952') is represented as 10 bits, but the DAC (959) is an 8-bit DAC. In these situations, an appropriate number of LSBs are discarded, and the remaining MSBs are processed by the DAC without loss of visual quality of the resulting image on the display.

[0106] Preferably, after the entire digital value is modulated, these modulated digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary digit of a digital value and then sums these modulated bits to generate an output. For example, assuming each digital value has B bits, CDMA has a total of B*L output levels to transmit, whereas using this new digital (or analog) encoding technique has the advantage of having only a total of L output levels to transmit.

[0107] FIG. 16 shows the decoding of an analog input level encoded using the encoder of FIG. 14. As illustrated, L input levels (950) are received through a single electromagnetic path of a transmission medium (34). As described herein and mentioned above, a codebook (920) contains N orthogonal codes (932-938) to be used to decode the input levels (950) to produce an output vector of N analog values ​​(902-908), i.e., the same analog values ​​(902-908) previously encoded. To perform the decoding, as indicated by the vertical arrow, each input level (952-958) is modulated (961) by each chip of each code corresponding to a specific index of the output vector (902-908). Considering the modulation of levels (952-958) by the first code (932), such modulation produces a series of modulated values ​​"2, 0, 0.6, -1.4". The modulation of levels (952-958) by the second code (934) produces a series of modulated values ​​"2, 0, -0.6, 1.4". The modulation by the third code (936) produces "2, 0, -0.6, -1.4" and the modulation by the fourth code (938) produces "2, 0, 0.6, 1.4".

[0108] Next, as indicated by the horizontal arrow, each series of modulated values ​​is summed to generate one of the analog values ​​(902-908). For example, the first series is summed to generate the analog value "1.2" (which becomes ".3" after normalization using a scale of "4"). In a similar manner, the other three series of modulated values ​​are summed to generate the analog values ​​"2.8", "0", and "4", and after normalization, generate the output vector of the analog values ​​(902-908). Each code can modulate the input level and then sum the corresponding series, or all input levels can be modulated before each series is summed. Thus, the output vector of N analog values ​​(902-908) was transmitted in parallel using L output levels.

[0109] Although these examples do not illustrate the decoding of digital input levels, a person of ordinary skill in the art will understand from the above description that performing such decoding is simple when reading the encoding of digital values.

[0110] FIGS. 17a, 17b, and 17c illustrate that the encoder and decoder can operate on analog samples or digital samples, and various analog and digital encoders and decoders have been previously described above. As described above, there may be two or more EM paths, and thus, in some cases, there may be one or more encoder / decoder pairs and a corresponding number of DACs or ADCs.

[0111] FIG. 17a illustrates the use of an analog encoder and a corresponding analog decoder. The input to the analog encoder (900) is an analog sample (970) or a digital sample (971) converted into analog by a DAC (972) located in the analog encoder. In this way, the analog or digital sample reaching the analog encoder can be encoded for transmission through the electromagnetic path of the transmission medium (34). The analog decoder (900') decodes the encoded analog sample to generate an analog sample (970) for output. The analog sample (970) can be used as is or converted into a digital sample using an ADC (not shown).

[0112] FIG. 17b illustrates the use of a digital encoder and a corresponding analog decoder. The input to the digital encoder (901) is a digital sample (971) or an analog sample (970) that has been converted digitally by an ADC (973) located in the digital encoder. Since the encoder is digital, a DAC (959) located in the encoder converts the encoded sample into analog before transmitting it through an electromagnetic path. In this way, the analog or digital sample reaching the digital encoder can be encoded for transmission through an electromagnetic path of a transmission medium (34). An analog decoder (900') decodes the encoded analog sample to produce an analog sample (970) for output. The analog sample (970) can be used as is or converted into a digital sample using an ADC (not shown).

[0113] FIG. 17c illustrates the use of a digital decoder to decode an encoded analog signal that arrives via the electromagnetic path of a transmission medium (34). The encoded analog signal may be transmitted using the analog encoder or digital encoder described immediately above. An ADC (974) located in a digital decoder (976) receives the encoded analog samples transmitted via the electromagnetic path and converts the samples into digital. These encoded digital samples are decoded into digital samples (978) by the digital decoder (976) (corresponding to the value of the input vector of the sample that was originally encoded before being transmitted via the electromagnetic path). The digital samples (978) may be used as is or converted into analog samples using a DAC.

[0114] FIG. 18 shows a simulation (similar to an idealized oscilloscope trace) of an SSVT waveform (602) transmitted through an electromagnetic path after being output from an analog encoder (or after being digitally encoded and then converted by a DAC). The vertical scale is the voltage, and the horizontal scale is the 100 ps oscilloscope measurement time interval. Note that the SSVT signal (602) is an analog waveform rather than a digital signal (i.e., the signal does not represent binary numbers), and in this embodiment, it can transmit a voltage range from approximately -15 V to approximately +15 V. All analog waveforms are completely analog (or at least they may be completely analog). Also, the voltage is not limited to some maximum value, but high values ​​are not practical.

[0115] As previously explained, analog voltage levels are transmitted sequentially through an electromagnetic path, and each level is the sum of modulated samples over time intervals, such as the analog output levels (952-958) above or the digital output levels (952'-958') above (which then pass through a DAC). When transmitted, these output levels appear as waveforms such as waveform (602). In particular, voltage level (980) represents the sum of modulated samples over a specific time interval (i.e., output level). Using a simple example, sequential voltage levels (980-986) represent the transmission of four output levels. In this example, 32 codes are used, which means that 32 samples can be transmitted in parallel, and thus voltage levels (980-986) (followed by multiple subsequent voltage levels depending on the number of chips L in the code) form the parallel transmission of 32 encoded samples (e.g., pixel voltages of a video source). Following the transmission, the next set of L voltage levels of the waveform (602) represents the transmission of the next 32 samples. Generally, the waveform (602) represents encoding analog or digital values ​​into analog output levels and transmitting these levels at discrete time intervals to form a composite analog waveform.

[0116] Since all electromagnetic paths degrade the electromagnetic signal propagating through them due to phenomena such as attenuation, reflections caused by impedance mismatch, and attacker signal collisions, an error may always occur when measuring the input level at the receiving terminal in relation to the corresponding output level available at the transmitting terminal. Therefore, as is known in the art, scaling of the input level at the receiver (or normalization or amplification of the output level at the transmitter) may be performed for compensation. Additionally, due to process gain (i.e., due to an increase in L that increases electrical elasticity), the input level decoded at the decoder is normalized by a scaling factor using the code length to recover the transmitted output level, as is known in the art.

[0117] Detailed example of a decoder

[0118] FIG. 19 is a logic diagram for one of four decoders (780). The decoder (780) includes a differential amplifier (1092) and a sample and hold circuit (1094) arranged to receive, sample, and hold one of four differential EM level signals received through a transmission medium. Other types of circuits (receivers) configured to receive, sample, and hold the input EM level signal may also be used. The sampled EM level signal is N decoder track circuits (1096)(N n-1 Provided to each of N0). The sequencer controller (1098) provides the same SSDS chip to each of the N decoder track circuits (1096) applied to the transmitting side. Consequently, the sample output (N n-1 The samples (N0) are provided to the reconstruction bank (782). Since the same SSDS chip used at the transmitting side is used by each decoder track circuit (1096), the demodulated samples (N n-1 N0) is the same as before modulation at the transmitting side.

[0119] Each controller (1098) of the decoder (780) also generates a number of control signals, including a strobe signal, an End-of-Bank (EOB) signal, an aperture signal, and a framing signal. The EOB signal is provided to the reconstruction bank (782) and indicates the timing when the staging bank (786) is completely filled with samples. When this occurs, the EOB signal is asserted to the next reconstructed sample (N n-1 Both the decoder track (1096) and the staging bank (786) are emptied in anticipation of the next set of (1096) and (786). A gap control signal is provided to the sample-and-hold circuit (1094), and a framing signal is provided to the channel aligner (787) and the staging controller (789).

[0120] Referring to FIG. 20, there is a diagram of an exemplary decoder track circuit (1096). The decoder track circuit (1096) includes a multiplier section and an accumulator section. The multiplier section includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1-C1 on the first (positive) and second (negative) power rails. The accumulator section includes additional transistor pairs S4-S4, S5-S5, S6-S6, and S7-S7, an operational amplifier, and a pair of capacitors C1-C1 on the first (positive) and second (negative) power rails, respectively. F and C F Includes

[0121] For each demodulation cycle, a differential EM level signal pair is received at the first level input (level +) terminal and the second level input (level -) terminal. The differential EM level signal pair is demodulated in the multiplier section by conditionally inverting it by multiplying it by a positive (1) or negative (-1) value depending on the received SSDS chip value.

[0122] When the value of the SSDS chip is (+1), when clk 1 is activated, transistor pairs S1-S1 and S3-S3 are closed, and S2-S2 remains open. Consequently, the voltage values ​​of the first level input (level +) terminal and the second level input (level -) are transferred to and stored in two capacitors C1 and C1 on the positive and negative rails, respectively. That is, the input value is multiplied by (+1), and no inversion occurs.

[0123] When the value of the SSDS chip is -1, the S1-S1 switches are all turned off, whereas when clk 1 is activated, the S2-S2 and S3-S3 switches are all turned on. As a result, the voltage values ​​received at the positive (+) terminal and the negative (-) terminal are swapped. That is, the input voltage value provided to the first or positive terminal is stored in capacitor C1 on the lower negative rail, and the voltage value provided to the second or (-) terminal is stored in capacitor C1 on the upper positive rail. Accordingly, the voltage value received at the input terminal is inverted or multiplied by (-1).

[0124] When clk 1 is switched to the inactive state, C1 and the charge accumulated in C1 remain unchanged. When clk 2 is switched to the active state, transistor pairs S4-S4 are opened, and transistor pairs S5-S5 and S6-S6 are closed. The charge accumulated in capacitor C1 on the top or positive rail and C1 on the bottom or negative rail is supplied to the differential input of the operational amplifier. The output of the operational amplifier is the original + / - sample pair before encoding at the transmitting side.

[0125] The charge accumulated in the two capacitors C1 and C1 is transferred to capacitors CF and CF on the top or positive rail and bottom or negative rail, respectively, when Clk 2 is activated. For each demodulation cycle, the charge from capacitors C1 and C1 on the top and bottom rails is accumulated in the two capacitors CF and CF on the top and bottom rails, respectively. When both clk 1 and the EOB signal are activated, transistor pair S7-S7 are closed, shorting the plates of each capacitor CF and CF. Consequently, the accumulated charge is removed, and the two capacitors CF and CF are reset, preparing them for the next demodulation cycle.

[0126] Since each decoder (780) has N decoder track circuits (1096), N decoded or original + / - sample pairs are regenerated for each demodulation cycle. These N + / - sample pairs are provided to the reconstruction bank (782) and then to the staging bank (786). As a result, the original sample set is regenerated with original color content information (e.g., S=3 for RGB).

[0127] The decoder track (1096) reconstructs incoming level samples over a successive L cycle and demodulates each successive input level to a successive SSDS chip of the corresponding track code. The result of each of the L demodulations is accumulated in the feedback capacitor CF. If EOB is asserted while clk1 corresponds to the first demodulation cycle of the decoding cycle, CF is emptied after EOB and can start accumulating again at 0V or another reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the SSDS process gain and the better the electrical recovery of the SSVT signal transmission through the transmission medium. On the other hand, the higher the parameter L, the higher the frequency required for SSVT modulation application, which can degrade signal quality due to insertion loss caused by the transmission medium.

[0128] The previously described demodulation cycle is repeated repeatedly in each decoder. The final result is to recover a set of samples arranged in the original chronological order, each containing the original color content information (i.e., the S sample set).

[0129] Although the invention has been described in some detail for clarity of understanding, it will be apparent that specific changes and modifications may be made within the scope of the appended claims. Accordingly, the described embodiments should be taken as illustrative and not restrictive, and the invention should not be limited to the details provided herein but should be defined by the full scope of the following claims and their equivalents. Listing of embodiments of the present inventionEmbodiment 1. A video display unit comprising a display panel including a plurality of gate drivers and a plurality of source drivers, and a video signal transmitter that receives a video stream in a digital representation and encodes the video stream into a plurality of aligned sequences of analog levels to be transmitted to the source drivers through a transmission medium using modulation, wherein each of the source drivers is configured to receive one of the plurality of aligned sequences of analog levels representing the video stream through the transmission medium and to decode the analog levels using demodulation to generate a plurality of samples to be output from the output of each of the source drivers, and wherein the video stream is displayed on the display panel of the display unit. Embodiment 3. A video display unit according to Embodiment 1, further comprising an input port for receiving the aligned sequences of analog levels from an external display controller. Embodiment 4. A video display unit according to Embodiment 1, wherein each of the source drivers does not include a digital-to-analog converter for the purpose of converting digital pixel data into analog pixel data. Embodiment 5. A video display unit according to Embodiment 1, further comprising a plurality of decoders—the number of decoders being equal to the number of electromagnetic paths used to transmit the analog level through the transmission medium to the source driver. Embodiment 6. A video display unit according to Embodiment 1, wherein the video signal transmitter is implemented as an integrated circuit separate from the video processor. Embodiment 7. A video display unit according to Embodiment 1, wherein the video signal transmitter is implemented as a system on module together with the video processor. Embodiment 8. A video display unit according to Embodiment 1, wherein the video signal transmitter is integrated within the video processor. Embodiment 9.A video display unit in embodiment 1, wherein at least one of the source drivers extracts a gate driver control signal from the analog level and outputs the gate driver control signal to the plurality of gate drivers, and is arranged to synchronize the output of each of the source drivers with the gate drivers. Embodiment 10. A video display unit in embodiment 1, wherein each of the source drivers includes a decoder that decodes each of the series of the analog level into an output vector of N analog samples by referring to a designated code set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the samples, and each of the series has L analog levels, and L >= N >= 2; a buffer arranged to collect the output vector of N analog samples from the decoder and output the output vector of N analog samples in parallel; and a plurality of amplifiers arranged to amplify the analog samples of the output vector and output each of the analog samples to a column of a display panel. Embodiment 11. A source driver comprising: a receiver arranged to receive a plurality of aligned series of L analog input values ​​from an electromagnetic path; a decoder that decodes each of the series of L analog input values ​​into an output vector of N analog samples by referring to a designated set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the analog samples, and L >= N >= 2; a buffer arranged to collect the output vector of each of the N analog samples from the decoder and output the output vector of each of the N analog samples in parallel; and a plurality of amplifiers arranged to amplify the analog samples of the output vector and output each of the analog samples to a column of a display panel. Embodiment 12.A source driver in embodiment 11, wherein the designated code set is the same as the code set used to encode the aligned series of L analog input values. Embodiment 13. A source driver in embodiment 11, wherein the plurality of aligned series of L analog input values ​​is received from a transmitter within a display unit including the display panel. Embodiment 14. A source driver in embodiment 11, wherein the plurality of aligned series of L analog input values ​​is received from a transmitter outside the display unit including the display panel. Embodiment 15. A source driver in embodiment 11, wherein the source driver does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data into analog pixel data. Embodiment 16. In Embodiment 11, the source driver wherein the display panel comprises C columns, the aligned series of L analog input values ​​is received serially at frequency freq(SSVT), each of the output vectors of N analog samples is output from the decoder at frequency freq(sample) = freq(SSVT) / N, and the buffer outputs the output vectors of N analog samples in parallel at frequency freq(line) = freq(sample) × N / C. Embodiment 17.In embodiment 11, each of the N codes is indexed, and the source driver further comprises: a set of N 2-input correlators—each correlator is associated with one of the N positions of the output vector, and each correlator has a value of an aligned series of L input values ​​as one input and a corresponding value within the code associated with one of the N positions as another input— and a set of N 2-input summing circuits—each summing circuit is associated with one of the N positions, and each 2-input summing circuit has an output of a corresponding 2-input correlator as one input and a content of a corresponding output vector position as another input. Embodiment 18. In embodiment 11, the aligned series of L analog input values ​​is received serially at the receiver, and each output vector of N analog samples is output in parallel from the decoder. Embodiment 19. A source driver arranged to receive a plurality of aligned series of L analog input values ​​from an electromagnetic path. A source driver comprising: a receiver; a decoder that decodes each of the series of L analog input values ​​into an output vector of N analog samples by referring to a designated code set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the analog samples, and L >= N >= 2; a plurality of amplifiers arranged to amplify each of the analog samples of each of the output vectors and output each of the output vectors; and a buffer arranged to collect each of the output vectors of each of the N analog samples from the amplifiers and output each of the analog samples in parallel to a column of a display panel. The source driver of claim 20 embodiment 19, wherein the designated code set is the same as the code set used to encode the aligned series of L analog input values. Embodiment 21.In embodiment 19, the source driver, wherein the plurality of aligned series of L analog input values ​​is received from a transmitter within a display unit including the display panel. Embodiment 22. In embodiment 19, the source driver, wherein the plurality of aligned series of L analog input values ​​is received from a transmitter outside the display unit including the display panel. Embodiment 23. In embodiment 19, the source driver does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data into analog pixel data. Embodiment 24. In Embodiment 19, the source driver wherein the display panel comprises C columns, the aligned series of L analog input values ​​is received serially at frequency freq(SSVT), each of the output vectors of N analog samples is output from the decoder at frequency freq(sample) = freq(SSVT) / N, and the buffer outputs the output vectors of N analog samples in parallel at frequency freq(line) = freq(sample) × N / C. Embodiment 25. In Embodiment 19, each of the N codes is indexed, and the source driver comprises a set of N 2-input correlators - each correlator is associated with one of the N positions of the output vector, and each correlator has a value of the aligned series of L input values ​​as one input and a corresponding value within the code associated with one of the N positions as another input - and a set of N 2-input summing circuits - each summing circuit is among the N positions A source driver further comprising, in association with the above one, wherein each 2-input summing circuit has the output of a 2-input correlator corresponding to one input and the other input has the contents of a corresponding output vector position. Embodiment 26.In embodiment 19, the aligned series of L analog input values ​​is received serially at the receiver, and each output vector of N analog samples is output in parallel from the decoder, a source driver.

Claims

Claim 1 A video display unit comprising a display panel including a plurality of gate drivers and a plurality of source drivers, and a video signal transmitter that receives a video stream as a digital representation and encodes the video stream into a plurality of aligned sequences of analog levels to be transmitted to the source drivers through a transmission medium using modulation, wherein each of the source drivers is configured to receive one of the plurality of aligned sequences of analog levels representing the video stream through the transmission medium and to decode the analog levels using demodulation to generate a plurality of samples to be output from the output of each of the source drivers, and wherein the video stream is displayed on the display panel of the display unit. Claim 2 delete Claim 3 A video display unit according to claim 1, further comprising an input port for receiving the aligned sequence of analog levels from an external display controller. Claim 4 A video display unit according to claim 1, wherein each of the source drivers does not include a digital-to-analog converter for the purpose of converting digital pixel data into analog pixel data. Claim 5 A video display unit according to claim 1, further comprising a plurality of decoders—the number of decoders being equal to the number of electromagnetic paths used to transmit the analog level through the transmission medium to the source driver. Claim 6 A video display unit, wherein the video signal transmitter is implemented as an integrated circuit separate from the video processor in the first paragraph. Claim 7 In claim 1, the video signal transmitter is a video display unit implemented as a system on module together with a video processor. Claim 8 In paragraph 1, the video signal transmitter is a video display unit integrated within a video processor. Claim 9 A video display unit according to claim 1, wherein at least one of the source drivers extracts a gate driver control signal from the analog level and outputs the gate driver control signal to the plurality of gate drivers, so as to synchronize the output of each of the source drivers with the gate drivers. Claim 10 A video display unit according to claim 1, wherein each of the source drivers comprises a decoder that decodes each of the series of analog levels into an output vector of N analog samples by referring to a designated code set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the samples, and each of the series has L analog levels, and L >= N >= 2; a buffer arranged to collect the output vector of N analog samples from the decoder and output the output vector of N analog samples in parallel; and a plurality of amplifiers arranged to amplify the analog samples of the output vector and output each of the analog samples to a column of a display panel. Claim 11 A source driver comprising: a receiver arranged to receive a plurality of aligned series of L analog input values ​​from an electromagnetic path; a decoder that decodes each of the series of L analog input values ​​into an output vector of N analog samples by referring to a designated set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the analog samples, and L >= N >= 2; a buffer arranged to collect the output vector of each of the N analog samples from the decoder and output the output vector of each of the N analog samples in parallel; and a plurality of amplifiers arranged to amplify the analog samples of the output vector and output each of the analog samples to a column of a display panel. Claim 12 In paragraph 11, the source driver, wherein the specified code set is the same as the code set used to encode the aligned series of L analog input values. Claim 13 In paragraph 11, the plurality of aligned series of L analog input values ​​is a source driver received from a transmitter within a display unit including the display panel. Claim 14 In paragraph 11, the plurality of aligned series of L analog input values ​​is a source driver received from a transmitter outside the display unit including the display panel. Claim 15 In claim 11, the source driver is a source driver that does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data into analog pixel data. Claim 16 A source driver according to claim 11, wherein the display panel comprises C columns, the aligned series of L analog input values ​​is received serially at frequency freq(SSVT), each of the output vectors of N analog samples is output from the decoder at frequency freq(sample) = freq(SSVT) / N, and the buffer outputs the output vectors of N analog samples in parallel at frequency freq(line) = freq(sample) × N / C. Claim 17 In claim 11, each of the N codes is indexed, and the source driver further comprises: a set of N 2-input correlators—each correlator is associated with one of the N locations of the output vector, and each correlator has a value of an ordered series of L input values ​​as one input and a corresponding value within the code associated with one of the N locations as another input— and a set of N 2-input summing circuits—each summing circuit is associated with one of the N locations, and each 2-input summing circuit has the output of the corresponding 2-input correlator as one input and the contents of the corresponding output vector location as another input. Claim 18 In paragraph 11, the source driver wherein the aligned series of L analog input values ​​is received serially at the receiver, and each output vector of N analog samples is output in parallel from the decoder. Claim 19 A source driver comprising: a receiver arranged to receive a plurality of aligned series of L analog input values ​​from an electromagnetic path; a decoder that decodes each of the series of L analog input values ​​into an output vector of N analog samples by referring to a designated set of N mutually orthogonal codes of length L, wherein each of the N codes is associated with one of the analog samples, and L >= N >= 2; a plurality of amplifiers arranged to amplify each of the analog samples of each of the output vectors and output each of the output vectors; and a buffer arranged to collect each of the output vectors of each of the N analog samples from the amplifiers and output each of the analog samples in parallel to a column of a display panel. Claim 20 In paragraph 19, the source driver, wherein the specified code set is the same as the code set used to encode the aligned series of L analog input values. Claim 21 In paragraph 19, the plurality of aligned series of L analog input values ​​is a source driver received from a transmitter within a display unit including the display panel. Claim 22 In paragraph 19, the plurality of aligned series of L analog input values ​​is a source driver received from a transmitter outside the display unit including the display panel. Claim 23 In claim 19, the source driver is a source driver that does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data into analog pixel data. Claim 24 In claim 19, the source driver, wherein the display panel comprises C columns, the aligned series of L analog input values ​​is received serially at frequency freq(SSVT), each of the output vectors of N analog samples is output from the decoder at frequency freq(sample) = freq(SSVT) / N, and the buffer outputs the output vectors of N analog samples in parallel at frequency freq(line) = freq(sample) × N / C. Claim 25 In claim 19, each of the N codes is indexed, and the source driver further comprises: a set of N 2-input correlators—each correlator is associated with one of the N locations of the output vector, and each correlator has, as one input, a value of an aligned series of L input values ​​and as another input, a corresponding value within the code associated with one of the N locations—and a set of N 2-input summing circuits—each summing circuit is associated with one of the N locations, and each 2-input summing circuit has, as one input, the output of the corresponding 2-input correlator and as another input, the content of the corresponding output vector location. Claim 26 In paragraph 19, the source driver wherein the aligned series of L analog input values ​​is received serially at the receiver, and each output vector of N analog samples is output in parallel from the decoder.

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