System and method for controlling the order of instruction execution by a target device

Abstract

A method for executing commands in a limited order according to an embodiment of the present invention may include the steps of: a host sending a first command and transmitting a second command in sequence by a sequence limiting command; a target receiving the first command, the sequence limiting command, and the second command; and the target executing the first command, executing the sequence limiting command after executing the first command, and executing the second command after executing the sequence limiting command.

Description

Technology Field

[0001] The present invention relates to communication between a host and a target, and more specifically, to a system and method for controlling the order of command execution by a target. Background Technology

[0002] In a specific system where a host sends commands to a target, it can be advantageous to ensure that specific commands are executed by the target in an order that follows the execution order restrictions specified by the host.

[0003] In such a system, a system and method are required to control the order of instruction execution by a target. The information disclosed above in the background section is intended to aid in understanding the background technology of the present disclosure and may include information that does not constitute prior art. The problem to be solved

[0004] The present invention aims to solve the aforementioned technical problem, and the objective of the present invention is to provide a system and method for controlling the instruction execution order by a target. means of solving the problem

[0005] In some embodiments, the host may be connected to the target (e.g., a persistent storage device) via a transport interconnect (e.g., an expander) that provides multiple paths from the host to the target. The expander may be a hub or a switch that allows multiple persistent storage devices (e.g., solid-state drives (SSDs)) to be connected to a single host interface. The latency of each path may be variable, for example, as a result of a first-in-first-out (FIFO) storage structure or a buffering mechanism of the transport interconnect. The host may transmit a command, which may be referred to as a "fence" in some cases. This command is to be executed by the target after all commands previously sent by the host and before any subsequent commands transmitted by the host. There may not be a mechanism for the host to identify to the target which commands must precede each fence and which commands must follow each fence. Therefore, it may not be feasible to determine whether constraints on the order of execution must be observed from a series of commands received by the target in an order different from the order in which they were transmitted.

[0006] In some embodiments, the target may transmit an acknowledgment upon receiving any command. The target may create entries in the command ordering FIFO in the same order as the transmission of acknowledgments. The target may continue to receive and simultaneously execute commands with a slight delay between reception and execution, and the commands may be executed in the order in which their corresponding entries were created in the command ordering FIFO. In such embodiments, the host may wait until it has received all acknowledgments for commands preceding the fence. After transmitting the fence, the host may wait until it has received an acknowledgment for the fence before transmitting commands following the fence. This process verifies that the order of entries in the command ordering FIFO complies with the execution order constraint for the fence. Because the target executes commands in the same order as their corresponding entries in the command ordering FIFO, it may also verify that the order in which commands are executed complies with the execution order constraint for the fence.

[0007] A method for executing commands in a limited order according to an embodiment of the present invention may include the steps of: a host sending a first command and transmitting a second command in sequence by a sequence limiting command; a target receiving the first command, the sequence limiting command, and the second command; and the target executing the first command, executing the sequence limiting command after executing the first command, and executing the second command after executing the sequence limiting command.

[0008] As an example embodiment, the method further includes the step of the target sending a plurality of corresponding approvals to the host, wherein the approvals include approval for the first command, approval for the order restriction command, and approval for the second command, and the step of the target receiving the first command, the order restriction command, and the second command includes the target executing the first command, the order restriction command, and the second command in the same order as the target sending the corresponding approvals, and the step of the host transmitting the first command, the order restriction command, and the second command may include the host transmitting the order restriction command after the host receives approval for the first command, and the host transmitting the second command after the host receives approval for the order restriction command.

[0009] As an example of an embodiment, the target may be a solid-state drive.

[0010] As an example, the host is connected to the target via a SCSI connection, and each command may be a SCSI command or a SCSI job management function.

[0011] As an example, the SCSI connection may be a Wide Serial Attached SCSI (SAS) connection.

[0012] As an example of an embodiment, the host may be connected to the target through a transmission interconnect.

[0013] As an example of an embodiment, the method may further include the step of transmitting a third command after the host transmits the first command and before transmitting the sequence restriction command.

[0014] As an example of an embodiment, the method may further include the step of the target receiving the third command before the target receives the first command.

[0015] As an example of an embodiment, the target may further include the step of transmitting approval for the third command to the host before the target transmits approval for the first command to the host.

[0016] As an example of an embodiment, the method may further include the step of the target executing the third instruction before the target executes the first instruction.

[0017] A system including a target according to an embodiment of the present invention is configured such that the target includes a processing circuit, and the processing circuit receives a first command; transmits an acknowledgment for the first command; executes the first command; receives a second command; transmits an acknowledgment for the second command; and executes the second command, and the execution of the first command and the execution of the second command may be performed in the same order as transmitting an acknowledgment for the first command and transmitting an acknowledgment for the second command. As an example of an embodiment, the target includes an instruction ordering FIFO, and the processing circuit is further configured to create a first entry corresponding to the first instruction in the instruction ordering FIFO and a second entry corresponding to the second instruction in the instruction ordering FIFO, and the first entry and the second entry may be in the same order as transmitting an acknowledgment for the first instruction and transmitting an acknowledgment for the second instruction in the instruction ordering FIFO.

[0018] As an example of an embodiment, the target may be a solid-state drive.

[0019] As an example of an embodiment, the target may have a serial-attached SCSI interface.

[0020] As an example, the target further comprises a first port, a second port, and an arbitrator circuit, and the arbitrator circuit may be configured to receive an entry corresponding to a command from the first port and the second port and to create a corresponding entry in the command ordering FIFO.

[0021] As an example, the target is a permanent storage device having a wide serial attached SCSI interface; the first port is a port of the wide serial attached SCSI interface; and the second port may be a port of the wide serial attached SCSI interface.

[0022] As an example of an embodiment, the system further includes a host connected to the target, wherein the host includes a processing circuit, and the processing circuit of the host may be configured to transmit the first command to the target, receive an acknowledgment for the first command, and transmit a sequence restriction command to the target after receiving the acknowledgment for the first command.

[0023] As an example, the processing circuit of the target may be further configured to receive the sequence restriction command and transmit an acknowledgment for the sequence restriction command, and the processing circuit of the host may be further configured to transmit the second command after receiving the acknowledgment for the sequence restriction command.

[0024] As an example, the host is connected to the target via a SCSI connection, and each command may be a SCSI command or a SCSI job management function.

[0025] A system including a target according to an embodiment of the present invention, wherein the target includes a processing means, and the processing means is configured to receive a first command; transmit an acknowledgment for the first command; execute the first command; receive a second command; transmit an acknowledgment for the second command; and execute the second command, and the execution of the first command and the execution of the second command may be performed in the same order as transmitting an acknowledgment for the first command and transmitting the second command. Effects of the invention

[0026] A system and method for controlling the instruction execution order by a target device according to an embodiment of the present invention controls the instruction execution order by the target, thereby enabling a specific instruction to be executed by the target in an order that follows the execution order restriction specified by the host. Brief explanation of the drawing

[0027] The features and advantages of the present invention may be interpreted and understood by referring to the specification, claims and the attached drawings. FIG. 1a is a block diagram exemplarily showing a target (e.g., a target device such as a permanent storage device) connected to a host according to one embodiment of the present invention. FIG. 1b is a block diagram exemplarily showing a target connected to a host through a transmission interconnect according to one embodiment of the present invention. FIG. 2 is a time sequence diagram exemplarily showing commands and acknowledgments transmitted between a host and a target according to an embodiment of the present invention. FIG. 3 is a block diagram exemplarily showing a part of a target according to one embodiment of the present invention. FIG. 4 is a flowchart illustrating an exemplary method for transmitting commands and acknowledgments between a host and a target according to an embodiment of the present invention. Specific details for implementing the invention

[0028] The detailed description below, in connection with the attached drawings, is intended to describe exemplary embodiments of a system and method for controlling the order of instruction execution by a target provided according to the present invention, and is not merely intended to indicate forms in which the present invention may be configured or utilized. This specification describes the features of the present invention in connection with the illustrated embodiments. However, it should also be understood that identical or equivalent functions and structures may be achieved by other embodiments intended to be included within the spirit and scope of the present invention. As indicated elsewhere in this specification, identical component reference numbers are intended to indicate identical components or features.

[0029] In Small Computer System Interface (SCSI, SAS) protocols, a host can transmit commands and task management functions (collectively referred to as “commands”) to a target. Additionally, the host can sometimes send commands known as “task management functions” to the target (105). Each task management function can act as a fence or an “order-constrained instruction.” The terms “fence” and “order-constrained instruction” may be used interchangeably herein. Execution order constraints may be applied to the execution of order-constrained instructions (i.e., task management functions). Such execution order constraints may require that all commands transmitted prior to the order-constrained instruction be executed before the order-constrained instruction is executed. Execution order constraints may also require that the order-constrained instruction be executed before any commands transmitted after the order-constrained instruction is executed.

[0030] As an example, the host and the target may handle the transmission and execution of commands in a manner that ensures compliance with execution order constraints, without informing the target of (i) which command is a fence, (ii) which command was transmitted before the fence, and iii) which command was transmitted after the fence. This may be done as follows: The target may send an acknowledgment upon receiving any command. Before command execution begins, the target may enter an entry for each command in the order of the command in a First-in First-Out (FIFO) structure. This may be done in the same order as the acknowledgment is transmitted. The target may continue to receive and execute commands with a slight delay between reception and execution. Commands may be executed in the order in which the corresponding entries were created in the commands placed in the FIFO. As an example, the host may wait until it has received all acknowledgments for commands preceding the fence. And after sending the fence, it may wait until it has received an acknowledgment for the fence before sending commands following the fence. This process can verify whether the entry order of the FIFO ordering command complies with the execution order constraints for the fence. Because the target executes the command in the same order as the corresponding entry order of the command ordering, the FIFO can also verify whether the order in which the command is executed complies with the execution order constraints for the fence. Some embodiments of this specification describe a system and method for controlling the command execution order by a target in the context of a host and a target connected by a SAS link or connected by a SAS link through a SAS expander. However, the invention is not limited to these embodiments and may relate to any situation in which the command execution order by the target (105) is generally controlled. For example, some embodiments may operate in conjunction with any other suitable standard or independently.

[0031] Referring to FIG. 1a, as an embodiment, a target (105) is connected to a host (110) by a 2-wide SAS connection. In this embodiment, the target (105) and the host (110) are connected by two data links, each of which can be used by the host (110) to transmit commands to the target (105). The latencies of the links may vary, for example, because each port interface of the host (110) may include a FIFO for buffering commands, and the fullness of such FIFO may vary as commands are added and removed by the host (110) as they are transmitted. Thus, the order in which commands are received by the target (105) may differ from the order in which they are added to a queue by the host (110) for transmission to the target (105).

[0032] Similarly, in the embodiment of FIG. 1b, two targets (105) are connected to a host (110) via a transmission interconnect (115) (e.g., a SAS expander) by a wide SAS connection. There may be additional variability in the delay between the enqueueing of an instruction by the host (110) and the receipt of the instruction by the target (105) to which it is sent. This is because, for example, the transmission interconnect (115) may also include a FIFO, and the fullness of such a FIFO varies and may cause a change in the delay experienced by any instruction when traversing the FIFO.

[0033] Partially for this reason, commands sent from the host (110) may be received out of order; that is, received in a different order than the order in which they were sent. FIG. 2 shows a timeline of events for transmitting seven commands. The timeline of events includes, for example, a sequence restriction command (or "fence"), which is command 4. In the example of FIG. 2, the host (110) transmits a first plurality of instructions containing three commands in order (i.e., order 1, 2, 3), which are received by the target (105) in order (order 1, 3, 2). When moving from the host (110) to the target (105), the third command may be received before the second command. As illustrated in FIG. 2, variable latency within the host (110) may be assumed not to reorder commands for simplicity, allowing commands to be sent by the host (110) in the order in which they are included in the queue. After receiving each command, the target (105) may send an acknowledgment ("Ack") to the host (110) and create an entry in the instruction ordering FIFO. The acknowledgment is sent in the same order in which the entry was created in the instruction ordering FIFO. Then, the target (105) may proceed with the execution of the command. Execution may potentially occur much later than reception and may be executed in the same order in which the corresponding entry was added to the instruction ordering FIFO. This is the same order in which acknowledgments are sent.

[0034] The host (110) may transmit instruction 4, which is an order-constrained instruction, only after receiving all acknowledgments for previously transmitted instructions (instructions 1, 2, and 3). In the example of FIG. 2, acknowledgments may be received in reverse order, i.e., in the order A3, A2, and A1. Both acknowledgments A2 and A3 may overtake acknowledgment A1 while returning to the host (110). The host (110) may send instruction 4, which is an order-constrained instruction, before instruction 2 is executed. Nevertheless, instruction 4 may be executed after instruction 2. This is because, for the host (110) that has received an acknowledgment for instruction 2, it means that an entry for instruction 2 is already in the instruction ordering FIFO. Therefore, when instruction 4 is received by the target (105), the corresponding entry in the instruction ordering FIFO will necessarily be after the entry for instruction 2. Thus, instruction 4 will be executed later than instruction 2 and will be subject to execution order constraints. The same reasoning can be applied to instructions 1 and 3. The entries for each of these two instructions are already in the instruction ordering FIFO when the host (110) sends instruction 4, which is an execution order constraint instruction. This can be verified by the reception of the corresponding acknowledgments A1 and A3 by the host (110). (i) It is certain that the entry for instruction 4 will be after the entry for instruction 4 in the instruction ordering FIFO.Therefore, (ii) it is certain that instruction 4 will be executed after instruction 1 and after instruction 3.

[0035] Likewise, the host (110) waits for the receipt of an acknowledgment for command 4 before transmitting one of the subsequent commands 5, 6, and 7. This ensures that an entry for command 4 is in the command ordering FIFO before any of the subsequent commands 5, 6, and 7 are transmitted. Thus, command 4 will be executed before any of the subsequent commands 5, 6, and 7. This is also the case when some of the subsequent commands 5, 6, and 7 are transmitted through the host (110), even if command 4 has not yet been executed. This is equivalent to command 5 being transmitted before command 4 is executed, as seen in the example of FIG. 2.

[0036] In some embodiments, compliance with execution order constraints may be ensured even if the target (105) does not guarantee that the entries corresponding to the acknowledgments are transmitted in the order created in the command ordering FIFO under all circumstances. For example, if there is a difference of a first time interval t for two commands received almost simultaneously, the order of entries in the command ordering FIFO may differ from the order in which the acknowledgments for each row were transmitted. Nevertheless, if t is less than T, which is the minimum round-trip time from the host (110) to the target (105), the aforementioned system and method are reliable. For example, if command 4 is transmitted immediately upon receiving acknowledgment A1, command 4 may be received by the target (105) later than command 1 by at least a time interval T greater than t. For this reason, it would be highly desirable that the entry for command 4 is not placed before the entry for command 1 in the command ordering FIFO.

[0037] FIG. 3 is a block diagram showing a portion of a target having a wide serial attached SCSI interface as an example. The target (105) may have a first port (305) which is a port of the wide serial attached SCSI interface and a second port (310) which is a port of the wide serial attached SCSI interface. When operating, the first port (305) receives a command from the host (110) via the wide SAS interface (315). Each received command is stored in a first buffer (320) (e.g., a circular buffer) upon receipt. When a complete command is received, the first port (305) performs a validation (e.g., a cyclic redundancy check (CRC)). If the first port (305) determines that the received command is valid (e.g., that no bit errors occurred during transmission), it sends an acknowledgment of the command back to the host (110). It sends an entry (e.g., a FIFO entry) corresponding to the command to the arbitrator (330). For example, the entry may be a pointer to the location where the instruction is stored in the first buffer (320).

[0038] The second port (310) can operate in the same manner as the first port (305). It can store commands in the second buffer (335) and cause the arbitrator (330) to create an entry in the command ordering FIFO pointing to the second buffer (335). The arbitrator (330) can determine the order in which the entry for the command ordering FIFO can be placed within the command ordering FIFO. For example, the arbitrator (330) can create entries in the command ordering FIFO (325) in the order received from either the first port (305) or the second port (310). And for the simultaneously received entries, it can take an action selected from a list that is included but not limited to the following actions. (i) the entry received from the first port (305) may be placed first in the command ordering FIFO, (ii) the entry received from the second port (310) may be placed first in the command ordering FIFO, (iii) the entry may be placed alternately between the first port (305) and the second port (310), or (iv) one or the other of the first port (305) and the second port (310) may be selected based on a pseudo-random number.

[0039] The command handler (340) can sort the execution of commands in the first buffer (320) and the second buffer (335) one at a time by reading entries from the command ordering FIFO (325). For each entry, the corresponding command can be executed. For example, the command pointed to by the entry can be executed. The embodiment of FIG. 3 cannot guarantee all situations. It cannot be guaranteed that acknowledgments are transmitted in all situations in the order in which the commands in the row were created in the command ordering FIFO. For example, if the first port (305) and the second port (310) simultaneously determine that their respective received commands are valid (e.g., during the same clock cycle), they may send their acknowledgments simultaneously. On the other hand, the arbitrator (330) must place one entry in the command ordering FIFO before another entry. In some embodiments, to avoid this limitation, each port may wait for acknowledgment from the arbitrator (330) before transmitting an acknowledgment. Here, consent may be provided only after the relevant entry has been created within the instruction ordering FIFO. In such an embodiment, the requirement that T is greater than t may be eliminated.

[0040] FIG. 4 is a flowchart illustrating, as an example, a method for controlling the execution order of commands by a target (105). At 405, the host (110) transmits a first command to the target (105). At 410, the target (105) receives the first command. At 415, the target (105) transmits an acknowledgment for the first command to the host (110). At 420, the host (110) receives an acknowledgment for the first command from the target (105). At 425, the host (110) transmits a sequence restriction command (i.e., a fence command) to the target (105). The host (110) may transmit the sequence restriction command only after receiving an acknowledgment for the first command from the target (105) at 420. At 430, the target (105) receives the sequence restriction command (i.e., a fence command). At 435, the target (105) transmits an acknowledgment for a sequence restriction command (i.e., a fence acknowledgment) to the host (110). At 440, the host (110) receives an acknowledgment for a sequence restriction command (i.e., a fence acknowledgment) from the target (105). At 445, the host (110) transmits a second command to the target (105). The host (110) may transmit the second command only after receiving it. At 450, the target (105) receives the second command. At 455, the target (105) transmits an acknowledgment for the second command to the host (110). At 460, the host (110) receives an acknowledgment for the second command from the target (105).

[0041] Each of the host (110) and the target (105) may include a processing circuit for performing the method described herein. The term “processing circuit” is used herein to mean any combination of hardware, firmware, and software used to process data or digital signals. Processing circuit hardware may include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable logic devices (FPGAs). In the processing circuit, as used herein, each function is performed by hardware configured to perform that function, namely by hard-wired, or by more general hardware such as a CPU configured to execute instructions stored in a temporary storage medium. The processing circuit may be manufactured on a single printed circuit board (PCB) or distributed across multiple interconnected PCBs. The processing circuit may include other processing circuits. For example, the processing circuit may include two processing circuits, an FPGA, and a CPU interconnected on a PCB.

[0042] For example, in any system diagram included in this specification, any described component or any combination of components may be used to perform one or more of the operations of any flowchart included herein. Additionally, (i) the operations are exemplary and may include various additional steps not explicitly covered, and (ii) the chronological order of the operations may be changed.

[0043] As used herein, "part" of something means "at least part" of an object, and thus may mean all or less than all of the object. Accordingly, "part" of an object may include the whole object as a special case. That is, the whole object may be an example of a part of an object.

[0044] As used herein, the term “array” means a series of numbers designated in order, regardless of the storage method (e.g., whether stored in contiguous memory locations or in a linked list). The term “rectangle” as used herein includes a square in special cases. That is, a square is an example of a rectangle. As used herein, it may be said that the first rectangle “includes” the second rectangle when no part of the second rectangle is outside the first rectangle. Thus, when the first rectangle is identical to the second rectangle and the first rectangle is in the same location as the second rectangle, the first rectangle includes the second rectangle and the second rectangle includes the first rectangle. As used herein, when a first quantity (e.g., a first array) is referred to as being “based” on a second quantity (e.g., a second array), this means that the second quantity influences the first quantity, e.g., the second quantity. The first quantity may be an input to a function that calculates the first quantity (e.g., a single input or one of multiple inputs), the first quantity may be the same as the second quantity, or the first quantity may be stored, for example, in the same location or memory location as the second quantity.

[0045] The term "or" as used in this specification shall be interpreted as "and / or," for example, "A or B" means any one of "A" or "B" or "A and B".

[0046] Although terms such as first, second, third, etc. are used herein to describe various elements, components, regions, layers, and / or sections, it will be understood that these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Accordingly, the first component, component, region, layer, or section described below may refer to the second component, component, region, layer, or section without departing from the spirit and scope of the invention.

[0047] The terms used in the description of the technical concept of the present invention are used solely for the purpose of describing specific embodiments and are not intended to limit the technical concept of the present invention. As used herein, terms such as “generally,” “about,” and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for inherent variations in measured or calculated values ​​identified by those skilled in the art of the present invention.

[0048] As used herein, unless the context clearly indicates otherwise, the singular form “one” is intended to include the plural form. When the terms “comprising” and / or “comprising” are used herein, it will be more understood that these terms specify the presence of defined features, integers, steps, actions, elements, and / or components, but do not make possible the addition or presence of one or more other features, integers, steps, actions, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the listed entries. Expressions such as “at least one,” when preceding a list of components, modify the entire list of elements and do not modify the individual elements of the list. Additionally, when describing embodiments of the invention, the use of “may” means “one or more embodiments of the invention.” Also, the term “exemplar” means example or figure. As used herein, the terms “use,” “used,” and “used” may each be considered synonyms for the terms “utilization,” “used,” and “used.”

[0049] When an element or layer is referred to as being "on top of," "connected to," "combined to," or "adjacent to" another element or layer, it may be directly on top of, connected to, combined to, or adjacent to the other element or layer, or one or more intermediate elements or layers may exist. In contrast, when one element or layer is referred to as being "directly on top of," "directly connected to," "directly combined to," or "immediately adjacent to" another element or layer, no intermediate elements or layers exist.

[0050] Any numerical range cited herein is intended to include all partial ranges of the same numerical precision that are included within the cited range. For example, the range “from 10.0” includes all partial ranges between (and including) the cited minimum value 1.0 and the cited maximum value 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, from 2.4 to 7.6. Any maximum numerical limit cited herein is intended to include all lower numerical limits included herein, and any minimum numerical limit cited herein is intended to include all higher numerical limits included herein.

[0051] Although exemplary embodiments of a system and method for controlling the order of instruction execution by a target (105) have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it should be understood that a system and method for controlling the order of instruction execution by a target (105) configured according to the principles of the present invention may be implemented in ways other than those specifically described herein. The present invention is also defined by the following claims and their equivalents. Explanation of the symbols

[0052] 110: Host 105: Target 115: Transmission interconnect

Claims

Claim 1 A method for executing commands in a restricted order comprises the steps of: a host transmitting a first command, then transmitting a sequence restriction command, then transmitting a second command; a target receiving the first command, the sequence restriction command, and the second command; and the target executing the first command, executing the sequence restriction command after executing the first command, and executing the second command after executing the sequence restriction command, wherein the step of the target executing the first command, the sequence restriction command, and the second command comprises: inputting the first command into a command ordering; transmitting an acknowledgment to the host indicating that the first command is or will be input into the command ordering; and receiving the sequence restriction command from the host in response to the acknowledgment. A command execution method comprising the step of inputting the order restriction command into the command ordering in the order following the first command, wherein the target is configured to execute the first command and the order restriction command in the same order as the command ordering. Claim 2 A method for executing commands according to claim 1, further comprising the step of the target transmitting a plurality of corresponding approvals to the host, wherein the approvals include an approval for the first command, an approval for the order restriction command, and an approval for the second command, and the step of the target executing the first command, the order restriction command, and the second command includes the target executing the first command, the order restriction command, and the second command in the same order as the target sending the corresponding approvals, and the step of the host transmitting the first command, the order restriction command, and the second command includes the step of the host transmitting the order restriction command after the host receives an approval for the first command, and the step of the host transmitting the second command after the host receives an approval for the order restriction command. Claim 3 In claim 2, the host is a command execution method connected to the target through a transmission interconnection. Claim 4 A command execution method according to claim 2, further comprising the step of the host transmitting a third command after transmitting the first command and before transmitting the sequence restriction command. Claim 5 A method for executing a command according to claim 4, further comprising the step of the target receiving the third command before the target receives the first command. Claim 6 A method for executing a command according to claim 5, further comprising the step of the target transmitting approval for the third command to the host before the target transmits approval for the first command to the host. Claim 7 A method for executing an instruction according to claim 6, further comprising the step of the target executing the third instruction before the target executes the first instruction. Claim 8 A system comprising a target, wherein the target comprises a processing circuit, and the processing circuit is configured to receive a first command; transmit an acknowledgment for the first command; execute the first command; receive a second command; transmit an acknowledgment for the second command; and execute the second command, wherein executing the first command and executing the second command are performed in the same order as transmitting an acknowledgment for the first command and transmitting an acknowledgment for the second command, and executing the first command and the second command comprises: inputting the first command and the second command into a command ordering in the order in which they are received; transmitting the acknowledgments for the first and second commands in response to inputting the first command and the second command into the command ordering; and executing the first command and the second command in the same order as the command ordering. Claim 9 In claim 8, the target comprises an instruction ordering FIFO, and the processing circuit is further configured to make a first entry corresponding to the first instruction in the instruction ordering FIFO, and to make a second entry corresponding to the second instruction in the instruction ordering FIFO, wherein the first entry and the second entry are in the same order as transmitting an acknowledgment for the first instruction and transmitting an acknowledgment for the second instruction in the instruction ordering FIFO. Claim 10 A system comprising a target, wherein the target comprises processing means, and the processing means is configured to receive a first command; transmit an acknowledgment for the first command; execute the first command; receive a second command; transmit an acknowledgment for the second command; and execute the second command, wherein executing the first command and executing the second command are performed in the same order as transmitting an acknowledgment for the first command and transmitting the second command, and executing the first command and the second command comprises: inputting the first command and the second command into a command ordering in the order in which the first command and the second command are received; transmitting the acknowledgments for the first and second commands in response to inputting the first and second commands into the command ordering; and executing the first command and the second command in the same order as the command ordering.

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