Fan-out structure for light-emitting diode (LED) devices and lighting systems

Abstract

A system is described. The system comprises a silicon backplane having a top surface, a bottom surface, and side surfaces, and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface, and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and on the bottom surface of the silicon backplane, and the metal layer has a first portion electrically and thermally bonded to the bottom surface of the silicon backplane in a central region and a second portion extending between a peripheral region of the silicon backplane and at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Description

Technology Field

[0001] The present application claims the benefit of U.S. formal application No. 16 / 750,839 filed January 23, 2020; European patent application No. 20158481.0 filed February 20, 2020; U.S. provisional application No. 62 / 951,601 filed December 20, 2019; and U.S. provisional application No. 62 / 937,629 filed November 19, 2019, the contents of which are incorporated herein by reference. Background Technology

[0002] Precision control lighting applications may require the production and manufacturing of small addressable light-emitting diode (LED) lighting systems. The smaller size of such systems may require unconventional components and manufacturing processes.

[0003] LED lighting systems, vehicle headlamp systems, and manufacturing methods are described. An LED lighting system comprises a silicon backplane having a top surface, a bottom surface, and side surfaces, and a substrate surrounding the side surfaces of the silicon backplane, wherein the substrate has a top surface, a bottom surface, and side surfaces. First redistribution layers are provided on the top surface of the silicon backplane and the top surface of the substrate. Second redistribution layers are provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layers and the second redistribution layers and is filled with a metallic material. Brief explanation of the drawing

[0004] A more detailed understanding can be obtained from the following description, which is provided as an example together with the attached drawings, and in the drawings: FIG. 1a is a top view of an exemplary LED array; FIG. 1b is a cross-sectional view of an exemplary LED lighting system; FIG. 1c is a top view of an exemplary LED lighting system of FIG. 1b; FIG. 1d is a bottom view of an exemplary LED lighting system of FIG. 1b; FIG. 2 is a cross-sectional view of an exemplary application system including the LED lighting system of FIG. 1b; FIG. 3 is a drawing of an exemplary vehicle headlamp system including the LED lighting system of FIG. 1b; FIG. 4 is a drawing of another exemplary vehicle headlamp system; FIG. 5 is a flowchart of an exemplary method for manufacturing an LED lighting system, e.g., the LED lighting system of FIG. 1b; FIGS. 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 6i, and 6j are cross-sectional views of an LED lighting system at various stages of a manufacturing method; Figure 7 is a bottom view showing the bottom surface of the LED lighting system of Figure 6e. Specific details for implementing the invention

[0005] Examples of different light illumination systems and / or light-emitting diode ("LED") implementations will be described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional implementations. Accordingly, it will be understood that the examples depicted in the accompanying drawings are provided for exemplary purposes only and are not intended to limit the present disclosure in any way. Throughout the disclosure, similar numbers refer to similar elements.

[0006] It will be understood that terms such as first, second, third, etc., may be used herein to describe various elements, but that these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be named a second element, and a second element may be named a first element. As used herein, the term "and / or" may include any and all combinations of one or more of the associated enumerated items.

[0007] When one element, e.g., a layer, region, or substrate is referred to as being "on" or extending "on" another element, it will be understood that the element may be directly on or directly extending onto the other element, or that intervening elements may also exist. Conversely, when one element is referred to as being "directly" on or directly extending onto another element, intervening elements may not exist. When one element is referred to as being "connected" or "joined" to another element, it will also be understood that the element may be directly connected or joined to the other element and / or connected or joined to the other element through one or more intervening elements. Conversely, when one element is referred to as being "directly connected" or "directly joined" to another element, there are no intervening elements between the element and the other element. It will be understood that these terms are intended to include different orientations of the element in addition to any orientation depicted in the drawings.

[0008] Relative terms, such as "below," "above," "upper," "lower," "horizontal," or "vertical," may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the drawings. It will be understood that these terms are intended to include different orientations of the device in addition to the orientations illustrated in the drawings.

[0009] Additionally, whether LEDs, LED arrays, electrical components and / or electronic components are housed on one, two, or more electronic boards may also depend on design constraints and / or applications.

[0010] Semiconductor light-emitting devices (LEDs) or photovoltaic power-emitting devices, such as those emitting ultraviolet (UV) or infrared (IR) photovoltaic power, are among the most efficient light sources currently available. These devices (hereinafter referred to as "LEDs") may include light-emitting diodes, resonant cavity light-emitting diodes, vertical cavity laser diodes, side-emitting lasers, etc. For example, due to their small size and lower power requirements, LEDs can be attractive candidates for many different applications. For example, they can be used as light sources (e.g., flash lights and camera flashes) for portable battery-powered devices, such as cameras and mobile phones. They can also be used, for example, as automotive lighting, head-up display (HUD) lighting, gardening lighting, street lighting, video torches, general lighting (e.g., home, shop, office, and studio lighting, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, backlights for displays, and for IR spectroscopy. Since a single LED can provide less bright light than an incandescent light source, arrays of LEDs (such as monolithic LED arrays, micro LED arrays, etc.) or multi-junction devices can be used in applications where more brightness is desired or required.

[0011] FIG. 1a is a top view of an exemplary LED array (102). In the example illustrated in FIG. 1a, the LED array (102) is an array of emitters (120). LED arrays can be used for any application, such as an application requiring precise control of LED array emitters. The emitters (120) of the LED array (102) may be individually addressable or may be addressable in groups / subsets.

[0012] An exploded view of a 3x3 portion of the LED array (102) is also shown in FIG. 1a. As shown in the exploded view of the 3x3 portion, the LED array (102) may include emitters (120) each having a width (w1). In embodiments, the width (w1) may be approximately 100 μm or less (e.g., 40 μm). The lanes (122) between the emitters (120) may have a width (w2). In embodiments, the width (w2) may be approximately 20 μm or less (e.g., 5 μm). The lanes (122) may provide an air gap between adjacent emitters or may contain other materials. The distance (d1) from the center of one emitter (120) to the center of an adjacent emitter (120) may be approximately 120 μm or less (e.g., 45 μm). It will be understood that the widths and distances provided herein are merely examples and that actual widths and / or dimensions may vary.

[0013] Although rectangular emitters arranged in a symmetric matrix are illustrated in FIG. 1a, it will be understood that emitters of any shape and arrangement may be applied to the embodiments described herein. For example, the LED array (102) of FIG. 1a may include more than 20,000 emitters in any applicable arrangement, such as a 200x100 matrix, a symmetric matrix, an asymmetric matrix, etc. Additionally, it will be understood that multiple sets of emitters, matrices, and / or boards may be arranged in any applicable format to implement the embodiments described herein.

[0014] As mentioned above, LED arrays, such as an LED array (102), may contain up to 20,000 or more emitters. Such arrays may have a surface area of ​​90 mm² or more and may require significant power, such as 60 watts or more, to power them. Such LED arrays may be referred to as micro LED arrays or simply micro LEDs. A micro LED may comprise an array of individual emitters provided on a substrate, or may be a single silicon wafer or die divided into segments forming the emitters. A micro LED of the latter type may be referred to as a monolithic LED.

[0015] To drive or control individual LEDs of an array individually, a silicon backplane may be provided very close to the LED array and can become extremely hot during operation. Accordingly, heat dissipation can be a challenge for such devices. While some solutions for heat dissipation for semiconductor devices are known, such solutions often include structures that dissipate heat through the top of the device. However, due to light emission, LED arrays, such as the LED array (102) of FIG. 1a, may not be able to dissipate heat through the top of the device.

[0016] Additionally, LED arrays, e.g., LED array (102), may be used in applications such as vehicle headlamp systems, which may include passive components, e.g., resistors and capacitors, capable of forming drivers, controllers and other circuits. It may be desirable to package at least some of the passive components together with the LED array.

[0017] The embodiments described herein can provide a low-profile LED array package capable of accommodating one or more passive elements and enabling the dissipation of heat generated by the silicon backplane and the LED array.

[0018] FIG. 1b is a cross-sectional view of an exemplary LED lighting system (100). In the example illustrated in FIG. 1b, the LED lighting system (100) comprises a silicon backplane (104). The silicon backplane (104) has a top surface (101), a bottom surface (103), and side surfaces (105). The side surfaces (105) of the silicon backplane (104) are surrounded by a substrate (106) formed of a molding material. The substrate (106) has a top surface (107), a bottom surface (109), and side surfaces (190). One or more metal layers or redistribution layers (RDL) (110) (illustrated in an alternative embodiment of FIG. 6e) are provided on the bottom surface (103) of the silicon backplane (104) and the bottom surface (109) of the substrate (106). The RDL (117) may be formed on at least a portion of the top surface (107) of the substrate (106) and the top surface (101) of the silicon backplane (104). In the example illustrated in FIG. 1b, the RDL (117) comprises two layers (116a and 116b) of dielectric material (116) and a single metal layer (112). One or more vias (108) may extend through the substrate (106) and may be filled with metal material. Thus, the vias may form a continuous electrical connection between the silicon backplane (104), the RDL (117), and the metal layer / RDL (110). An LED array, e.g., the LED array (102) of FIG. 1a, may be provided on the upper surface (101) of a silicon backplane (104) and may be electrically coupled thereto through an array of metal connectors (not shown in FIG. 1b). In embodiments, electronic components (114) may be provided on the RDL (117) and may be electrically coupled to the LED lighting system (100) through a metal layer (112).

[0019] The LED array (102) may be a micro LED as described above in relation to FIG. 1a. The LED array (102) may have a depth (d1). In the embodiments, the depth (d1) may be, for example, 5 to 250 μm.

[0020] The silicon backplane (104) may include circuits and connectors forming individually addressable connections to the emitters of the LED array (102). In embodiments, the silicon backplane may be a complementary metal oxide semiconductor (CMOS) integrated circuit, which may be an application-specific integrated circuit (ASIC) in embodiments. The silicon backplane (104) may have a depth (d3). In embodiments, the depth (d3) may be, for example, 100 μm to 1 mm.

[0021] A structure composed of a silicon backplane (104), a substrate (106), a metal layer / RDL (110), an RDL (117), and vias (108) may have a depth (d2). In embodiments, the depth (d2) may be, for example, 100 μm to 1 mm. Since the silicon backplane (104) is integrated within the substrate and the LED array (102) is provided on the top of the silicon backplane (104), the LED lighting system (100) may have a lower profile compared to systems that vertically stack one or more of these elements.

[0022] In the example illustrated in FIG. 1b, the RDL (117) comprises two layers (116a and 116b) of a dielectric material (116) and a single metal layer (112). The first layer (116a) of the two layers of the dielectric material (116) may be on at least a portion of the top surface (107) of the substrate (106) and the top surface (101) of the silicon backplane (104). The metal layer (112) may be patterned on the first layer (116a) of the dielectric material (116), for example, by copper plating and copper etching. The second layer (116b) of the dielectric material (116) may be on the exposed portions of the first layer (116a) of the dielectric material (116) and on the top of the patterned metal layer (112). Although an RDL consisting of two layers of dielectric material and a single layer of metal is illustrated in FIG. 1b, a person skilled in the art will recognize that the RDL (117) may include more or fewer layers of dielectric material and / or more layers of metal, depending on design constraints. The dielectric material (116) may be any suitable dielectric material. In the embodiments, the dielectric material may be a polymeric dielectric material, e.g., polyimide.

[0023] The RDL (117) may extend from the peripheral region of the silicon backplane (104) toward the side surfaces (190) of the substrate (106). This can do both to accommodate an LED array (102) attached to the top surface (101) of the silicon backplane (104) in the central region, and to help dissipate heat by including dielectric materials that can further insulate the LED lighting system (100) from the highest thermal regions in the center of the LED lighting system (100) to regions further away. The metal layer (112) may have portions exposed from the dielectric material (116) to form bond pads. The metal layer (112) may include portions extending between the peripheral region of the silicon backplane (104) and the bond pads to create a continuous electrical connection between them. Bond pads can be electrically coupled to vias (108) to create a continuous electrical connection between the top surface and the bottom surface of the LED lighting system (100). The bond pads can be placed in a peripheral area of ​​the substrate, or (e.g., as shown in FIG. 1c) spaced apart from the array but closer to the array.

[0024] The metal layer / RDL (110) can be formed in a number of different ways. In the example illustrated in FIG. 1b, the metal layer / RDL (110) is a metal layer comprising a first portion electrically and thermally coupled to the bottom surface (103) of the silicon backplane (104) in a central region and a second portion fanning out from the peripheral region of the silicon backplane (104) toward the side surfaces (190) of the substrate (106). In the embodiments, the first portion and the second portion may be electrically insulated from each other. Although not shown in FIG. 1b, the second portion may extend from the silicon backplane (104) and be coupled to individual vias (108) at bond pads and may electrically couple the silicon backplane (104) to the metal layer (112) on the top surface. Both the first and second portions of the metal layer (110) can be joined to an external circuit board (not shown), for example, by soldering. This can enable a direct connection between the LED lighting system (100) and the external circuit board, which provides improved heat sinking through the bottom of the LED lighting system. Additionally, this structure can enable communication between the silicon backplane (104), the LED array (102), the passive components (114) on the substrate (106), and any electronic components on the external circuit board.

[0025] In another example to be described in more detail later in connection with FIGS. 6e and 7, the metal layer / RDL (110) may be a combination of a metal layer and an RDL. As in the embodiment illustrated in FIG. 1b, the metal layer may be electrically and thermally bonded to the bottom surface (103) of the silicon backplane (104) in the central region. However, fan-out may be achieved using an RDL instead of a metal layer. In such embodiments, the LED lighting device (100) may have an RDL on both the top and bottom surfaces.

[0026] In both cases, the metal layer / RDL (110) may be thinner than conventional silicon device packages and may contain significantly less dielectric material than conventional silicon device packages. For example, the metal layer (100) in the embodiment illustrated in FIG. 1b may be a single metal layer, and the RDL may contain as few dielectric layers as possible. This can increase the efficiency of heat dissipation in such packages and enable packaging for micro LEDs and CMOS backplanes capable of releasing significant heat.

[0027] In the LED lighting system (100) illustrated in FIG. 1b, the top surface (101) of the silicon backplane (104) and the top surface (107) of the substrate (106) are coplanar. Similarly, the bottom surface (103) of the silicon backplane (104) and the bottom surface (109) of the substrate (106) are coplanar. This arrangement may allow for the thinnest possible packaging and ease of manufacturing. However, a person skilled in the art will recognize that, since the substrate (106) is formed, the substrate (106) may take any shape, such as when the substrate has a top surface (107) that is higher than the top surface (101) of the silicon backplane (104) in order to keep the electronic components (114) further away from the high-temperature regions of the LED lighting system (100). Thus, in the embodiments, these surfaces may not be coplanar.

[0028] FIG. 1c is a top view illustrating the top surface (130) of the exemplary LED lighting system (100) of FIG. 1b. In the example illustrated in FIG. 1c, the top surface (130) of the LED lighting system comprises a top layer (116b) of the dielectric material (116) of the RDL (117). Electronic components (114) are electrically coupled to the metal layer (112) of the RDL and exposed from the dielectric material (116). In embodiments, the electronic components (114) may not be electrically coupled to all regions of the metal layer (112), and thus, the top surface (130) may also include some regions of the metal layer (112) exposed from the dielectric material (116). At least a portion of the uppermost surface of the silicon backplane (104) is illustrated in FIG. 1c and includes a portion of the uppermost surface of the silicon backplane (104) that is not covered by the LED array (102) or the dielectric material (116). The uppermost surface of the LED array (102) is also illustrated as being mounted on the uppermost surface of the silicon backplane (104).

[0029] As illustrated in FIG. 1c, the LED lighting system (100) has a length (l1) and a width (w1). In embodiments, the length (l1) may be approximately 20 mm and the width (w1) may be approximately 15 mm. The silicon backplane (104) may have a length (l2) and a width (w2). In embodiments, the length (l2) may be approximately 15.5 mm and the width (w2) may be approximately 6.5 mm. The LED array (102) may have a length (l3) and a width (w3). In embodiments, the length (l3) may be approximately 11 mm and the width (w3) may be approximately 4.4 mm.

[0030] Given these exemplary dimensions, an LED array package having a relatively large surface area (300 mm² in the above example) can be provided, wherein a relatively large amount of surface area is not occupied by the LED array (having a surface area of ​​approximately 100 mm² in the above example). Accordingly, this design provides sufficient space for attaching electronic components on the LED array package.

[0031] FIG. 1d is a bottom view illustrating the bottom surface (140) of the exemplary LED lighting system (100) of FIG. 1b. In the example illustrated in FIG. 1d, the bottom surface (140) comprises regions of a substrate (106) and regions of solder pads or metal (110) bonded thereto that are exposed from the molding material (106). In embodiments, some regions of the substrate may be covered by metallization and / or portions of RDL interconnecting the silicon backplane and bond pads, but these are not illustrated in FIG. 1d. In some embodiments, the interconnecting metal regions and / or RDL may be covered by a dielectric material or other encapsulating or protective material (not illustrated in FIG. 1d).

[0032] FIG. 2 is a cross-sectional view of an application system (200) including the LED lighting system (100) of FIG. 1b. The application system (200) may include a circuit board (150) having a plurality of bond pads (152). In the example illustrated in FIG. 2, the exposed metal regions / bond pads of the RDL / metallization (110) of the LED lighting system (100) are directly bonded to the bond pads (152) of the circuit board (150). As mentioned above, direct bonding between the metal layer (110) on the bottom surface of the silicon backplane (104) and the circuit board (150) enables efficient heat transfer from the LED lighting system (100) to the circuit board (150) for heat sinking purposes without requiring additional heat dissipation structures on the top (or elsewhere) of the LED lighting system (100), which, for example, could otherwise block light emission from the LED array (102). The circuit board (150) may be part of a larger system used in specific applications, such as vehicle lighting or flash applications (exemplary vehicle lighting systems are described below in relation to FIGS. 3 and 4). In such systems, some of the passive components used in the application may be components (114) and may be provided directly on the LED lighting system (100) before attachment to the circuit board (150). The circuit board (150) may include other circuit elements required for the larger system in addition to the heat sink. The RDL (117), RDL / metallization (110), and vias (108) can provide continuous electrical connections between the components (114), the silicon backplane (104), and the circuit board (150).

[0033] FIG. 3 is a drawing of an exemplary vehicle headlamp system (300) that may include the LED lighting system (100) of FIG. 1b. The exemplary vehicle headlamp system (300) illustrated in FIG. 3 includes power lines (302), a data bus (304), an input filter and protection module (306), a bus transceiver (308), a sensor module (310), an LED DC-to-DC (DC / DC) module (312), a logic low dropout (LDO) module (314), a microcontroller (316), and an active headlamp (318). In embodiments, the active headlamp (318) may include an LED lighting system, e.g., the LED lighting system (100) of FIG. 1b. As mentioned above, the LED lighting system (100) provides sufficient space and bond pads on the top surface of the substrate so that one, more than, or all of the modules exemplified in FIG. 3 can be accommodated on the top surface of the LED lighting system (100). Modules not provided on the top surface of the LED lighting system (100) may be provided on the circuit board (150) (as shown in FIG. 2). In some embodiments, some electronic components of some or all of the modules of the vehicle lighting system (300) may be accommodated on the top surface of the LED lighting system (100) and some may be provided on the circuit board (150) (as shown in FIG. 2).

[0034] Power lines (302) may have inputs for receiving power from the vehicle, and the data bus (304) may have inputs / outputs for exchanging data between the vehicle and the vehicle headlamp system (300). For example, the vehicle headlamp system (300) may receive commands from other locations within the vehicle, such as to turn on the turn signals or turn on the headlamps, and may transmit feedback to other locations within the vehicle if desired. A sensor module (310) may be communicably coupled to the data bus (304) and may provide additional data related to environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle status (e.g., parked, moving, speed, or direction of movement), and the presence / location of other objects (e.g., vehicles or pedestrians) to the vehicle headlamp system (300) or other locations within the vehicle. A headlamp controller separate from any vehicle controller coupled communically to a vehicle data bus may also be included in the vehicle headlamp system (300). In FIG. 3, the headlamp controller may be a microcontroller, e.g., a microcontroller (μc) (316). The microcontroller (316) may be communically coupled to a data bus (304).

[0035] The input filter and protection module (306) can be electrically coupled to the power lines (302) and can support various filters, for example, to reduce conducted emissions and provide power resistance. Additionally, the input filter and protection module (306) can provide electrostatic discharge (ESD) protection, load dump protection, alternator field attenuation protection, and / or reverse polarity protection.

[0036] The LED DC / DC module (312) may be coupled between the filter and protection module (306) and the active headlamp (318) to receive filtered power and provide a driving current to power the LEDs of the LED array of the active headlamp (318). The LED DC / DC module (312) may have an input voltage of 7 to 18 volts with a nominal voltage of approximately 13.2 volts, and an output voltage that may be slightly higher than the maximum voltage for the LED array (e.g., 0.3 volts) (as determined by factors such as load, temperature, or other factors, or by local calibration and adjustment of operating conditions).

[0037] The logic LDO module (314) may be coupled to the input filter and protection module (306) to receive filtered power. The logic LDO module (314) may also be coupled to the microcontroller (314) and the active headlamp (318) to provide power to the silicon backplane (e.g., CMOS logic) of the microcontroller (314) and / or the active headlamp (318).

[0038] The bus transceiver (308) may have, for example, a Universal Asynchronous Transceiver (UART) or Serial Peripheral Interface (SPI) interface and may be coupled to the microcontroller (316). The microcontroller (316) may convert vehicle input based on or containing data from the sensor module (310). The converted vehicle input may include a video signal that can be transmitted to the image buffer of the active headlamp module (318). Additionally, the microcontroller (316) may load default image frames and test for open / short pixels during startup. In embodiments, the SPI interface may load the image buffer in the CMOS. The image frames may be full frames, differential frames, or partial frames. Other features of the microcontroller (316) may include monitoring of the control interface of the CMOS state, including the die temperature, as well as logic LDO outputs. In embodiments, the LED DC / DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlamp functions, such as side markers or turn signals, and / or the activation of daytime running lights can also be controlled.

[0039] FIG. 4 is a drawing of another exemplary vehicle headlamp system (400). The exemplary vehicle headlamp system (400) illustrated in FIG. 4 includes an application platform (402), two LED lighting systems (406 and 408), and optical systems (410 and 412). The two LED lighting systems (406 and 408) may be LED lighting systems, e.g., the LED lighting system (100) of FIG. 1b, or may include all of the other modules of the vehicle headlamp system (300) of FIG. 3 in addition to the LED lighting system (100). In the latter embodiment, the LED lighting systems (406 and 408) may be vehicle headlamp subsystems.

[0040] The LED lighting system (408) can emit light beams (414) (illustrated between arrows (414a and 414b) in FIG. 4). The LED lighting system (406) can emit light beams (416) (illustrated between arrows (416a and 416b) in FIG. 4). In the embodiment illustrated in FIG. 4, a secondary optical system (410) is adjacent to the LED lighting system (408), and light emitted from the LED lighting system (408) passes through the secondary optical system (410). Similarly, a secondary optical system (412) is adjacent to the LED lighting system (412), and light emitted from the LED lighting system (412) passes through the secondary optical system (412). In alternative embodiments, the secondary optical systems (410 / 412) are not provided to the vehicle headlamp system.

[0041] If included, the secondary optical systems (410 / 412) may be one or more light guides or may include them. One or more light guides may be edge-lit or may have an inner opening defining the inner edge of the light guide. LED lighting systems (408 and 406) (or active headlamps of a vehicle headlamp subsystem) may be inserted into the inner openings of one or more light guides so as to inject light into the inner edge (inner opening light guide) or outer edge (edge-lit light guide) of one or more light guides. In embodiments, one or more light guides may shape the light emitted by the LED lighting systems (408 and 406) in a desired manner, e.g., tilt, chamfered distribution, narrow distribution, wide distribution, or angular distribution.

[0042] The application platform (402) may provide power and / or data to LED lighting systems (406 and / or 408) via lines (404) that may include one or more or some of the power lines (302) and data bus (304) of FIG. 3. One or more sensors (which may be sensors of the system (300) or other additional sensors) may be located inside or outside the housing of the application platform (402). Alternatively or additionally, as illustrated in the exemplary LED lighting system (300) of FIG. 3, each LED lighting system (408 and 406) may include its own sensor module, connection and control module, power module, and / or LED array.

[0043] In embodiments, the vehicle headlamp system (400) may represent a vehicle having steerable light beams in which LEDs can be selectively activated to provide steerable light. For example, an array of LEDs (e.g., LED array (102)) may be used to illuminate only selected sections of a road or to define or project shapes or patterns. In exemplary embodiments, infrared cameras or detector pixels within the LED systems (406 and 408) may be sensors (e.g., similar to the sensors of the sensor module (310) of FIG. 3) that identify parts of a scene (e.g., a road or a crosswalk) requiring illumination.

[0044] FIG. 5 is a flowchart of an exemplary method (500) for manufacturing an LED lighting system, e.g., the LED lighting system (100) of FIG. 1b. FIG. 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 6i and 6j are cross-sectional views of the LED lighting system at various stages of the manufacturing method. In the embodiments, the method (500) can produce a high-density LED lighting system that is panel-level packaged.

[0045] In the exemplary method (500) of FIG. 5, a silicon backplane may be attached to a first carrier (502) to form a first structure. In embodiments, the silicon backplane may be attached to a temporary (e.g., plastic) carrier through an adhesive material, such as tape or a temporary adhesive. An example (600A) of the first structure is illustrated in FIG. 6a and includes a silicon backplane (104), a first carrier (602), and an optional adhesive material (604).

[0046] A silicon backplane attached to a first carrier may be molded to form a second structure (504). An example of a second structure (600B) is illustrated in FIG. 6b and includes the first structure (600A) of FIG. 6a, in which a molding material surrounds the sides of the silicon backplane (104). The molding material forms a substrate (106) having the embedded silicon backplane (104). In embodiments, a mold may be placed over the structure (600A), filled with the molding material, and cured. Any excess molding material may be removed from the top surface of the silicon backplane if necessary. In embodiments, the molding may be panel-level molding, the molding material may be a polymer material, and the second structure (600B) may be a plastic substrate having the embedded silicon backplane on a temporary substrate.

[0047] One or more vias may be formed through the substrate (506) to form a third structure. In embodiments, one or more vias may be formed using a laser or a drill. An example (600C) of the third structure is illustrated in FIG. 6c and includes a silicon backplane (104) embedded in the substrate (106) formed through two vias (108). In this stage, the substrate (106) having the vias (108) and the silicon backplane (104) may be maintained attached to a first temporary carrier (602). The vias (108) may be filled with a metallic material.

[0048] At least one metal layer may be formed on one surface of the substrate (508) and the silicon backplane. This may be done in a number of different ways.

[0049] In some embodiments, the metal layer may be patterned or plated on one surface of the silicon backplane and the substrate to form a fourth structure. FIG. 6d illustrates an example (600D) of a fourth structure comprising a third structure having a metal layer (110). As can be seen in FIG. 6d, the metal layer (110) forms bond pads on regions and vias extending from the peripheral region of the silicon backplane (104). The metal layer is also provided on a central region of one surface of the silicon backplane (104). A bottom view of the LED lighting system (100) illustrated in FIG. 1d illustrates an example of this.

[0050] In other embodiments, the metal layer may be formed in a central region on one surface of the silicon backplane, and redistribution layers may be formed adjacent to a single metal layer on one surface of the silicon backplane and the substrate to form a fifth structure. FIG. 6e illustrates an example (600E) of a fifth structure comprising a third structure having a single metal layer (618) and redistribution layers (616). In the example illustrated in FIG. 6e, the redistribution layers (616) include metal layers (612) and layers of dielectric material (614). Although three metal layers are illustrated in FIG. 6e, one, two, or more than three metal layers may be used if necessary due to design constraints. The redistribution layers may be formed, for example, by alternating deposition of layers of dielectric material, (if necessary) selective removal of portions of dielectric material, and patterning of the metal layer on top. As can be seen in FIG. 6e, the metal layers (612) start from a peripheral region of one surface of the silicon backplane and extend toward the side surfaces of the substrate. The metal layers (612) are electrically coupled between the silicon backplane (104) and the vias. A portion of the metal layers (612) may be exposed from the dielectric material (614) to form a solder pad, or separate solder pads may be formed on the outermost surface of the outermost dielectric layer.

[0051] FIG. 7 is a bottom view showing the bottom surface (700) of the LED lighting system of FIG. 6e. Line (702) indicates the outermost perimeter of the substrate. Line (104) indicates the outermost perimeter of the region occupied by the silicon backplane (104) with respect to the outermost perimeter of the substrate. The dashed line (704) indicates the boundary of the region between the outermost perimeter of the silicon backplane (104) and Line (704), which may be referred herein as the peripheral region of the silicon backplane (104). The metal layers (612) of the redistribution layers (616) may extend from the peripheral region toward the side surfaces of the substrate (described by Line (702)). A gap exists between the boundary (704) of the peripheral region of the silicon backplane and a single metal layer (618) formed on one surface of the silicon backplane. This gap can be filled with a dielectric material, for example, as reflected in Fig. 6e.

[0052] The structure formed as a result of 508 (e.g., the fourth or fifth structure) may be inverted and attached to the second carrier (510) to form the sixth structure. In embodiments, the structure (e.g., the fourth or fifth structure) may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as tape or a temporary adhesive. The structure may be disposed adjacent to the second carrier with at least one metal layer. An example of the sixth structure (600G) is illustrated in FIG. 6g and includes the second carrier (608) and an optional adhesive material (606). Once the structure is attached to the second carrier, the first carrier may be removed to form the seventh structure (512). An example of the seventh structure (600G) is illustrated in FIG. 6g.

[0053] To form the eighth structure, an array of redistribution layers and metal connectors may be formed on a surface exposed by the removal of the second carrier (514). In embodiments, an array of metal connectors may be formed by plating, patterning, or forming an array of copper filler bumps on the surface. An example (600H) of the eighth structure is illustrated in FIG. 6h and includes metal connectors (640) and redistribution layers (117), comprising at least one metal layer (112) and a dielectric material (116). As described above in relation to FIG. 6e, the redistribution layers may be formed by the alternating deposition of layers of dielectric material, (if necessary) the selective removal of portions of dielectric material, and the patterning of a layer of metal on top. In embodiments, more than 20,000 (e.g., approximately 28,000) metal connectors may be formed on the surface.

[0054] The LED array may be attached to a silicon backplane via electrical connectors (516) to form a ninth structure. In embodiments, this may be accomplished by aligning the silicon backplane with the electrical connectors and heating to reflow the solder copper material of the copper filler bumps. Reflow may create an underfill beneath the LED array. In embodiments, the LED array may be a monolithic LED array. An example (600I) of the ninth structure is illustrated in FIG. 6i and includes an LED array (102) and an underfill.

[0055] The LED array may undergo a laser lift-off (LLO) process and phosphor integration (518). Any passive components may be mounted on exposed metal regions of the redistribution layers (117) to form the 10th structure. An example (600J) of the 10th structure is shown in FIG. 600J and includes an LED array (102) having passive components (114) and a phosphor material (610).

[0056] Optionally, the 10th structure, which may be an LED lighting system, e.g., the LED lighting system (100) of FIG. 1b, may be mounted on an external circuit board (520) to integrate the LED lighting system (100) into a vehicle headlamp or other application system.

[0057] Although embodiments have been described in detail, those skilled in the art will understand that, given this description, modifications can be made to the embodiments described herein without departing from the spirit of the concept of the invention. Therefore, the scope of the invention is not intended to be limited to the specific embodiments illustrated and described.

Claims

Claim 1 A system comprising: a silicon backplane (104) having a top surface (101), a bottom surface (103), and side surfaces (105); a substrate (106) surrounding the side surfaces of the silicon backplane—the substrate having a top surface (107), a bottom surface (109), and side surfaces (190); a first portion of a metal layer (110) formed on a central region of the bottom surface of the silicon backplane; a second portion of a metal layer (110) extending from a peripheral region of the bottom surface of the silicon backplane toward the side surfaces of the substrate and electrically insulated from the first portion; a third portion of a metal layer (110) on the bottom surface of the substrate; and an array of metal connectors on the top surface of the silicon backplane. Claim 2 A system according to claim 1, further comprising at least one via through the substrate, wherein the at least one via is filled with a metallic material and electrically coupled to a third portion of the metal layer. Claim 3 A system according to claim 2, further comprising redistribution layers on the uppermost surface of the silicon backplane and the uppermost surface of the substrate, wherein the redistribution layers comprise: at least one first dielectric layer and at least one first metal layer, wherein the at least one first metal layer extends from a peripheral region of the silicon backplane toward the side surfaces of the substrate and has at least a portion exposed from the at least one dielectric layer to form at least one bond pad. Claim 4 In paragraph 3, the system wherein the at least one bond pad is electrically coupled to the at least one via. Claim 5 A system according to claim 4, further comprising at least one passive component electrically coupled to at least one bond pad. Claim 6 A system according to claim 1, further comprising an array of light-emitting diodes (LEDs) electrically coupled to an array of metal connectors on the uppermost surface of the silicon backplane. Claim 7 In claim 6, the LED array is a monolithic LED array comprising emitters of a plurality of rows and columns, each of which has a width of 100 μm or less, and the lanes between adjacent rows and columns have a width of 20 μm or less, a system. Claim 8 A system according to claim 1, wherein the array of metal connectors is an array of copper filler bumps. Claim 9 In claim 1, the system comprises a substrate including a molding material. Claim 10 In claim 1, the silicon backplane is a complementary metal oxide semiconductor (CMOS) integrated circuit, the system. Claim 11 A system comprising: a silicon backplane (104) having a top surface (101), a bottom surface (103), and side surfaces (105); a substrate (106) surrounding the side surfaces of the silicon backplane—the substrate having a top surface (107), a bottom surface (109), and side surfaces (190)—; a first metal layer formed on a central region of the bottom surface of the silicon backplane; redistribution layers on the bottom surface of the silicon backplane and the bottom surface of the substrate—the redistribution layers comprising at least one dielectric layer and at least one second metal layer, wherein the at least one second metal layer extends from a peripheral region of the silicon backplane toward the side surfaces of the substrate, has at least one portion exposed from the at least one dielectric layer, and is electrically insulated from the first metal layer—; and an array of metal connectors on the top surface of the silicon backplane. Claim 12 A system according to claim 11, further comprising at least one via through the substrate, wherein the at least one via is filled with a metallic material and electrically coupled to the second metal layer. Claim 13 A system according to claim 12, further comprising other redistribution layers on the uppermost surface of the silicon backplane and the uppermost surface of the substrate, wherein the other redistribution layers comprise: at least one other dielectric layer and at least one third metal layer, wherein the at least one third metal layer extends from a peripheral region of the silicon backplane toward the side surfaces of the substrate and has at least a portion exposed from the at least one other dielectric layer to form at least one bond pad. Claim 14 In paragraph 13, the system wherein the at least one third metal layer is electrically coupled to the at least one via. Claim 15 A system according to claim 14, further comprising at least one passive component electrically coupled to at least one bond pad. Claim 16 A system according to claim 11, further comprising an array of light-emitting diodes (LEDs) electrically coupled to an array of metal connectors on the uppermost surface of the silicon backplane. Claim 17 In claim 16, the LED array is a monolithic LED array comprising emitters of a plurality of rows and columns, each of which has a width of 100 μm or less, and the lanes between adjacent rows and columns have a width of 20 μm or less, a system. Claim 18 In paragraph 11, the system, wherein the array of metal connectors is an array of copper filler bumps. Claim 19 In claim 11, the above substrate comprises a molding material, a system. Claim 20 In paragraph 11, the silicon backplane is a complementary metal oxide semiconductor (CMOS) integrated circuit, the system. Claim 21 A system according to claim 1, wherein the first portion of the metal layer is electrically insulated from the second portion of the metal layer. Claim 22 In claim 11, the system wherein the first metal layer is electrically insulated from the redistribution layers.

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