RF amplifier devices and methods of manufacturing

Abstract

A transistor amplifier comprises a semiconductor layer structure including first and second main surfaces, and a plurality of unit cell transistors on the first main surface connected in electrical parallel, wherein each unit cell transistor includes a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure does not have vias for the source fingers on the second main surface.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] The present application claims priority to U.S. patent application No. 17 / 018,762 filed on September 11, 2020, which claims priority as a partial continuation of U.S. patent application No. 16 / 906,610 filed on June 19, 2020, claiming priority under 35 USC § 119 to U.S. provisional application No. 63 / 004,765 filed on April 3, 2020, the entire contents of which are incorporated herein by reference.

[0003] The present disclosure relates to integrated circuit devices, and more specifically, to structures for integrated circuit device packaging. Background Technology

[0004] RF power amplifiers are used in various applications, such as base stations for wireless communication systems, multi-stage and multi-path amplifiers (e.g., Doherty amplifiers). Signals amplified by RF power amplifiers often include signals with modulated carriers having frequencies in the megahertz (MHz) to gigahertz (GHz) range. For example, electrical circuits requiring high power processing capabilities while operating at high frequencies such as the R-band (0.5 - 1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12 - 18 GHz), K-band (18 - 27 GHz), Ka-band (27 - 40 GHz), and V-band (40 - 75 GHz) are becoming more widespread. Currently, there is a high demand for radio frequency ("RF") transistor amplifiers used to amplify RF signals, particularly at frequencies such as 500 MHz and higher (including microwave frequencies). These RF transistor amplifiers may need to exhibit high reliability, good linearity, and handle high output power levels.

[0005] Many RF power amplifier designs utilize semiconductor switching devices as amplification devices. Examples of these switching devices include power transistor devices, such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), DMOS (Double-Diffusion Metal Oxide Semiconductor) transistors, HEMTs (High Electron Mobility Transistors), MESFETs (Metal Oxide Field-Effect Transistors), and LDMOS (Late-Diffusion Metal Oxide Semiconductor) transistors.

[0006] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented using silicon or wide-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and Group III nitride materials. As used herein, the term "Group III nitride" refers to semiconducting compounds formed between nitrogen and elements of Group III of the periodic table, generally aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have empirical formulas in which 1 mole of nitrogen is bonded to a total of 1 mole of Group III elements.

[0007] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can exhibit high levels of linearity with relatively low manufacturing costs. Group III nitride-based RF amplifiers are typically implemented using HEMTs, primarily in applications requiring high-power and / or high-frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0008] RF transistor amplifiers may include one or more amplification stages, each stage typically implemented as a transistor amplifier. To increase output power and current handling capabilities, RF transistor amplifiers are typically implemented in a "unit cell" configuration in which a large number of individual "unit cell" transistors are arranged electrically in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may comprise multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or parallel.

[0009] RF transistor amplifiers often include an active transistor die (e.g., MOSFETs, HEMTs, LDMOS, etc.) and matching circuits, such as impedance matching circuits, connected thereto and designed to improve impedance matching between transmission lines for RF signals at the fundamental operating frequency, and harmonic termination circuits designed to at least partially terminate harmonic products that may be generated during device operation, such as second and third harmonic products. Termination of harmonic products also affects the generation of intermodulation distortion products.

[0010] RF amplifier transistor die(s), as well as impedance matching and harmonic termination circuits, may be enclosed in a device package. A die or chip may refer to a small block of semiconductor material or another substrate upon which electronic circuit elements are manufactured. An integrated circuit package may refer to encapsulating one or more dies in a support case or package that protects the dies from physical damage and / or corrosion and supports electrical contacts for connections to external circuits. Input and output impedance matching circuits in an integrated circuit device package typically include LC networks that provide at least a portion of an impedance matching circuit configured to match the impedance of an active transistor die to a fixed value. Electrical leads may extend from the package to electrically connect the RF amplifier to external circuit elements, such as input and output RF transmission lines and bias voltage sources.

[0011] Some conventional methods for assembling RF power devices may involve assembling some of the transistor dies and matching network components into CPC (copper, copper-molybdenum, copper layered structure) or ceramic or over-molded packages on copper flanges. The transistor dies, capacitors, and input / output leads may be interconnected with wires, such as gold and / or aluminum wires. Such assembly processes can be slow and sequential (e.g., one package is bonded at a time), and assembly costs can be high (e.g., due to the cost of gold wires and expensive wire bonding machines).

[0012] According to some embodiments, a radio frequency ("RF") transistor amplifier comprises a semiconductor layer structure including first and second main surfaces, and a plurality of unit cell transistors on the first main surface connected electrically in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure does not have vias for the source fingers on the second main surface.

[0013] In some embodiments, the RF transistor amplifier further comprises a coupling element on a first main surface, the coupling element comprising a gate connection pad configured to be connected to a gate manifold, a drain connection pad configured to be connected to a drain manifold, and a source connection pad configured to be connected to source fingers among source fingers.

[0014] In some embodiments, the RF transistor amplifier further includes a carrier substrate on a second main surface of the semiconductor layer structure.

[0015] In some embodiments, the RF transistor amplifier further comprises a thermal and / or electrically conductive layer on a second main surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate.

[0016] In some embodiments, the RF transistor amplifier further comprises a circuit module on a semiconductor layer structure, wherein the circuit module comprises a gate lead connection pad electrically coupled to a gate manifold and a drain lead connection pad electrically coupled to a drain manifold.

[0017] In some embodiments, the RF transistor amplifier further comprises an input lead electrically coupled to a gate lead connection pad — the input lead is configured to extend outward from a package containing the RF transistor amplifier — and an output lead electrically coupled to a drain lead connection pad — the output lead is configured to extend outward from a package containing the RF transistor amplifier —.

[0018] In some embodiments, the RF transistor amplifier further includes one or more circuit elements mounted on the first side and / or second side of the circuit module.

[0019] In some embodiments, the RF transistor amplifier further includes a thermal and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0020] In some embodiments, the semiconductor layer structure further includes a high electron mobility transistor (HEMT) or a lateral diffusion metal oxide semiconductor (LDMOS) transistor.

[0021] According to some embodiments, the transistor amplifier comprises: a Group III nitride substrate amplifier die comprising a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die; and a circuit module on the first surface of the amplifier die and electrically coupled to the gate terminal, the drain terminal, and the source terminal of the amplifier die on the first surface. The circuit module comprises one or more circuit elements coupled between the gate terminal and a first lead of the transistor amplifier and / or between the drain terminal and a second lead of the transistor amplifier, and the circuit module has a first surface and a second surface on the side opposite to the first surface with respect to the circuit module, and the first surface of the circuit module is adjacent to the first surface of the amplifier die.

[0022] In some embodiments, one or more circuit elements are mounted on a first surface and / or a second surface of the circuit module.

[0023] In some embodiments, the transistor amplifier further includes a thermal and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0024] In some embodiments, one or more circuit elements are formed within a circuit module.

[0025] In some embodiments, the first and / or second leads are coupled to the second surface of the circuit module.

[0026] In some embodiments, the first and / or second leads are coupled to the first surface of the circuit module.

[0027] In some embodiments, the circuit module comprises a first interconnection pad and a second interconnection pad on a first surface of the circuit module, wherein the first interconnection pad is configured to be coupled to the gate terminal of an amplifier die and the second interconnection pad is configured to be coupled to the drain terminal of an amplifier die.

[0028] In some embodiments, the circuit module further includes a third interconnection pad on a first surface of the circuit module configured to be coupled to the source terminal of an amplifier die.

[0029] In some embodiments, the transistor amplifier further includes a coupling element located between the amplifier die and the circuit module.

[0030] According to some embodiments, a radio frequency ("RF") transistor amplifier comprises an RF transistor amplifier die having a first main surface and a second main surface — the RF transistor amplifier die comprises a gate terminal, a drain terminal, and a source terminal on the first main surface — a circuit module on the first main surface of the RF transistor amplifier die — the circuit module comprises a gate lead connection pad electrically coupled to the gate terminal and a drain lead connection pad electrically coupled to the drain terminal — a carrier substrate on the second main surface of the RF transistor amplifier die, and a thermal and / or electrically conductive spacer layer between the RF transistor amplifier die and the carrier substrate.

[0031] In some embodiments, the circuit module comprises a first side adjacent to a first main surface of an RF transistor amplifier die and a second side opposite to the first side, and the circuit module comprises one or more circuit elements coupled to a gate terminal and / or a drain terminal.

[0032] In some embodiments, one or more circuit elements are mounted on the first side and / or second side of the circuit module.

[0033] In some embodiments, the RF transistor amplifier further includes a thermal and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0034] In some embodiments, the spacer layer and the auxiliary spacer layer form an integrated spacer layer.

[0035] In some embodiments, the RF transistor amplifier further includes an input lead and / or an output lead coupled to a second side of the circuit module.

[0036] In some embodiments, the RF transistor amplifier further comprises a coupling element located between the RF transistor amplifier die and the circuit module, wherein the coupling element has a lower surface adjacent to a first main surface of the RF transistor amplifier die and a top surface facing the lower surface. The top surface of the coupling element comprises a gate connection pad configured to be connected to a first interconnection pad of the circuit module, a drain connection pad configured to be connected to a second interconnection pad of the circuit module, and a source connection pad configured to be connected to a third interconnection pad of the circuit module.

[0037] In some embodiments, the RF transistor amplifier further includes sidewalls and a lid. The carrier substrate, sidewalls, and lid define an internal cavity, and the RF transistor amplifier die is located within the internal cavity.

[0038] In some embodiments, the RF transistor amplifier further includes an overmolded material on the circuit module and the RF transistor amplifier die.

[0039] In some embodiments, the RF transistor amplifier die is a group III nitride-based RF transistor amplifier die.

[0040] In some embodiments, the operating frequency of the RF transistor amplifier is within the R-band, S-band, X-band, Ku-band, K-band, Ka-band, and / or V-band.

[0041] Upon review of the following drawings and detailed description, other devices, apparatuses, and / or methods according to some embodiments will become apparent to those skilled in the art. Any combination and all combinations of the above embodiments, in addition to all such additional embodiments, are intended to be incorporated within this description, within the scope of the invention, and protected by the appended claims. Brief explanation of the drawing

[0042] Figure 1a is a schematic cross-sectional view of a conventional high electron mobility transistor. FIG. 1b is a schematic side view of a conventional packaged group III nitride-based RF transistor amplifier. FIG. 1c is a schematic cross-sectional view taken along line (1C-1C) of FIG. 1b, illustrating the structure of the top metallization of the RF transistor amplifier die included in the RF transistor amplifier of FIG. 1b. FIG. 1d is a schematic side view of another conventional group III nitride-based RF transistor amplifier. FIG. 2a is a schematic side view of a group III nitride-based RF transistor amplifier according to some embodiments of the present invention. FIG. 2b is a schematic plan view of an RF transistor amplifier die, which is part of the group III nitride-based RF transistor amplifier of FIG. 2a, taken along the line (2B-2B) of FIG. 2a. FIG. 2c is a cross-sectional view taken along the line (2C-2C) of FIG. 2b. FIG. 2d is a cross-sectional view taken along the line (2D-2D) of FIG. 2b. FIG. 2e is a cross-sectional view taken along the line (2E-2E) of FIG. 2b. FIG. 2f is a cross-sectional view taken along the line (2F-2F) of FIG. 2b. FIGS. 2g to 2l are cross-sectional views of additional embodiments of the present invention. FIG. 3a is a schematic cross-sectional view of an RF transistor amplifier coupled to a circuit module according to some embodiments of the present invention. FIG. 3b is a schematic cross-sectional view of an RF transistor amplifier die coupled to a circuit module according to some embodiments of the present invention. FIG. 3c is a schematic cross-sectional view of an RF transistor amplifier die including a redistribution layer coupled to a circuit module according to some embodiments of the present invention. FIG. 3d is a schematic cross-sectional view of a circuit module coupled to a plurality of RF transistor amplifiers according to some embodiments of the present invention. FIG. 3e is a schematic cross-sectional view of a circuit module coupled to a plurality of RF transistor amplifier dies according to some embodiments of the present invention. FIG. 4a is a schematic cross-sectional view of an RF transistor amplifier and a circuit module coupled to a carrier substrate according to some embodiments of the present invention. FIG. 4b is a schematic cross-sectional view of an RF transistor amplifier and a circuit module coupled to a carrier substrate without coupling elements, according to some embodiments of the present invention. FIG. 4c is a schematic cross-sectional view of a plurality of RF transistor amplifier dies coupled to a circuit module and disposed on a carrier substrate according to some embodiments of the present invention. FIGS. 5a to 5c are schematic diagrams of various packaging options for an RF transistor amplifier according to some embodiments of the present invention. FIGS. 6a to 6c are schematic cross-sectional views of additional embodiments of an RF transistor amplifier coupled to a circuit module according to some embodiments of the present invention. FIGS. 7a through 7e are schematic diagrams illustrating methods of combining circuit modules and RF transistor amplifier dies according to specific embodiments of the present invention. FIGS. 8a and 8b are schematic cross-sectional views of various packaging options of a circuit module according to some embodiments of the present invention. FIG. 9a is a plan view of an embodiment of a circuit module according to some embodiments of the present invention. FIG. 9b is a cross-sectional view taken along the line (9B-9B) of FIG. 9a. FIG. 9c is a cross-sectional view taken along the line (9C-9C) of FIG. 9a. FIG. 9d is a cross-sectional view of the circuit module of FIG. 9a mounted on a substrate according to some embodiments of the present invention. FIGS. 10a and FIGS. 10b are schematic cross-sectional views of various packaging options of a circuit module according to some embodiments of the present invention. The dies in FIGS. 11a through 11d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier coupled to a circuit module according to some embodiments of the present invention. FIGS. 12a to 12d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die coupled to a circuit module according to some embodiments of the present invention. FIGS. 13a through 13d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die coupled to a circuit module and including a spacer, according to some embodiments of the present invention. FIGS. 14a through 14d are schematic cross-sectional views of various packaging options of a circuit module according to some embodiments of the present invention. FIGS. 15a through 15d are schematic cross-sectional views of additional RF transistor amplifier embodiments according to some embodiments of the present invention, comprising a circuit module and mechanisms for being coupled to first and second circuit elements. FIGS. 16a through 16d are schematic cross-sectional views of various packaging options of a circuit module according to some embodiments of the present invention. Specific details for implementing the invention

[0043] In the following detailed description, numerous specific details are described to provide a thorough understanding of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In some examples, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the present disclosure. All embodiments disclosed herein are intended to be implemented individually or combined in any manner and / or combination. Aspects described in connection with one embodiment may be incorporated into different embodiments, but are not specifically described therein. That is, features of all embodiments and / or any embodiments may be combined in any manner and / or combination.

[0044] According to embodiments of the present invention, RF transistor amplifiers based on Group III nitride are provided, comprising RF transistor amplifier dies having their own gate terminals, drain terminals, and source terminals, all located on the top side of the RF transistor amplifier dies. In some embodiments, the RF transistor amplifiers may not include junction wires for gate and drain connections, which may reduce the amount of inductance present in the circuit. The top side contacts may allow a coupling element to be directly coupled to the gate, drain, and source terminals of the RF transistor amplifier dies. The coupling element may additionally be connected in a convenient manner to additional circuits, such as a harmonic termination circuit, an input impedance matching circuit, and / or an output impedance matching circuit. In certain embodiments where the substrate of the transistor die has high thermal conductivity, such as a SiC growth substrate for a group III nitride-based HEMT, the die may be mounted on a thermally conductive carrier substrate or submount, such as a metal slug, lead frame, or flange, to provide improved heat dissipation of heat generated by the die from the amplifier package.

[0045] FIG. 1a is a schematic cross-sectional view of a conventional high electron mobility transistor (10). As shown in FIG. 1a, the high electron mobility transistor (10) may be formed on a substrate (22), such as silicon carbide, silicon, or sapphire. A channel layer (24) is formed on the substrate (22). A barrier layer (26) is formed on the channel layer (24) opposite the substrate (22). The channel layer (24) may comprise, for example, gallium nitride (GaN), and the barrier layer (26) may comprise, for example, aluminum gallium nitride (AlGaN).

[0046] The channel layer (24) and the barrier layer (26) can together form a semiconductor structure (90) on the substrate (22). A source contact (56) and a drain contact (54) are formed on the upper surface of the barrier layer (26) and are laterally spaced apart from each other. The source contact (56) and the drain contact (54) can form ohmic contacts with the barrier layer (26).

[0047] A gate contact (52) is formed on the upper surface of the barrier layer (26) between the source contact (56) and the drain contact (54). When the HEMT device (10) is biased to be in its conductive or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer (24) and the barrier layer (26). The 2DEG layer acts as a highly conductive layer that allows current to flow between the source and drain regions of the device located below the source contact (56) and the drain contact (54), respectively.

[0048] The source contact (56) can be coupled to a reference signal, such as a ground voltage. Coupling to the reference signal can be provided by a via (66) extending from the lower surface (22A) of the substrate (22) through the substrate (22) to the upper surface (26A) of the barrier layer. The via (66) can expose the lower surface (56A) of the source contact (56). A backmetal layer (35) can be formed on the lower surface (22A) of the substrate (22) and on the sidewalls of the via (66). The backmetal layer (35) can be in direct contact with the source contact (56). Accordingly, the backmetal layer (35) and the signal coupled thereto can be electrically connected to the source contact (56).

[0049] In some embodiments, one or more insulating layers (50) may be in direct contact with the upper surface of the semiconductor structure (90) (e.g., in contact with the upper surface (26A) of the barrier layer (26)). One or more insulating layers (50) may serve as passivation layers for the HEMT device (10). In some embodiments, additional metal contacts (not shown) may be provided to contact the gate contact (52) and / or drain contact (54).

[0050] As mentioned above, Group III nitride-based RF amplifiers, including the HEMT device exemplified in FIG. 1a, are often used in high-power and / or high-frequency applications. Typically, high levels of heat are generated within the Group III nitride-based RF amplifier die(s) during operation. If the RF die(s) become too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) may deteriorate and / or the RF amplifier die(s) may be damaged. Therefore, Group III nitride-based RF amplifiers that can be optimized for heat dissipation are typically mounted in packages. FIG. 1b and FIG. 1c illustrate a conventional packaged Group III nitride-based RF amplifier. In particular, FIG. 1b is a schematic side view of a conventional packaged group III nitride-based RF amplifier (100), and FIG. 1c is a schematic cross-sectional view of an RF transistor amplifier die included in the packaged group III nitride-based RF transistor amplifier (100), wherein the cross-section is taken along the line (1C-1C) of FIG. 1b. FIG. 1b through 1c (and various other figures) are highly simplified figures, and it will be recognized that actual RF amplifiers may include more unit cells and various circuits and elements not shown in the simplified figures herein.

[0051] As illustrated in FIG. 1b, a group III nitride-based RF amplifier (100) comprises an RF amplifier die (110) mounted within a package (170). The package (170) comprises a gate lead (172), a drain lead (174), a carrier substrate (176), and a housing (178). The RF transistor amplifier die (110) is mounted on the upper surface of the carrier substrate (176), which may include, for example, a metal flange. The RF amplifier die (110) has a top side (112) and a bottom side (114). The RF amplifier die (110) comprises a bottom side (also referred to as the “rear” side) metallization structure (120), a semiconductor layer structure (130), and a top side metallization structure (140) that are sequentially stacked. The rear side metallization structure (120) includes a source terminal (126). The RF amplifier (100) may be a HEMT-based RF amplifier such as that illustrated in FIG. 1a, in which case the semiconductor layer structure (130) may include at least a channel layer and a barrier layer formed on a semiconductor or insulating growth substrate (e.g., SiC, silicon, or sapphire substrate). The growth substrate may be considered part of the semiconductor layer structure (130) even if it is formed of a non-semiconductor material. The top metallization structure (140) includes, among other things, a gate terminal (142) and a drain terminal (144).

[0052] Input matching circuits (190) and / or output matching circuits (192) may also be mounted within the housing (178). The matching circuits (190, 192) may be impedance matching circuits that match the impedance of the fundamental component of RF signals input to or output from the RF transistor amplifier (100) to the impedance at the input or output of the RF transistor amplifier die (110), respectively, and / or harmonic termination circuits configured to short to ground the harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die (110), such as second or third harmonics. As schematically illustrated in FIG. 1b, the input and output matching circuits (190, 192) may be mounted on a metal flange (176). The gate lead (172) may be connected to an input matching circuit (190) by one or more first junction wires (182), and the input matching circuit (190) may be connected to the gate terminal (142) of the RF amplifier die (110) by one or more second junction wires (183). Similarly, the drain lead (174) may be connected to an output matching circuit (192) by one or more fourth junction wires (185), and the output matching circuit (192) may be connected to the drain terminal (144) of the RF amplifier die (110) by one or more third junction wires (184). The source terminal (126) of the RF transistor amplifier die (110) may be mounted directly on the metal flange (176). The metal flange (176) may provide an electrical connection to the source terminal (126) and may also serve as a heat dissipation structure. The first to fourth junction wires (182-185) may form part of the input and / or output matching circuits. The housing (178) may include a ceramic housing, and the gate lead (172) and drain lead (174) may extend through the housing (178).The housing (178) may include a plurality of pieces, such as a frame that forms the lower portion of the side walls and supports the gate and drain lids (172, 174), and a cover disposed on the uppermost portion of the frame. The interior of the device may include an air-filled cavity.

[0053] FIG. 1c is a schematic cross-sectional view of an RF amplifier die (110) taken through a portion of the uppermost metallized structure (140). Dielectric layers isolating various conductive elements of the uppermost metallized structure (140) from each other are not shown in FIG. 1c for the sake of simplicity.

[0054] As illustrated in FIG. 1c, the RF transistor amplifier die (110) comprises a group III nitride-based HEMT RF transistor amplifier having a plurality of unit cell transistors (116), each comprising a gate finger (152), a drain finger (154), and a source finger (156). The gate fingers (152) are electrically connected to a common gate manifold (146), and the drain fingers (154) are electrically connected to a common drain manifold (148). A gate manifold (146) is electrically connected to a gate terminal (142), which can be implemented as a gate junction pad (see FIG. 1b), (e.g., via a conductive via extending upward from the gate manifold (146)), and a drain manifold (148) is electrically connected to a drain terminal (144), which can be implemented as a drain junction pad (see FIG. 1b), (e.g., via a conductive via extending upward from the drain manifold (148)). Source fingers (156) are electrically connected to a source terminal (126) through a plurality of conductive source vias (166) extending through a semiconductor layer structure (130). The conductive source vias (166) may include metal-plated vias that extend through the semiconductor layer structure (130) completely.

[0055] Referring again to FIG. 1b, the carrier substrate (176) (here, a metal flange) can act as a heat sink to dissipate heat generated in the RF amplifier die (110). Heat is generated mainly in the upper part of the RF amplifier die (110), where relatively high current densities are generated, for example, in the channel regions of the unit cell transistors (116). This heat can be transferred to the carrier substrate (176) through both the source vias (166) and the semiconductor layer structure (130).

[0056] FIG. 1d is a schematic side view of a conventional packaged Group III nitride-based RF transistor amplifier (100') similar to the RF transistor amplifier discussed above with reference to FIG. 1b. The RF transistor amplifier (100') differs from the RF transistor amplifier (100) in that it includes a different package (170'). The package (170') includes a metal submount (176) (which acts as a metal heat sink and may be implemented as a metal slug) as well as gate and drain leads (172', 174'). In some embodiments, a metal lead frame may be formed, which is then processed to provide the metal submount (176) and / or the gate and drain leads (172', 174'). The RF transistor amplifier (100') also includes a plastic overmold (178') that at least partially surrounds the RF transistor amplifier die (110), leads (172', 174'), and metal submount (176). The plastic overmold (178') replaces the ceramic sidewalls and cover (178) included in the RF transistor amplifier (100).

[0057] According to an embodiment, the packaged transistor amplifier (100') may include a monolithic microwave integrated circuit (MMIC) as, for example, an RF transistor amplifier die (110), in which case the RF transistor amplifier die (110) includes a plurality of individual devices. In some embodiments, the packaged RF transistor amplifier (100) may include multiple RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier, and / or multiple transistor dies arranged in multiple paths (e.g., in parallel) to form an RF transistor amplifier having multiple RF transistor amplifier dies and multiple paths, as in a Doherty amplifier configuration.

[0058] In other cases, Group III nitride-based RF amplifiers may be implemented as MMIC devices in which one or more RF amplifier die(s) are implemented together with their associated impedance matching and harmonic termination circuits on a single integrated circuit die. Examples of such Group III nitride-based RF amplifiers are disclosed, for instance, in U.S. Patent No. 9,947,616, the entire contents of which are incorporated herein by reference. When the RF transistor amplifier die (110) is an MMIC implementation, the input matching circuits (190) and / or output matching circuits (192) may be omitted (since they can be implemented within the RF transistor amplifier die (110) instead), and the junction wires (182 and / or 185) may be extended directly from the gate and drain leads (172', 174') to the gate and drain terminals (142, 144).

[0059] Conventional group III nitride-based RF transistor amplifiers, such as the RF transistor amplifier (100) of FIGS. 1a through 1d, may use junction wires (182, 184) to connect the RF transistor amplifier die (110) to other parts of the package. These junction wires (182, 184) have an inherent inductance that can be used to implement some of the inductors in the impedance matching and / or harmonic termination circuits of the RF transistor amplifiers. The amount of inductance provided may be varied by changing the length and / or cross-sectional area (e.g., diameter) of the junction wires (182, 184) so ​​that the junction wires (182, 184) provide the desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the junction wires (182, 184) may exceed the desired amount of inductance for impedance matching and / or harmonic termination circuits. When this occurs, junction wires (182, 184) with very short and / or large cross-sectional areas may be used in an effort to reduce their inductance to suitable levels. However, very short junction wires (182, 184) may be difficult to solder in the proper place, which may increase manufacturing costs and / or result in a higher device failure rate. Junction wires (182, 184) with large cross-sectional areas may require larger gate and drain junction pads on the RF transistor amplifier die, which may result in an increase in the overall size of the RF transistor amplifier die, which is also undesirable. Furthermore, in some higher frequency applications, even very short junction wires (182, 184) with large cross-sectional areas can have too much inductance, and consequently, matching networks cannot properly terminate, for example, second or third harmonics.RF transistor amplifiers can be implemented as MMIC devices to avoid the problem of too much inductance in the junction wires (182, 184), but MMIC RF amplifiers are more expensive to manufacture and can only be used within the frequency range of the matching circuits, thus reducing flexibility.

[0060] Furthermore, wire splicing equipment typically used for mass manufacturing may have a tolerance of + / -1 mil, which means that the length of any particular wire splicing can vary by 2 mil (i.e., + / -1 mil at each end of the spliced ​​wire). For high-frequency applications, the variation in inductance associated with a 2 mil wire splicing can be significant; therefore, if the spliced ​​wire is 1-2 mil too short or too long from the desired nominal length, the performance of the matching circuits may degrade. Forming gate and drain terminals on the top side of the device and using a coupling element to connect these terminals to additional circuits can largely eliminate these process variations, resulting in improved performance.

[0061] Embodiments of the present invention will now be discussed in more detail with reference to the attached drawings.

[0062] FIGS. 2a through 2g illustrate a Group III nitride-based RF transistor amplifier (200) according to specific embodiments of the present invention. In particular, FIG. 2a is a schematic side view of a Group III nitride-based RF transistor amplifier (200). FIG. 2b is a schematic plan view of an RF transistor amplifier die (210), which is part of the Group III nitride-based RF transistor amplifier (200) of FIG. 2a, taken along the line (2B-2B) of FIG. 2a. FIGS. 2c through 2f are schematic cross-sectional views of the RF transistor amplifier die (210), taken along the lines (2C-2C through 2F-2F) of FIG. 2b, respectively. FIG. 2g is an alternative embodiment of the source terminal illustrated in FIG. 2d. FIGS. 2h through 2l are cross-sectional views of additional embodiments of Group III nitride-based RF transistor amplifiers (200', 200'') according to specific embodiments of the present invention.

[0063] As illustrated in FIG. 2a, in some embodiments, a group III nitride-based RF transistor amplifier (200) may include an RF transistor amplifier die (210) mounted on the bottom surface of a coupling element (270). The RF transistor amplifier die (210) has a top side (212) and a back side (214). The RF transistor amplifier die (210) includes a top side metallization structure (220), a semiconductor layer structure (230), and a bottom side thermal layer (240) that are sequentially stacked. The top side metallization structure (220) includes a gate terminal (222), a drain terminal (224), and one or more source terminal(s) (226). The RF transistor amplifier (200) may be a HEMT-based RF transistor amplifier, in which case the semiconductor layer structure (230) may include at least a channel layer and a barrier layer, as will be discussed in more detail with reference to FIG. 2c and FIG. 2d. In some configurations, as will be further discussed herein, the coupling element (270) may be omitted from the RF transistor amplifier (200).

[0064] The coupling element (270) may be configured to be coupled to a gate terminal (222), a drain terminal (224), and one or more source terminal(s) (226). In some cases, the coupling element (270) may include a redistribution layer (RDL) layered structure and / or an interposer. An RDL layered structure refers to a substrate having conductive layer patterns and / or conductive vias. RDL layered structures may be manufactured using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a base material and by forming vias and routing patterns (e.g., copper) within a structure for transmitting signals through the RDL layered structure. For example, as illustrated in FIG. 2a, the coupling element (270) may include conductive patterns (273) formed within an encapsulation structure (277).

[0065] A gate connection pad (272), a drain connection pad (274), and a source connection pad (276) are provided on the uppermost surface of the coupling element (270). Each of these connection pads (272, 274, 276) may include, for example, an exposed copper pad, but the invention is not limited thereto. The gate connection pad (272) may be electrically coupled to the gate terminal (222) by one or more conductive patterns (273) in the coupling element (270). Similarly, the drain connection pad (274) may be electrically coupled to the drain terminal (224) by one or more conductive patterns (273) of the coupling element (270), and the source connection pad (276) may be electrically coupled to the source terminal(s) (226) by one or more conductive patterns (273) of the coupling element (270).

[0066] In some embodiments, the conductive patterns (273) of the coupling element (270) may be configured in a fan-out (FO) configuration. The FO configuration may allow for increased separation of connections by allowing the spacing of connections to individual source, gate, and drain terminals to be extended. However, the invention is not limited to FO connections. In some embodiments, fan-in connections, fan-in and fan-out configurations, or other configurations may be used.

[0067] In some embodiments, the coupling element (270) and / or RDL layered structure may be formed as part of a wafer-level processing (WLP) operation, but the invention is not limited thereto. For example, the coupling element (270) may be formed by placing conductive pillars on a gate terminal (222), a drain terminal (224), and one or more source terminal(s) (226). In some embodiments, the conductive pillars may comprise copper. For example, the conductive pillars may be formed by electroplating a copper seed using one or more masks to form patterns. The conductive pillars may form conductive patterns (273). Furthermore, the gate connection pad (272), drain connection pad (274), and source connection pad (276) may be formed on the conductive patterns (273). The conductive patterns (273), gate connection pad (272), drain connection pad (274), and source connection pad (276) may be at least partially disposed within an encapsulation structure (277) that may include an overmolding material. The overmolding material may include, for example, silicon oxide, silicon nitride, oxide of the conductive patterns (273), polymer, molding compound, and / or combinations thereof. The overmolding material may be processed (e.g., flattened) to expose the gate connection pad (272), drain connection pad (274), and / or source connection pad (276). In some embodiments, the formation of the coupling element (270) may be performed at the wafer level, and individual RF transistor amplifier dies (210) and / or RF transistor amplifiers (200) may be singulated from the wafer.

[0068] In some embodiments, the bonding element (270) may be formed in a chip-first or chip-last process. In a chip-first process, the RDL structure may be formed on the die (210) (or a wafer containing the die (210)). For example, a seed layer may be deposited (e.g., on one or more of the gate terminal (222), drain terminal (224), and one or more source terminal(s) (226). Subsequently, the seed may be patterned and electroplated to form a layer of conductive material. This process may be repeated multiple times to form conductive patterns (273) of the bonding element (270). Subsequently, these conductive patterns (273) may be enclosed in an encapsulation structure (277) to form the bonding element (270).

[0069] In a chip-last process, the RDL layers of the bonding element (270) may be formed on a temporary carrier layer. Conductive patterns (273) may be formed on the temporary carrier layer in a manner similar to a chip-first process. When completed, the bonding element (270) may be disassembled from the temporary carrier layer and subsequently reassembled into the die (210). For example, the bonding element (270) may be bonded (e.g., by soldering) to one or more of the gate terminal (222), drain terminal (224), and one or more source terminal(s) (226).

[0070] For example, other coupling elements (270), such as a printed circuit board (e.g., a multilayer printed circuit board), a ceramic substrate including conductive vias and / or pads, or any coupling structure for an RF transistor amplifier die (210) capable of forming electrical connections to the upper side (212) of the RF transistor amplifier die (210), may be used alternatively.

[0071] The arrangement of conductive patterns (273) illustrated in FIG. 2a is merely an example, and other arrangements are possible without departing from the invention. For example, in some embodiments, the conductive patterns (273) of the coupling element (270) may extend adjacent to the sides of the RF transistor amplifier die (210). In some embodiments, the coupling element (270) may have terminals other than those illustrated in FIG. 2a.

[0072] A thermal layer (240) may be on the rear side (214) of the RF transistor amplifier die (210). The thermal layer (240) may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die (210) and the carrier substrate on which the RF transistor amplifier die (210) is mounted. In some embodiments, the thermal layer (240) may be omitted. In some embodiments, the thermal layer (240) may be a die attachment layer such as a eutectic layer. The thermal layer (240) may be on the transistor amplifier die (210) and / or may extend onto the encapsulation structure (277). The thermal layer (240) may be a metal layer for forming a eutectic or other metal bond. In some embodiments, the thermal layer (240) may be a thermal adhesive.

[0073] The RF transistor amplifier die (210) may include a group III nitride-based HEMT RF transistor amplifier comprising a plurality of unit cell transistors (216) electrically connected in parallel with one another. This is most clearly seen in FIG. 2b, which schematically illustrates a plan view of the RF transistor amplifier die (210) under the top-side metallization structure (220). The top-side metallization structure (220), comprising a gate terminal (222), a drain terminal (224), and one or more source terminals (226), is illustrated by dashed lines in FIG. 2b.

[0074] As illustrated in FIG. 2b, the RF transistor amplifier die (210) comprises a gate manifold (242) and a drain manifold (244), a plurality of gate fingers (252), a plurality of drain fingers (254), and a plurality of source fingers (246), all of which may be formed on the upper surface of a semiconductor layer structure (230). The gate manifold (242) and the gate fingers (252) are part of the gate electrode of the RF transistor amplifier die (210). The gate manifold (242) and the gate fingers (252) may be implemented as a first monolithic metal pattern, but the invention is not limited thereto. The drain manifold (244) and the drain fingers (254) are part of the drain electrode of the RF transistor amplifier die (210) and may be implemented as a second monolithic metal pattern, but the invention is not limited thereto.

[0075] The gate fingers (252) may be formed of a material capable of forming Schottky contacts with a Group III nitride-based semiconductor material such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain fingers (254) and source fingers (246) may comprise a metal (e.g., TiAlN, TiSiNi, etc.) capable of forming ohmic contacts with Group III nitride-based materials. A dielectric layer (or a series of dielectric layers) that helps isolate the gate manifold / fingers (242, 252), drain manifold / fingers (244, 254), and source fingers (246) from each other is not shown in FIG. 2b to better illustrate the elements of the RF transistor amplifier die (210).

[0076] A gate terminal (222), a drain terminal (224), and source terminal(s) (226) may be provided on the upper surface of an RF transistor amplifier die (210). The gate terminal (222) may be physically and electrically connected to a gate manifold (242) (e.g., by conductive vias), the source terminal(s) (226) may be physically and electrically connected to source fingers (246) (e.g., by conductive vias), and the drain terminal (224) may be physically and electrically connected to a drain manifold (244) (e.g., by conductive vias). While various terminals are exemplified as being directly connected to the gate / drain manifold and / or source fingers, it will be understood that in some embodiments, intermediate elements may be present. For example, in some embodiments, capacitors, inductors, resistors, etc. may be coupled between the terminal and the individual manifold and / or fingers. For example, a capacitor may be formed on the surface of an RF transistor amplifier die (210) that is coupled to a drain manifold (244), and a drain terminal (224) may be coupled to the capacitor.

[0077] One of the unit cell transistors (216) is also illustrated in FIG. 2b. As illustrated, the unit cell transistor (216) includes a gate finger (252), a drain finger (254), and a source finger (246) together with a base portion of the semiconductor layer structure (230). Since all of the gate fingers (252) are electrically connected to a common gate manifold (242), all of the drain fingers (254) are electrically connected to a common drain manifold (244), and all of the source fingers (246) are electrically connected together through source terminal(s) (226) (discussed below), it can be seen that all of the unit cell transistors (216) are electrically connected in parallel together.

[0078] The unit cell transistors (216) may be HEMT devices. Suitable structures for Group III nitride-based HEMT devices capable of utilizing embodiments of the present invention are, for example, co-assigned U.S. Patent Publication No. 2002 / 0066908A1 titled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same" disclosed on June 6, 2002; U.S. Patent Publication No. 2002 / 0167023A1 titled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer" disclosed on November 14, 2002; and U.S. Patent Publication No. 2002 / 0167023A1 titled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses" disclosed on April 1, 2004. As described in U.S. Patent No. 2004 / 0061129, U.S. Patent No. 7,906,799 titled “Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess” granted on March 15, 2011, and U.S. Patent No. 6,316,793 titled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates” granted on November 13, 2001, the disclosures thereof are incorporated herein by reference in their entirety.

[0079] Referring to FIGS. 2c and 2d, the semiconductor layer structure (230) comprises a plurality of semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers are illustrated, namely, a channel layer (234) and a barrier layer (236) located on the upper side of the channel layer (234). The semiconductor layer structure (230) may include additional semiconductor and / or non-semiconductor layers. For example, the semiconductor layer structure (230) may include a growth substrate (232) on which other semiconductor layers are grown. The growth substrate (232) may be a semi-insulating silicon carbide (SiC) substrate, for example, which may be a silicon carbide 4H polytype. Other silicon carbide candidate polytypes may include 3C, 6H, and 15R polytypes. The growth substrate (232) may be a High Purity Semi-Insulating (HPSI) substrate available from Cree, Inc. The term “semi-insulating” is used herein descriptively rather than in an absolute sense.

[0080] In some embodiments of the present invention, the silicon carbide bulk crystal of the growth substrate (232) is about 1 x 10⁻⁶ at room temperature. 5It may have a resistivity of ohm-cm or greater. Exemplary SiC substrates that may be used in some embodiments of the present invention are manufactured, for example, by Cree, Incorporated, Durham, North Carolina, the assignee of the present invention, and methods for producing such substrates are described, for example, in U.S. Patent No. Re. 34,861, U.S. Patent No. 4,946,547, U.S. Patent No. 5,200,022, and U.S. Patent No. 6,218,680, the disclosures thereof are incorporated herein by reference in their entirety. While silicon carbide may be used as a substrate material, embodiments of the present application may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The growth substrate (232) may be a silicon carbide wafer, and the RF transistor amplifier (200) may be formed at least partially through wafer-level processing, and the wafer may then be diced to provide a plurality of individual RF transistor amplifiers (200).

[0081] SiC has a crystal lattice match much closer to Group III nitrides than sapphire (Al2O3) or silicon, which are very common substrate materials for Group III nitride devices. The closer lattice match of SiC can result in higher quality Group III nitride films than are generally available on sapphire or silicon. SiC also has very high thermal conductivity, and accordingly, the total output power of Group III nitride devices on silicon carbide is typically not limited by the heat dissipation of the substrate, as is the case with the same devices formed on sapphire. Additionally, the availability of semi-insulating SiC substrates can provide device isolation and reduced parasitic capacitance.

[0082] Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the growth substrate (232) below the channel layer (234). For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate (232) and the remainder of the semiconductor layer structure (230). Additionally, strain-balanced transition layer(s) may also be provided, for example, as described in U.S. Patent Publication No. 2003 / 0102482A1, co-assigned and published June 5, 2003, titled “Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” the disclosure of which is incorporated herein by reference as fully described herein.

[0083] The channel layer (234) and the barrier layer (236) may each be formed by epitaxial growth, in some embodiments. Techniques for the epitaxial growth of group III nitrides are described, for example, in U.S. Patent No. 5,210,051, U.S. Patent No. 5,393,993, and U.S. Patent No. 5,523,589, the disclosures thereof are also incorporated herein by reference in their entirety. The channel layer (234) may have a bandgap smaller than that of the barrier layer (236), and the channel layer (234) may also have an electron affinity greater than that of the barrier layer (236). The channel layer (234) and the barrier layer (236) may comprise group III nitride-based materials.

[0084] In some embodiments, if the energy of the conduction band edge of the channel layer (234) is less than the energy of the conduction band edge of the barrier layer (236) at the interface between the channel layer (234) and the barrier layer (236), the channel layer (234) is a group III nitride material, such as Al x Ga1-x N, and here, In certain embodiments of the present invention, x = 0 indicates that the channel layer (234) is gallium nitride ("GaN"). The channel layer (234) may also be other group III nitrides, such as InGaN, AlInGaN, etc. The channel layer (234) may be undoped or unintentionally doped and may be grown to a thickness greater than, for example, about 2 nm. The channel layer (234) may also be a multilayer structure, such as a superlattice or combination of GaN, AlGaN, etc.

[0085] The channel layer (234) may have a band gap smaller than at least a portion of the band gap of the barrier layer (236), and the channel layer (234) may also have an electron affinity greater than that of the barrier layer (236). In certain embodiments, the barrier layer (236) is AlN, AlInN, AlGaN, or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In certain embodiments, the barrier layer (236) has a sufficiently high Al composition and doping and is thick enough to induce a significant carrier concentration at the interface between the channel layer (234) and the barrier layer (236).

[0086] The barrier layer (236) may be a group III nitride and may have a bandgap greater than the bandgap of the channel layer (234) and an electron affinity smaller than that of the channel layer (234). Accordingly, in certain embodiments of the present invention, the barrier layer (236) may comprise AlGaN, AlInGaN, and / or AlN or a combination of layers thereof. The barrier layer (236) may be, for example, about 0.1 nm to about 30 nm thick. In certain embodiments, the barrier layer (236) may be undoped or about 10 as an n-type dopant 19 cm -3 It is doped to a concentration of less than . In some embodiments of the present invention, the barrier layer (236) is Al x Ga 1-xN, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the invention, the barrier layer (236) comprises AlGaN having an aluminum concentration of about 5% to about 100%. In certain embodiments of the invention, the aluminum concentration is greater than about 10%.

[0087] Due to the difference in bandgap between the barrier layer (236) and the channel layer (234) and the piezoelectric effects at the interface between the barrier layer (236) and the channel layer (234), a two-dimensional electron gas (2DEG) is induced into the channel layer (234) at the junction between the channel layer (234) and the barrier layer (236). The 2DEG acts as a highly conductive layer that allows conduction between the source region and its associated drain region of each unit cell transistor (216), where the source region is a part of the semiconductor layer structure (230) located directly below the source finger (246) and the drain region is a part of the semiconductor layer structure (230) located directly below the corresponding drain finger (254).

[0088] For the purposes of illustration, a semiconductor structure (230) having a channel layer (234) and a barrier layer (236) is illustrated, but the semiconductor structure (230) may include additional layers / structures / elements such as a buffer and / or nucleation layer(s) between the channel layer (234) and the substrate (232), and / or a cap layer on the barrier layer (236). HEMT structures comprising substrates, channel layers, barrier layers, and other layers are discussed by example in U.S. Patent No. 5,192,987, U.S. Patent No. 5,296,395, U.S. Patent No. 6,316,793, U.S. Patent No. 6,548,333, U.S. Patent No. 7,544,963, U.S. Patent No. 7,548,112, U.S. Patent No. 7,592,211, U.S. Patent No. 7,615,774, U.S. Patent No. 7,548,112, and U.S. Patent No. 7,709,269, the disclosures thereof are incorporated herein by reference in their entirety. For example, an AlN buffer layer may be formed on the upper surface of the substrate (232) to provide a suitable crystal structure transition between the silicon carbide substrate (232) and the remainder of the RF transistor amplifier (200). Additionally, strain-balancing transition layer(s) may also and / or alternatively be provided as described, for example, in the jointly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as fully described herein. Optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0089] An interlayer insulating layer (238) is formed on the gate finger (252), drain finger (254), and source finger (246). The interlayer insulating layer (238) may include a dielectric material such as SiN, SiO2, etc.

[0090] The coupling element (270) may be on the semiconductor layer structure (230) and / or may be coupled thereto. For example, conductive patterns (273) may be coupled between the gate connection pad (272) and the gate terminal (222), between the drain connection pad (274) and the drain terminal (224), and between the source connection pad (276) and the source terminal (226), respectively. In FIG. 2c, the encapsulation structure (277) of the coupling element (270) is omitted for ease of explanation. The gate connection pad (272), drain connection pad (274), and source connection pad (276) of the coupling element (270) may extend perpendicularly to the gate fingers (252) and drain fingers (254).

[0091] By placing all terminals on the upper side of the RF transistor amplifier die (210), the RF transistor amplifier (200) according to specific embodiments of the present invention may omit vias on the rear side of the RF transistor amplifier die (210). If there are no vias on the rear side of the RF transistor amplifier die (210) connecting the source to a grounded electrically conductive submount, the conductive submount does not need to be electrically active. Additionally, the rear side of the substrate (232) of the RF transistor amplifier die (210) may be thermally coupled to a thermally conductive submount, such as a heat sink or flange (not shown), to provide improved heat dissipation. In some embodiments, a thermal layer (240) may facilitate this thermal coupling. When SiC is used as the substrate material, the thermal properties of the package may be further improved due to the improved thermal conductivity of SiC.

[0092] Furthermore, placing all the terminals on the upper side of the RF transistor amplifier die (210) allows for the use of a coupling element (270), which can bring all the transistor connections to individual connection pads. This allows the RF transistor amplifier die (210) to be additionally coupled to other elements of the circuit (e.g., other routing elements, ground elements, harmonics and / or input / output impedance matching elements) through the use of connection methods that avoid junction wires such as soldering.

[0093] FIG. 2d illustrates examples of connections between various source fingers (246) and source terminals (226). As illustrated in FIG. 2d, each source finger (246) may be coupled to an individual source terminal (226), but the invention is not limited thereto. In some embodiments, one or more source terminals (226) may be coupled to more than one source finger (246). For example, as illustrated in FIG. 2g, in some embodiments, a single source terminal (226) may be provided, and the source terminal (226) may be connected to each individual source finger (246). In some embodiments, a plurality of source terminals (226) may be provided, and each of these is connected to a plurality of source fingers (246). One or more source terminals (226) may be coupled to a source connection pad (276) by conductive patterns (273) of a coupling element (270).

[0094] FIG. 2e illustrates examples of connections between a gate manifold (242) and a gate terminal (222). As illustrated in FIG. 2e, the gate manifold (242) may be coupled to the gate terminal (222), for example, by a plurality of vias. FIG. 2f illustrates examples of connections between a drain manifold (244) and a drain terminal (224). As illustrated in FIG. 2e, the drain manifold (244) may be coupled to the drain terminal (224), for example, by a plurality of vias. In both FIG. 2e and FIG. 2f, the gate terminal (222) and / or the drain terminal (224) may be coupled to the gate connection pad (272) and / or the drain connection pad (274) of the coupling element (270), respectively, by one or more conductive patterns (273).

[0095] FIGS. 2c, 2e, and 2f illustrate embodiments in which the gate manifold (242) and the gate terminal (222) are separate elements and the drain gate manifold (244) and the drain terminal (224) are separate elements (e.g., connected by vias), but the invention is not limited thereto. For example, FIGS. 2h through 2j illustrate examples in which the gate / drain manifold and the terminal are a single element. For example, referring to FIGS. 2h and 2i, the device (200') may be configured such that the gate manifold (242) extends to the surface of the RF transistor amplifier die (210) to serve as the gate terminal (222). Similarly, FIGS. 2h and 2j illustrate that the device (200') can be configured so that the drain manifold (244) extends to the surface of the RF transistor amplifier die (210) to serve as a drain terminal (224).

[0096] In some embodiments, additional conductive elements and / or individual circuit components may be formed as part of the RF transistor amplifier die. FIG. 2k illustrates an additional embodiment of the RF transistor amplifier die (210') according to some embodiments of the present invention. FIG. 2k is an embodiment illustrated in terms of lines (2C-2C) of FIG. 2a with modifications as described herein. For example, as illustrated in FIG. 2k, the RF transistor amplifier die (210') may utilize a plurality of conductive patterns (223) between the gate manifold (242) and the gate terminal (222), between the drain gate manifold (244) and the drain terminal (222), and / or between one or more of the source fingers (246) and the source terminal (246). The conductive patterns (223) may be formed within the interlayer insulating layer (238) of the RF transistor amplifier die (210').

[0097] Conductive patterns (223) can be utilized to form individual circuit elements integrated into the RF transistor amplifier die (210'). For example, the conductive patterns (223) can form an RDL within the RF transistor amplifier die (210'). FIG. 2k illustrates a fan-in configuration in which gate / drain manifolds (242, 244) and source fingers (246) are coupled to the gate, drain, and source terminals (222, 224, 226), respectively. However, the invention is not limited thereto. In some embodiments, the conductive patterns (223) may also be coupled to individual circuit elements within an interlayer insulation layer (238), as in an MMIC configuration. The use of an on-die RDL may allow for more flexible packaging options as well as the integration of specific circuit functions, such as impedance matching and / or harmonic termination.

[0098] FIG. 21 illustrates that an RF transistor amplifier die (210') can also be used with a coupling element (270) in an RF transistor amplifier (200). An embodiment of FIG. 21 may include a first RDL as part of the RF transistor amplifier die (210') and a second RDL as part of the coupling element (270). In some embodiments, the conductive patterns (223) of the RF transistor amplifier die (210') may provide one or more additional integrated circuits, such as impedance matching or harmonic termination, and the conductive patterns (273) of the coupling element (270) may provide fan-in, fan-out, or other configurations. In some embodiments, the combination of the coupling element (270) and the RF transistor amplifier die (210') may be enclosed in an encapsulation structure (not shown).

[0099] FIGS. 2a through 2l illustrate a semiconductor layer structure (230) including a HEMT, and it will be understood that other types of semiconductor devices may be formed in the semiconductor layer structure (230) without departing from the invention. For example, the semiconductor layer structure (230) may include a MOSFET, a DMOS transistor, a MESFET, and / or an LDMOS transistor. A person skilled in the art will recognize that arranging all source / drain / gate contacts on a single side of the semiconductor layer structure (230), including the use of a coupling element (270), may allow for improved connectivity possibilities and better thermal performance.

[0100] By placing the gate, drain, and source contacts on the same side of the RF transistor amplifier (200), connection options that were previously not possible may be available. These connection options may also allow for embodiments that can more strongly utilize the improved thermal conductivity of SiC materials.

[0101] FIG. 3a is a schematic cross-sectional view of an RF transistor amplifier (200) coupled to a circuit module (310) according to some embodiments of the present invention. FIG. 3a includes elements of the RF transistor amplifier (200) previously discussed. Therefore, the discussion of FIG. 3a will focus on such parts that differ from those discussed in relation to the previous drawings among the embodiments.

[0102] Referring to FIG. 3a, the circuit module (310) may be configured to be coupled to the gate connection pad (272), drain connection pad (274), and source connection pad (276) of the coupling element (270). For example, the circuit module (310) may expose interconnection pads (322, 324, 326) that may be configured to be coupled to the gate connection pad (272), drain connection pad (274), and source connection pad (276). For example, the first interconnection pad (322) may be configured to be coupled to the gate connection pad (272), the second interconnection pad (324) may be configured to be coupled to the drain connection pad (274), and the third interconnection pad (326) may be configured to be coupled to the source connection pad (276). In some embodiments, a bonding element (e.g., solder balls and / or bumps (320)) may be used to bond the first, second, and third interconnect pads (322, 324, 326) to the gate connection pad (272), drain connection pad (274), and source connection pad (276), respectively. Although exemplified as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads (322, 324, 326) may include a plurality of pads.

[0103] Each of the first, second, and third interconnect pads (322, 324, 326) can be coupled to one or more conductive patterns (373) within the circuit module (310). The conductive patterns (373) can provide various routing and / or circuits within the circuit module (310). For example, the conductive patterns (373) can connect the first interconnect pad (322) to one or more first surface connection pads (372) and one or more gate lead connection pads (382). Accordingly, the gate connection pad (272) can be electrically coupled to one or more first surface connection pads (372) and one or more gate lead connection pads (382). The conductive patterns (373) can also connect the second interconnect pad (324) to one or more second surface connection pads (374) and one or more drain lead connection pads (384). Accordingly, the drain connection pad (274) can be electrically coupled to one or more second surface connection pads (374) and one or more drain lead connection pads (384). Conductive patterns (373) can also connect the third interconnect pad (326) to one or more third surface connection pads (376) and one or more source lead connection pads (386). Accordingly, the source connection pad (276) can be electrically coupled to one or more third surface connection pads (376) and one or more source lead connection pads (386). Accordingly, the circuit module (310) may have a surface (e.g., a top surface) having a plurality of first surface connection pads (372) — each of these first surface connection pads is connected to a gate connection pad (272) of the coupling element (270) — a plurality of second surface connection pads (374) — each of these second surface connection pads is connected to a drain connection pad (274) of the coupling element (270) — and a plurality of third surface connection pads (376) — each of these third surface connection pads is connected to a source connection pad (276) of the coupling element (270).

[0104] The conductive patterns (373) may be encased within the insulating material (315). In some embodiments, the insulating material (315) may comprise, for example, silicon oxide, silicon nitride, an oxide of the conductive patterns (273), a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module (310) may be formed as a printed circuit board (PCB). In the PCB embodiment, the insulating material (315) may be a substrate of the PCB, and the conductive patterns (373) may be traces formed within the substrate.

[0105] The presence of the conductive pattern (373) and the first, second, and third surface connection pads (372, 374, 376) may allow a number of different circuits to be coupled to the RF transistor amplifier (200). For example, circuit elements (350) may be coupled between two or more of the first, second, and third surface connection pads (372, 374, 376) (e.g., through soldering or other joining). The circuit elements (350) may provide various electronic capabilities to the RF transistor amplifier (200). For example, the circuit elements (350) may include impedances (e.g., including resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, the circuit elements (350) may provide stripline components and / or baseband termination to the RF transistor amplifier (200).

[0106] Although illustrated as being on the surface of the circuit module (310), it will be understood that additional circuit elements (350) may be provided internally within the circuit module (310). For example, one or more ground planes may be formed within the circuit module (310) as circuit elements (350). Similarly, a stripline may be formed within the circuit module (310) (e.g., together with one or more ground planes). The configurations of the conductive patterns (373) and circuit elements (350) illustrated in FIG. 3a are merely examples and are not intended to limit embodiments of the invention. In some embodiments, the circuit elements (350) and / or the conductive patterns (373) may be configured to provide at least part of a harmonic termination circuit, a matching circuit, a split circuit, a coupling circuit, and / or a biasing circuit. Conductive patterns (373) of other configurations and / or circuit elements (350) of other types may be used without departing from the scope of the invention.

[0107] In some embodiments, the circuit module (310) and circuit elements (350) may optionally be enclosed within an encapsulation material (316). In some embodiments, the encapsulation material (316) may comprise, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof.

[0108] The gate lead connection pads (382), drain lead connection pads (384), and source lead connection pads (386) may provide terminals for connecting signals to individual gates, drains, and sources of the RF transistor amplifier (200). For example, a connection for providing an input signal to the RF transistor amplifier (200) may be coupled to one or more of the gate lead connection pads (382). In some embodiments, a connection for receiving an output signal from the RF transistor amplifier (200) may be coupled to the drain lead connection pads (384). In some embodiments, a ground signal may be coupled to the source lead connection pads (386), but the invention is not limited thereto. The gate lead connection pads (382), drain lead connection pads (384), and source lead connection pads (386) are exemplified as being on the bottom surface of the circuit module (310), but this is merely an example and is not intended to limit the invention. In some embodiments, various lead connections may be on the top or other surface of the circuit module (310).

[0109] Using a circuit module (310) together with the upper side contacts of the RF transistor amplifier (200) allows additional functionalities, such as impedance matching and / or harmonic termination, to be conveniently added to the RF transistor amplifier (200) without the use of extensive wire junctions. Accordingly, different functionalities and / or capabilities can be combined in the RF transistor amplifier (200) simply by using different circuit modules (310). Because the connection points (e.g., terminals) of the RF transistor amplifier (200) are consistent, variations in the configuration of the RF transistor amplifier (200) can be achieved more efficiently than previously available. The reduced or eliminated need for wire junctions can also allow for a reduced die size in some applications (where the sizes of the wire junction pads drive the die size), and thus, RF transistor amplifier dies according to embodiments of the present invention can also exhibit increased integration density. Accordingly, the RF amplifier die according to the embodiments of the present invention can exhibit improved product assembly consistency, higher yields, increased product integration, reduced cost, and improved RF performance, particularly for products operating at high frequencies such as millimeter wave frequencies.

[0110] The techniques disclosed herein may be particularly beneficial in higher frequency applications because the inductance required in matching circuits may be much lower in such applications, and therefore, the use of conventional junction wires may introduce too much inductance. Additionally, tolerances in junction wire lengths may have a greater impact at higher frequencies, and in high frequency applications (especially in the case of lower power), the size of the junction pads may lead the size of the die. In some embodiments, any of the RF transistor amplifier dies disclosed herein may be configured to operate at frequencies greater than 1 GHz. In other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 2.5 GHz. In yet another embodiment, these RF transistor amplifier dies may be configured to operate at frequencies greater than 3.1 GHz. In further additional embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, or 5.1 - 5.8 GHz frequency bands or sub-parts thereof.

[0111] FIG. 3b is a schematic cross-sectional view of an RF transistor amplifier die (210) coupled to a circuit module (310) according to some embodiments of the present invention. FIG. 3b includes the previously discussed circuit module (310), circuit elements (350), and elements of the RF transistor amplifier die (210). Therefore, the discussion of FIG. 3b will focus on such parts that differ from those discussed in relation to the previous drawings among the embodiments.

[0112] FIG. 3b illustrates an embodiment in which a circuit module (310) is directly connected to an RF transistor amplifier die (210) without an intervening coupling element (270). Accordingly, the circuit module (310) may be configured to be coupled to one or more source terminals among the gate terminal (222), drain terminal (224), and source terminal(s) (226) of the RF transistor amplifier die (210). For example, a first interconnection pad (322) of the circuit module (310) may be configured to be coupled to the gate terminal (222), a second interconnection pad (324) of the circuit module (310) may be configured to be coupled to the drain terminal (224), and a third interconnection pad (326) of the circuit module (310) may be configured to be coupled to one or more source terminal(s) (226). In some embodiments, a bonding element (e.g., solder balls and / or bumps) (320) may be used to bond the first, second, and third interconnecting pads (322, 324, 326) to one or more of the source terminals of the gate terminal (222), drain terminal (224), and source terminal(s) (226), respectively. Although illustrated as a single pad, in some embodiments, one or more of the first, second, and / or third interconnecting pads (322, 324, 326) may include multiple pads. The configuration illustrated in FIG. 3b may be useful when a fan-in or fan-out configuration of the bonding element (270) is not required to provide a connection between the RF transistor amplifier die (210) and the circuit module (310).

[0113] FIG. 3c illustrates an embodiment in which a circuit module (310) is directly connected to an RF transistor amplifier die (210') including an on-die RDL by utilizing conductive patterns (223) without an intervening coupling element (270). Accordingly, the circuit module (310) may be configured to be coupled to one or more source terminals among the gate terminal (222), drain terminal (224), and source terminal(s) (226) of the RF transistor amplifier die (210'). The RF transistor amplifier die (210') of FIG. 3c is illustrated in cross-section to show examples of internal conductive patterns (e.g., of the RDL) coupled to one or more source terminals among the gate terminal (222), drain terminal (224), and source terminal(s) (226). In some embodiments, the RF transistor amplifier die (210') may be an MMIC. Although illustrated without a coupling element (270), it will be understood that in some embodiments, a coupling element (270) may also be present between the RF transistor amplifier die (210') and the circuit module (310).

[0114] The use of a coupling element (270) utilizing conductive patterns (273) (if present), an on-die RDL utilizing conductive patterns (223) (if present), and a circuit module (310) utilizing conductive patterns (373) can provide an interconnection structure between the gate, drain, and source of the RF transistor amplifier die (210) and the gate lead connection pads (382), drain lead connection pads (384), and source lead connection pads (386). By utilizing various combinations of these elements and electrical junction techniques, a semiconductor package that eliminates and / or reduces wire junctions can be provided.

[0115] FIG. 3d is a schematic cross-sectional view of a circuit module (310') coupled to a plurality of RF transistor amplifiers (200) according to some embodiments of the present invention. FIG. 3e is a schematic cross-sectional view of a circuit module (310') coupled to a plurality of RF transistor amplifier dies (210) according to some embodiments of the present invention. FIG. 3e and FIG. 3e include the previously discussed circuit module (310'), circuit elements (350), RF transistor amplifier dies (210), and elements of the RF transistor amplifiers (200). Therefore, the discussion of FIG. 3d and FIG. 3e will focus on such parts that differ from those discussed in relation to the previous drawings among the embodiments.

[0116] Referring to FIG. 3d, the circuit module (310') may be configured to be coupled to one or more RF transistor amplifiers (200). FIG. 3d also illustrates that the conductive patterns (373), interconnect pads, and surface connection pads may be modified without departing from the scope of the invention. For example, the circuit module (310') may include a plurality of interconnect pads (327). The interconnect pads (327) may be configured to be coupled to the terminals of the plurality of RF transistor amplifiers (200). For example, the interconnect pads (327) of the circuit module (310') may be configured to be coupled to the gate connection pad (272), drain connection pad (274), and / or source connection pad (276) of one or more of the plurality of RF transistor amplifiers (200).

[0117] Similarly, the circuit module (310') may have surface connection pads (377) that are coupled to one or more of the interconnection pads (327) through conductive patterns (373). Circuit elements (350) may be coupled to one or more of the surface connection pads (377). By using the conductive patterns (373), interconnection pads (327), surface connection pads (377), and / or circuit elements (350), various circuit connections between multiple RF transistor amplifiers (200) can be realized. It will be understood that the configuration illustrated in FIG. 3d is merely a schematic example, and the routing and connections of the various elements of the circuit module (310') can be modified in various ways to create complex circuits involving RF transistor amplifiers (200).

[0118] In some embodiments, the circuit module (310') may include one or more gate lead connection pads (382), one or more drain lead connection pads (384), and one or more source lead connection pads (386). Signals provided to one or more gate lead connection pads (382), one or more drain lead connection pads (384), and one or more source lead connection pads (386) may be distributed to various RF transistor amplifiers (200) via conductive patterns (373) through the circuit module (310').

[0119] FIG. 3d illustrates an embodiment in which each of the plurality of RF transistor amplifiers (200) has its own coupling element (270), and it will be understood that other configurations are possible. For example, in some embodiments, a single coupling element (270) may be coupled to the plurality of RF transistor amplifier dies (210). The use of a single coupling element (270) may allow the use of a circuit module (310') having fewer interconnections for the transistor elements of the circuit.

[0120] FIG. 3d illustrates an embodiment in which a circuit module (310') is coupled to a plurality of RF transistor amplifiers (200) comprising a coupling element (270). However, the invention is not limited thereto. In some embodiments, the circuit module (310') may be directly coupled to a plurality of RF transistor amplifier dies (210, 210') that do not include a coupling element (270). FIG. 3e illustrates an embodiment in which a circuit module (310') is coupled to a plurality of RF transistor amplifier dies (210). It will be understood that the circuit module (310') may also be coupled to a plurality of RF transistor amplifier dies (210') without departing from the invention (e.g., as illustrated in FIG. 2k). The circuit module (310') may be coupled to the RF transistor amplifier dies (210, 210') by, for example, by a coupling element (e.g., a solder ball and / or bump) (320). It will be understood that the circuit module (310) can be combined with a combination of RF transistor amplifiers (200) including a coupling element (270) and RF transistor amplifier dies (210, 210').

[0121] The circuit module (310') can be used to provide interconnects for RF transistor amplifiers (200) that can be used to implement multi-stage and / or multi-path amplifier circuits, such as Doherty amplifiers, for example. Conductive patterns (373) can provide electrical connections for multi-stage and / or multi-path amplifier circuits, which can be coupled to circuit elements of circuit elements (350) to provide capacitors, inductors, resistors, and / or other circuit elements used in multi-stage and / or multi-path amplifier circuits. Accordingly, the circuit module (310') can be configured to provide modular interconnects that can be easily coupled to multiple RF transistor amplifiers without the use of junction wires.

[0122] While FIGS. 3a through 3e illustrate various combinations of circuit modules (310, 310'), coupling elements (270), and RF transistor amplifier dies (210, 210'), it will be understood that the present invention is not limited to the specific combinations illustrated in such drawings. As will be understood by a person skilled in the art, the circuit modules (310, 310'), coupling elements (270), and RF transistor amplifier dies (210, 210') may be combined in a number of variations including those not specifically illustrated without departing from the present invention. For example, embodiments of the present invention include transistor amplifier dies (210, 210') that are directly coupled to circuit modules (310, 310'). Some embodiments of the present invention include transistor amplifier dies (210, 210') that are coupled to circuit modules (310, 310') through coupling elements (270). The coupling element (270) and / or circuit module (310, 310') may include traces on a patterned dielectric material as well as a PCB or a metal core PCB. In some embodiments, the transistor amplifier die (210') may have conductive patterns, such as RDL at the die level, which may include a fan-in and / or fan-out configuration that can be connected to other structures such as the coupling element (270) or the circuit module (310, 310').

[0123] FIG. 4a is a schematic cross-sectional view of an RF transistor amplifier (200) and a circuit module (310) coupled to a carrier substrate (410) according to some embodiments of the present invention. FIG. 4b is a schematic cross-sectional view of an RF transistor amplifier (200) coupled to a carrier substrate (410) without a coupling element (270) according to some embodiments of the present invention. FIG. 4a and FIG. 4b include elements of the RF transistor amplifier (200), coupling element (270), and circuit module (310) that have been previously discussed. Therefore, the discussion of FIG. 4a and FIG. 4b will focus on such parts that differ from those discussed in relation to the previous drawings among the embodiments.

[0124] Referring to FIG. 4a, an RF transistor amplifier (200) may be placed on a carrier substrate (410). The carrier substrate (410) may include any structure that provides a suitable mounting surface for the RF transistor amplifier (200). In some embodiments, the carrier substrate (410) may include a thermal conductive element, such as a metal flange. In some embodiments, the carrier substrate (410) may include, for example, an RDL layered structure or a PCB. In some embodiments, the carrier substrate (410) may include copper, molybdenum, and / or a combination thereof. In some embodiments, the carrier substrate (410) may be composed of a plurality of layers and / or include vias / interconnects. The carrier substrate (410) may be configured to allow the RF transistor amplifier (200) to be easily packaged. As illustrated in FIG. 4a, the circuit module (310) can be coupled to an RF transistor amplifier (200) as discussed herein.

[0125] In some embodiments, the thermal layer (240) may be disposed between the bottom surface of the RF transistor amplifier (200) and the carrier substrate (410). The thermal layer (240) may help transfer thermal energy from the RF transistor amplifier (200) to the carrier substrate (410). In embodiments where SiC is utilized as part of the RF transistor amplifier (200), the excellent thermal conductivity of SiC may allow the carrier substrate (410) to dissipate heat from the device more efficiently. In some embodiments, the thermal layer (240) may include or be replaced with a eutectic layer.

[0126] One or more leads (415) may be coupled to one or more gate lead connection pads (382), one or more drain lead connection pads (384), and one or more source lead connection pads (386) of the circuit module (310). For example, a first input lead (415A) may be coupled to one or more gate lead connection pads (382) to provide an input signal to an RF transistor amplifier (200) (e.g., through a junction layer (420A), such as soldering), and a second output lead (415B) may be coupled to one or more drain lead connection pads (384) to receive an output signal from an RF transistor amplifier (200) (e.g., through a junction layer (420B), such as soldering), but the invention is not limited thereto.

[0127] The lead connections of FIG. 4a are merely examples, and other connections and / or connection pads are possible. For example, in FIG. 4a, one or more source lead connection pads (386) are illustrated as being connected to both leads (415A and 415B). However, in some embodiments, one or more source lead connection pads (386) may not be coupled to the source of the RF transistor amplifier (200) (e.g., via one or more source terminal(s) (226). For example, in some embodiments, one or more of the circuit elements (350) and / or conductive patterns (373) may be configured to control whether one or more source lead connection pads (386) are coupled to the input lead (415A), to the output lead (415B), or not to either. For example, a circuit element (350) may be provided on the circuit module (310) to connect the source terminal (226) of the RF transistor amplifier (200) to the lead (415). Similarly, the circuit module (310) may be configured to allow the removal of the circuit element (350) (e.g., a resistor) to disconnect the coupling between the lead (415A or 415B) and the source terminal (226) of the RF transistor amplifier (200).

[0128] Furthermore, FIG. 4a illustrates an embodiment in which two leads (415A and 415B) are present, but this is merely an example and is not intended to limit the invention. In some embodiments, a plurality of leads may be provided, and their individual leads are coupled to gate lead connection pads (382), drain lead connection pads (384), source lead connection pads (386), and / or combinations thereof. For example, in some embodiments, an additional lead may be provided configured to provide a ground connection to the source lead connection pads (386). In some embodiments, the source lead connection pads (386) may be configured to be coupled to leads of an RF semiconductor package that may be coupled to ground, for example. As used herein, the combination of the RF transistor amplifier (200), circuit module (310), leads (415A, 415B), and carrier substrate (410) may be referred to as a packaged RF transistor amplifier, an RF transistor amplifier package, or simply an RF transistor amplifier.

[0129] The leads (415A, 415B) may be located between the circuit module (310) and the carrier substrate (410), but the invention is not limited thereto. In some embodiments, the carrier substrate (410) may have pedistels (410p) that are located below the leads (415A and 415B) and support the leads in some embodiments, but the invention is not limited thereto. In some embodiments, the pedistels (410p) may include an insulating material and / or may be separated from the leads (415A, 415B) by an insulating layer (460). In some embodiments, as will be further discussed herein, the leads (415A, 415B) may be supported by a portion of the package of the RF transistor amplifier (200).

[0130] Although FIG. 4a illustrates the use of a coupling element (270), the invention is not limited thereto. FIG. 4b illustrates an embodiment in which the coupling element is omitted. In the embodiment of FIG. 4b, the circuit module (310) may have first, second, and third interconnection pads (322, 324, 326) spaced apart from each other by distances similar to the distances between a gate terminal (222), a drain terminal (224), and one or more source terminal(s) (226). For example, the first interconnection pad (322) may be connected to the gate terminal (222) (e.g., via bonding elements, such as a solder ball and / or bump (320)), the second interconnection pad (324) may be connected to the drain terminal (224), and the third interconnection pad (326) may be connected to the source terminal (226). Direct connection to the circuit module (310) may be useful when adjustment of the spacing of the terminals of the RF transistor amplifier (200) (e.g., through a fan-in or fan-out structure) is not required. Accordingly, in some embodiments, the coupling element (270) is optional in the RF transistor amplifier (200).

[0131] FIG. 4c illustrates an embodiment in which a plurality of RF transistor amplifiers (200) are coupled to a circuit module (310') and disposed on a carrier substrate (410). For example, as discussed herein in relation to FIG. 3d and 3e, a plurality of RF transistor amplifier dies (210, 210') may be coupled to a circuit module (310'). The plurality of RF transistor amplifier dies (210, 210') may be coupled to the circuit module (310') via a coupling element (270) or directly coupled to the circuit module (310') (as illustrated in FIG. 3e). The RF transistor amplifier dies (210, 210') and / or the circuit module (310') may additionally be disposed on a carrier substrate (410), and leads (415A and 415B) are coupled thereto. In some embodiments, the thermal layer (240) may be placed between the RF transistor amplifier dies (210, 210') and the carrier substrate (410).

[0132] Although FIGS. 4a through 4c illustrate various combinations of circuit modules (310, 310'), coupling elements (270), and RF transistor amplifier dies (210, 210'), it will be understood that the present invention is not limited to the specific combinations illustrated in such drawings. As will be understood by a person skilled in the art, the circuit modules (310, 310'), coupling elements (270), and RF transistor amplifier dies (210, 210') may be combined in a number of variations including those not specifically illustrated without departing from the present invention. Each of these combinations may be disposed on a carrier substrate (410), as generally illustrated in FIGS. 4a through 4c, and suitable leads (e.g., leads (415A, 415B)) are connected thereto.

[0133] FIGS. 5a through 5c are schematic cross-sectional views of various packaging options (500a, 500b, 500c) of an RF transistor amplifier (200) according to some embodiments of the present invention. FIGS. 5a through 5c include elements of the RF transistor amplifier (200), coupling element (270), and circuit module (310) that were previously discussed. Therefore, the discussion of FIGS. 5a through 5c will focus on those parts of the embodiments that differ from those discussed in relation to the previous drawings.

[0134] Referring to FIG. 5a, the semiconductor package (500a) may include an RF transistor amplifier (200) according to some embodiments of the present invention. The semiconductor package (500a) may be, for example, an open-air or open-cavity package. The semiconductor package (500a) may include a carrier substrate (410), sidewalls (520), and a cover (525). The carrier substrate (410), sidewalls (520), and cover (525) may define an internal cavity (530). The RF transistor amplifier (200) and the circuit module (310) may be placed inside the internal cavity (530). The term "semiconductor package" is not intended to be limiting. As previously mentioned, the combination of the RF transistor amplifier (200), circuit module (310), leads (415A, 415B), and carrier substrate (410) may be referred to as a packaged RF transistor amplifier, a semiconductor package, or simply an RF transistor amplifier.

[0135] The carrier substrate (410) may include materials configured to assist in the thermal management of the semiconductor package (500a). For example, the carrier substrate (410) may include copper and / or molybdenum. In some embodiments, the carrier substrate (410) may be composed of a plurality of layers and / or include vias / interconnections. In an exemplary embodiment, the carrier substrate (410) may be a multilayer copper / molybdenum / copper metal flange comprising a core molybdenum layer having copper cladding layers on any one of its main surfaces. Examples of materials of the provided carrier substrate (410) are not intended to limit the invention. In some embodiments, a thermal layer (240) may be located between the RF transistor amplifier (200) and the carrier substrate (410).

[0136] The sidewalls (520) and / or cover (525) may be formed of or comprise an insulating material in some embodiments. For example, the sidewalls (520) and / or cover (525) may be formed of or comprise ceramic and / or PCB. In some embodiments, the sidewalls (520) and / or cover (525) may be formed of, for example, Al2O3. The cover (525) may be glued to the sidewalls (520) using epoxy glue. The sidewalls (520) may be attached to the carrier substrate (410), for example, by brazing. The leads (415A, 415B) may be configured to extend through the sidewalls (520), but the invention is not limited thereto.

[0137] In some embodiments, the RF transistor amplifier (200) may be placed on the carrier substrate (410) and leads (415A, 415B), and the circuit module (310) may be placed on the RF transistor amplifier (200). The leads (415A, 415B) may be coupled to the circuit module (310), for example, using a conductive die attachment material. In some embodiments, the leads (415A, 415B) may extend from the sidewalls (520) to contact the circuit module (310). Therefore, in some embodiments, the use of wire junctions to connect the RF transistor amplifier (200) to the leads (415A, 415B) may be avoided and / or reduced.

[0138] Additional circuit elements (350) are mounted on the circuit module (310). These additional components may include, for example, input matching components and output matching components used to impedance match at the fundamental frequency and / or terminate intermodulation products to ground. These circuit elements (350) may be passive RF components, such as resistors, capacitors, and / or inductors, which are, for example, implemented (at least partially) in integrated passive devices or printed circuit boards. Leads (415A, 415B) allow the RF transistor amplifier (200) to be connected to external devices / circuits / power sources. In the illustrated embodiment, the circuit module (310) is used to connect the conductive leads (415A, 415B) to the circuit elements (350) on the circuit module (310). An RF signal input to an RF transistor amplifier (200) on the first lead (415A) can be transmitted through a circuit module (310) to circuit elements (350) and from there to the gate terminal (222) of the RF transistor amplifier die (210), and an amplified output RF signal can be transmitted from the drain terminal (224) of the RF transistor amplifier die (210) to circuit elements (350) and from there to the circuit module (310), where the RF signal is output through the lead (415B).

[0139] Referring to FIG. 5b, the semiconductor package (500b) may include an RF transistor amplifier (200) according to embodiments of the present invention. The semiconductor package (500b) may be, for example, an overmolded plastic (OMP) package. The semiconductor package (500b) may include a carrier substrate (410) upon which the RF transistor amplifier (200) is disposed. A circuit module (310) may be disposed on the RF transistor amplifier (200).

[0140] The RF transistor amplifier (200) and the circuit module (310) may be enclosed within an overmolded material (540). The overmolded material (540) may be formed of a plastic or plastic polymer compound that is injection molded around the RF transistor amplifier (200) and / or the circuit module (310), thereby providing protection from the external environment.

[0141] Methods for manufacturing an OMP semiconductor package (500b) that may be modified to incorporate an RF transistor amplifier (200) and / or a circuit module (310) are described in U.S. Patent No. 9,515,011, titled “Over-mold plastic packaged wide band-gap power transistors and MMICS”, granted to Wood et al. on December 6, 2016, the disclosure thereof is incorporated herein by reference as fully described herein. In the semiconductor package (500b) according to the present invention, leads (415A, 415B) may extend from outside the semiconductor package (500b) into the overmolded material (540) to be connected to the circuit module (310). Thus, in some embodiments, the use of wire junctions to connect the RF transistor amplifier (200) to the leads (415A, 415B) may be avoided and / or reduced.

[0142] As in the semiconductor package (500a), the carrier substrate (410) of the semiconductor package (500b) may include materials configured to assist in thermal management. For example, the carrier substrate (410) may include copper and / or molybdenum. In some embodiments, the carrier substrate (410) may be composed of a plurality of layers and / or include vias / interconnects. In some embodiments, the carrier substrate (410) may include a metal heat sink that is part of a lead frame or metal slug that is at least partially surrounded by a plastic overmold (540). Examples of materials of the provided carrier substrate (410) are not intended to limit the invention. In some embodiments, the thermal layer (240) may be located between the RF transistor amplifier (200) and the carrier substrate (410).

[0143] FIG. 5c is a schematic cross-sectional view of a packaged RF transistor amplifier (500c) comprising an RF transistor amplifier die within a printed circuit board-based package. The packaged RF transistor amplifier (500c) is very similar to the packaged RF transistor amplifier (500a) discussed above with reference to FIG. 5a, except that the leads (415A, 415B) of the packaged RF transistor amplifier (500c) are replaced by a printed circuit board (522) comprising traces (415A, 415B) that act as input and output leads. The printed circuit board (522) may be attached to a carrier substrate (410), for example, via conductive glue. The carrier substrate (410) may include, for example, pedestals (410P). The pedestals (410P) may be composed of an insulating material and / or metal. The printed circuit board (652) may include a central opening, and the circuit module (310) is mounted within this opening on a carrier substrate (e.g., a metal flange) (410). An RF transistor amplifier (200) and circuit elements (350) are mounted on the circuit module (310).

[0144] FIGS. 5a through 5c illustrate the use of an RF transistor amplifier (200) having a coupling element (270), but the invention is not limited thereto. In some embodiments, semiconductor packages (500a, 500b, 500c) may be configured to include a circuit module (310) that is directly coupled to an RF transistor amplifier die (210), as illustrated in FIGS. 3b, 3c, and 4b. In some embodiments, semiconductor packages (500a, 550b, and 500c) may be configured to include a circuit module (310) that is coupled to a plurality of RF transistor amplifiers (200, 200') and / or a plurality of RF transistor amplifier dies (210, 210), as illustrated in FIGS. 3d, 3e, and 4c.

[0145] It will be recognized that any of the RF transistor amplifiers according to the embodiments of the present invention discussed herein may be mounted in packages such as those shown in FIGS. 5a through 5c. Accordingly, the RF transistor amplifier die (210), coupling element (270), and / or circuit modules (310) shown in FIGS. 5a through 5c may be replaced with an RF transistor amplifier die (210, 210'), coupling element (270), and / or circuit modules (310, 310') according to any of the embodiments of the present invention discussed herein to provide many additional embodiments of packaged RF transistor amplifiers. According to an embodiment, the packaged RF transistor amplifier may include a single-piece microwave integrated circuit (MMIC) as the RF transistor amplifier die, wherein the RF transistor amplifier die includes a plurality of individual circuits on a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies in a path connected in series to form a multi-stage RF transistor amplifier and / or multiple RF transistor dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having multiple transistor amplifier dies and a plurality of paths, as in a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier may include an RF transistor amplifier die according to embodiments of the present invention having conductive gate and / or conductive drain vias providing electrical connections to rear-side interconnection structures, as well as a conventional RF transistor amplifier die having gate and drain terminals connected to other structures via wire junctions.

[0146] In some embodiments described herein, circuit elements (350) may be disposed on the uppermost surface of the circuit module (310), but the embodiments described herein are not limited thereto. FIGS. 6a through 6c are schematic cross-sectional views of additional embodiments of an RF transistor amplifier (200) coupled to the circuit module (610) according to some embodiments of the present invention. FIGS. 6a through 6c correspond to the cross-section of FIG. 3a. FIGS. 6a through 6c include elements of the RF transistor amplifier (200) previously discussed. Therefore, the discussion of FIGS. 6a through 6c will focus on such parts of the embodiments that differ from those discussed in relation to the previous drawings.

[0147] Referring to FIG. 6a, the circuit module (610) may be configured to be coupled to the gate connection pad (272), drain connection pad (274), and source connection pad (276) of the coupling element (270). The coupling element (270) may be coupled to an RF transistor amplifier die (210), for example, as discussed herein in relation to FIG. 2a through 2l.

[0148] For example, the circuit module (610) may have exposed interconnection pads (622, 624, 626) that can be configured to be coupled to the gate connection pad (272), drain connection pad (274), and source connection pad (276), respectively. In some embodiments, a bonding element (e.g., solder balls and / or bumps (320)) may be used to couple the first, second, and third interconnection pads (622, 624, 626) to the gate connection pad (272), drain connection pad (274), and source connection pad (276), respectively. Although exemplified as a single pad, in some embodiments, one or more of the first, second, and / or third interconnection pads (622, 624, 626) may comprise a plurality of pads.

[0149] A circuit module (610) may be coupled to a coupling element (270) on a first side (601) of the circuit module (610). On a second side (602) of the circuit module (610) facing the first side (601), a plurality of pads may be exposed. For example, a gate lead (682), a drain lead (684), and a source lead (686) may be exposed on the second side (602) of the circuit module (610). Although only a single gate lead (682), drain lead (684), and source lead (686) are illustrated in FIG. 6a, it will be understood that a plurality of leads of each type may be provided. As will be further discussed herein, the gate lead (682), drain lead (684), and source lead (686) may be configured to be coupled to the gate terminal (222), drain terminal (224), and source terminal (226), respectively, of the RF transistor amplifier die (210). The encapsulation material (625) may be on the surfaces of the RF transistor amplifier die (210), the coupling element (270), and / or the circuit module (610). The encapsulation material (625) may be formed of a plastic or a plastic polymer compound, but the invention is not limited thereto. In some embodiments, the encapsulation material (625) may be a polymer having fillers or may comprise the same.

[0150] Each of the first, second, and third interconnect pads (622, 624, 626) may be coupled to one or more conductive patterns (673) within the circuit module (610). The conductive patterns (673) may provide various routing and / or circuits within the circuit module (610). For example, the conductive patterns (673) may connect the first interconnect pad (622) to one or more first surface connection pads (672) and a gate lead (682). In some embodiments, the first surface connection pads (672) may be exposed on the first side (601) of the circuit module (610). In some embodiments, the first circuit element (650a) may be coupled to one or more of the first surface connection pads (672) so as to be electrically coupled between the gate lead (682) and the first interconnect pad (622). In some embodiments, the first circuit element (650a) may be coupled between the gate terminal (222) and the gate lead (682) of the RF transistor amplifier die (210) (e.g., via the coupling element (270)). Consequently, the first circuit element (650a) may be electrically coupled between the gates of the RF transistor amplifier die (210) and the gate lead (682). In some embodiments, the first circuit element (650a) may be coupled to the first side (601) of the circuit module (610). Accordingly, the first circuit element (650a) may be coupled to the same side of the circuit module (610) as the coupling element (270) (e.g., the first side (601)).

[0151] Similarly, conductive patterns (673) may connect the second interconnect pad (624) to one or more second surface interconnect pads (674) and drain lead (684). In some embodiments, the second circuit element (650b) may be coupled to one or more of the second surface interconnect pads (674) so ​​as to be electrically coupled between the drain lead (684) and the second interconnect pad (624). In some embodiments, the second surface interconnect pads (674) may be exposed on the first side (601) of the circuit module (610). In some embodiments, the second circuit element (650b) may be coupled between the drain terminal (224) of the RF transistor amplifier die (210) and the drain lead (684) (e.g., via a coupling element (270)). Consequently, the second circuit element (650b) can be electrically coupled between the drains of the RF transistor amplifier die (210) and the drain lead (684).

[0152] The first circuit element (650a) and / or the second circuit element (650b) may provide various electronic capabilities to the RF transistor amplifier (200). For example, the first circuit element (650a) and / or the second circuit element (650b) may include impedances (e.g., including resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, the first circuit element (650a) and / or the second circuit element (650b) may be surface-mount devices or may include them. In some embodiments, the first circuit element (650a) and / or the second circuit element (650b) may be integrated passive devices (IPDs) or may include them. In some embodiments, the first circuit element (650a) and / or the second circuit element (650b) may be harmonic and / or input / output impedance matching elements or may include them.

[0153] For example, the first circuit element (650a) may be configured to provide input matching capabilities. Due to its position between the gate lead (682) and the RF transistor amplifier die (210), the first circuit element (650a) may be able to influence and / or condition the signal provided to the gates of the RF transistor amplifier die (210). Similarly, the second circuit element (650b) may be configured to provide output matching capabilities. Due to its position between the drain lead (684) and the RF transistor amplifier die (210), the second circuit element (650b) may be able to influence and / or condition the signal provided from the drains of the RF transistor amplifier die (210).

[0154] Surface mount devices can be used to provide circuit elements that can be coupled to an RF transistor amplifier die (210) by using a circuit module (610) having exposed connection pads such as first and second surface connection pads (672, 674). Surface mount devices can be replaced and / or configured as needed to provide a more flexible solution. For example, when different types of input / output matching and / or harmonic termination are required, the same circuit module (610) may be used, but the first and / or second circuit elements (650a, 650b) may be swapped to provide different capabilities.

[0155] Although the first circuit element (650a) and the second circuit element (650b) are each exemplified as a single element, it will be understood that in some embodiments, the first circuit element (650a) and / or the second circuit element (650b) may comprise a plurality of individual devices. Similarly, the interconnections between the first and second circuit elements (650a, 650b) and the RF transistor amplifier die (210) are merely examples, and conductive patterns (673) of different configurations may be provided without departing from the invention.

[0156] The conductive patterns (673) can also connect the third interconnection pad (626) to one or more source leads (686). Accordingly, the source connection pad (276) can be electrically coupled to one or more source leads (686).

[0157] The conductive patterns (673) may be enclosed within the insulating material (615). In some embodiments, the insulating material (615) may comprise, for example, silicon oxide, silicon nitride, an oxide of the conductive patterns (673), a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module (610) may be formed as a printed circuit board (PCB). In a PCB embodiment, the insulating material (615) may be the substrate(s) of the PCB, and the conductive patterns (673) may be traces formed within the substrate(s).

[0158] FIG. 6a illustrates the use of a circuit module (610) to be coupled to an RF transistor amplifier die (210) using coupling elements (270), but the invention is not limited thereto. As illustrated in FIG. 6b, in some embodiments, the RF transistor amplifier die (210) may be directly coupled to the circuit module (610). For example, the gate terminal (222), drain terminal (224), and source terminal (226) of the RF transistor amplifier die (210) may each be coupled to interconnection pads (622, 624, 626) of the circuit module (610), for example, using junction elements (320).

[0159] Similarly, it will be understood that other configurations of the circuit module (610) and the RF transistor amplifier die (210), such as those illustrated in FIGS. 3c through 3e, are possible. In some embodiments, the circuit module (610) may be configured to be coupled to an RF transistor amplifier die (210') including internal conductive patterns, as illustrated in FIG. 3c. In some embodiments, the circuit module (610) may be configured to be coupled to a plurality of RF transistor amplifier dies (210), as illustrated in FIGS. 3d and 3e.

[0160] It will also be recognized that the RF transistor amplifier die (210) may have various different configurations. For example, the RF transistor amplifier dies (210) have top-side gate, drain, and source terminals (222, 224, 226), but they may also have one or more of the back-side gate, drain, and source terminals (222', 224', 226') in some embodiments. Such a configuration is schematically illustrated in FIG. 6c, which is a schematic cross-sectional view of the RF transistor amplifier die (210''). As illustrated in FIG. 6c, gate vias (211), drain vias (213), and / or source vias (215) connected to the individual gate, drain, and source terminals (222', 224', 226') may be formed through a semiconductor layer structure (230). For example, as described in U.S. provisional patent application serial number 63 / 004,985 filed on April 3, 2020 ("Application '985"), including gate and drain terminals on the rear side of an RF transistor amplifier die can have various advantages, such as allowing more flexible impedance matching circuit implementations. The entire contents of Application '985 are incorporated herein by reference. It will be recognized that rear side gate, drain, and source terminals (222', 224', 226') and / or corresponding gate, drain, and source vias (211, 213, 215) may be included in any of the RF transistor amplifier dies disclosed herein.

[0161] FIGS. 3a through 3e illustrate embodiments in which a circuit element (350) is on the uppermost surface of a circuit module (310) (e.g., opposite the RF transistor amplifier die (210) to the circuit module (310)), and FIGS. 6a through 6c illustrate embodiments in which a circuit element (650) is on the lowermost surface of a circuit module (610) (e.g., between the circuit module (610) and the RF transistor amplifier die (210)), but it will be understood that other combinations are available. In some embodiments, the circuit elements (350 / 650) may be on both sides of the circuit module (310 / 610). In some embodiments, the circuit elements (350 / 650) may be on the side surfaces of the circuit module (310 / 610).

[0162] As illustrated in FIGS. 6a through 6c, multiple configurations of the RF transistor amplifier die (210) and / or the RF transistor amplifier (200) may be coupled to the circuit module (610). In the following drawings, the discussion will focus on embodiments in which the RF transistor amplifier die (210) is directly coupled to the circuit module (610). However, this commitment is merely for ease of explanation, and it will be understood that the following discussion regarding the circuit module (610) can be equally applied to other types of interconnections between the RF transistor amplifier (210) (e.g., using the coupling element (270)) and / or the RF transistor amplifier (200) without departing from the invention.

[0163] FIGS. 7a through 7e are schematic diagrams illustrating methods of combining circuit modules and RF transistor amplifier dies according to specific embodiments of the present invention. As illustrated in FIG. 7a, a circuit module (610) may be provided. The circuit module (610) may have a first side (601) and a second side (602). In some embodiments, the first side (601) may expose first, second, and third interconnect pads (622, 624, 626) as well as first and second surface interconnect pads (672, 674). In some embodiments, the second side (602) may have exposed gate leads (682), drain leads (684), and source leads (686).

[0164] Referring to FIG. 7b, a first circuit element (650a) and a second circuit element (650b) may be provided on the first side (601) of the circuit module (610). For example, a bonding element (e.g., solder balls and / or bumps (320)) may be used to bond the first circuit element (650a) to the first surface connection pad (672). Similarly, a bonding element (e.g., solder balls and / or bumps (320)) may be used to bond the second circuit element (650b) to the second surface connection pad (674).

[0165] Referring to FIG. 7c, an RF transistor amplifier die (210) may be provided on the first side (601) of the circuit module (610). For example, a junction element (e.g., solder balls and / or bumps (320)) may be used to connect the gate terminal (222), drain terminal (224), and source terminal (226) of the RF transistor amplifier die (210) to the first, second, and third interconnection pads (622, 624, 626), respectively. It will be understood that the order of FIG. 7b and FIG. 7c may be reversed so that the RF transistor amplifier die (210) is connected to the circuit module (610) before the first and second circuit elements (650a, 650b).

[0166] As illustrated in FIG. 7d, a capillary underfill process may be used to inject an encapsulation material (625) between the conductive structures of the RF transistor amplifier die (210), the first and second circuit elements (650a, 650b), and / or the circuit module (610). The encapsulation material (625) can help prevent short circuits, improve the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material (625) may also encapsulate the RF transistor amplifier die (210) within a protective material.

[0167] FIG. 7e illustrates an additional optional step in which a thermal layer (240) is placed on the rear side of the RF transistor amplifier die (210). In some embodiments, additional thermal management structures (642), such as a metal flange, a metal fin, a heat sink, or other structures, may be provided on the thermal layer (240). In some embodiments, the thermal management structures (642) may be part of a larger semiconductor package (e.g., a carrier substrate), as will be further discussed herein. The thermal layer (240) may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die (210) and the thermal management structure (642) on which the RF transistor amplifier die (210) is mounted. In some embodiments, the thermal layer (240) and / or the thermal management structures (642) may be omitted. In some embodiments, the thermal layer (240) may be a die attachment layer, such as a eutectic layer. The thermal layer (240) may be on the transistor amplifier die (210) and / or extend onto the encapsulation material (625) and / or the first and second circuit elements (650a, 650b). The thermal layer (240) may be a metal layer for forming a eutectic or other metal bond. In some embodiments, the thermal layer (240) may be a thermal adhesive.

[0168] The embodiments of FIGS. 6a through 6c provide a common gate lead (682), a drain lead (684), and a source lead (686) on the common side (e.g., the second side (602)) of the circuit module (610). This allows the circuit module (610) to be attached to the second side (602) in various different configurations. For example, FIGS. 8a and 8b are schematic cross-sectional views of various packaging options (800a, 800b) of the circuit module (610) according to some embodiments of the present invention. FIGS. 8a and 8b include elements of the RF transistor amplifier die (210) and the circuit module (610) that were previously discussed. Therefore, the discussion of FIGS. 8a and 8b will focus on such parts of the embodiments that differ from those discussed in relation to the previous drawings.

[0169] Referring to FIG. 8a, the semiconductor package (800a) may be similar to the semiconductor package (500a) discussed herein in relation to FIG. 5a, and redundant descriptions already discussed in relation to that figure will be omitted. The semiconductor package (800a) may be, for example, an open-air or open-cavity package. The semiconductor package (800a) may include a carrier substrate (410), sidewalls (520), and a cover (525). The carrier substrate (410), sidewalls (520), and cover (525) may define an internal cavity (530). An RF transistor amplifier die (210) and a circuit module (610) may be placed inside the internal cavity (530). In some embodiments, a thermal layer (240) may be between the RF transistor amplifier die (210) and the carrier substrate (410).

[0170] The leads (415A, 415B) may be configured to extend through the sidewalls (520), but the invention is not limited thereto. In some embodiments, an RF transistor amplifier (210) may be placed on the carrier substrate (410) and the leads (415A, 415B), and a circuit module (610) may be placed on the RF transistor amplifier die (210). The leads (415A, 415B) may be coupled to the circuit module (610), for example, using a conductive die attachment material. In some embodiments, the leads (415A, 415B) may extend from the sidewalls (520) to contact and / or be connected to the circuit module (610). For example, the lead (415a) may be coupled to the gate lead (682), and the lead (415b) may be coupled to the drain lead (684). In some embodiments, additional leads and / or connections (not shown) may be coupled to the source lead (686). Therefore, in some embodiments, the use of wire junctions to connect the RF transistor amplifier die (210) to the leads (415A, 415B) may be avoided and / or reduced.

[0171] Referring to FIG. 8b, the semiconductor package (800b) may include an RF transistor amplifier (210) and a circuit module (610) according to embodiments of the present invention. The semiconductor package (800b) may be similar to the semiconductor package (500b) discussed herein in relation to FIG. 5b, and redundant descriptions already discussed in relation to the drawings will be omitted. The semiconductor package (800b) may be, for example, an overmolded plastic (OMP) package.

[0172] In the semiconductor package (800b) according to the present invention, leads (415A, 415B) may extend from outside the semiconductor package (800b) into an overmolded material (540) to be connected to a circuit module (610). For example, a lead (415a) may be coupled to a gate lead (682), and a lead (415b) may be coupled to a drain lead (684). In some embodiments, additional leads and / or connections (not shown) may be coupled to a source lead (686). In some embodiments, a thermal layer (240) may be present between the carrier substrate (410) and the RF transistor amplifier die (210) within the semiconductor package (800b).

[0173] It will be understood that, in addition to the semiconductor packages (800a, 800b) illustrated in relation to FIGS. 8a and 8b, other packaging configurations are possible without departing from the invention. For example, the circuit module (610) can be utilized with other configurations as well as semiconductor packages similar to those of FIG. 5c.

[0174] In FIGS. 6a through 6c, the circuit elements (650a, 650b) and the RF transistor amplifier die (210) are on the same side of the circuit module (610), while the gate, drain, and source leads (682, 684, 686) are on opposite sides, but the embodiments are not limited thereto. FIG. 9a is a plan view of an embodiment of a circuit module (610B) according to some embodiments of the present invention, wherein the leads (682, 684, 686), the circuit elements (650a, 650b), and the RF transistor amplifier die (210) are all on the same side of the circuit module (610B). FIG. 9b is a cross-sectional view taken along the line (9B-9B) of FIG. 9a. FIG. 9c is a cross-sectional view taken along the line (9C-9C) of FIG. 9a. FIGS. 9a through 9c include elements of the RF transistor amplifier die (210) and circuit module (610) previously discussed. Therefore, the discussion of FIGS. 9a through 9c will focus on those parts of the embodiments that differ from those discussed in relation to the previous drawings.

[0175] Referring to FIGS. 9a through 9c, a circuit module (610B) may be mounted on an RF transistor amplifier die (210). The RF transistor amplifier die (210) is mounted below the circuit module (610B) in the schematic plan view of FIG. 9a and is therefore illustrated using dashed lines. The circuit module (610B) may be configured to be coupled to the gate terminal (222), drain terminal (224), and / or source terminal (226) of the RF transistor amplifier die (210). FIGS. 9a through 9c illustrate the circuit module (610B) being directly coupled to the RF transistor amplifier die (210), but it will be understood that other types of connections, such as those illustrated in FIGS. 2a through 2l, are possible for the RF transistor amplifier (200) in other configurations. For example, the coupling element (270) can be coupled between the circuit module (610B) and the RF transistor amplifier die (210).

[0176] For example, the circuit module (610B) may have exposed interconnection pads (622, 624, 626) that can be configured to be coupled to the gate terminal (222), drain terminal (224), and source terminal (226), respectively, of the RF transistor amplifier die (210). For example, the first interconnection pad (622) may be configured to be coupled to the gate terminal (222), the second interconnection pad (624) may be configured to be coupled to the drain terminal (224), and the third interconnection pad (626) may be configured to be coupled to the source terminal (226). In some embodiments, a bonding element (e.g., solder balls and / or bumps) (320) may be used to bond the first, second, and third interconnect pads (622, 624, 626) to the gate terminal (222), drain terminal (224), and source terminal(s) (226), respectively. Although exemplified as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads (622, 624, 626) may include a plurality of pads.

[0177] The circuit module (610B) may be coupled to the RF transistor amplifier die (210) on the first side (601) of the circuit module (610B). Additionally, the gate lead (682B), drain lead (684B), and source lead (686B) may be exposed on the first side (601) of the circuit module (610B). As will be further discussed herein, the gate lead (682B), drain lead (684B), and source lead (686B) may be configured to be coupled to the gate terminal (222), drain terminal (224), and source terminal (226) of the RF transistor amplifier die (210), respectively. The encapsulation material (625) may be on the surfaces of the RF transistor amplifier die (201) and / or on the circuit module (610B).

[0178] Each of the first, second, and third interconnect pads (622, 624, 626) may be coupled to one or more conductive patterns (673B) within the circuit module (610B). The conductive patterns (673B) may provide various routing and / or circuits within the circuit module (610B). For example, the conductive patterns (673B) may connect the first interconnect pad (622) to one or more first surface connection pads (672) and a gate lead (682B). In some embodiments, the first surface connection pads (672) may be exposed on the first side (601) of the circuit module (610B). In some embodiments, the first circuit element (650a) may be coupled to one or more of the first surface connection pads (672) so as to be electrically coupled between the gate lead (682B) and the first interconnect pad (622). In some embodiments, the first circuit element (650a) may be coupled between the gate terminal (222) of the RF transistor amplifier die (210) and the gate lead (682B). Consequently, the first circuit element (650a) may be electrically coupled between the gates of the RF transistor amplifier die (210) and the gate lead (682B). In some embodiments, the first circuit element (650a) may be coupled to the first side (601) of the circuit module (610B). Accordingly, the first circuit element (650a) may be coupled to the same side of the circuit module (610B) (e.g., the first side (601)) as the RF transistor amplifier die (210) and the gate lead (682B).

[0179] Similarly, conductive patterns (673B) can connect the second interconnect pad (624) to the drain terminal (224) and the drain lead (684B). In some embodiments, the second circuit element (650b) may be coupled to one or more of the second surface connection pads (674) so ​​as to be electrically coupled between the drain lead (684B) and the second interconnect pad (624). In some embodiments, the second surface connection pads (674) may be exposed on the first side (601) of the circuit module (610B). In some embodiments, the second circuit element (650b) may be coupled between the drain terminal (224) of the RF transistor amplifier die (210) and the drain lead (684B). Consequently, the second circuit element (650b) may be electrically coupled between the drains of the RF transistor amplifier die (210) and the drain lead (684B).

[0180] The conductive patterns (673B) may also connect the third interconnect pad (626) to one or more source leads (686B). The source leads (686B) may be on the same first side (601) as the third interconnect pad (626) and the RF transistor amplifier die (210). In some embodiments, as illustrated in FIG. 9a, the gate lead (682B) and the drain lead (684B) may be on two opposing sides of the RF transistor amplifier die (210), and the source leads (686B) may be on sides of the RF transistor amplifier die (210) different from the two opposing sides. To mention it in another way, in some embodiments, the gate lead (682B) may be adjacent to the first side of the RF transistor amplifier die (210), the drain lead (684B) may be adjacent to the second side of the RF transistor amplifier die (210), and one or more of the source leads (686B) may be adjacent to the third side of the RF transistor amplifier die (210) which is different from the first and second sides of the RF transistor amplifier die (210).

[0181] The circuit module (610B) of FIGS. 9a through 9c may differ from the circuit module (610) of FIGS. 6a through 6c in that the circuit module (610B) provides gate, drain, and source leads (682B, 684B, 686B) on the same side of the RF transistor amplifier die (210) and the circuit module (610B). In other words, the conductive patterns (673) of the circuit module (610B) may be configured to allow the gate, drain, and source leads (682B, 684B, 686B) to be exposed on different parts of the circuit module (610B). Additional packaging options are possible by shifting the side on which the gate, drain, and source leads (682B, 684B, 686B) are located.

[0182] FIG. 9d is a cross-sectional view of the circuit module (610B) of FIG. 9a mounted on a carrier substrate (410) according to some embodiments of the present invention. As illustrated in FIG. 9d, the circuit module (610B) may be coupled to an RF transistor amplifier die (210), which in turn may be on the carrier substrate (410).

[0183] In some embodiments, the thermal layer (240) may be located between the RF transistor amplifier die (210) and the carrier substrate (410). In some embodiments, additional thermal management structures (642), such as metal flanges, metal fins, heat sinks, or other structures, may be provided on the thermal layer (240) and / or between the thermal layer (240) and the carrier substrate (410). The thermal layer (240) may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die (210) and the carrier substrate (410) on which the RF transistor amplifier die (210) is mounted. In some embodiments, the thermal layer (240) and / or thermal management structures (642) may be omitted. In some embodiments, the thermal layer (240) may be a die attachment layer, such as a eutectic layer. The thermal layer (240) may be on the RF transistor amplifier die (210) and / or extend onto the encapsulation material (625) and / or the first and second circuit elements (650a, 650b). The thermal layer (240) may be a metal layer for forming a eutectic or other metal bond. In some embodiments, the thermal layer (240) may be a thermal adhesive.

[0184] In some embodiments, additional contacts may be provided within the carrier substrate (410), but the invention is not limited thereto. For example, a gate connector (982), a drain connector (984), and / or a source connector (not shown) may be provided on and / or within the carrier substrate (410). For example, the gate lead (682B) of the circuit module (610B) may be configured to be coupled to the gate connector (982) (e.g., via a bonding element, such as solder balls and / or bumps (320)), the drain lead (684B) may be configured to be coupled to the drain connector (984), and the source lead (686B) may be configured to be coupled to the source connector (not shown).

[0185] It will be understood that the packaging example of FIG. 9b is merely an example and the invention is not limited thereto. In some embodiments, the circuit module (610B) of FIG. 9a through 9c may be combined within other semiconductor packages described herein, such as those discussed in relation to FIG. 5a through 5c and FIG. 8a and 8b. For example, FIG. 10a and FIG. 10b are schematic cross-sectional views of various packaging options (1000a, 1000b) of the circuit module (610B) according to some embodiments of the invention. FIG. 10a and FIG. 10b include elements of the RF transistor amplifier die (210) and circuit module (610B) previously discussed. Therefore, the discussion of FIG. 10a and FIG. 10b will focus on such parts that differ from those discussed in relation to the previous figures among the embodiments.

[0186] Referring to FIG. 10a, the semiconductor package (1000a) may be similar to the semiconductor packages (500a and 800a) discussed herein in relation to FIG. 5a and FIG. 8a, respectively, and redundant descriptions already discussed in relation to such figures will be omitted. The semiconductor package (1000a) may be, for example, an open-air or open-cavity package. The semiconductor package (1000a) may include a carrier substrate (410), sidewalls (520), and a cover (525). The carrier substrate (410), sidewalls (520), and cover (525) may define an internal cavity (530). An RF transistor amplifier die (210) and a circuit module (610B) may be disposed inside the internal cavity (530). In some embodiments, a thermal layer (240) may be between the RF transistor amplifier die (210) and the carrier substrate (410).

[0187] The leads (415A, 415B) may be configured to extend through the sidewalls (520), but the invention is not limited thereto. In some embodiments, an RF transistor amplifier (210) may be placed on the carrier substrate (410) and the leads (415A, 415B), and a circuit module (610B) may be placed on the RF transistor amplifier die (210). The leads (415A, 415B) may be coupled to the circuit module (610B), for example, using a conductive die attachment material. For example, lead (415a) may be coupled to the gate lead (682B), and lead (415b) may be coupled to the drain lead (684B). In some embodiments, additional leads and / or connections (not shown) may be coupled to the source lead (686B). Therefore, in some embodiments, the use of wire junctions to connect the RF transistor amplifier die (210) to the leads (415A, 415B) may be avoided and / or reduced.

[0188] Referring to FIG. 10b, the semiconductor package (1000b) may include an RF transistor amplifier (210) and a circuit module (610B) according to embodiments of the present invention. The semiconductor package (1000b) may be similar to the semiconductor packages (500b and 800b) discussed herein in relation to FIG. 5b and FIG. 8b, and redundant descriptions already discussed in relation to those figures will be omitted. The semiconductor package (1000b) may be, for example, an overmolded plastic (OMP) package.

[0189] In the semiconductor package (1000b) according to the present invention, leads (415A, 415B) may extend from outside the semiconductor package (800b) into the overmolded material (540) to be connected to the circuit module (610B). For example, a lead (415a) may be coupled to a gate lead (682B), and a lead (415b) may be coupled to a drain lead (684B). In some embodiments, additional leads and / or connections (not shown) may be coupled to a source lead (686B).

[0190] It will be understood that, in addition to the semiconductor packages (1000a, 1000b) illustrated in relation to FIGS. 10a and 10b, other packaging configurations are possible without departing from the invention. For example, the circuit module (610B) can be utilized with other configurations as well as semiconductor packages similar to those of FIG. 5c.

[0191] As discussed herein, circuit modules may include circuit elements on the surfaces of the circuit modules, but may also include circuit elements within the circuit module itself. FIGS. 11a through 11d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die (210) coupled to a circuit module (610C) according to some embodiments of the present invention. FIGS. 11a through 11d include elements of the RF transistor amplifier die (210) and circuit module (610C) previously discussed. Therefore, the discussion of FIGS. 11a through 11d will focus on such parts of the embodiments that differ from those discussed in relation to the previous drawings.

[0192] Referring to FIG. 11a, a circuit module (610C) may be mounted on an RF transistor amplifier die (210). The circuit module (610C) may be configured to be coupled to the gate terminal (222), drain terminal (224), and source terminal (226) of the RF transistor amplifier die (210). FIG. 11a illustrates the circuit module (610C) being directly coupled to the RF transistor amplifier die (210), but it will be understood that other types of connections, such as those illustrated in FIG. 2a through 2l, are possible for the RF transistor amplifier (200) in other configurations. For example, a coupling element (270) may be coupled between the circuit module (610C) and the RF transistor amplifier die (210).

[0193] The circuit module (610C) may have exposed interconnection pads (622, 624, 626) that can be configured to be coupled to a gate terminal (222), a drain terminal (224), and a source terminal (226), respectively. In some embodiments, a bonding element (e.g., solder balls and / or bumps) (320) may be used to couple the first, second, and third interconnection pads (622, 624, 626) to the gate terminal (222), the drain terminal (224), and the source terminal(s) (226), respectively. Although exemplified as a single pad, in some embodiments, one or more of the first, second, and / or third interconnection pads (622, 624, 626) may comprise a plurality of pads.

[0194] The circuit module (610C) may be coupled to an RF transistor amplifier die on the first side (601) of the circuit module (610C). Additionally, a gate lead (682C), a drain lead (684C), and / or a source lead (not shown) may be exposed on the first side (601) of the circuit module (610C). The gate lead (682C), the drain lead (684C), and / or the source lead may be configured to be coupled to the gate terminal (222), the drain terminal (224), and the source terminal (226) of the RF transistor amplifier die (210), respectively.

[0195] The circuit module (610C) may include one or more conductive patterns (1173), a first circuit element (1150a), and a second circuit element (1150b). The first and second circuit elements (1150a and 1150b) are schematically illustrated in FIG. 11a. The circuit module (610C) may differ from that of the circuit modules (610, 610B) described herein in that the first and second circuit elements (1150a and 1150b) may be included within the structure of the circuit module (610C). For example, plate capacitors, interdigitated finger capacitors, and / or capacitors may be implemented using the conductive patterns (1173) within the circuit module (610C). Likewise, spiral inductors or other inductive elements may also be implemented within the circuit module (610C). Resistive elements may be formed on or within the circuit module (610C) by forming trace segments or conductive vias using, for example, conductive materials of higher resistance.

[0196] In some embodiments, the first and second circuit elements (1150a, 1150b) and / or the conductive patterns (1173) may be configured to provide at least part of a harmonic termination circuit, a matching circuit, a splitting circuit, a coupling circuit, and / or a biasing circuit. Conductive patterns (1173) of other configurations and / or circuit elements (1150a, 1150b) of other types may be used without departing from the scope of the invention. Additionally, it will be recognized that the configurations of the conductive patterns (1173) and circuit elements (1150a, 1150b) illustrated in FIG. 11a are merely examples and are not intended to limit the embodiments of the invention.

[0197] In some embodiments, the circuit module (610C) may be formed as a PCB module, and the first and second circuit elements (1150a, 1150b) may be formed from traces within the PCB. In some embodiments, the circuit module (610C) may be formed from an insulating material (615), and the conductive patterns (1173) may be a conductive material within the insulating material (615), such as conductive fillers and / or vias (e.g., copper fillers).

[0198] Each of the first, second, and third interconnect pads (622, 624, 626) may be coupled to one or more of the conductive patterns (1173) within the circuit module (610C). The conductive patterns (1173) may provide various routing and / or circuits within the circuit module (610C). For example, the conductive patterns (1173) may connect the first interconnect pad (622) to the gate lead (682C) through the first circuit element (1150a). The first circuit element (1150a) may provide input matching and / or harmonic termination functionality between the gate lead (682C) and the first interconnect pad (622).

[0199] Similarly, the conductive patterns (1173) can connect the second interconnect pad (624) to the drain lead (684C) through the second circuit element (1150b). The second circuit element (1150b) can provide output matching and / or harmonic termination functionality between the drain lead (684C) and the second interconnect pad (624).

[0200] As illustrated in FIG. 11a, in some embodiments, an encapsulation material (1125) may be formed on the RF transistor amplifier die (210), circuit module (610C), gate lead (682C), and / or drain lead (684C). The encapsulation material (1125) may help prevent short circuits, improve the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material (1125) may also encapsulate the RF transistor amplifier die (210) within a protective material.

[0201] In some embodiments, through-vias (1115) may be formed within the encapsulating material (1125). The through-vias (1115) may include a conductive material and may provide a conductive path to the gate lead (682C) and / or drain lead (684C). For example, the through-vias (1115) may expose a gate connection (1182) and / or drain connection (1184) on the bottom surface of the encapsulating material (1125). The gate connection (1182) and / or drain connection (1184) may provide connection points to the gate lead (682C) and drain lead (684C), respectively.

[0202] In some embodiments, the gate connection (1182) and the drain connection (1184) may be approximately coplanar. In some embodiments, the encapsulation material (1125) may be configured to expose the bottom surface of the RF transistor amplifier die (210), and the gate connection (1182) and the drain connection (1184) may also be approximately coplanar with the bottom surface of the RF transistor amplifier die (210), but the invention is not limited thereto. Although only the gate connection (1182) and the drain connection (1184) are illustrated in FIG. 11a, it will be understood that source connections may also be provided in a similar manner.

[0203] The use of the gate connection (1182) and drain connection (1184) may allow for the use of a combination of the RF transistor amplifier die (210) and the circuit module (610C) and direct junctions between other pads and / or dies. For example, as illustrated in FIG. 11b, the gate connection (1182) may be coupled to the gate pad (1192) (e.g., via a junction element, such as soldering), and the drain connection (1184) may be coupled to the gate pad (1194). In some embodiments, a thermal layer (240) may also be provided below the RF transistor amplifier die (210), but the invention is not limited thereto. In some embodiments, the thermal layer (240) may be omitted. In some embodiments, additional contacts may be provided to connect to the source terminal (226) and / or the third interconnection pad (626) of the RF transistor amplifier die (210).

[0204] It will be understood that the packaging example of FIG. 11b is merely an example and the invention is not limited thereto. FIG. 11c and FIG. 11d illustrate the use of packaging similar to that discussed herein in relation to FIG. 5a through 5c, FIG. 8a, FIG. 8b, FIG. 10a, and FIG. 10b. For example, encapsulation material (1125), including a circuit module (610C), an RF transistor amplifier die (210), and gate and drain connections (1182, 1184), may be placed in an open-cavity semiconductor package (1100a) ( FIG. 11c) or an OMP package (1100b) ( FIG. 11d). The elements of FIGS. 11c and FIGS. 11d of the semiconductor package (1100a) and semiconductor package (1100b), which are similar to those previously discussed in relation to FIGS. 5a to 5c, FIGS. 8a, FIGS. 8b, FIGS. 10a, and FIGS. 10b, will be omitted for brevity.

[0205] In some embodiments, the gate connection (1182) may be coupled to the gate lead (415A) by a bonding element (e.g., solder balls and / or bumps), and the drain connection (1184) may also be coupled to the drain lead (415B). The gate lead (415A) and the drain lead (415B) may be electrically insulated from the carrier substrate (410) (e.g., by an insulating layer and / or an overmolding material (540)). In some embodiments, the thermal layer (240) may be located between the RF transistor amplifier die (210) and the carrier substrate (410). In some embodiments, the thermal layer (240) may be omitted. In some embodiments, the thermal layer (240) may be a die attachment layer such as a eutectic layer. The thermal layer (240) may be located on the transistor amplifier die (210) and / or may extend onto the encapsulation material (1125). The thermal layer (240) may be a metal layer for forming a eutectic or other metal bond. In some embodiments, the thermal layer (240) may be a thermal adhesive. Although not shown in FIG. 11c and FIG. 11d, in some embodiments, additional thermal management structures such as those exemplified in FIG. 7e and FIG. 9d may be used.

[0206] The packaging embodiments illustrated in FIGS. 11c and 11d are merely examples intended to illustrate the manner in which the circuit module (610C) and the RF transistor amplifier die (210) can be combined within a semiconductor package. It will be understood that a number of other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0207] In some embodiments, through-vias (1115) and / or encapsulation material (1125) may be omitted. For example, FIGS. 12a through 12d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die (210) coupled to a circuit module (610C) according to some embodiments of the present invention. As illustrated in FIG. 12a, the circuit module (610C) may be substantially similar to that of FIGS. 11a through 11d, and therefore, its redundant description will be omitted. The embodiment of FIG. 12a may, for example, omit the encapsulation material (1125), through-vias (1115), and / or gate / drain connections (1182, 1184), and directly expose the gate lead (682C) and drain lead (684C). FIG. 12a illustrates that the entire encapsulation material (1125) has been removed, but it will be understood that in some embodiments, some encapsulation material (1125) may be present. For example, in some embodiments, the encapsulation material (1125) may be on parts of the RF transistor amplifier die (210) and circuit module (610C), but the gate lead (682C) and drain lead (684C) may be exposed.

[0208] The embodiments illustrated in FIG. 12a may be utilized in a number of packaging configurations. FIG. 12b and FIG. 12c illustrate the use of packaging similar to that discussed herein in relation to FIG. 5a through 5c, FIG. 8a, FIG. 8b, FIG. 10a, and FIG. 10b. For example, a circuit module (610C) and an RF transistor amplifier die (210) may be placed in an open-cavity semiconductor package (1200a) ( FIG. 12b) or an OMP package (1200b) ( FIG. 12c). Elements of FIG. 12b and FIG. 12c of semiconductor packages (1200a) and semiconductor packages (1200b) similar to those previously discussed in relation to FIG. 5a through 5c, FIG. 8a, FIG. 8b, FIG. 10a, and FIG. 10b will be omitted for brevity. In some embodiments, the gate lead (682C) may be coupled to the gate lead (415A) by a bonding element (e.g., solder balls and / or bumps (320)), and the drain lead (684C) may also be coupled to the drain lead (415B). It will be understood that a number of other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0209] While many of the embodiments described herein have reduced or / or omitted wire junctions, it will be understood that the present invention can still improve configurations by utilizing wire junctions. For example, FIG. 12d illustrates a semiconductor package (1200c) utilizing a circuit module (610C) utilizing wire junctions. Referring to FIG. 12d, the semiconductor package (1200c) may be, for example, an open-air or open-cavity package. The semiconductor package (1200c) may include a carrier substrate (410), sidewalls (520), and a cover (525). The carrier substrate (410), sidewalls (520), and cover (525) may define an internal cavity (530). An RF transistor amplifier die (210) and a circuit module (610C) may be placed inside the internal cavity (530).

[0210] The leads (415A, 415B) may be configured to extend through the sidewalls (520), but the invention is not limited thereto. In some embodiments, a circuit module (610C) may be placed on the carrier substrate (410) and the leads (415A, 415B), and an RF transistor amplifier die (210) may be placed on the circuit module (610C). The leads (415A, 415B) may be coupled to the circuit module (610C), for example, using wire junctions (1280). For example, lead (415a) may be coupled to the gate lead (682C), and lead (415b) may be coupled to the drain lead (684C). The semiconductor package (1200c) utilizes wire junctions (1280) but still benefits from a direct connection between the RF transistor amplifier die (210) and the circuit modules (610C). Furthermore, the circuit module (610C) includes first and second circuit elements (1150a, 1150b) that can allow for additional internalized functionality, such as harmonic termination and / or input / output impedance matching. In addition, the use of the circuit modules (610C) allows for greater flexibility in that different performance characteristics (e.g., for handling harmonics at different frequencies, different impedances, etc.) can be achieved simply by swapping the circuit modules (610C).

[0211] FIG. 12d utilizes a circuit module (610C), but it will be understood that wire junctions (1280) may be included in other semiconductor packaging configurations utilizing any of the circuit modules and / or RF transistor amplifiers described herein.

[0212] Referring again to FIGS. 6a through 6c, various embodiments are illustrated that provide an RF transistor amplifier die (210) coupled to a circuit module (610). In some embodiments, the RF transistor amplifier die (210) is coupled directly to the circuit module (610) (e.g., FIG. 6b), and in some embodiments, the RF transistor amplifier die (210) is coupled to the circuit module (610) through a coupling element (270) (e.g., FIG. 6a). In embodiments such as those of FIGS. 6a through 6c, an encapsulation material (625) may be on one or more sides of the RF transistor amplifier die (210) to protect / enclose the RF transistor amplifier die (210). In some embodiments, as illustrated in FIGS. 6a through 6c, the bottom surface of the RF transistor amplifier die (210) may be exposed by the encapsulation material (625), but the invention is not limited thereto.

[0213] FIGS. 13a through 13d are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die (210) coupled to a circuit module (610) and including a spacer, according to some embodiments of the present invention. Parts of FIGS. 13a through 13d previously described will not be described again here for brevity. Referring to FIG. 13a, in some embodiments, a spacer (245) may be placed on the bottom surface (210a) of the RF transistor amplifier die (210). An encapsulating material (625) may expose the bottom surface (245a) of the spacer (245).

[0214] In some embodiments, the spacer (245) may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, the spacer (245) may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, but the invention is not limited thereto. In some embodiments, the spacer (245) may be electrically insulated and / or may be, for example, a dielectric material, such as silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, but the invention is not limited thereto. In some embodiments, the spacer (245) may be thermally conductive. Therefore, the spacer (245) may be configured to dissipate heat transferred from the RF transistor amplifier die (210). In some embodiments, the spacer (245) may be composed of a plurality of layers, but the invention is not limited thereto. In some embodiments, the spacer (245) may perform functions similar to the thermal layer (240) described herein and / or may be composed of a similar material. Including the spacer (245) on the RF transistor amplifier die (210) within the encapsulation material (625) may provide a packaging option that is easier to distribute and attach. FIG. 13a illustrates an embodiment in which the RF transistor amplifier die (210) is directly coupled to the circuit module (610), but the invention is not limited thereto. In some embodiments, the transistor amplifier die (210) may be coupled to the circuit module (610) via a coupling element (270) in a manner similar to that illustrated in FIG. 6b. Similarly, in some embodiments, the RF transistor amplifier die (210) may include an on-die RDL, as in the RF transistor amplifier die (210') of FIG. 3c.

[0215] As illustrated in FIG. 13a, the encapsulation material (625) may be on the RF transistor amplifier die (210) and on the first and second circuit elements (650a, 650b). However, the invention is not limited to such a configuration. Depending on the electrical and thermal requirements for the first and second circuit elements (650a, 650b), alternative and / or additional terminal / junction / spacer structures may be utilized with at least one of the first and second circuit elements (650a, 650b) to provide electrical conductivity, thermal conductivity, and / or mechanical interfaces to one or more of the first and second circuit elements (650a, 650b).

[0216] In some embodiments, the surfaces of the first and second circuit elements (650a, 650b) may be exposed as part of an RF transistor amplifier and / or coupled to auxiliary spacers. For example, FIG. 13b is a schematic cross-sectional view of an RF transistor amplifier die (210) coupled to a circuit module (610) according to some embodiments of the present invention. As illustrated in FIG. 13b, the circuit module (610) and / or the RF transistor amplifier die (210) may be substantially similar to the previously described embodiments, and therefore, their redundant description will be omitted. The embodiment illustrated in FIG. 13b may include, for example, a first auxiliary spacer (246a) and a second auxiliary spacer (246b).

[0217] In some embodiments, the first auxiliary spacer (246a) may be formed on the first circuit element (650a). In some embodiments, the second auxiliary spacer (246b) may be formed on the second circuit element (650B). For example, the first auxiliary spacer (246a) may be formed to be on the first circuit element (650a) and / or in contact with it, and the second auxiliary spacer (246b) may be formed to be on the second circuit element (650b) and / or in contact with it. In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, the surface of the first and / or second auxiliary spacers (246a, 246b) may be exposed from the encapsulation material (625). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be or include gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, but the invention is not limited thereto. The first and / or second auxiliary spacers (246a, 246b) may be configured to be electrically coupled to the first and / or second circuit elements (650a, 650b) and, for example, may provide a mechanism for providing a ground signal to the first and / or second circuit elements (650a, 650b). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be thermally conductive. Therefore, the first and / or second auxiliary spacers (246a, 246b) may be configured to dissipate heat transferred from the first and / or second circuit elements (650a, 650b). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be electrically insulated and / or may be, for example, a dielectric material, such as silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, or may include these, but the invention is not limited thereto.In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a plurality of layers, but the invention is not limited thereto.

[0218] In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a material similar to that of the spacer (245), but the invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a material different from that of the spacer (245). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be electrically disconnected from the spacer (245). Forming the first and / or second auxiliary spacers (246a, 246b) of a material different from and / or electrically disconnected from the spacer (245) can help limit current sharing and / or current eddy between the RF transistor amplifier die (210) and the first and / or second circuit elements (650a, 650b). Although the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) are exemplified as distinct individual elements, the invention is not limited thereto. In some embodiments, the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) may be connected together as an integral layer (e.g., see FIG. 13c).

[0219] The materials / thicknesses of the first and second auxiliary spacers (246a, 246b) may be the same as or different from the spacer (245). In some embodiments, the spacer (245) and the first and second auxiliary spacers (246a, 246b) may have different thicknesses so that the bottom portions of the first and second auxiliary spacers (246a, 246b) are flat with the bottom portion of the spacer (245) for ease of packaging / manufacturing / bonding of the RF transistor amplifier die (210) and circuit module (610) to a package substrate or circuit board. In some embodiments, the spacer (245) and the first and second auxiliary spacers (246a, 246b) have the same thickness. In other embodiments, the spacer (245) spans at least one or all of the RF transistor amplifier die (210) and the first and second circuit elements (650, 650b) to provide, for example, the advantages of a planar interface surface.

[0220] Additional and / or interposed spacers, junctions, and other layers may be provided to provide desired electrical, thermal, and mechanical interfaces. Depending on the desired electrical, thermal, and / or mechanical properties, the layers may be made of electrical and / or thermally conductive and / or insulating materials. For example, in some embodiments, the spacer (245) may be thermally conductive and electrically insulating, while the first and second auxiliary spacers (246a, 246b) may be electrically conductive as well as thermally conductive. In some embodiments, only the spacer (245) may be present on the RF transistor amplifier die (210). In some embodiments, only the first auxiliary spacer (246a) may be present on the first circuit element (650a). In some embodiments, only the second auxiliary spacer (246b) may be present on the second circuit element (650b). In other embodiments, any combination of the spacer (245), the first auxiliary spacer (246a), and the second auxiliary spacer (246b) may exist.

[0221] In some embodiments, the exposed surfaces of the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) may be substantially on the same plane. That is, the exposed surfaces of the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (24) may be configured to be mounted on separate boards (e.g., by an attachment method, such as soldering).

[0222] It will be understood that the manufacturing method of the embodiments of FIGS. 13a through 13c may be similar to that illustrated in connection with FIGS. 7a through 7d. For example, manufacturing an RF transistor amplifier device may include the placement of a spacer (245) on an RF transistor amplifier die (210), the placement of a first auxiliary spacer (246a) on a first circuit element (650a), and the placement of a second auxiliary spacer (246b) on a second circuit element (650b). For example, the spacer (245) may be electrically and / or thermally connected to the RF transistor amplifier die (210) (e.g., through a die attachment material). For example, the first auxiliary spacer (246a) and the second auxiliary spacer (246b) may be electrically and / or thermally connected to the first and second circuit elements (650a, 650b), respectively (e.g., through a die attachment material). These steps may be performed, for example, after the placement of the first and second circuit elements (650a, 650b) on the circuit module (610) (exemplified in relation to FIG. 7b and 7c) and the RF transistor amplifier die (210). In some embodiments, the placement of the spacer (245), the first auxiliary spacer (246a), and the second auxiliary spacer (246b) may be performed before or after the formation of the encapsulation material (625) on the RF transistor amplifier die (210) (exemplified in relation to FIG. 7d). In some embodiments, the deposition of the spacer (245) may be performed by a different process than that of the first auxiliary spacer (246a) and / or the second auxiliary spacer (2465b).

[0223] As discussed above, in some embodiments, the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) may be interconnected and / or formed integrally. FIG. 13c illustrates an embodiment having an integrated spacer layer (245'). The integrated spacer layer (245') may be connected to and / or extended to contact the first circuit element (350a), the second circuit element (350b), and the RF transistor amplifier die (10) (e.g., the source terminal (26) of the RF transistor amplifier die (10)). In some embodiments, the surface (245a') of the integrated spacer layer (245') may be exposed from the encapsulation material (325). In some embodiments, the integrated spacer layer (245') may be formed of the same or similar material as the first auxiliary spacer (246a), the second auxiliary spacer (246b), and / or the spacer (245) described in relation to previous embodiments. For example, the integrated spacer layer (245') may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, the integrated spacer layer (245') may be gold (Au), copper (Cu), a Cu alloy, a gold-tin (AuSn), and / or epoxy, but the invention is not limited thereto. In some embodiments, the integrated spacer layer (245') may be electrically insulating and / or may be, for example, a dielectric material, such as silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, but the invention is not limited thereto. In some embodiments, the integrated spacer layer (245') may be composed of multiple layers, but the invention is not limited thereto. As used herein, the "integrated" spacer layer (245') refers to a substantially continuous spacer layer (245') which does not necessarily have a uniform composition. In some embodiments, different parts of the integrated spacer layer (245') may be composed of different materials.For example, a portion of the integrated spacer layer (245') on the first auxiliary spacer (246a) and / or the second auxiliary spacer (246b) may be different from a portion of the integrated spacer layer (245') on the RF transistor amplifier die (210).

[0224] Although the integrated spacer layer (245') is exemplified as a uniform layer having a relatively flat top surface (245b'), the invention is not limited thereto. In some embodiments, the top surface (245b') of the integrated spacer layer (245') may be non-flat. For example, in some embodiments, the first circuit element (650a), the second circuit element (650b), and the RF transistor amplifier die (210) may have different heights, and the integrated spacer layer (245') may be formed to have a top surface (245b') having portions at each of the different heights of the first circuit element (650a), the second circuit element (650b), and the RF transistor amplifier die (210).

[0225] FIG. 13d illustrates an exemplary embodiment of an RF transistor amplifier device in which the first auxiliary spacer (246a) and the second auxiliary spacer (246b) are omitted. Referring to FIG. 13d, the surface (650a_s) of the first circuit element (650a) and / or the surface (650b_s) of the second circuit element (650b) may be exposed by an encapsulation material (625). The exposure of the surfaces (650a_s, 650b_s) of the first and / or second circuit elements (650a, 650b) may allow additional external connections to be applied to the first and / or second circuit elements (650a, 650b). For example, separate electrical connections for ground signals may be connected to the first and / or second circuit elements (650a, 650b) through their respective exposed surfaces (650a_s, 650b_s).

[0226] The RF transistor amplifier device of FIG. 13d can be formed, for example, by configuring an embodiment similar to the embodiment of FIG. 13a, and then performing a flattening operation on parts of the encapsulation material (625) to expose the surfaces (650a_s, 650b_s) of the first and / or second circuit elements (650a, 650b).

[0227] RF transistor amplifier dies (210) coupled to the circuit modules (610) illustrated in FIGS. 13a through 13d can be utilized in a number of packaging configurations. FIGS. 14a through 14d illustrate the use of packaging similar to that discussed herein in relation to FIGS. 8a and 8b. For example, the circuit module (610) and the RF transistor amplifier die (210) can be placed in an open-cavity semiconductor package (1400a_1, 1400a_2) ( FIGS. 14a and 14b) or an OMP package (1400b_1, 1400b_2) ( FIG. 14c and 14d). For instance, elements of FIGS. 14a and 14b of semiconductor packages (1400a_1) and semiconductor packages (1400a_2) similar to those previously discussed in relation to FIG. 8a will not be discussed further for the sake of brevity. For example, elements of FIG. 14c and FIG. 14d of semiconductor packages (1400b_1) and semiconductor packages (1400b_2) similar to those previously discussed in relation to FIG. 8b will not be discussed further for the sake of brevity.

[0228] In FIG. 14a and FIG. 14c, semiconductor packages (1400a_1 and 1400b_1) illustrate the use of a circuit module (610) coupled to an RF transistor amplifier die (210) within an open-cavity package and an OMP package. FIG. 14a illustrates an open-cavity semiconductor package (1400a_1), and FIG. 14c illustrates an OMP semiconductor package (1400b_1). The semiconductor packages (1400a_1 and 1400b_1) further include a spacer (425), a first auxiliary spacer (246a), and a second auxiliary spacer (246b), such as those illustrated and described in relation to FIG. 13b. The circuit module (610) may expose a gate lead (682) and a drain lead (684) that can be connected to leads (415A, 415B), respectively. In some embodiments, the semiconductor packages (1400a_1 and 1400b_1) may include a first auxiliary spacer (246a), a second auxiliary spacer (246b), and a spacer (245) that are substantially coplanar. Depending on the electrical and thermal requirements for the first and second circuit elements (650a, 650b), additional terminal / junction / spacer structures may be utilized with at least one of the first and second circuit elements (650a, 650b) to provide an electrical, thermal, and / or mechanical interface between at least one of the first and second circuit elements (650a, 650b) and the carrier substrate (410).

[0229] In some embodiments, the first auxiliary spacer (246a) and the second auxiliary spacer (246b) may be composed of materials different from the spacer (425). For example, in some embodiments, the first auxiliary spacer (246a) and the second auxiliary spacer (246b) may be electrically conductive to be electrically coupled to the carrier substrate (410). For example, the first auxiliary spacer (246a) and the second auxiliary spacer (246b) may provide an electrical connection (e.g., a ground signal) to the first and second circuit elements (650a, 650b). In some embodiments, the spacer (245) may be thermally conductive but electrically insulator. This may allow the spacer (245) to dissipate heat from the RF transistor amplifier die (210). In some embodiments, the first and second auxiliary spacers (246a, 246b) may be electrically insulated or conductive, but the first and second circuit elements (650a, 650b) may be thermally connected to the carrier substrate (410) to dissipate thermal energy (e.g., heat) from the first and second circuit elements (650a, 650b).

[0230] FIGS. 14b and FIGS. 14d illustrate exemplary semiconductor packages (1400a_2, 1400b_2) comprising an integrated spacer layer (245) within an open-cavity package and an OMP package. FIG. 14b illustrates an open-cavity semiconductor package (1400a_2), and FIG. 14d illustrates an OMP semiconductor package (1400b_2). The semiconductor packages (1400a_2, 1400b_2) may utilize an integrated spacer layer (245') as discussed herein in relation to FIG. 13c. The integrated spacer layer (245') may be connected to and / or in direct contact with a carrier substrate (410). The integrated spacer (245') may be coupled to a first circuit element (650a), a second circuit element (650b), and / or an RF transistor amplifier die (210). In some embodiments, the integrated spacer layer (245') may be configured to have a non-planar surface (e.g., top surface) to be coupled to the first circuit element (650a), the second circuit element (650b), and the RF transistor amplifier die (210). The invention is not limited thereto, and in some embodiments, the top surface of the integrated spacer layer (245') may be planar. In some embodiments, different parts of the integrated spacer layer (245') may be composed of different materials. In some embodiments, additional layers (e.g., additional spacer layers) may be disposed between the first and second circuit elements (650a, 650b) and the integrated spacer layer (245') or between the integrated spacer layer (245') and the carrier substrate (410).

[0231] In FIGS. 14a through 14d, the RF transistor amplifier die (210) is illustrated as being directly coupled to the circuit module (610) in semiconductor packages (1400a_1, 1400a_2, 1400b_1, and 1400b_2), but it will be understood that the RF transistor amplifier die (210) can also be coupled to the circuit module via a coupling element (270) or by utilizing an on-die RDL with necessary modifications.

[0232] FIGS. 15a through 15d are schematic cross-sectional views of additional RF transistor amplifier embodiments according to some embodiments of the present invention, comprising a circuit module (610B) and mechanisms for coupling to first and second circuit elements (650a, 650b). Parts of the RF transistor amplifier die (210) and the circuit module (610B) may be substantially similar to parts of FIGS. 9a through 9d as well as other previously described figures, and therefore, their redundant description will be omitted. The embodiments of FIGS. 15a through 15d may include a circuit module (610B) that exposes a gate lead (682B) and / or a drain lead pad (684B) on the same side (601) (e.g., bottom surface) of the circuit module (610B) to which the RF transistor amplifier die (210) is coupled. The embodiments of the RF transistor amplifiers of FIGS. 15a to 15d may include embodiments similar to the embodiment of FIG. 9b, for example, with a spacer (245), a first auxiliary spacer (246a), and / or a second auxiliary spacer (246b) added.

[0233] For example, FIG. 15a illustrates an RF transistor amplifier die (210) coupled to a circuit module (610B), wherein a spacer (245) is disposed on the lowermost surface (210a) of the RF transistor amplifier die (210). The encapsulating material (625) may expose the lowermost surface (245a) of the spacer (245).

[0234] In some embodiments, the spacer (245) may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, the spacer (245) may be or include gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, but the invention is not limited thereto. In some embodiments, the spacer (245) may be electrically insulated and / or may be or include, for example, a dielectric material, such as silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, but the invention is not limited thereto. In some embodiments, the spacer (245) may be thermally conductive. Therefore, the spacer (245) may be configured to dissipate heat transferred from the RF transistor amplifier die (210). In some embodiments, the spacer (245) may be composed of a material that can perform functions similar to the thermal layer (240) described herein and / or similar material. In some embodiments, the spacer (245) may be composed of multiple layers, but the invention is not limited thereto. FIG. 15a illustrates an embodiment in which the RF transistor amplifier die (210) is directly coupled to the circuit module (610), but the invention is not limited thereto. In some embodiments, the transistor amplifier die (210) may be coupled to the circuit module (610) via a coupling element (270) in a manner similar to that illustrated in FIG. 6b. Similarly, in some embodiments, the RF transistor amplifier die (210) may include an on-die RDL, as in the RF transistor amplifier die (210') of FIG. 3c.

[0235] FIG. 15b illustrates an embodiment similar to the embodiment of FIG. 15a with added first auxiliary spacers (246a) and second auxiliary spacers (246b). In some embodiments, the first auxiliary spacer (246a) may be formed to be on and / or in contact with the first circuit element (650a), and the second auxiliary spacer (246b) may be formed to be on and / or in contact with the second circuit element (650b). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, the surface of the first and / or second auxiliary spacers (246a, 246b) may be exposed from the encapsulation material (625). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be or include gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, but the invention is not limited thereto. The first and / or second auxiliary spacers (246a, 246b) may provide a mechanism to provide a ground signal to the first and / or second circuit elements (650a, 650b) or to dissipate thermal energy therefrom, as discussed herein in relation to other embodiments.

[0236] In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a material similar to that of the spacer (245), but the invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a material different from that of the spacer (245). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be electrically disconnected (e.g., isolated) from the spacer (245). In some embodiments, the first and / or second auxiliary spacers (246a, 246b) may be composed of a plurality of layers, but the invention is not limited thereto.

[0237] Although the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) are exemplified as separate individual elements, the invention is not limited thereto. In some embodiments, the first auxiliary spacer (246a), the second auxiliary spacer (246b), and the spacer (245) may be formed as an integrated (e.g., interconnected) spacer layer (245'). Such an embodiment is exemplified in FIG. 15c, which depicts an RF transistor amplifier die (210) coupled to a circuit module (610B) comprising the integrated spacer layer (245'). The integrated spacer layer (245') may be similar to that discussed herein in relation to FIG. 13c. The integrated spacer layer (245') may extend to contact the first circuit element (650a), the second circuit element (650b), and / or the RF transistor amplifier die (210). In some embodiments, the surface (245a) of the integrated spacer layer (245') may be exposed from the encapsulating material (625). In some embodiments, the integrated spacer layer (245') may be formed of the same or similar material as the first auxiliary spacer (246a), the second auxiliary spacer (246b), and / or the spacer (245). In some embodiments, the upper surface (245b') of the integrated spacer layer (245') may be non-planar or planar. For example, in some embodiments, the first circuit element (650a), the second circuit element (650b), and / or the RF transistor amplifier die (210) may have different heights, and the integrated spacer layer (245') may be formed to have an upper surface (245b') having portions at each of the different heights of the first circuit element (650a), the second circuit element (650b), and the RF transistor amplifier die (210).

[0238] FIG. 15d illustrates an embodiment of an RF transistor amplifier device in which the first auxiliary spacer (246a) and the second auxiliary spacer (246b) are omitted. The RF transistor amplifier die (210) may be coupled to a circuit module (610B) similar to that of FIG. 15a, and thus, its redundant description will be omitted. Referring to FIG. 15a and FIG. 15d, the upper surface (650a_s) of the first circuit element (650a) and / or the upper surface (650b_s) of the second circuit element (650b) may be exposed from the encapsulation material (625). The exposure of the surfaces (650a_s, 650b_s) of the first and / or second circuit elements (650a, 650b) may allow additional external connections to be applied to the first and / or second circuit elements (650a, 650b). For example, separate electrical connections for ground signals may be connected to the first and / or second circuit elements (650a, 650b) through their respective exposed surfaces (650a_s, 650b_s).

[0239] The RF transistor amplifier device of FIG. 15d can be formed, for example, by configuring the RF transistor amplifier device of FIG. 15a and then performing a flattening operation on parts of the encapsulation material (625) to expose the surfaces (650a_s, 650b_s) of the first and / or second circuit elements (650a, 650b).

[0240] The RF transistor amplifier devices illustrated in FIGS. 15a through 15d can be utilized in a number of packaging configurations. FIGS. 16a through 16d illustrate the use of packaging similar to that discussed herein in relation to FIGS. 10a, FIG. 10b, and FIGS. 14a through 14d. For example, the circuit module (610B) and the RF transistor amplifier die (210) can be placed in an open-cavity semiconductor package (1600a_1, 1600a_2) ( FIG. 16a, FIG. 16b) or an OMP package (1600b_1, 1600b_2) ( FIG. 16c, FIG. 16d). In some embodiments, the spacer layer (245) may be utilized with first and second auxiliary spacers (246a, 246b) in an open-cavity semiconductor package (1600a_1) (Fig. 16a) or an OMP package (1600b_1) (Fig. 16c). In some embodiments, the integrated spacer layer (245') may be utilized with an open-cavity semiconductor package (1600a_2) (Fig. 16b) or an OMP package (1600b_2) (Fig. 16d). The elements of FIGS. 16a through 16d of semiconductor packages (1600a_1, 1600a_2, 1600b_1, and 1600b_2) similar to those previously discussed in relation to other figures, such as FIGS. 10a and 10b, will not be further discussed for the sake of brevity. In some embodiments, semiconductor packages (1600a_1, 1600a_2, 1600b_1, and 1600b_2) may accommodate an RF transistor amplifier device in which a gate lead pad (682B) and a drain lead pad (684B) are exposed on the lower surface of a circuit module (610B).In FIGS. 16a through 16d, the RF transistor amplifier die (210) is illustrated as being directly coupled to the circuit module (610B) in semiconductor packages (1600a_1, 1600a_2, 1600b_1, and 1600b_2), but it will be understood that the RF transistor amplifier die (210) can also be coupled to the circuit module via a coupling element (270) or by utilizing an on-die RDL with necessary modifications.

[0241] Referring to FIGS. 16a and 16c, the first and second auxiliary spacers (246a, 246b) may be connected to and / or in direct contact with the carrier substrate (410). In this way, the first and second auxiliary spacers (246a, 246b) may be configured to dissipate heat from the first and second circuit elements (650a, 650b) and / or provide an electrical signal (e.g., a ground signal) to them. Depending on the electrical and thermal requirements for the first and second circuit elements (650a, 650b), additional terminal / junction / spacer structures may be utilized with at least one of the first and second circuit elements (650a, 650b) to provide an electrical, thermal, and / or mechanical interface between at least one of the first and second circuit elements (650a, 650b) and the carrier substrate (410).

[0242] Referring to FIGS. 16b and 16d, the first and second auxiliary spacers (246a, 246b) may be replaced by an integrated spacer layer (245') coupled to the first circuit element (650a), the second circuit element (650b), and / or the RF transistor amplifier die (210). The integrated spacer layer (245') may be connected to and / or in direct contact with the carrier substrate (410). The integrated spacer layer (245') may have a planar or non-planar top surface. In some embodiments, additional layers (e.g., additional spacer layers) may be disposed between the first and second circuit elements (650a, 650b) and the integrated spacer layer (245'), or between the integrated spacer layer (245') and the carrier substrate (410).

[0243] The embodiments described herein provide an improved RF transistor amplifier and an improved packaging including such an RF transistor amplifier. By avoiding and / or reducing the use of backside vias, some embodiments of the present invention provide improved thermal management of the power amplifier. Furthermore, by positioning the contacts of the power amplifier on the same side of the device, interconnects and circuit modules can be utilized, which can reduce the need for wire junctions. Consequently, the RF transistor amplifier and associated package can exhibit improved performance and thermal characteristics compared to conventional devices. The advantages of direct junctions provided by the embodiments of the present invention include a reduction in form factor, lower electrical resistance, as well as improved communication speed.

[0244] Various embodiments have been described herein with reference to the accompanying drawings, in which exemplary embodiments are illustrated. However, such embodiments may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Rather, such embodiments are provided to ensure that the disclosure is thorough and complete and to fully convey the concept of the invention to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not depicted in actual measurements and, in some examples, may be exaggerated for clarity.

[0245] While terms such as “first,” “second,” etc., may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, without departing from the scope of the invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the terms “and / or,” “and / or,” and “and / or” include any and all combinations of one or more of the associated enumerated items.

[0246] The technical terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the invention. As used herein, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprising,” “include,” and / or “including,” as used herein, specify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0247] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and it will be further understood that they should not be interpreted in an ideal or overly formal sense unless explicitly defined as so herein.

[0248] When an element, such as a layer, region, or substrate, is referred to as being "on" another element, attached "on" it, or extending "on" it, it will be understood that the element is directly on the other element, or that intervening elements may also exist. In contrast, when an element is referred to as being "directly" on another element, "directly attached on" it, or extending "directly" onto it, no intervening elements exist. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that the element may be directly connected or coupled to the other element, or that intervening elements may exist. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements exist.

[0249] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as exemplified in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientations illustrated in the drawings.

[0250] Embodiments of the present invention are described herein with reference to cross-sectional examples, which are schematic examples of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the examples are expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be interpreted as being limited to the regions of the specific shapes illustrated herein, but should include variations in shapes, for example, due to manufacturing. The elements illustrated by dashed lines may be optional in the illustrated embodiments.

[0251] Identical numbers refer to identical elements throughout. Accordingly, identical or similar numbers may be described by reference to other drawings even if they are not mentioned or described in the corresponding drawings. Additionally, elements not indicated by reference numbers may be described by reference to other drawings.

[0252] In the drawings and specification, typical embodiments of the invention are disclosed and specific terms are used, but are used only in a general and illustrative sense and are not for the purpose of limitation, and the scope of the invention is set forth in the following claims.

Claims

Claim 1 A transistor device comprising: a transistor die including a gate terminal, a drain terminal, and a source terminal; a circuit module on the transistor die and electrically coupled to the gate terminal, the drain terminal, and / or the source terminal by individual interconnection pads; and one or more passive electrical components on a first surface of the circuit module, wherein the one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor device and / or between the drain terminal and a second lead of the transistor device by individual interconnection pads exposed on the first surface of the circuit module, and the circuit module comprises conductive patterns that electrically connect the individual interconnection pads exposed on the first surface to the individual interconnection pads and to the individual leads of the first and second leads exposed on the second surface of the circuit module. Claim 2 In claim 1, the transistor die is a transistor device located on the first surface of the circuit module adjacent to the one or more passive electrical components. Claim 3 In claim 1, the transistor die is a transistor device located on a second surface of the circuit module facing the first surface. Claim 4 A transistor device according to claim 1, wherein one or more passive electrical components comprise a surface mount device and / or an integrated passive device. Claim 5 delete Claim 6 A transistor device according to claim 4, wherein the one or more passive electrical components comprise a plurality of conductive pads aligned with and electrically coupled to the individual connection pads of the circuit module. Claim 7 A transistor device according to claim 1, wherein the gate terminal, the drain terminal, and the source terminal comprise conductive pillar structures adjacent to a first surface of the transistor die and facing the circuit module. Claim 8 A transistor device according to claim 7, further comprising a coupling element between the first surface of the transistor die and the circuit module, wherein the coupling element comprises a redistribution layer structure including conductive coupling patterns electrically coupled to the gate terminal, the drain terminal, and the source terminal. Claim 9 A transistor device according to claim 7, further comprising a thermally conductive flange on a second surface of the transistor die facing the circuit module. Claim 10 A transistor device according to claim 9, wherein the transistor die is on a second surface of the circuit module facing the first surface, and further comprises a mechanical support structure on the second surface of the circuit module adjacent to the transistor die, wherein the mechanical support structure is between the thermally conductive flange and the second surface of the circuit module. Claim 11 In claim 9, the transistor device further comprises side walls and a cover, wherein the thermal conductive flange, the side walls and the cover define an internal cavity, and the transistor die and the circuit module are located within the internal cavity. Claim 12 A transistor device according to claim 9, further comprising an overmolded material on the circuit module, the transistor die, and the thermally conductive flange. Claim 13 A transistor device according to claim 1, wherein the first and / or second leads are coupled to one of the first surface of the circuit module or the second surface of the circuit module facing the first surface. Claim 14 A transistor device comprising: a transistor die including a gate terminal, a drain terminal, and a source terminal; and a passive component assembly electrically coupled to the gate terminal, the drain terminal, and / or the source terminal, and comprising one or more passive electrical components on a first surface and electrically coupled to individual connection pads exposed on the first surface, wherein the transistor die is on a second surface of the passive component assembly facing the first surface, and the gate terminal, the drain terminal, and / or the source terminal are electrically coupled to individual interconnect pads exposed on the second surface, and the passive component assembly comprises conductive patterns electrically connecting the individual connection pads exposed on the first surface to the individual interconnect pads exposed on the second surface and to at least one lead of the transistor device exposed on the second surface. Claim 15 A transistor device according to claim 14, wherein one or more passive electrical components are electrically coupled between the gate terminal and the first lead of the transistor device, and / or between the drain terminal and the second lead of the transistor device. Claim 16 In paragraph 14, the transistor device wherein one or more passive electrical components comprise a surface mount device and / or an integrated passive device. Claim 17 A transistor device according to claim 14, wherein the passive component assembly comprises a multilayer structure including conductive traces and / or vias that are electrically coupled to one or more passive electrical components on the first surface and coupled to the gate terminal, the drain terminal, and / or the source terminal of the transistor die on the second surface. Claim 18 A transistor device according to claim 17, wherein the gate terminal, the drain terminal, and the source terminal comprise conductive filler structures adjacent to a first surface of the transistor die and facing a second surface of the passive component assembly. Claim 19 A transistor device according to claim 18, further comprising a coupling element between the first surface of the transistor die and the second surface of the passive component assembly, wherein the coupling element comprises a redistribution layer structure comprising conductive coupling patterns that are electrically coupled to conductive filler structures. Claim 20 A transistor device according to claim 18, further comprising a thermally conductive flange on the second surface of the transistor die facing the second surface of the passive component assembly. Claim 21 A transistor device according to claim 20, further comprising a mechanical support structure adjacent to the transistor die and extending between the second surface of the passive component assembly and the thermally conductive flange. Claim 22 In paragraph 20, the transistor device further comprises side walls and a cover, wherein the thermal conductive flange, the side walls and the cover define an internal cavity, and the transistor die and the passive component assembly are located within the internal cavity. Claim 23 A transistor device comprising: a transistor die including a gate terminal, a drain terminal, and a source terminal; and a passive component assembly electrically coupled to the gate terminal, the drain terminal, and / or the source terminal, and comprising one or more passive electrical components on a first surface and electrically coupled to individual connection pads exposed on the first surface, wherein the transistor die is on the first surface of the passive component assembly adjacent to the one or more passive electrical components, and the gate terminal, the drain terminal, and / or the source terminal are electrically coupled to individual interconnect pads exposed on the first surface, and the passive component assembly comprises conductive patterns electrically connecting the individual connection pads to the individual interconnect pads exposed on the first surface and to at least one lead of the transistor device exposed on a second surface of the passive component assembly. Claim 24 A transistor device according to claim 23, wherein one or more passive electrical components are electrically coupled between the gate terminal and the first lead of the transistor device, and / or between the drain terminal and the second lead of the transistor device. Claim 25 In paragraph 23, the one or more passive electrical components are transistor devices comprising surface mount devices and / or integrated passive devices. Claim 26 A transistor device according to claim 23, wherein the passive component assembly comprises a multilayer structure including conductive traces and / or vias that are electrically coupled to one or more passive electronic components on the first surface and coupled to the gate terminal, the drain terminal, and / or the source terminal of the transistor die on the first surface. Claim 27 A transistor device according to claim 26, wherein the gate terminal, the drain terminal, and the source terminal comprise conductive filler structures adjacent to a first surface of the transistor die and facing a first surface of the passive component assembly. Claim 28 A transistor device according to claim 27, further comprising a coupling element between the first surface of the transistor die and the first surface of the passive component assembly, wherein the coupling element comprises a redistribution layer structure comprising conductive coupling patterns that are electrically coupled to the conductive filler structures. Claim 29 A transistor device according to claim 27, further comprising a thermally conductive flange on a second surface of the transistor die facing the first surface of the passive component assembly. Claim 30 A transistor device according to claim 1, wherein the transistor die comprises a HEMT (high electron mobility transistor) or an LDMOS (laterally-diffused metal-oxide semiconductor) transistor. Claim 31 In claim 1, the transistor device is a transistor die that is a group III nitride-based RF transistor amplifier die.

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