Memory device performing incremental step pulse program operation and operation method thereof

Abstract

The present technology relates to a memory device and a method of operation thereof that performs an Incremental Step Pulse Program (ISPP) method of program operation. The memory device comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a peripheral circuit that uses an Increment Step Pulse Program (ISPP) method to repeatedly perform program operations until the program is completed, wherein, each time a program operation is performed, a pass voltage is applied to a first word line selected for program and a second word line not selected among a plurality of word lines from a first time point to a second time point, respectively, and then applies a program voltage to the first word line and a pass voltage to the second word line from a second time point to a third time point. The peripheral circuit, among the program operations repeated through the ISPP method, performs a bit line precharge operation to precharge each of a plurality of bit lines to a set potential level from a fourth time point to a second time point that precedes the first time point when performing the first program operation, and performs the bit line precharge operation from the fourth time point to a time point that is the same as or precedes the first time point. Perform up to the 5th point.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device that performs an Incremental Step Pulse Program (ISPP) method of program operation and a method of operation thereof. Background Technology

[0002] Generally, among various semiconductor devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP), devices that use a memory system as a storage medium—such as portable digital electronic devices like digital cameras, smartphones, and tablet PCs—may include volatile memory devices and nonvolatile memory devices to store data. A volatile memory device is a memory device in which stored data is lost when the power supply is cut off. Examples of volatile memory devices include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). A nonvolatile memory device is a memory device in which stored data is retained even when the power supply is cut off. Non-volatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash Memory Devices, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory can be broadly classified into NOR type and NAND type. Generally, during the programming operation of non-volatile memory devices, the Incremental Step Pulse Programming (ISPP) method is used, which precisely controls the threshold voltage distribution of memory cells by gradually increasing the voltage level of the program pulse.In addition, to prevent Program Disturbance, a phenomenon in which memory cells connected to unselected word lines are unintentionally programmed during program operation, a Channel Boosting technique may be applied in which the channel region is floated and the channel potential is raised through coupling with the word line voltage. Meanwhile, regarding the technical configuration of applying such Channel Boosting and ISPP methods during the program operation process, reference may be made to Korean Published Patent No. 10-2009-0108267, etc. The problem to be solved

[0003] An embodiment of the present invention provides a memory device and a method of operation thereof that can prevent a decrease in program efficiency due to channel boosting in an Incremental Step Pulse Program (ISPP) method of program operation.

[0004] The technical problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0005] A memory device according to an embodiment of the present invention comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines; The ISPP (Increment Step Pulse Program) method is used to repeat program operations until the program is completed, and a peripheral circuit is included that applies a pass voltage to each of the first word line selected and the second word line not selected among the plurality of word lines from the first time point to the second time point each time the program operation is performed, and then applies a program voltage to the first word line and the pass voltage to the second word line from the second time point to the third time point. The peripheral circuit may include a memory device that, during the program operations repeated through the ISPP method, when the first program operation is performed, performs a bit line precharge operation to precharge each of the plurality of bit lines to a set potential level from the fourth time point, which is earlier than the first time point, to the second time point, and when the remaining program operations excluding the first are performed, performs the bit line precharge operation from the fourth time point to the fifth time point, which is the same as or earlier than the first time point.

[0006] A method of operation of a memory device according to another embodiment of the present invention comprises: a method of operation of a memory device including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, wherein, after a start time, from a first time point to a second time point, a pass voltage is applied to each of a first word line that is programmed selected and a second word line that is not selected among the plurality of word lines, and then from the second time point to a third time point, a program operation step of applying a program voltage to the first word line and the pass voltage to the second word line; a repetition step of repeating the program operation step through an Increment Step Pulse Program (ISPP) method until the program is completed; and a first precharge step of performing a bit line precharge operation of precharging each of the plurality of bit lines to a set potential level from a fourth time point preceding the first time point to the second time point when performing the first program operation step in the repetition step. And when performing the remaining program operation steps excluding the first one in the above repetition step, a second precharge step may be included in which the bitline precharge operation is performed from the fourth time point up to the fifth time point, which is the same as or earlier than the first time point. Effects of the invention

[0007] This technology can control the bitline precharge interval during the first program operation of the ISPP (Incremental Step Pulse Program) method to have a relatively longer length than the bitline precharge interval during the remaining program operations excluding the first.

[0008] This prevents a decrease in program efficiency caused by channel boosting during the first program operation in the ISPP method. Brief explanation of the drawing

[0009] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention. FIG. 2 is a drawing for explaining in detail the memory device illustrated in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a drawing for explaining in detail the memory block illustrated in FIG. 2 according to an embodiment of the present invention. FIG. 4 is a diagram illustrating the program operation of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention. FIG. 5 is a drawing for explaining in detail the page buffer illustrated in FIG. 2 according to the operation according to an embodiment of the present invention. FIG. 6 is a diagram illustrating the first program operation among the program operations of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention. FIG. 7 is a diagram illustrating the remaining program operations, excluding the first, of the program operations of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention. FIGS. 8 and 9 are drawings for explaining the operation of the page buffer illustrated in FIG. 4 according to an embodiment of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below and may be configured in various different forms; the embodiments provided are merely intended to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the present invention.

[0011] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention.

[0012] Referring to FIG. 1, the data processing system may include a host (102) and a memory system (110). The host (102) may include electronic devices, such as portable electronic devices like mobile phones, MP3 players, laptop computers, etc., or electronic devices such as desktop computers, game consoles, TVs, projectors, etc., i.e., computing devices or wired / wireless electronic devices.

[0013] The host (102) includes at least one operating system (OS), and the operating system manages and controls the overall functions and operations of the host (102) and can provide mutual operations between the host (102) and the user using the memory system (110). Here, the operating system supports functions and operations corresponding to the user's purpose and use, and, for example, can be classified into a general operating system and a mobile operating system depending on the mobility of the host (102). In addition, the general operating system in the operating system can be classified into a personal operating system and an enterprise operating system depending on the user's usage environment. For example, the personal operating system is a system specialized to support service provision functions for general users and includes Windows and Chrome, etc., and the enterprise operating system is a system specialized to secure and support high performance and may include Windows Server, Linux and Unix, etc. In addition, the mobile operating system in the operating system is a system specialized to support mobility service provision functions and system power saving functions for the user, and may include Android, iOS, Windows Mobile, etc. At this time, the host (102) may include multiple operating systems and also executes the operating system to perform operations with the memory system (110) corresponding to the user request. Here, the host (102) transmits multiple commands corresponding to the user request to the memory system (110), and accordingly, the memory system (110) can perform operations corresponding to the commands, that is, operations corresponding to the user request.

[0014] Additionally, the memory system (110) operates in response to a request from the host (102) and can store data accessed by the host (102), in particular. In other words, the memory system (110) can be used as the main memory or secondary memory of the host (102). Here, the memory system (110) can be implemented as any one of various types of storage devices according to the host interface protocol connected to the host (102). For example, the memory system (110) can be implemented as any one of various types of storage devices such as a solid state drive (SSD), MMC, eMMC (embedded MMC), RS-MMC (Reduced Size MMC), micro-MMC type multimedia card (MMC), SD, mini-SD, micro-SD type secure digital (SD) card, USB (Universal Storage Bus) storage device, UFS (Universal Flash Storage) device, CF (Compact Flash) card, Smart Media card, Memory Stick, etc.

[0015] And, the memory system (110) may include a memory device (150) that stores data accessed by a host (102), and a controller (130) that controls data storage to the memory device (150).

[0016] Additionally, the controller (130) and memory device (150) included in the memory system (110) can be integrated into a single semiconductor device. For example, the controller (130) and memory device (150) can be integrated into a single semiconductor device to form an SSD. When the memory system (110) is used as an SSD, the operating speed of the host (102) connected to the memory system (110) can be further improved. Furthermore, the controller (130) and memory device (150) can be integrated into a single semiconductor device to form a memory card, and for example, memory cards such as PC cards (PCMCIA: Personal Computer Memory Card International Association), Compact Flash cards (CF), Smart Media cards (SM, SMC), Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), and Universal Flash Storage (UFS) can be formed.

[0017] In addition, as another example, the memory system (110) is a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, tablet computer, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, 3-dimensional television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, storage constituting a data center, and a device for transmitting and receiving information in a wireless environment. It can be configured as a device, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID (radio frequency identification) device, or one of various components constituting a computing system, etc.

[0018] Meanwhile, the memory device (150) in the memory system (110) can maintain stored data even when power is not supplied, and in particular, can store data provided from the host (102) through a write operation and provide the stored data to the host (102) through a read operation. Here, the memory device (150) may include a memory cell array (not shown) comprising a plurality of memory cells that store data.

[0019] A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include a plurality of pages. According to an embodiment, a page may be a unit for storing data in a memory device (150) or reading data stored in a memory device (150). A memory block may be a unit for erasing data.

[0020] According to an embodiment, the memory device (150) may be a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (150) is a NAND flash memory.

[0021] A memory device (150) may be configured to receive a command and an address from a controller (130) and to access an area of ​​a memory cell array selected by the address. The memory device may perform an operation directed by the command on the area selected by the address. For example, the memory device (150) may perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device (150) will program data into the area selected by the address. During a read operation, the memory device (150) will read data from the area selected by the address. During an erase operation, the memory device (150) will erase data stored in the area selected by the address.

[0022] The controller (130) can control the overall operation of the memory system (110).

[0023] When power is applied to the memory system (110), the controller (130) can execute firmware (FW). If the memory device (150) is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host (102), a Flash Translation Layer (FTL) that controls communication between the host (102) and the memory device (150), and a Flash Interface Layer (FIL) that controls communication with the memory device (150).

[0024] According to an embodiment, the controller (130) receives data and a logical block address (LBA) from the host (102) and can convert the logical block address into a physical block address (PBA) representing the address of a memory cell to be stored in the memory device (150). In this specification, the logical block address (LBA) and "logical address" or "logical address" may be used interchangeably. In this specification, the physical block address (PBA) and "physical address" or "physical address" may be used interchangeably.

[0025] The controller (130) can control the memory device (150) to perform a program operation, a read operation, or an erase operation, etc., according to a request from the host (102). When performing a program operation, the controller (130) can provide a write command, a physical block address, and data to the memory device (150). When performing a read operation, the controller (130) can provide a read command and a physical block address to the memory device (150). When performing an erase operation, the controller (130) can provide an erase command and a physical block address to the memory device (150).

[0026] According to an embodiment, the controller (130) may generate commands, addresses, and data independently of a request from the host (102) and transmit them to the memory device (150). For example, the controller (130) may provide commands, addresses, and data to the memory device (150) for performing read operations and program operations associated with performing wear leveling, read reclaim, garbage collection, etc.

[0027] According to an embodiment, the controller (130) may control at least two memory devices (150). In this case, the controller (130) may control the memory devices (150) according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices (150) so that the operation overlaps.

[0028] The host (102) can communicate with the memory system (110) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0029] FIG. 2 is a drawing for explaining in detail the memory device illustrated in FIG. 1 according to an embodiment of the present invention.

[0030] Referring to FIG. 2, the memory device (150) may include a memory cell array (151) and peripheral circuits (152).

[0031] A memory cell array (151) may include a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) may be connected to an address decoder (155) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) may be connected to a page buffer group (156) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. As an example, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a single page. Thus, a single memory block may include a plurality of pages.

[0032] A row line (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0033] The memory cells included in the memory cell array (151) can each be configured as a single level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) that can store four data bits.

[0034] The peripheral circuit (152) may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array (151). The peripheral circuit (152) may drive the memory cell array (151). For example, the peripheral circuit (152) may apply various operating voltages to row lines (RL) and bit lines (BL1 to BLm), or discharge the applied voltages.

[0035] The peripheral circuit (152) may include an address decoder (155), a voltage generator (154), a page buffer group (156), a data input / output circuit (157), a sensing circuit (158), and a control logic (153).

[0036] The peripheral circuit (152) can drive the memory cell array (151). For example, the peripheral circuit (152) can drive the memory cell array (151) to perform program operation, read operation, and erase operation.

[0037] The address decoder (155) can be connected to the memory cell array (151) via a row line (RL). The row line (RL) may include a drain select line, a word line, a source select line, and a common source line. According to an embodiment of the present invention, the word line may include a normal word line and a dummy word line. According to an embodiment of the present invention, the row line (RL) may further include a pipe select line.

[0038] The address decoder (155) may be configured to operate in response to the control of the control logic (153). The address decoder (155) may receive an address (RADD) from the control logic (153).

[0039] The address decoder (155) may be configured to decode a block address among the received addresses (RADD). The address decoder (155) may select at least one memory block among the memory blocks (BLK1~BLKz) according to the decoded block address. The address decoder (155) may be configured to decode a row address among the received addresses (RADD). The address decoder (155) may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder (155) may apply an operating voltage (Vop) supplied from the voltage generation unit (154) to the selected word line.

[0040] During program operation, the address decoder (155) will apply a program voltage to the selected word line and a pass voltage of a level lower than the program voltage to the unselected word line. During program verification operation, the address decoder (155) will apply a verification voltage to the selected word line and a verification pass voltage of a level higher than the verification voltage to the unselected word line.

[0041] During a read operation, the address decoder (155) will apply a read voltage to the selected word line and apply a read pass voltage of a higher level than the read voltage to the unselected word line.

[0042] According to an embodiment of the present invention, the erase operation of the memory device (150) can be performed in units of memory blocks. The address (ADDR) input to the memory device (150) during the erase operation may include a block address. The address decoder (155) decodes the block address and can select at least one memory block according to the decoded block address. During the erase operation, the address decoder (155) can apply a ground voltage to the word line input to the selected memory block.

[0043] The voltage generation unit (154) may be configured to generate a plurality of operating voltages (Vop) using an external power supply voltage supplied to the memory device (150). The voltage generation unit (154) may operate in response to the control of the control logic (153).

[0044] As an example, the voltage generating unit (154) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (154) can be used as the operating voltage of the memory device (150).

[0045] As an example, the voltage generating unit (154) can generate a plurality of operating voltages (Vop) using an external power supply voltage or an internal power supply voltage. The voltage generating unit (154) can be configured to generate various voltages required by the memory device (150). For example, the voltage generating unit (154) can generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0046] The voltage generation unit (154) includes a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages (Vop) having various voltage levels, and will generate a plurality of operating voltages (Vop) by selectively activating the plurality of pumping capacitors in response to the control of the control logic (153).

[0047] A number of generated operating voltages (Vop) can be supplied to the memory cell array (151) by the address decoder (155).

[0048] The page buffer group (156) may include a plurality of page buffers (PB1 to PBm). Each of the plurality of page buffers (PB1 to PBm) may be connected to a memory cell array (151) through a plurality of bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) may operate in response to the control of the control logic (153).

[0049] A plurality of page buffers (PB1 to PBm) can communicate data (DATA) with the data input / output circuit (157). During programming, the plurality of page buffers (PB1 to PBm) can receive data (DATA) to be stored through the data input / output circuit (157) and the data line (DL).

[0050] When a program is executed, when a program voltage is applied to a selected word line, the multiple page buffers (PB1 to PBm) will transmit the data (DATA) to be stored through the data input / output circuit (157) to the selected memory cell via the bit lines (BL1 to BLm). The memory cell of the selected page can be programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allowance voltage (e.g., ground voltage) is applied will have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibition voltage (e.g., power supply voltage) is applied will maintain its threshold voltage. When a program verification operation is executed, the multiple page buffers (PB1 to PBm) can read the data (DATA) stored in the memory cell from the selected memory cell via the bit lines (BL1 to BLm).

[0051] When a read operation is performed, the page buffer group (156) can read data (DATA) from the memory cell of the selected page through the bit line (BL) and store the read data (DATA) in a plurality of page buffers (PB1~PBm).

[0052] During an erase operation, the page buffer group (156) can float the bit line (BL). As an example, the page buffer group (156) may include a column selection circuit.

[0053] The data input / output circuit (157) can be connected to a plurality of page buffers (PB1~PBm) via a data line (DL). The data input / output circuit (157) can operate in response to the control of the control logic (153).

[0054] The data input / output circuit (157) may include a plurality of input / output buffers (not shown) for receiving input data (DATA). During program operation, the data input / output circuit (157) may receive data (DATA) to be stored from the controller (130, see FIG. 1). During a read operation, the data input / output circuit (157) may output data (DATA) transmitted from a plurality of page buffers (PB1~PBm) included in the page buffer group (156) to the controller (130, see FIG. 1).

[0055] The sensing circuit (158) can generate a reference current in response to an allow bit (VRYBIT) signal generated by the control logic (153) during a read operation or a verification operation, and compare the sensing voltage (VPB) received from the page buffer group (156) with the reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic (153).

[0056] The control logic (153) may be connected to an address decoder (155), a voltage generator (154), a page buffer group (156), a data input / output circuit (157), and a sensing circuit (158). The control logic (153) may be configured to control the general operation of the memory device (150). The control logic (153) may operate in response to a command (CMD) transmitted from an external device.

[0057] The control logic (153) can generate various signals in response to a command (CMD) and an address (ADDR) to control the remaining components (154, 155, 156, 157, 158) included in the peripheral circuit (152). For example, the control logic (153) can generate an operation signal (OPSIG), an address (RADD), a read and write circuit control signal (PBSIGNALS), and an allow bit (VRYBIT) in response to a command (CMD) and an address (ADDR). The control logic (153) can output the operation signal (OPSIG) to the voltage generator (154), output the address (RADD) to the address decoder (155), output the read and write control signal (PBSIGNALS) to the page buffer group (156), and output the allow bit (VRYBIT) to the sensing circuit (158). Additionally, the control logic (153) can determine whether the verification operation has passed or failed in response to a pass or fail signal (PASS / FAIL) output by the sensing circuit (158).

[0058] FIG. 3 is a drawing for explaining in detail the memory block illustrated in FIG. 2 according to an embodiment of the present invention.

[0059] Referring to FIG. 3, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line (SSL), and the second selection line may be a drain selection line (DSL). More specifically, a memory block (BLKi) may include a plurality of memory cell strings (ST) connected between bit lines (BL1~BLm) and a common source line (CSL). Bit lines (BL1~BLm) may each be connected to a memory cell string (ST), and the common source line (CSL) may be connected to a memory cell string (ST) in common. Since memory cell strings (ST) may be configured identically, a memory cell string (ST) connected to the first bit line (BL1) will be specifically described as an example.

[0060] A memory cell string (ST) may include a source select transistor (SST), a plurality of memory cells (MC1 to MC16), and a drain select transistor (DST) connected in series between a common source line (CSL) and a first bit line (BL1). A single memory cell string (ST) may include at least one drain select transistor (DST), and may also include more source select transistors (SST) and memory cells (MC1 to MC16) than the number shown in the drawing.

[0061] The source of the source select transistor (SST) can be connected to the common source line (CSL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (MC1~MC16) can be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gate of the source select transistor (SST) included in different memory cell strings (ST) can be connected to the source select line (SSL), the gate of the drain select transistor (DST) can be connected to the drain select line (DSL), and the gate of the memory cells (MC1~MC16) can be connected to multiple word lines (WL1~WL16). Among the memory cells included in different memory cell strings (ST), a group of memory cells connected to the same word line can be called a physical page (PG). Accordingly, the memory block (BLKi) may contain as many physical pages (PG) as there are word lines (WL1~WL16).

[0062] A single memory cell can store 1 bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of cells contained in one physical page (PG).

[0063] A single memory cell can store 2 bits or more of data. In this case, a single physical page (PG) can store 2 or more logical pages (LPG) of data.

[0064] FIG. 4 is a diagram illustrating the program operation of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention.

[0065] Referring to FIG. 4, the ISPP method program operation according to an embodiment of the present invention may include a plurality of program operations (PL1 to PLn). That is, a memory device (150) that performs the ISPP method program operation may program a selected memory cell to have one of the plurality of program states by repeatedly performing a plurality of program operations (PL1 to PLn) one by one according to a set order until the program is completed.

[0066] Each of the multiple program operations (PL1 to PLn) may include a program voltage application step (PGM Step) for applying a program voltage and a verification step (Verify Step) for applying a verification voltage to determine whether the memory cell is programmed.

[0067] In the program voltage application step, a program voltage application operation may be performed to apply a program voltage to a selected word line connected to a memory cell selected as a program target. The memory cell selected by the program voltage application operation may be programmed into any one of a plurality of program states.

[0068] According to an embodiment, the potential level of the program voltage may increase each time a plurality of program operations (PL1 to PLn) are performed in the ISPP program operation. That is, the level of the program voltage may increase or decrease stepwise by a predetermined voltage increase as each of the plurality of program operations (PL1 to PLn) is repeatedly performed. The number of times the program voltage is applied, the voltage level, and the voltage application time used in each of the plurality of program operations (PL1 to PLn) may be determined in various forms according to the control of the control logic (153).

[0069] A program voltage may be applied to the word line selected as the program target. A pass voltage may be applied to the remaining unselected word lines, excluding the word line selected as the program target. The memory device (150) may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of word lines. Accordingly, among the plurality of word lines included in one memory block selected as the program target, a program voltage may be applied to the selected word line, and a pass voltage may be applied to the remaining unselected word lines.

[0070] According to an embodiment, in each of a plurality of program operations (PL1 to PLn), a pass voltage may be applied to all word lines included in a memory block selected as a program target from a first time point to a second time point after the start time. Subsequently, in the memory block selected from a second time point to a third time point, a program voltage may be applied to the word lines selected as a program target, and a pass voltage may continue to be applied to the unselected word lines. According to an embodiment, the pass voltage may always have a set level. According to an embodiment, the pass voltage may have different levels depending on the physical location of the word lines.

[0071] A program allowance voltage may be applied to selected bit lines connected to memory cells selected as program targets. A program prohibition voltage may be applied to unselected bit lines connected to memory cells other than the memory cells selected as program targets. According to an embodiment, the program allowance voltage may be ground voltage (VSS) and the program prohibition voltage may be power supply voltage (VCORE).

[0072] Whenever each of the multiple program operations (PL1~PLn) is performed, a bitline precharge operation can be performed to precharge each of the multiple bitlines (BL1~BLm) connected to the multiple memory cells to a set potential level, for example, a program allow potential level or a program prohibit potential level.

[0073] According to an embodiment, among a plurality of program operations (PL1~PLn), when performing the first program operation (PL1), a bitline precharge operation that precharges each of a plurality of bitlines (BL1~BLm) connected to a plurality of memory cells to a set potential level can be controlled to have a longer length than a bitline precharge operation that precharges each of a plurality of bitlines (BL1~BLm) connected to a plurality of memory cells to a set potential level when performing the remaining program operations (PL2~PLn) excluding the first.

[0074] For example, when performing the first program operation (PL1), a bitline precharge operation can be performed from the fourth time point, which precedes the first time point, to the second time point, in which each of the multiple bitlines (BL1~BLm) connected to multiple memory cells is precharged to a set potential level.

[0075] When performing the remaining program operations (PL2~PLn) excluding the first, a bitline precharge operation in which each of the multiple bitlines (BL1~BLm) connected to multiple memory cells is precharged to a set potential level can be performed from the fourth time point up to the fifth time point, which is the same as or earlier than the first time point.

[0076] Here, the fourth time point may be a time point preceding the first time point at which a pass voltage begins to be applied to a plurality of word lines included in the memory block selected as the program target. Additionally, the second time point may be a time point later than the first time point at which a program voltage begins to be applied to a program-selected word line among a plurality of word lines included in the memory block selected as the program target. Additionally, the fifth time point may be the same as or earlier than the first time point at which a pass voltage begins to be applied to all word lines of the selected memory block.

[0077] Therefore, among the multiple program operations (PL1~PLn), it can be seen that the bitline precharge operation performed in the first program operation (PL1) and the bitline precharge operation performed in the remaining program operations (PL2~PLn), excluding the first, start at the same point in time (the fourth point in time) but end at different points in time (the second point in time / the fifth point in time). At this time, since the second point in time is later than the fifth point in time, it can be seen that the bitline precharge operation performed in the first program operation (PL1) among the multiple program operations (PL1~PLn) has a longer length than the bitline precharge operation performed in the remaining program operations (PL2~PLn), excluding the first.

[0078] In the program verification step, the memory device (150) may apply a verification voltage to a word line selected as a program target and apply a verification pass voltage to a word line not selected. The memory device (150) may detect a voltage or current output through a bit line connected to each memory cell connected to the word line selected as a program target, and determine whether the verification step is a pass or a fail based on the detected result.

[0079] In the program verification step, a program verification operation may be performed for at least one of a plurality of program states. For example, if a memory cell to be programmed into the k-th program state (where k is a natural number greater than or equal to 1) is read as an off cell by a verification voltage corresponding to the k-th program state, the program verification operation for the k-th state may be passed.

[0080] In FIG. 4, if the memory cell selected as the program target is a Multi-Level Cell (MLC) that stores two data bits, the selected memory cell may be programmed into an erase state and any one of the first to third program states. The number of data bits stored by the memory cell is not limited to this embodiment.

[0081] In such a case, when the first program operation (PL1) is performed, after the first program voltage (Vpgm1) is applied, the first to third verification voltages (V_vfy1~V_vfy3) may be applied sequentially to verify the program state of a plurality of memory cells. At this time, a memory cell whose target state is the first program state may be verified by the first verification voltage (V_vfy1), a memory cell whose target state is the second program state may be verified by the second verification voltage (V_vfy2), and a memory cell whose target state is the third program state may be verified by the third verification voltage (V_vfy3). The number of verification voltages is not limited to this embodiment.

[0082] Memory cells that pass verification by each verification voltage (V_vfy1~V_vfy3) are determined to have a target state and will then be switched to a program inhibit state in the second program operation (PL2). A program inhibit voltage may be applied to the bit line connected to the program inhibited memory cell. In the second program operation (PL2), a second program voltage (Vpgm2) that is unit voltage (△Vpgm) higher than the first program voltage (Vpgm1) may be applied to the selected word line.

[0083] The verification operation for the second program operation (PL2) may be the same as the verification operation for the first program operation (PL1). For example, the verification pass indicates that the memory cell is read as off-cell by the corresponding verification voltage.

[0084] According to an embodiment, if the program is not completed within a preset number of program operations, the ISPP program operation may be determined to fail. If the program is completed within a preset number of program operations, the ISPP program operation may be determined to pass. Whether the program is completed may be determined by whether the program verification operation for memory cells of a set ratio or higher among the memory cells selected as program targets has passed.

[0085] According to an embodiment, at least one program operation may be performed during the ISPP program operation. The program operation progress may indicate how many of the multiple program operations (PL1 to PLn) have been completed during the ISPP program operation.

[0086] FIG. 5 is a drawing for explaining in detail the page buffer illustrated in FIG. 2 according to an embodiment of the present invention.

[0087] First, referring to FIGS. 1 to 5, a memory device (150) may include a memory cell array (151) and a peripheral circuit (152). Here, the memory cell array (151) may include a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines (BL1 to BLm). And, the plurality of memory cells may be connected to a plurality of page buffers (PB1 to PBm) included in a page buffer group (156) included in the peripheral circuit (152) through a plurality of bit lines (BL1 to BLm).

[0088] Multiple page buffers (PB1~PBm) can store data (DATA) received from the outside through the data input / output circuit (157) under the control of the control logic (153) by transmitting it to multiple memory cells through the bit lines (BL1~BLm). Additionally, multiple page buffers (PB1~PBm) can sense data (DATA) stored in multiple memory cells under the control of the control logic (153) and transmit it to the data input / output circuit (157) through the bit lines (BL1~BLm) to output it externally.

[0089] The operation of transferring and storing data (DATA) received from the outside in multiple page buffers (PB1~PBm) to multiple memory cells through bit lines (BL1~BLm) may be an operation of programming each of the multiple memory cells included in the memory cell array (151) to have one of the multiple program states according to the value of the data (DATA) received from the outside.

[0090] Specifically, each (PBx) of the plurality of page buffers (PB1~PBm) according to an embodiment of the present invention may be connected between one of the bitlines (BL1~BLm) and a detection node (SO). Additionally, each (PBx) of the plurality of page buffers (PB1~PBm) may include a bitline control unit (410) and a latch (430).

[0091] Here, the latch (430) included in each of the multiple page buffers (PB1~PBm) can have a logical level stored internally determined according to whether a program is allowed for each of the multiple bit lines (BL1~BLm).

[0092] Additionally, the bitline control unit (410) included in each of the multiple page buffers (PB1~PBm) can electrically connect each of the multiple bitlines (BL1~BLm) to the power supply voltage (VCORE) terminal or the ground voltage (VSS) terminal based on the logic level stored in the latch (430) during the execution period of the bitline precharge operation.

[0093] Here, the bitline precharge operation may refer to an operation of precharging each of a plurality of bitlines (BL1~BLm) connected to a plurality of memory cells to a set potential level, for example, a program allowable potential level or a program prohibition potential level, whenever each of a plurality of program operations (PL1~PLn) is repeated one by one according to the ISPP (Incremental Step Pulse Program) method as described in FIG. 4 above. According to an embodiment, the program allowable voltage may be the ground voltage (VSS), and the program prohibition voltage may be the power supply voltage (VCORE).

[0094] More specifically, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that a first logic level is stored in a latch (430) corresponding to a first bit line that is allowed to program among a plurality of bit lines (BL1~BLm).

[0095] Additionally, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that a second logic level is stored in a latch (430) corresponding to a second bit line that is prohibited from programming among a plurality of bit lines (BL1~BLm).

[0096] For reference, the first logic level and the second logic level may represent opposite logic levels. For example, if the first logic level is a logic 'high' level corresponding to the power supply voltage (VCORE) level, the second logic level may be a logic 'low' level corresponding to the ground voltage (VSS).

[0097] And, the bitline control unit (410) included in each of the multiple page buffers (PB1~PBm) can electrically connect the bitline (BL) and the ground voltage (VSS) terminal when the first logic level is stored in the latch (430) during the execution period of the bitline precharge operation.

[0098] Additionally, the bitline control unit (410) included in each of the multiple page buffers (PB1~PBm) can electrically connect the bitline (BL) and the power supply voltage (VCORE) terminal when the second logic level is stored in the latch (430) during the execution period of the bitline precharge operation.

[0099] More specifically, the bitline control unit (410) included in each of the multiple page buffers (PB1~PBm) may include a first connection control unit (411), a second connection control unit (412), and a third connection control unit (413).

[0100] Here, the first connection control unit (411) can electrically connect the bit line (BL) and the detection node (SO) in response to the first control signal (SEL_BL, PBSENSE, SA_SENSE).

[0101] Additionally, the second connection control unit (412) can electrically connect the detection node (SO) and the power supply voltage (VCORE) terminal in response to the second control signal (SA_PRECH_N) and the logic level stored in the latch (430).

[0102] Additionally, the third connection control unit (413) can electrically connect the detection node (SO) and the ground voltage (VSS) terminal in response to the third control signal (SA_DISCH) and the logic level stored in the latch (430).

[0103] At this time, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) can be generated in the control logic (153) included in the peripheral circuit (152). Additionally, the control logic (153) can activate the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) from the fourth time point to the second time point in response to performing the first program operation (PL1) among a plurality of program operations (PL1~PLn) according to the ISPP method. Additionally, the control logic (153) can activate the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) from the fourth time point to the fifth time point in response to performing the remaining program operations (PL2~PLn) excluding the first of the multiple program operations (PL1~PLn) according to the ISPP method.

[0104] Here, the fourth time point may be a time point preceding the first time point at which a pass voltage begins to be applied to a plurality of word lines included in the memory block selected as the program target. Additionally, the second time point may be a time point later than the first time point at which a program voltage begins to be applied to a program-selected word line among a plurality of word lines included in the memory block selected as the program target. Additionally, the fifth time point may be the same as or earlier than the first time point at which a pass voltage begins to be applied to all word lines of the selected memory block.

[0105] According to an embodiment, the first connection control unit (411) may include three transistors (N1, N2, N6). In this case, each of the three transistors (N1, N2, N6) included in the first connection control unit (411) may be an NMOS transistor.

[0106] According to an embodiment, the first transistor (N1) included in the first connection control unit (411) can be turned on in response to the page buffer sensing signal (PBSENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE). That is, the page buffer sensing signal (PBSENSE) is applied to the gate terminal of the first transistor (N1), and the drain terminal of the first transistor (N1) is connected to a node where the source terminal of the second transistor (N2) and the drain terminal of the third transistor (N3) are electrically connected, and the source terminal of the first transistor (N1) can be connected to the source terminal of the sixth transistor (N6).

[0107] Here, since the first transistor (N1) is an NMOS transistor, the page buffer sensing signal (PBSENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE) can be considered to be in an active state when it is in a logic 'high' state. In addition, when the page buffer sensing signal (PBSENSE) is in an active state, it may have a level that is sufficient to turn on the first transistor (N1) but is lower than the power supply voltage (VCORE) level. For example, assuming the power supply voltage (VCORE) level is 1.8V, the page buffer sensing signal (PBSENSE) may have a level between 1.1V and 1.8V. According to an embodiment, the potential level of the page buffer sensing signal (PBSENSE) may increase stepwise when transitioning from an inactive state to an active state.

[0108] According to an embodiment, the second transistor (N2) included in the first connection control unit (411) can be turned on in response to the bit line selection signal (SEL_BL) among the first control signals (SEL_BL, PBSENSE, SA_SENSE). That is, the bit line selection signal (SEL_BL) is applied to the gate terminal of the second transistor (N2), the drain terminal of the second transistor (N2) is connected to the bit line (BL), and the source terminal of the second transistor (N2) can be connected to a node where the drain terminal of the third transistor (N3) and the drain terminal of the first transistor (N1) are electrically connected.

[0109] Here, since the second transistor (N1) is an NMOS transistor, the bit line selection signal (SEL_BL) among the first control signals (SEL_BL, PBSENSE, SA_SENSE) can be considered to be in an active state when it is in a logic 'high' state. In addition, when the bit line selection signal (SEL_BL) is in an active state, it may have a potential level sufficient to turn on the second transistor (N2), for example, a power supply voltage (VCORE) level.

[0110] According to an embodiment, the sixth transistor (N6) included in the first connection control unit (411) can be turned on in response to the detection signal (SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE). That is, the detection signal (SA_SENSE) is applied to the gate terminal of the sixth transistor (N6), the drain terminal of the sixth transistor (N6) is connected to the detection node (SO), and the source terminal of the sixth transistor (N6) can be connected to the source terminal of the first transistor (N1).

[0111] Here, since the sixth transistor (N6) is an NMOS transistor, the detection signal (SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE) can be considered as an active state when it is in a logic 'high' state. In addition, when the detection signal (SA_SENSE) is in an active state, it may have a potential level sufficient to turn on the sixth transistor (N6), for example, a power supply voltage (VCORE) level.

[0112] According to an embodiment, the second connection control unit (412) may include two transistors (N4, N5). In this case, each of the two transistors (N4, N5) included in the second connection control unit (412) may be a PMOS transistor.

[0113] According to an embodiment, the fourth transistor (N4) included in the second connection control unit (412) can be turned on in response to the logic level of the first node (QS) of the latch (430). That is, the first node (QS) of the latch (430) is connected to the gate terminal of the fourth transistor (N4), the source terminal of the fourth transistor (N4) is connected to the power supply voltage (VCORE) terminal, and the drain terminal of the fourth transistor (N4) can be connected to the source terminal of the fifth transistor (N5).

[0114] Here, since the fourth transistor (N4) is a PMOS transistor, the fourth transistor (N4) can be turned on when the first node (QS) of the latch (430) is in a logic 'low' state.

[0115] According to an embodiment, the fifth transistor (N5) included in the second connection control unit (412) can be turned on in response to the second control signal (SA_PRECH_N). That is, the second control signal (SA_PRECH_N) is applied to the gate terminal of the fifth transistor (N5), the source terminal of the fifth transistor (N5) is connected to the drain terminal of the fourth transistor (N4), and the drain terminal of the fifth transistor (N5) can be connected to the sensing node (SO).

[0116] Here, since the fifth transistor (N5) is a PMOS transistor, the second control signal (SA_PRECH_N) can be considered to be in an active state when it is in a logic 'low' state. In addition, when the second control signal (SA_PRECH_N) is in an active state, it may have a potential level sufficient to turn on the fifth transistor (N5), for example, a ground voltage (VSS) level.

[0117] According to an embodiment, the third connection control unit (413) may include two transistors (N8, N9). In this case, each of the two transistors (N8, N9) included in the third connection control unit (413) may be an NMOS transistor.

[0118] According to an embodiment, the ninth transistor (N9) included in the third connection control unit (413) can be turned on in response to the logic level of the first node (QS) of the latch (430). That is, the first node (QS) of the latch (430) is connected to the gate terminal of the ninth transistor (N9), the source terminal of the ninth transistor (N9) is connected to the ground voltage (VSS) terminal, and the drain terminal of the ninth transistor (N9) can be connected to the source terminal of the eighth transistor (N8).

[0119] Here, since the ninth transistor (N9) is an NMOS transistor, the ninth transistor (N9) can be turned on when the first node (QS) of the latch (430) is in a logic 'high' state.

[0120] According to an embodiment, the eighth transistor (N8) included in the third connection control unit (413) can be turned on in response to the third control signal (SA_DISCH). That is, the third control signal (SA_DISCH) is applied to the gate terminal of the eighth transistor (N8), the source terminal of the eighth transistor (N8) is connected to the drain terminal of the ninth transistor (N9), and the drain terminal of the eighth transistor (N8) can be connected to the sensing node (SO).

[0121] Here, since the 8th transistor (N8) is an NMOS transistor, the 3rd control signal (SA_DISCH) can be considered to be in an active state when it is in a logic 'high' state. In addition, when the 3rd control signal (SA_DISCH) is in an active state, it may have a potential level sufficient to turn on the 8th transistor (N8), for example, a power supply voltage (VCORE) level.

[0122] In addition, the bit line control unit (410) included in each of the multiple page buffers (PB1~PBm) (PBx) may further include a third transistor (N3) in addition to the aforementioned first connection control unit (411), second connection control unit (412), and third connection control unit (413). In this case, the third transistor (N3) may be an NMOS transistor.

[0123] According to an embodiment, the third transistor (N3) can be turned on in response to a bit line discharge signal (BLDIS). That is, a bit line discharge signal (BLDIS) is applied to the gate terminal of the third transistor (N3), the drain terminal of the third transistor (N3) is connected to a node where the source terminal of the second transistor (N2) and the drain terminal of the first transistor (N1) are electrically connected, and the source terminal of the third transistor (N3) can be connected to a ground voltage (VSS) terminal.

[0124] Here, the bit line discharge signal (BLDIS) may be a signal generated by the control logic (153) included in the peripheral circuit (152). The bit line discharge signal (BLDIS) can be activated to discharge the potential level of the bit line (BL) to the ground voltage (VSS) level and turn on the third transistor (N3).

[0125] More specifically, the latch (430) included in each of the multiple page buffers (PB1~PBm) may include a first inverter (IV1), a second inverter (IV2), a tenth transistor (N10), an eleventh transistor (N11), a twelfth transistor (N12), and a thirteenth transistor (N13). In this case, each of the tenth transistor (N10), the eleventh transistor (N11), the twelfth transistor (N12), and the thirteenth transistor (N13) may be an NMOS transistor.

[0126] The first inverter (IV1) and the second inverter (IV2) can be connected in reverse parallel between the first node (QS) and the second node (QS_N) of the latch (430).

[0127] The 10th transistor (N10) and the 11th transistor (N11) can be connected in series between the first node (QS) of the latch (430) and the ground voltage (VSS) terminal. The 10th transistor (N10) can be turned on in response to a first reset signal (SRST), and the 11th transistor (N11) can be turned on in response to a second reset signal (PBRST). When the 10th transistor (N10) and the 11th transistor (N11) are turned on, the first node (QS) and the ground voltage (VSS) terminal can be connected.

[0128] The 12th transistor (N12) and the 13th transistor (N13) can be connected in series between the second node (QS_N) of the latch (430) and the ground voltage (VSS) terminal. The 12th transistor (N12) can be turned on according to the potential level of the sensing node (SO), and the 13th transistor (N13) can be turned on in response to a set signal (SSET). When the 12th transistor (N12) and the 13th transistor (N13) are turned on, the second node (QS_N) and the ground voltage (VSS) terminal can be connected.

[0129] Here, the first reset signal (RST), the second reset signal (PBRST), and the set signal (SSET) may be signals generated by the control logic (153) included in the peripheral circuit (152). The first reset signal (RST) and the second reset signal (PBRST) may be used to initialize the logic level stored in the latch (430). The set signal (SSET) may be used to perform the operation of storing the potential level of the sensing node (SO) as a logic level in the latch (430).

[0130] FIG. 6 is a diagram illustrating the first program operation among the program operations of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention.

[0131] Referring to FIGS. 1 to 6, it can be seen how the first program operation (PL1) among the multiple program operations (PL1 to PLn) in the ISPP method program operation is performed.

[0132] First, a pass voltage (Vpass) can be applied to all word lines (SEL_WL, UNSEL_WL) included in the selected memory block from the first time point (t2) to the second time point (t3) after the start time of the first program operation (PL1).

[0133] Subsequently, from the second time point (t3) to the third time point (t4) of the first program operation (PL1), a program voltage (Vpgm) may be applied to the selected word line (SEL_WL) among all word lines (SEL_WL, UNSEL_WL) included in the selected memory block, and a pass voltage (Vpass) may be applied to the unselected word line (UNSEL_WL).

[0134] When performing the first program operation (PL1), a bitline precharge operation to precharge each of the multiple bitlines (BL1~BLm) connected to multiple memory cells to a set potential level can be started from a fourth time point (t1) which is earlier than a first time point (t2) at which a pass voltage (Vpass) is applied to all wordlines (SEL_WL, UNSEL_WL) included in the selected memory block.

[0135] Thus, the bitline precharge operation started at the fourth time point (t1) can be performed until the second time point (t3) when a program voltage (Vpgm) begins to be applied to the selected wordline (SEL_WL) among all wordlines (SEL_WL, UNSEL_WL) included in the selected memory block.

[0136] That is, when performing the first program operation (PL1), the bitline precharge operation, which precharges each of the multiple bitlines (BL1~BLm) connected to multiple memory cells to a set potential level, can be performed from the fourth time point (t1) to the second time point (t3).

[0137] Meanwhile, to control the execution of the bitline precharge operation, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) may be activated at the fourth time point (t1) and then deactivated at the second time point (t3).

[0138] The first control signal (SEL_BL, PBSENSE, SA_SENSE) and the third control signal (SA_DISCH) can be activated to logic 'high' at the fourth time point (t1) and deactivated to logic 'low' at the second time point (t3). The second control signal (SA_PRECH_N) can be activated to logic 'low' at the fourth time point (t1) and deactivated to logic 'high' at the second time point (t3).

[0139] In the drawing, it can be seen that among the first control signals (SEL_BL, PBSENSE, SA_SENSE), the page buffer sensing signal (PBSENSE) is depicted as being activated to logic 'high' at the fourth time point (t1) and then deactivated to logic 'low' at the second time point (t3). Thus, although the drawing only shows whether the page buffer sensing signal (PBSENSE) is activated, the remaining signals (SEL_BL, SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE), excluding the page buffer sensing signal (PBSENSE), can also be activated to logic 'high' at the fourth time point (t1) and then deactivated to logic 'low' at the second time point (t3).

[0140] Thus, when the first control signal (SEL_BL, PBSENSE, SA_SENSE) is activated at the fourth time point (t1), the sensing node (SO) included in each of the multiple page buffers (PB1~PBm) can be electrically connected to the bit line (BL1~BLm).

[0141] Additionally, when the second control signal (SA_PRECH_N) and the third control signal (SA_DISCH) are activated at the fourth time point (t1), the sensing node (SO) can be electrically connected to the power supply voltage (VDD) terminal or the ground voltage (VSS) terminal depending on the logic level of the first node (QS) of the latch (430).

[0142] Here, the latch (430) included in each of the multiple page buffers (PB1~PBm) may have a logical level stored internally determined according to whether a program is allowed for each of the multiple bit lines (BL1~BLm) prior to the fourth time point (t1).

[0143] That is, the peripheral circuit (152) can control the operation of multiple page buffers (PB1~PBm) so that a first logic level is stored in a latch (430) corresponding to a first bit line that is allowed to program among multiple bit lines (BL1~BLm) before the fourth time point (t1).

[0144] For example, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that the first node (QS) of the latch (430) corresponding to the first bit line becomes the power supply voltage (VDD) level before the fourth time point (t1).

[0145] Thus, when the first node (QS) of the latch (430) corresponding to the first bit line is set to the power supply voltage (VDD) level, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) are activated from the fourth time point (t1) to the second time point (t3), and the state as shown in FIG. 8 can be achieved. That is, from the fourth time point (t1) to the second time point (t3), the first bit line and the ground voltage (VSS) terminal are electrically connected, so the first bit line can be precharged to the ground voltage (VSS) level.

[0146] Additionally, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that a second logic level is stored in a latch (430) corresponding to a second bit line that is prohibited from programming among a plurality of bit lines (BL1~BLm).

[0147] For example, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that the first node (QS) of the latch (430) corresponding to the second bit line becomes the ground voltage (VSS) level before the fourth time point (t1).

[0148] Thus, when the first node (QS) of the latch (430) corresponding to the first bit line is set to the ground voltage (VSS) level, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) are activated from the fourth time point (t1) to the second time point (t3), and the state as shown in FIG. 9 can be achieved. That is, from the fourth time point (t1) to the second time point (t3), the first bit line and the power supply voltage (VDD) terminal are electrically connected, so the first bit line can be precharged to the power supply voltage (VDD) level.

[0149] For reference, it can be seen that when the page buffer sensing signal (PBSENSE) transitions from an inactive state to an active state at the fourth time point (t1), the potential level increases in stages. This may be a method used to prevent the peak current of the memory device from becoming excessively high if the page buffer sensing signal (PBSENSE) transitions to the maximum active potential level all at once at the fourth time point (t1). Additionally, regarding the signals (SEL_BL, SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE) that are not directly illustrated in the drawing, when transitioning from an inactive state to an active state at the fourth time point (t1), the potential level may increase in stages like the page buffer sensing signal (PBSENSE), or the potential level may increase all at once, unlike the page buffer sensing signal (PBSENSE).

[0150] FIG. 7 is a diagram illustrating the remaining program operations, excluding the first, of the program operations of the ISPP (Incremental Step Pulse Program) method according to an embodiment of the present invention.

[0151] Referring to FIGS. 1 to 7, it can be seen how the remaining program operations (PL2 to PLm), excluding the first of the multiple program operations (PL1 to PLn), are performed in the ISPP method program operation.

[0152] First, a pass voltage (Vpass) can be applied to all word lines (SEL_WL, UNSEL_WL) included in the selected memory block from the first time point (t7) to the second time point (t8) after the start time of each of the remaining program operations (PL2~PLm) excluding the first one.

[0153] Next, from the second time point (t8) to the third time point (t9) of each of the remaining program operations (PL2~PLm) excluding the first, a program voltage (Vpgm) may be applied to the selected word line (SEL_WL) among all word lines (SEL_WL, UNSEL_WL) included in the selected memory block, and a pass voltage (Vpass) may be applied to the unselected word line (UNSEL_WL).

[0154] When performing each of the remaining program operations (PL2~PLm) excluding the first one, a bitline precharge operation that precharges each of the multiple bitlines (BL1~BLm) connected to multiple memory cells to a set potential level can be started from a fourth time point (t5) which is earlier than a first time point (t7) at which a pass voltage (Vpass) is applied to all wordlines (SEL_WL, UNSEL_WL) included in the selected memory block.

[0155] Thus, the bitline precharge operation started at the fourth time point (t5) can be performed up to the fifth time point (t6), which is the same as or earlier than the first time point (t7) at which a pass voltage (Vpass) begins to be applied to all wordlines (SEL_WL, UNSEL_WL) included in the selected memory block. For reference, although the drawing shows the fifth time point (t6) as being earlier than the first time point (t7), this is merely one embodiment, and the fifth time point (t6) and the first time point (t7) may be the same time point depending on the designer's choice.

[0156] That is, when performing each of the remaining program operations (PL2~PLm) excluding the first one, the bitline precharge operation, which precharges each of the multiple bitlines (BL1~BLm) connected to multiple memory cells to a set potential level, can be performed from the fourth time point (t5) to the fifth time point (t6).

[0157] Meanwhile, to control the execution of the bitline precharge operation, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) may be activated at the fourth time point (t5) and then deactivated at the fifth time point (t6).

[0158] The first control signal (SEL_BL, PBSENSE, SA_SENSE) and the third control signal (SA_DISCH) can be activated to logic 'high' at the fourth time point (t5) and deactivated to logic 'low' at the fifth time point (t6). The second control signal (SA_PRECH_N) can be activated to logic 'low' at the fourth time point (t5) and deactivated to logic 'high' at the fifth time point (t6).

[0159] In the drawing, it can be seen that among the first control signals (SEL_BL, PBSENSE, SA_SENSE), the page buffer sensing signal (PBSENSE) is depicted as being activated to logic 'high' at the fourth time point (t5) and then deactivated to logic 'low' at the fifth time point (t6). Thus, although the drawing only shows whether the page buffer sensing signal (PBSENSE) is activated, the remaining signals (SEL_BL, SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE), excluding the page buffer sensing signal (PBSENSE), can also be activated to logic 'high' at the fourth time point (t5) and then deactivated to logic 'low' at the fifth time point (t6).

[0160] In this way, when the first control signal (SEL_BL, PBSENSE, SA_SENSE) is activated at the fourth time point (t5), the sensing node (SO) included in each of the multiple page buffers (PB1~PBm) can be electrically connected to the bit line (BL1~BLm).

[0161] Additionally, when the second control signal (SA_PRECH_N) and the third control signal (SA_DISCH) are activated at the fourth time point (t5), the sensing node (SO) can be electrically connected to the power supply voltage (VDD) terminal or the ground voltage (VSS) terminal depending on the logic level of the first node (QS) of the latch (430).

[0162] Here, the latch (430) included in each of the multiple page buffers (PB1~PBm) can have its internally stored logic level determined according to whether a program is allowed for each of the multiple bit lines (BL1~BLm) prior to the fourth time point (t5).

[0163] That is, the peripheral circuit (152) can control the operation of multiple page buffers (PB1~PBm) so that a first logic level is stored in a latch (430) corresponding to a first bit line among multiple bit lines (BL1~BLm) for which a program is allowed before the fourth time point (t5).

[0164] For example, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that the first node (QS) of the latch (430) corresponding to the first bit line becomes the power supply voltage (VDD) level before the fourth time point (t5).

[0165] Thus, when the first node (QS) of the latch (430) corresponding to the first bit line is set to the power supply voltage (VDD) level, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) are activated from the fourth time point (t5) to the fifth time point (t6), and the state as shown in FIG. 8 can be achieved. That is, from the fourth time point (t5) to the fifth time point (t6), the first bit line and the ground voltage (VSS) terminal are electrically connected, so the first bit line can be precharged to the ground voltage (VSS) level.

[0166] Additionally, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that a second logic level is stored in a latch (430) corresponding to a second bit line that is prohibited from programming among a plurality of bit lines (BL1~BLm).

[0167] For example, the peripheral circuit (152) can control the operation of a plurality of page buffers (PB1~PBm) so that the first node (QS) of the latch (430) corresponding to the second bit line becomes the ground voltage (VSS) level before the fourth time point (t5).

[0168] Thus, when the first node (QS) of the latch (430) corresponding to the first bit line is set to the ground voltage (VSS) level, the first control signal (SEL_BL, PBSENSE, SA_SENSE), the second control signal (SA_PRECH_N), and the third control signal (SA_DISCH) are activated from the fourth time point (t5) to the fifth time point (t6), and the state as shown in FIG. 9 can be achieved. That is, from the fourth time point (t5) to the fifth time point (t6), the first bit line and the power supply voltage (VDD) terminal are electrically connected, so the first bit line can be precharged to the power supply voltage (VDD) level.

[0169] For reference, it can be seen that when the page buffer sensing signal (PBSENSE) transitions from an inactive state to an active state at the fourth time point (t5), the potential level increases in stages. This may be a method used to prevent the peak current of the memory device from becoming excessively high if the page buffer sensing signal (PBSENSE) transitions to the maximum active potential level all at once at the fourth time point (t5). Additionally, regarding the signals (SEL_BL, SA_SENSE) among the first control signals (SEL_BL, PBSENSE, SA_SENSE) that are not directly illustrated in the drawing, when transitioning from an inactive state to an active state at the fourth time point (t5), the potential level may increase in stages like the page buffer sensing signal (PBSENSE), or the potential level may increase all at once, unlike the page buffer sensing signal (PBSENSE).

[0170] It will be obvious to those skilled in the art that the invention described above is not limited by the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the invention.

[0171] For example, the logic gates and transistors exemplified in the above-described embodiment must be implemented with different positions and types depending on the polarity of the input signal.

Claims

Claim 1 A memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines; and a memory device comprising a peripheral circuit that uses an Increment Step Pulse Program (ISPP) method to repeat program operations until the program is completed, wherein, each time the program operation is performed, a pass voltage is applied to each of the first word line selected by the program and the second word line not selected among the plurality of word lines from a first time point to a second time point, and then applies a program voltage to the first word line and the pass voltage to the second word line from the second time point to a third time point, wherein the peripheral circuit, during the program operations repeated through the ISPP method, performs a bit line precharge operation to precharge each of the plurality of bit lines to a set potential level from a fourth time point preceding the first time point to the second time point, and performs the bit line precharge operation from the fourth time point to a fifth time point that is the same as or preceding the first time point when performing the remaining program operations excluding the first. Claim 2 A memory device according to claim 1, wherein the peripheral circuit comprises: an address decoder for applying the pass voltage or the program voltage to the plurality of word lines; and a plurality of page buffers each connected to the plurality of memory cells through the plurality of bit lines, wherein each of the plurality of page buffers includes: a latch in which a logic level stored internally is determined according to whether a program for the bit line is allowed; and a bit line control unit that electrically connects the bit line to a power supply voltage terminal or a ground voltage terminal based on the logic level stored in the latch during the bit line precharge operation period. Claim 3 In paragraph 2, the peripheral circuit is a memory device that controls the operation of the plurality of page buffers so that a first logic level is stored in the latch corresponding to the first bit line for which a program is allowed among the plurality of bit lines. Claim 4 In paragraph 3, the peripheral circuit is a memory device that controls the operation of the plurality of page buffers so that a second logic level is stored in the latch corresponding to the second bit line for which a program is prohibited among the plurality of bit lines. Claim 5 In paragraph 4, the bitline control unit is a memory device that electrically connects the bitline and the ground voltage terminal when the first logic level is stored in the latch during the bitline precharge operation section. Claim 6 In claim 5, the bitline control unit is a memory device that electrically connects the bitline and the power supply voltage terminal when the second logic level is stored in the latch during the bitline precharge operation period. Claim 7 In paragraph 2, the bitline control unit comprises: a first connection control unit for electrically connecting the bitline and the sensing node in response to a first control signal; a second connection control unit for electrically connecting the sensing node and the power supply voltage terminal in response to a second control signal and the logic level of the latch; and a third connection control unit for electrically connecting the sensing node and the ground voltage terminal in response to a third control signal and the logic level of the latch. Claim 8 A memory device according to claim 7, wherein the peripheral circuit further comprises control logic that activates the first to third control signals from the fourth time point to the second time point in response to performing the first program operation, and activates the first to third control signals from the fourth time point to the fifth time point in response to performing the remaining program operations excluding the first. Claim 9 A method of operation of a memory device comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, comprising: a program operation step of applying a pass voltage to each of a first word line selected by program and a second word line not selected among the plurality of word lines from a first time point to a second time point after a start time point, and then applying a program voltage to the first word line and the pass voltage to the second word line from the second time point to a third time point; a repetition step of repeating the program operation step through an Increment Step Pulse Program (ISPP) method until the program is completed; and a first precharge step of performing a bit line precharge operation to precharge each of the plurality of bit lines to a set potential level from a fourth time point preceding the first time point to the second time point when performing the first program operation step in the repetition step. A method of operation of a memory device comprising a second precharge step in which the bitline precharge operation is performed from the fourth time point to the fifth time point, which is the same as or earlier than the first time point, when performing the remaining program operation steps excluding the first in the above repetition step. Claim 10 A method of operation of a memory device according to claim 9, further comprising: a latching step of determining a logic level corresponding to each of the plurality of bit lines and latching according to whether a program is allowed for each of the plurality of bit lines when performing the program operation step; and a connection step of electrically connecting each of the plurality of bit lines to a power supply voltage terminal or a ground voltage terminal based on the logic level of the latching step during the execution period of the bit line precharge operation. Claim 11 In claim 10, the above latching step comprises: a step of latching a first logic level corresponding to a first bit line among the plurality of bit lines for which a program is allowed; and a step of latching a second logic level corresponding to a second bit line among the plurality of bit lines for which a program is prohibited. Claim 12 A method of operation of a memory device according to claim 11, wherein the connection step comprises: a step of electrically connecting the first bit line and the ground voltage terminal during the execution period of the bit line precharge operation; and a step of electrically connecting the second bit line and the power supply voltage terminal during the execution period of the bit line precharge operation. Claim 13 A method of operation of a memory device comprising a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, comprising: a step of applying a pass voltage to each of the plurality of word lines from a first time point to a second time point in each of an initial program loop and a plurality of subsequent program loops following the same for the plurality of memory cells according to an Increment Step Pulse Program (ISPP) method; a first pulse step of precharging the plurality of bit lines from a third time point preceding the first time point to the second time point in the initial program loop; and a second precharge step of precharging the plurality of bit lines from the third time point to a fourth time point that is the same as or preceding the first time point in each of the plurality of subsequent programs.

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