Apparatus and method for artificial neural network model based electronic design automation using homomorphic encryption

Abstract

The electronic design automation method based on an artificial neural network model of a server according to the present invention may include: receiving circuit representation data generated from a netlist in a form encrypted using a homomorphic encryption method; applying the encrypted circuit representation data to a predetermined Graph Neural Network (GNN) model to output an encrypted circuit characteristic vector in which the topology of the circuit and component information are expressed as a context; applying the encrypted circuit characteristic vector to a predetermined surrogate model to output an encrypted circuit operation characteristic prediction value; applying a circuit design netlist and a PDK (Process Design Kit) stored in the server to a simulator to output a circuit operation characteristic value; applying the encrypted circuit operation characteristic prediction value and the circuit operation characteristic value to a predetermined optimization policy-based artificial neural network model to output a circuit design parameter value; and updating the circuit design parameters within the circuit design netlist stored in the server with the output circuit design parameter value.

Description

Technology Field

[0001] The present invention relates to an apparatus and method for electronic design automation based on an artificial neural network model, and more specifically, to an apparatus and method for electronic design automation based on an artificial neural network model that uses or applies homomorphic encryption during learning or inference to ensure client privacy, and automatically adjusts circuit design parameter values ​​through an optimization policy-based artificial neural network model to iteratively optimize the circuit so that it satisfies target specifications while complying with PDK constraints. Background Technology

[0002] Federated learning is a distributed machine learning technique that enables AI models to train by collaborating on data stored across multiple locations without directly sharing it. It is one of the methods used to train deep learning models. The quality and quantity of data are critical for training deep learning models. Generally, to train deep learning models, data is collected on a single server and refined for use. However, due to the nature of the data, it is difficult to export externally, and in the case of data related to personal privacy, directly transferring it to a server poses a risk of personal information infringement.

[0003] Federated learning is a method for training deep learning models using such data, which allows the model to be trained without leaking data from the user's device.

[0004] Since the only information exchanged between the server and the local client is the local model and the global model, the data collected by the local client never goes beyond the local client's control, so sensitive information related to users can be protected.

[0005] However, as the number of clients participating in federated learning increases, there are issues such as rising network costs for exchanging models and training parameters, and bottlenecks caused by performance differences among clients leading to a decrease in the learning speed.

[0006] In particular, in the field of Electronic Design Automation (EDA), federated learning is deemed necessary because there is a large amount of data treated as confidential by each company and maintaining and protecting ownership of design data is crucial; however, there has been almost no research on the specific details of learning methods and mechanisms in federated learning within the EDA field. Prior art literature

[0007] Korean Patent Publication No. 10-2025-0013087 The problem to be solved

[0008] The technical problem to be solved by the present invention is to provide an electronic design automation method based on an artificial neural network model using homomorphic encryption.

[0009] Another technical objective of the present invention is to provide an electronic design automation device based on an artificial neural network model using homomorphic encryption.

[0010] Another technical objective of the present invention is to provide a method for a client to perform data processing for electronic design automation based on an artificial neural network model using homomorphic encryption.

[0011] Another technical objective of the present invention is to provide a client device that performs data processing for electronic design automation based on an artificial neural network model using homomorphic encryption.

[0012] Another technical objective of the present invention is to provide a computer-readable recording medium that records a program for executing on a computer an electronic design automation method based on an artificial neural network model using homomorphic encryption.

[0013] The technical problems to be solved by the present invention are not limited to the above technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0014] A method for automating electronic design based on an artificial neural network model of a server according to the present invention, for achieving the above technical objectives, may include: receiving circuit representation data generated from a netlist in a form encrypted using a homomorphic encryption method; applying the encrypted circuit representation data to a predetermined Graph Neural Network (GNN) model to output an encrypted circuit characteristic vector in which the circuit topology and component information are expressed as a context; applying the encrypted circuit characteristic vector to a predetermined surrogate model to output an encrypted circuit operation characteristic prediction value; applying a circuit design netlist and a PDK (Process Design Kit) stored in the server to a simulator to output a circuit operation characteristic value; applying the encrypted circuit operation characteristic prediction value and the circuit operation characteristic value to a predetermined optimization policy-based artificial neural network model to output a circuit design parameter value; and updating the circuit design parameters within the circuit design netlist stored in the server with the output circuit design parameter value.

[0015] The above method may further include a step of optimizing the circuit design parameters by repeating the above steps until the updated circuit design parameter values ​​satisfy the target specifications while complying with the constraints of the PDK.

[0016] The above method may include the steps of: receiving model update information generated by local learning from a plurality of clients; aggregating the received model update information to update the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on federated learning; and redistributing the updated model parameters to the plurality of clients.

[0017] The steps of outputting the encrypted circuit characteristic vector and outputting the encrypted circuit operation characteristic prediction value can perform operations on the GNN model and the surrogate model on the encrypted circuit representation data without decryption. Operations on the encrypted circuit representation data can be performed using a homomorphic encryption method in both the model training step and the inference step. Circuit design parameter values ​​can be output in an encrypted state.

[0018] The above method includes the step of providing an initial integrated model, comprising the GNN model, the surrogate model, and the optimization policy-based artificial neural network model, to each client, wherein the federated learning is performed on the initial integrated model as a unit, and the initial integrated model is initialized on the server prior to the start of the federated learning.

[0019] In the above method, the federated learning-based parameter update step may include: a step of applying weights to the model update information for each of the plurality of clients to reflect the contribution to performance improvement of the artificial neural network model-based electronic design automation; and a step of updating the parameters of the GNN model and the surrogate model using the model update information to which the weights have been applied. A method for a client according to the present invention to perform data processing for artificial neural network model-based electronic design automation using homomorphic encryption to achieve other technical objectives may include: a step of generating circuit representation data representing the topology and component information of a circuit by applying a netlist to a graph embedding or feature extraction process; a step of generating encrypted circuit representation data by encrypting the generated circuit representation data using a homomorphic encryption method; a step of transmitting the encrypted circuit representation data to a server; and a step of receiving updated model parameters from the server and applying them to local learning or subsequent data processing. The encrypted circuit representation data may be generated to be used as a common input in both the training and inference stages of a predetermined Graph Neural Network (GNN) model.

[0020] An electronic design automation device based on an artificial neural network model according to the present invention, for achieving another technical objective described above, may include: a communication unit that receives circuit representation data generated from a netlist in a form encrypted using a homomorphic encryption method; a first processing unit that applies the encrypted circuit representation data to a predetermined Graph Neural Network (GNN) model to output an encrypted circuit characteristic vector in which the topology of the circuit and component information are expressed as a context; a second processing unit that applies the encrypted circuit characteristic vector to a predetermined surrogate model to output a predicted value of circuit operation characteristics; a simulator that outputs a circuit operation characteristic value using a netlist for circuit design stored in the server and the PDK (Process Design Kit); a third processing unit that applies the predicted value of circuit operation characteristics and the circuit operation characteristic value to a predetermined optimization policy-based artificial neural network model to output a circuit design parameter value; and a fourth processing unit that updates the circuit design parameters within the netlist with the outputted circuit design parameter value.

[0021] The above-mentioned fourth processing unit can optimize the circuit design parameters by controlling the first to third processing units until the updated circuit design parameter values ​​satisfy the target specifications while complying with the constraints of the PDK.

[0022] The communication unit receives model update information generated by local learning from a plurality of clients, and the fourth computation processing unit aggregates the received model update information and updates the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on federated learning, and the communication unit can redistribute the updated model parameters to the plurality of clients.

[0023] The first operation processing unit and the second operation processing unit can perform operations on the GNN model and the surrogate model on the encrypted circuit representation data without decryption. Operations on the encrypted circuit representation data can be performed using a homomorphic encryption method in both the model training phase and the inference phase.

[0024] The communication unit provides an initial integrated model including the GNN model, the surrogate model, and the optimization policy-based artificial neural network model to each client, and the federated learning is performed on the initial integrated model as a unit, and the initial integrated model may be initialized on the device before the federated learning starts.

[0025] The fourth computational processing unit may apply weights to the model update information for each of the plurality of clients to reflect the contribution to the performance improvement of the artificial neural network model-based electronic design automation for the federated learning-based parameter update, and update the parameters of the GNN model and the surrogate model using the model update information to which the weights have been applied. The predetermined optimization policy-based artificial neural network model may be a reinforcement learning-based model.

[0026] A client device for performing data processing for electronic design automation based on an artificial neural network model according to the present invention, for achieving another technical challenge described above, comprises: a processing unit that generates circuit representation data representing the topology and component information of a circuit by applying a netlist to a graph embedding or feature extraction process, and generates encrypted circuit representation data by encrypting the generated circuit representation data using a homomorphic encryption method; and a communication unit that transmits the encrypted circuit representation data to a server, wherein the processing unit may apply updated model parameters received from the server by the communication unit to local learning or subsequent data processing. Effects of the invention

[0027] The present invention can significantly improve the simulation speed during the iterative optimization process by introducing a surrogate model (Neural Simulator) to approximate the calculations of the actual simulator (160). Therefore, it has the advantage of being able to secure valid design candidates in a short time, even when the design search space is wide.

[0028] In addition, the present invention has the advantage of achieving both accuracy and efficiency by combining the output of a surrogate model (Neural Simulator) with that of an actual simulator to simultaneously perform rapid search / approximation and accurate verification.

[0029] Furthermore, the present invention goes beyond simply analyzing performance to automatically adjust circuit design parameter values ​​through an optimization policy-based artificial neural network model. As a result, the circuit is iteratively optimized to satisfy target specifications while complying with PDK constraints, thereby reducing the burden of manual tuning for circuit designers and enabling automatic design optimization that meets target specifications.

[0030] Furthermore, since the present invention utilizes GNN-based circuit characteristic vector representation to handle various topologies and device conditions without being limited to specific circuit blocks, it is applicable in various design areas such as analog circuits, digital circuits, and mixed-signal circuits.

[0031] The present invention simultaneously realizes rapid search, accurate verification, and automatic optimization, thereby having the effect of improving design speed, accuracy, productivity, and security compared to conventional technology.

[0032] In addition, by combining with a federated learning structure, it is possible to train and optimize global models without directly sharing confidential data from various companies / clients, which offers the advantage of high industrial utility. By securely utilizing local data from various clients through federated learning, this invention can significantly contribute to the efficient construction and maintenance of highly reliable circuit simulation prediction models. Furthermore, as it can simultaneously realize data privacy protection and maximize model performance, it can serve as a solution that dramatically enhances competitiveness in the semiconductor and electronic design fields.

[0033] In addition, since the server in the present invention does not directly recognize the client's original circuit structure, component connection relationships, and circuit design know-how, it is possible to fundamentally prevent design data requiring a high degree of confidentiality, such as semiconductor circuit design, from being leaked or exposed to the outside.

[0034] Furthermore, since the present invention uses encrypted circuit representation data as input in both the model training and inference stages, it enables consistent data privacy protection throughout the entire training and inference process, unlike existing methods where protection is limited to specific stages.

[0035] In addition, the present invention can continuously improve the performance of a global model while maintaining the privacy of circuit design data by providing only the generated model update information to the server.

[0036] Furthermore, in the present invention, by utilizing the output results of a GNN model for homomorphic encryption-based circuit representation data together with actual circuit operation characteristic values ​​calculated through a Process Design Kit (PDK) stored on a server and a simulator, high-precision prediction of circuit operation characteristics and reliable optimization of design parameters can be performed simultaneously. Accordingly, compared to a method that relies solely on inference results for encrypted data, design optimization reflecting actual process conditions becomes possible.

[0037] In addition, the present invention provides the advantage of minimizing the computational burden associated with homomorphic encryption operations by selectively applying homomorphic encryption to abstracted input data, such as circuit representation data, and configuring areas such as process design kits (PDKs), simulators, and design parameter updates to be processed in plaintext within a trusted server environment.

[0038] The effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0039] The accompanying drawings, which are included as part of the detailed description to aid in understanding the present invention, provide embodiments of the present invention and explain the technical concept of the present invention together with the detailed description. Figure 1 is a diagram illustrating the layer structure of an artificial neural network. Figure 2 is a diagram illustrating an example of a deep neural network. Figure 3 is a diagram illustrating a system that performs learning by collaborating on a circuit simulation prediction model using a federated learning method. FIG. 4 is a block diagram schematically showing the internal configuration of a client (device) according to the present invention. Figure 5 is a conceptual diagram of the design learning process for utilizing GNN in a homomorphic encryption-based federated learning environment according to the present invention. FIG. 6 is a diagram illustrating the uplink in which data is transmitted from a client to a server during the inference process of a circuit optimization technology utilizing a homomorphic encryption-based GNN according to an embodiment of the present invention. FIG. 7 is a conceptual diagram of the downlink transmission of the GNN inference process in a homomorphic encryption-based federated learning environment according to one embodiment of the present invention. FIG. 8 is a block diagram illustrating the configuration of an artificial neural network model-based electronic design automation device (100) using homomorphic encryption according to the present invention. FIG. 9 is an exemplary diagram illustrating the operating principle of an artificial neural network model-based electronic design automation device (100) using homomorphic encryption according to the present invention. Specific details for implementing the invention

[0040] Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The detailed description disclosed below, together with the accompanying drawings, is intended to describe exemplary embodiments of the present invention and is not intended to represent the only embodiment in which the present invention may be practiced. The following detailed description includes specific details to provide a complete understanding of the present invention. However, those skilled in the art will know that the present invention may be practiced without such specific details.

[0041] In some cases, to avoid obscuring the concept of the present invention, known structures and devices may be omitted or illustrated in the form of block diagrams focusing on the core functions of each structure and device. Additionally, throughout this specification, the same components are described using the same reference numerals.

[0042] The present invention is capable of various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0043] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0044] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0045] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0046] Furthermore, the components of the embodiments described with reference to each drawing are not limited to the respective embodiments and may be implemented to be included in other embodiments within the scope of maintaining the technical spirit of the present invention. It is also obvious that multiple embodiments may be re-implemented as a single embodiment that integrates multiple embodiments, even if a separate description is omitted.

[0047] In addition, terms such as "~part," "~unit," "~module," and "~device" described in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware, software, or a combination of hardware and software. In the present invention, "~part" may be replaced with "~module."

[0048] Before describing the present invention below, the artificial neural network model used in the present invention will be briefly described first.

[0049] Deep learning is a type of artificial neural network (ANN) based on human neural network theory. It is a set of machine learning models or algorithms that refer to a deep neural network (DNN) composed of a layer structure and having one or more hidden layers (hereinafter referred to as intermediate layers) between the input layer and the output layer. Simply put, deep learning can be described as an artificial neural network with deep layers.

[0050] Artificial neural networks (ANNs), a field of artificial intelligence, are mathematical models modeled by mimicking the structure of the biological (typically human) brain (neural networks). In other words, artificial neural networks are implemented by imitating the information processing and transmission processes of these biological neurons. As they are implemented similarly to how the human brain solves problems, neural networks possess excellent parallelism because each neuron operates independently. Furthermore, since information is distributed across numerous connections, problems in a few neurons do not significantly affect the entire network; consequently, they are resilient to a certain level of error and possess the ability to learn from a given environment.

[0051] Deep neural networks can be viewed as descendants of artificial neural networks. They are the latest version of artificial neural networks, having overcome existing limitations and achieved success in areas where numerous artificial intelligence technologies had previously failed. When examining the modeling of artificial neural networks that mimic biological neural networks, biological neurons are modeled as nodes in terms of processing units, and synapses are modeled as weights in terms of connections, as shown in Table 1 below.

[0052] biological neural networks artificial neural networks cell body node dendrites input Axon output synapse weight

[0053] Figure 1 is a diagram illustrating the layer structure of an artificial neural network.

[0054] Just as human biological neurons perform meaningful tasks by connecting multiple cells rather than just one, artificial neural networks connect individual neurons to one another through synapses, creating multiple interconnected layers where the connection strength between layers can be updated using weights. In this way, they are utilized in fields for learning and cognition through their multi-layered structure and connection strengths.

[0055] Each node is connected by weighted links, and the entire model learns by repeatedly adjusting these weights. Weights represent the importance of each node as a fundamental means for long-term memory. Simply put, an artificial neural network trains the entire model by initializing these weights and updating and adjusting them with the data set to be trained. Once training is complete, when a new input is received, it infers an appropriate output value. The learning principle of an artificial neural network can be viewed as the process by which intelligence is formed from the generalization of experience, and it operates in a bottom-up manner. In Figure 1, when there are two or more intermediate layers (i.e., 5 to 10), the layers are considered to be deep, and it is called a Deep Neural Network; the learning and inference model achieved through such a Deep Neural Network can be referred to as Deep Learning.

[0056] Artificial neural networks can perform a certain role even with only one intermediate layer (commonly referred to as a 'hidden layer') in addition to inputs and outputs, but as the complexity of the problem increases, the number of nodes or layers must be increased. Among these, adopting a multi-layered model by increasing the number of layers is effective, but its scope of application is limited due to the limitations that efficient learning is impossible and the amount of computation required to train the network is large.

[0057] However, as the existing limitations mentioned above have been overcome, artificial neural networks have become capable of adopting deep structures. This has enabled the construction of complex and highly expressive models, leading to the 발표 of groundbreaking results in various fields such as speech recognition, face recognition, object recognition, and character recognition.

[0058] Figure 2 is a diagram illustrating an example of a deep neural network.

[0059] A Deep Neural Network (DNN) is an Artificial Neural Network (ANN) composed of multiple hidden layers between an input layer and an output layer. It is a set of machine learning models or algorithms referring to a Deep Neural Network (DNN) that has one or more hidden layers between an input layer and an output layer. Connections in a neural network are formed from the input layer to the hidden layer, and from the hidden layer to the output layer.

[0060] Deep neural networks, like general artificial neural networks, can model complex non-linear relationships. For example, in a deep neural network structure for an object identification model, each object can be represented as a hierarchical composition of the basic elements of an image. In this case, additional layers can combine features from progressively gathered lower layers. This characteristic of deep neural networks enables the modeling of complex data with fewer units (nodes) compared to similarly performed artificial neural networks.

[0061] Previous deep neural networks were typically designed as feedforward networks, but recent research has successfully applied deep learning structures to Recurrent Neural Networks (RNNs). Examples include the application of deep neural network structures in the field of language modeling. In the case of Convolutional Neural Networks (CNNs), not only have they been successfully applied in the field of computer vision, but their successful applications are also well-documented. More recently, CNNs have been applied to acoustic modeling for Automatic Speech Recognition (ASR) and are considered to have been more successful than existing models. Deep neural networks can be trained using the standard backpropagation algorithm. In this process, weights can be updated through stochastic gradient descent.

[0062] Reinforcement learning is a type of machine learning in which an agent learns actions to maximize rewards while interacting with an environment. The agent refers to a machine learning model as the entity performing the learning. The agent selects an action from a specific state within the environment. A state is information representing the current situation of the environment, and the agent determines its next action based on this state. An action is a behavior that the agent can choose based on the state, and each action changes the state of the environment. The environment is the world in which the agent interacts; it changes its state according to the agent's actions and provides rewards in return. A policy is a strategy that determines which action an agent will take in a given state. Policies can be defined probabilistically or deterministically. A reward is the feedback obtained as a result of the agent performing a specific action.

[0063] The process of reinforcement learning consists of: 1) an initialization process in which the agent observes the state within the environment and recognizes the initial state; 2) a behavior selection process in which the agent selects an action based on the current state and the agent's policy; 3) an environment response process in which the environment transitions to a new state and provides a reward based on the agent's action; 4) a learning process in which the agent evaluates how good the chosen action was based on the received reward and updates the policy or value function; and 5) an iterative process in which the agent learns better actions by repeating this process and forms a policy that obtains maximum rewards in the long term. Matters related to reinforcement learning will be explained in more detail below in the predetermined optimized policy-based artificial neural network model described in the present invention.

[0064] Due to the rapid increase in complexity in the field of circuit design, traditional simulators require high computational costs and long execution times, leading to a growing demand for artificial neural network models capable of providing efficient and fast approximations.

[0065] This invention proposes a technique and apparatus for Electronic Design Automation (EDA) based on an artificial neural network model. Data held by individual companies differs, and utilizing this data enables the model to learn more broadly. However, since direct data sharing between clients poses a risk of confidential information leakage, a federated learning approach is required to enable secure collaboration. The artificial neural network model-based EDA tool according to this invention offers many advantages when employing federated learning.

[0066] Applying artificial intelligence to EDA tools requires a large amount of semiconductor design data. However, design data is a top-secret corporate secret and can never be shared externally. Various fabless companies hold their data separately, and the specific situation varies by company regarding GPU simulation, PPA analysis, and batch processing. Federated learning is a technique designed to address these issues. By utilizing federated learning, each company can participate in AI training without leaking its proprietary design data. Furthermore, it allows for the creation of an advanced common model by aggregating model results from multiple companies, while enabling individual firms to maintain their own local improvement models.

[0067] Figure 3 is a diagram illustrating a system that performs learning by collaborating on a circuit simulation prediction model using a federated learning method.

[0068] Referring to FIG. 3, for performing federated learning, a server (100) and multiple clients (Client 1 (Agent 1) (300), Client 2 (400), Client N (500)) are deployed in the system. The operating principle of federated learning is that the server (100) distributes an integrated model or a global model to each client (or client device). The server (100) may distribute a basic circuit simulation prediction model (including initial parameters) to the clients. Then, local learning is performed using local training data with the initial integrated model distributed to each client. Each client can fine-tune the model or perform additional training using its own data. During this process, sensitive original data is not leaked to the outside.

[0069] Afterward, each client can transmit model parameters updated after training (e.g., weights), gradients generated during training, and statistical characteristics of the model to the server (100). If even parameters are not possible for security reasons, only gradient information or synthesized statistics (e.g., mean, variance) may be transmitted. The client can perform self-training using actual circuit design data and, without sharing the training data itself, transmit only the learned model parameters (weights, gradients) and statistical characteristics of the learned model (size of training data, etc.) to the server (100).

[0070] The server (100) can simply sum, average, or apply more advanced optimization techniques to the model parameters / gradients collected from each client. The server (100) can generate a newly updated model based on the integrated results. The server (100) can redistribute the updated model (parameters) back to each client. Each client can continue to improve performance by performing additional learning from the updated model (updated integrated model).

[0071] In one embodiment, client 1 (300) can train a model using a dataset that reflects semiconductor manufacturing process characteristics and then transmit only the gradient to the server (100). Client 2 (400) can update model parameters using power consumption and heat generation specialized data and transmit the parameters to the server (100). Client (900) may not share both data and parameters due to concerns about the leakage of confidential information regarding the design architecture, and may provide modified parameters through a Secure Aggregation method.

[0072] In this way, the server (100) can integrate the information received from each client to complete a more generalized circuit simulation prediction model. This ultimately leads to an improved model that encompasses a wider range of situations and has higher accuracy than the individual client models.

[0073] The following briefly explains the terms to be used in relation to the artificial neural network model-based EDA technology according to the present invention.

[0074] A netlist describes the electrical connections and components of an electronic circuit, while a Process Design Kit (PDK) is a collection of files that models semiconductor manufacturing processes, providing the tools and data necessary for integrated circuit design. Netlists are used for simulation and manufacturing, and PDKs are utilized to identify the characteristics of devices usable in specific manufacturing technologies. PDKs provide all the necessary information and tools to enable designers to design chips using specific process technologies. Federated learning carries the potential for privacy breaches, as client data can be sufficiently decrypted by utilizing gradient updates and model parameter updates. The homomorphic encryption used in this invention is characterized by the fact that applying specific mathematical operations to the ciphertext produces the same effect as applying them to the plaintext. Accordingly, this is a method that can fundamentally prevent security-related problems by enabling model operations to be applied directly to encrypted data and allowing the client to handle decryption.

[0075] The present invention proposes a structure utilizing homomorphic encryption in which a server applies model operations to data encrypted by a client, and the client receives the result of the application and decrypts it. This ensures secure circuit design data for each client.

[0076] FIG. 4 is a block diagram schematically showing the internal configuration of a client (device) according to the present invention.

[0077] Referring to FIG. 4, a client (300) according to one embodiment of the present invention may include a communication unit (310), a computation processing unit (320), and a memory (330).

[0078] The computation processing unit (320) can execute instructions stored in memory (330) to perform at least one of generating a circuit netlist-based graph representation, performing graph embedding, encryption operation, and decryption operation. The computation processing unit (320) may include at least one of a processor, a microprocessor, or a dedicated accelerator.

[0079] The computation processing unit (320) can generate circuit representation data representing the topology and component information of a circuit by applying a netlist to a graph embedding or feature extraction process. The computation processing unit (320) can generate encrypted circuit representation data by encrypting the generated circuit representation data using a homomorphic encryption method. The computation processing unit (3200) can apply the updated model parameters received by the communication unit (320) from the server (100) to local learning or subsequent data processing.

[0080] The communication unit (310) performs wired or wireless communication with the server (100) and may be configured to transmit and receive encrypted data or unencrypted data. The communication unit (310) may transmit encrypted circuit representation data to the server (100). The communication unit (310) may transmit and receive encrypted model information, inference results, or learning parameters through a secure channel.

[0081] The memory (330) may be configured to store a circuit netlist, graph representation data, graph embedding data, encryption key information, and inference results. With this configuration, the client (300) can perform cooperative operations with the server (100) while preventing sensitive circuit design information from being exposed to the outside.

[0082] Figure 5 is a conceptual diagram of the design learning process for utilizing GNN in a homomorphic encryption-based federated learning environment according to the present invention.

[0083] Referring to FIG. 5, each of the multiple clients (300) receives a circuit netlist as input, performs graph embedding, and generates a graph representation. The graph representation is encrypted by homomorphic encryption and converted into a secure graph representation. This graph representation can be referred to as circuit representation data. Each client (300) transmits the secure graph representation or circuit representation data to a server (Model Server), and the server (100) can aggregate and batch process the encrypted data received from the multiple clients.

[0084] The server (100) can perform model training without accessing original data or plaintext information by performing gradient descent, etc. on the central model while maintaining an encrypted state. With this structure, cooperative learning using data from multiple clients becomes possible without the circuit design information of each client being exposed to the server (100).

[0085] In the present invention, the homomorphic encryption method is intended to encrypt circuit representation data input to an artificial intelligence model, and does not imply encrypting the parameters of the artificial intelligence model itself.

[0086] FIG. 6 is a conceptual diagram of the uplink transmission of the GNN inference process in a homomorphic encryption-based federated learning environment according to one embodiment of the present invention.

[0087] FIG. 6 shows an uplink concept diagram of the inference process, wherein each client (300) can convert a circuit netlist into a graph embedding, generate a graph representation, and encrypt it using a homomorphic encryption method. The encrypted graph representation can be configured to enable computation without exposing plaintext data.

[0088] Each client (300) can transmit encrypted graph representation or encrypted circuit representation data to the server (100) via an uplink. At this time, the uplink transmits only the encrypted data, and the circuit netlist or plaintext graph information is not transmitted to the server (100). The server (100) performs a forward pass of the model using the encrypted data as input. The server (100) can perform operations while maintaining the encrypted state by batch processing and aggregating the encrypted graph representations received from each client (300). At this time, the server (100) does not decrypt the plaintext data and performs operations in the encrypted state.

[0089] The server (100) can transmit the encrypted inference results to each client (300). Accordingly, the server (100) cannot know the actual value of the circuit structure or the inference result. Since the server (100) does not decrypt the encrypted information, the confidentiality of the circuit information of each client (300), etc., is guaranteed.

[0090] FIG. 7 is a conceptual diagram of the downlink transmission of the GNN inference process in a homomorphic encryption-based federated learning environment according to one embodiment of the present invention.

[0091] Referring to FIG. 7, the server (100) performs batch inference using encrypted input data received from multiple clients and generates an encrypted batch inference result.

[0092] The server can partition the encrypted batch inference results by client to generate encrypted individual inference results corresponding to each client. Subsequently, the server (100) transmits the generated encrypted individual inference results to each client device via a downlink. The data transmitted via the downlink remains in an un-decrypted encrypted state.

[0093] Each client device (300) can obtain a decrypted inference result by decrypting the encrypted inference result received via the downlink using its own encryption key. As a result, the inference result is not exposed to the server (100), and independent result reception is possible for each client.

[0094] This homomorphic encryption is characterized by the fact that applying specific mathematical operations to the ciphertext has the same effect as applying them to the plaintext; accordingly, it enables the direct application of model operations to encrypted data and allows the client to handle decryption, thereby preventing security-related problems at the source.

[0095] FIG. 8 is a block diagram for explaining the configuration of an artificial neural network model-based electronic design automation device (100) using homomorphic encryption according to the present invention, and FIG. 9 is an example diagram explaining the operating principle of an artificial neural network model-based electronic design automation device (100) using homomorphic encryption according to the present invention.

[0096] The following description refers to FIGS. 8 and FIGS. 9. The artificial neural network model-based electronic design automation device (100) according to the present invention may be the server in FIG. 3, but is not limited thereto. Although the artificial neural network model-based electronic design automation device (100) can efficiently build a more reliable circuit simulation prediction model through federated learning, it is not necessarily limited to performing federated learning.

[0097] The electronic design automation device (100) based on an artificial neural network model according to the present invention may include a memory (110), a first computational processing unit (120), a second computational processing unit (130), a third computational processing unit (140), a fourth computational processing unit (150), a simulator (160), and a communication unit (170).

[0098] A simulator (160) (which may be referred to in various ways, such as circuit simulator, real simulator, etc.) may include an input section (165) and a computation section (167), and the simulator (160) may be a real circuit simulator (Real Simulator) and may be a traditional circuit analysis tool such as NgSPICE, HSPICE, Spectre, etc. The simulator (160) can provide very accurate results based on the actual semiconductor process (PDK) and netlist, but the simulation time is long and tends to consume a lot of computational resources.

[0099] The terms used in this specification, the first operation processing unit (120), the second operation processing unit (130), and the third operation processing unit (140), may each mean a processor capable of performing matrix operations in parallel (e.g., Graphic Processing Unit, GPU)) and its dedicated memory (e.g., VRAM), and the term used in this specification, the fourth operation processing unit (130), may mean a processor capable of performing general-purpose operations (e.g., Central Processing Unit, CPU) and system memory (RAM).

[0100] The memory (110) may store artificial neural network models according to the present invention, training data, netlist, PDK, and target spec, etc., before learning or prediction (inference). In addition, the memory (110) may store information for various operations and information for various controls.

[0101] The present invention proposes an electronic design automation device and method based on an artificial neural network model utilizing homomorphic encryption, and includes a configuration for calculating circuit design parameter values ​​that satisfy target specifications through high-speed simulation and iterative optimization.

[0102] Referring to FIG. 8, the communication unit (170) can receive circuit representation data generated by each client from a netlist in a homomorphic encryption form from each client.

[0103] The first processing unit (120) can input the received homomorphic encrypted circuit representation data into a predetermined Graph Neural Network (GNN) model and execute the GNN model. The GNN model receives basic information about the circuit, such as a netlist and PDK, as input, interprets the circuit as a graph structure, converts various circuit topologies into a context of a predetermined length (e.g., a vector) (or converts it by quantifying it), and outputs a circuit embedding. The output circuit embedding is a circuit characteristic vector that expresses the circuit topology and component information as a context, and may be an encrypted circuit characteristic vector. Even if the circuits have different topologies, the GNN model compresses them into a vector space of the same dimension, making it easier for the artificial neural network model to process them, thereby helping to enable fast and efficient learning in subsequent stages. That is, the GNN model can perform the process of converting complex circuit structures into data representations that are easy to understand.

[0104] In this way, the first computation processing unit (120) can apply homomorphically encrypted circuit representation data to a predetermined (trained) GNN model to output an encrypted circuit feature vector in which the circuit topology and component information are represented as context. The output result is an encrypted circuit feature vector, which can be efficiently utilized in subsequent processing steps by converting circuits with various structures into a consistent data representation. Although the term "circuit feature vector" is used in the present invention, it may be referred to in various ways, such as "circuit structural representation data" or "circuit graph representation vector." The first computation processing unit (120) can perform operations on the GNN model and the surrogate model on the encrypted circuit representation data without decryption.

[0105] The second computation processing unit (130) can apply the encrypted circuit characteristic vector output from the GNN model to a predetermined (trained) surrogate model to output a predicted value of the circuit operation characteristic. The surrogate model is an artificial neural network-based alternative simulator and can also be called a Neural Simulator, and serves as a high-speed approximation simulator. The surrogate model is primarily trained on an artificial neural network to approximate the circuit operation characteristic value output by an existing actual circuit simulator.

[0106] Circuit operation characteristic values ​​are values ​​representing actual circuit operation characteristics, such as power consumption (e.g., 4.5mW), latency (e.g., 0.8ns), and chip area (e.g., 0.1mm²). 2There may be the internal operating temperature of the chip, output voltage waveform, etc. The circuit operation characteristic value used in the present invention represents a performance indicator and may be referred to by various terms such as circuit performance metric, circuit performance parameters, and circuit operation result data.

[0107] In this way, the second operation processing unit (130) receives the encrypted circuit characteristic vector output from the first operation processing unit (120) and outputs a predicted value of circuit operation characteristics that approximates the result of the actual simulator.

[0108] The second operation processing unit (130) can perform operations on the GNN model and surrogate model without decryption on the encrypted circuit representation data.

[0109] Operations on the above encrypted circuit representation data can be performed using a homomorphic encryption method in both the model training phase and the inference phase.

[0110] The simulator (160) can output or calculate circuit operation characteristic values ​​using the netlist and PDK stored in the server (100). The value calculated by the simulator (160) is a physically accurate reference value and is compared with the predicted circuit operation characteristic value output from the second computation processing unit (130) or used to verify artificial neural network-based optimization.

[0111] The third computational processing unit (140) can output circuit design parameter values ​​by applying the circuit operation characteristic prediction value provided from the second computational processing unit (130) and the circuit operation characteristic value provided from the simulator (160) to a predetermined optimization policy-based artificial neural network model.

[0112] Circuit design parameter values ​​can be categorized by, for example, device level, power / bias level, and environment / condition level. Device-level parameters may include transistor (MOSFET) width (channel width) / length (channel length), threshold voltage, and number of stacks. Power / bias level parameters may include the circuit's operating voltage (internal power supply voltage) (Vdd), preset bias current / voltage for electronic components such as transistors to perform specific functions, and reference voltage / current. Furthermore, environment / condition level parameters may include ambient temperature (input condition), load, and PVT (Process Voltage Temperature).

[0113] The third computational processing unit (140) may be implemented as a predetermined optimization policy-based artificial neural network model, and as an example, may be implemented as a reinforcement learning (Policy Network) or an optimization agent. In this case, the third computational processing unit (140) may be referred to as an AI Agent model, etc. The third computational processing unit (140) receives both the predicted value of the circuit operation characteristic and the value of the circuit operation characteristic, calculates a reward by reflecting the difference from the pre-prepared target specification, and outputs an optimized circuit design parameter value.

[0114] The third computational processing unit (140) briefly explains the input, output, state, and action when operating based on reinforcement learning, for example. The inputs of the third computational processing unit (140) may include predicted values ​​of circuit operation characteristics, values ​​of circuit operation characteristics, target specifications, PDK constraint information, etc., and the output is a value of circuit design parameters. This output is used to adjust design variables to guide the circuit to satisfy target performance. Through this, the simulation speed can be dramatically improved during the iterative search process.

[0115] The State can be a circuit characteristic vector, current or previous circuit operation characteristic values ​​(predicted / measured), target specifications, or PDK constraints. The Action can be the output of circuit design parameter values. Rewards and Penalties can be applied by aggregating or weighting factors such as the degree to which target specifications are met or whether PDK constraints have been violated.

[0116] The third computational processing unit (140) can determine compensation based on how well the design result satisfies the target specifications, for example, based on the predicted value of the circuit operation characteristic and the value of the circuit operation characteristic. That is, if the design result satisfies the target specifications, a large compensation can be given. If the design result violates the target specifications (exceeds or falls short of the target conditions of the target specifications), the third computational processing unit (140) can impose a penalty by compensating with a negative value, and a larger penalty can be imposed as the degree of violation increases. In addition, the third computational processing unit (140) can also impose a penalty in the case of PDK constraint violation. For example, if PDK constraints are violated, such as the width or length of the MOSFET being within a range not allowed in the process or the voltage exceeding a limit, a penalty can be imposed, and a larger penalty can be imposed as the degree of violation increases. In this way, the third computational processing unit (140) can output / predict circuit design parameter values ​​based on reinforcement learning. The third operation processing unit (140) can repeatedly perform reinforcement learning under the control of the fourth operation processing unit (150) until the circuit design parameter value satisfies the target specification while complying with PDK constraints.

[0117] The fourth operation processing unit (150) can update the circuit design parameter items within the netlist stored in the server (100) by reflecting the circuit design parameter values ​​output from the third operation processing unit (140). This creates a new netlist (updates the netlist), and the new netlist is then transmitted back to the first operation processing unit (120) so that the same process can be repeated. In this way, the fourth operation processing unit (150) can control the first to third operation processing units (120, 130, 140) to optimize the circuit design parameters until the updated circuit design parameter values ​​satisfy the target specifications while complying with the constraints of the PDK. By performing this until the circuit design parameter values ​​satisfy the target specifications while complying with the constraints of the PDK, an optimized circuit design result can be derived. The circuit design parameter values ​​output from the fourth operation processing unit (150) can be output in an encrypted state.

[0118] After performing such optimization, the artificial neural network model-based electronic design automation device (100) according to the present invention may provide and share an updated integrated model (updated global model) to each client, which includes a GNN model of the first computational processing unit (120), a surrogate model (130) of the second computational processing unit (130), and an artificial neural network model based on a predetermined optimization policy of the third computational processing unit (140). The communication unit (170) may transmit or redistribute the updated integrated model to each client. Each client may perform learning again locally based on the updated integrated model provided by the device (100) according to the present invention.

[0119] To this end, the communication unit (170) of the device (100) according to the present invention provides an initial integrated model to each client in advance, and the communication unit (170) can receive model update information generated by local learning from a plurality of clients. The fourth computational processing unit (150) can aggregate the received model update information and update the parameters of the GNN model, the surrogate model, and the artificial neural network model based on federated learning. At this time, to update the initial integrated model, the fourth computational processing unit (150) can apply weights to each update information for each client by reflecting the contribution each client made to improving the performance of the artificial neural network model-based electronic design automation. In addition, the weights can be set differently depending on the size or number of the learning data sets learned by each client. The fourth computational processing unit (150) can update the GNN model and the surrogate model based on the applied weights.

[0120] Additionally, the fourth computation processing unit (150) can control the integration of GNN model parameters by applying a robust aggregation method as a federated learning strategy to prevent distortion caused by malicious clients or abnormal data. The fourth computation processing unit (150) can also perform checks on self-validation sets and self-supervised learning performance to prevent distortion in learning.

[0121] As described above, the present invention can significantly improve the simulation speed during the iterative optimization process by introducing a surrogate model (Neural Simulator) to approximate the calculations of the actual simulator (160). Therefore, it has the advantage of being able to secure valid design candidates in a short time, even when the design search space is wide.

[0122] In addition, the present invention has the advantage of achieving both accuracy and efficiency by combining the output of a surrogate model (Neural Simulator) and an actual simulator (160) to simultaneously perform fast search / approximation and accurate verification.

[0123] Furthermore, the present invention goes beyond simply analyzing performance to automatically adjust circuit design parameter values ​​through an optimization policy-based artificial neural network model. As a result, the circuit is iteratively optimized to satisfy target specifications while complying with PDK constraints, thereby reducing the burden of manual tuning for circuit designers and enabling automatic design optimization that meets target specifications.

[0124] Furthermore, since the present invention utilizes GNN-based circuit characteristic vector representation to handle various topologies and device conditions without being limited to specific circuit blocks, it is applicable in various design areas such as analog circuits, digital circuits, and mixed-signal circuits.

[0125] The present invention simultaneously realizes rapid search, accurate verification, and automatic optimization, thereby having the effect of improving design speed, accuracy, productivity, and security compared to conventional technology.

[0126] In addition, by combining with a federated learning structure, it is possible to train and optimize global models without directly sharing confidential data from various companies / clients, which offers the advantage of high industrial utility. By securely utilizing local data from various clients through federated learning, this invention can significantly contribute to the efficient construction and maintenance of highly reliable circuit simulation prediction models. Furthermore, as it can simultaneously realize data privacy protection and maximize model performance, it can serve as a solution that dramatically enhances competitiveness in the semiconductor and electronic design fields.

[0127] In addition, the present invention provides circuit representation data generated from a netlist defining a circuit to a server in a homomorphic encryption state, and the server performs operations on the encrypted circuit representation data using a graphical neural network (GNN) model and a related artificial neural network model without decryption. Accordingly, since the server does not directly recognize the client's original circuit structure, component connection relationships, and circuit design know-how, it is possible to fundamentally prevent design data requiring a high degree of confidentiality, such as semiconductor circuit design, from being leaked or exposed to the outside.

[0128] Furthermore, the homomorphic encryption-based circuit representation data processing structure according to the present invention can be applied equally to forward pass operations during the learning process as well as to the inference process of the GNN model. Therefore, since the server uses encrypted circuit representation data as input in both the model learning and inference phases, consistent data privacy protection is possible throughout the entire learning and inference process, unlike existing methods where protection is limited to specific stages.

[0129] The present invention provides a structure that enables multiple clients to jointly train an artificial neural network model based on federated learning without directly sharing their respective circuit design data. Each client performs local training based on server computation results using encrypted circuit representation data, and by providing only the model update information generated as a result to the server, the performance of the global model can be continuously improved while maintaining the privacy of the circuit design data.

[0130] In this invention, by utilizing the output results of a GNN model for homomorphic encryption-based circuit representation data together with actual circuit operation characteristic values ​​calculated through a Process Design Kit (PDK) stored on a server and a simulator, high-precision prediction of circuit operation characteristics and reliable optimization of design parameters can be performed simultaneously. Accordingly, compared to a method that relies solely on inference results for encrypted data, design optimization reflecting actual process conditions becomes possible.

[0131] The present invention provides the advantage of minimizing the computational burden associated with homomorphic encryption operations by selectively applying homomorphic encryption to abstracted input data, such as circuit representation data, and configuring areas such as process design kits (PDKs), simulators, and design parameter updates to be processed in plaintext within a trusted server environment.

[0132] The processing device in the present invention may perform an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, the processing device may be described as being used as a single unit, but those skilled in the art will understand that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0133] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computing devices and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0134] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either individually or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software.

[0135] Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operation of the embodiments, and vice versa.

[0136] The embodiments described above are combinations of the components and features of the present invention in a specific form. Each component or feature should be considered optional unless otherwise explicitly stated. Each component or feature may be implemented in a form not combined with other components or features.

[0137] Additionally, it is possible to construct embodiments of the present invention by combining some components and / or features. The order of operations described in the embodiments of the present invention may be changed. Some components or features of one embodiment may be included in another embodiment, or may be replaced with corresponding components or features of another embodiment. It is obvious that embodiments may be constructed by combining claims that are not explicitly related in the claims, or that new claims may be included by amendment after filing.

[0138] It is obvious to those skilled in the art that the present invention may be embodied in other specific forms without departing from the essential features of the invention. Accordingly, the foregoing detailed description should not be interpreted restrictively in all respects but should be considered exemplary. The scope of the invention shall be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the invention are included within the scope of the invention.

Claims

Claim 1 A method for performing electronic design automation using an artificial neural network model based on federated learning, wherein an electronic design automation device interacts with multiple clients, comprising: receiving circuit representation data generated from a netlist in a form encrypted using a homomorphic encryption method; receiving model update information generated by local learning from each of the multiple clients; applying the encrypted circuit representation data to a predetermined Graph Neural Network (GNN) model without decryption to output an encrypted circuit characteristic vector representing the circuit topology and component information as context; applying the encrypted circuit characteristic vector to a predetermined surrogate model without decryption to output an encrypted circuit operation characteristic prediction value that approximates the result of a circuit simulator; applying a circuit design netlist and a PDK (Process Design Kit) stored in the electronic design automation device to the circuit simulator to output a circuit operation characteristic value; and applying the encrypted circuit operation characteristic prediction value and the circuit operation characteristic value to a predetermined optimization policy-based artificial neural network model to calculate a reward by reflecting the difference from a pre-prepared target specification and output a circuit design parameter value. A method comprising: a step of updating circuit design parameters within the netlist using the output circuit design parameter values; a step of aggregating model update information received from each of the plurality of clients and updating the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on federated learning; and a step of delivering the updated parameters of the artificial neural network model to each of the plurality of clients. Claim 2 A method according to claim 1, further comprising the step of optimizing the circuit design parameters by repeating the steps until the updated circuit design parameter values ​​satisfy the target specifications while complying with the constraints of the PDK. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A method according to claim 1, comprising the step of providing an initial integrated model, including the GNN model, the surrogate model, and the optimization policy-based artificial neural network model, to each of the plurality of clients, wherein the federated learning is performed on the initial integrated model as a unit, and the initial integrated model is initialized in the electronic design automation device prior to the start of the federated learning. Claim 8 A method according to claim 1, wherein the step of updating the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on the federated learning includes: a step of applying weights to the model update information by reflecting the contribution to the performance improvement of the artificial neural network model-based electronic design automation for each of the plurality of clients; and a step of updating the parameters of the GNN model and the surrogate model using the model update information to which the weights have been applied. Claim 9 delete Claim 10 delete Claim 11 An electronic design automation device based on an artificial neural network model comprises: a communication unit that receives circuit representation data generated from a netlist in a form encrypted using a homomorphic encryption method and receives model update information generated by local learning from a plurality of clients; a first processing unit that applies the encrypted circuit representation data to a predetermined Graph Neural Network (GNN) model without decryption to output an encrypted circuit characteristic vector in which the circuit topology and component information are expressed as a context; a circuit simulator that outputs circuit operation characteristic values ​​using a circuit design netlist and a PDK (Process Design Kit) stored in the electronic design automation device; a second processing unit that applies the encrypted circuit characteristic vector to a predetermined surrogate model without decryption to output a predicted circuit operation characteristic value that approximates the result of the circuit simulator; and a third processing unit that applies the predicted circuit operation characteristic value and the circuit operation characteristic value to a predetermined optimization policy-based artificial neural network model to calculate a reward by reflecting the difference from a pre-prepared target specification and output a circuit design parameter value. The device includes a fourth processing unit that updates circuit design parameters within the netlist using the outputted circuit design parameter values, wherein the fourth processing unit aggregates model update information received from each of the plurality of clients and updates the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on federated learning, and the communication unit transmits the updated parameters of the artificial neural network model to each of the plurality of clients. Claim 12 In claim 11, the device wherein the fourth processing unit controls the first to third processing units to optimize the circuit design parameters until the updated circuit design parameter value satisfies the target specifications while complying with the constraints of the PDK. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 A device according to claim 11, wherein the communication unit provides an initial integrated model including the GNN model, the surrogate model, and the optimization policy-based artificial neural network model to each of the plurality of clients, and the federated learning is performed on the initial integrated model, and the initial integrated model is initialized in the electronic design automation device prior to the start of the federated learning. Claim 17 In claim 11, the fourth processing unit applies weights to the model update information by reflecting the contribution to the performance improvement of the artificial neural network model-based electronic design automation for each of the plurality of clients in order to update the parameters of the GNN model, the surrogate model, and the optimization policy-based artificial neural network model based on the federated learning, and updates the parameters of the GNN model and the surrogate model using the model update information to which the weights are applied. Claim 18 delete Claim 19 A computer-readable recording medium having a program for executing a method described in any one of paragraphs 1, 2, 7 and 8 on a computer.

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