Semiconductor device having shield member

Abstract

One embodiment relates to a semiconductor device and may include: a first semiconductor chip comprising a memory cell array and a plurality of bit lines; a second semiconductor chip comprising a peripheral circuit and bonded to the first semiconductor chip; and a shielding member comprising a link pattern having a grid or stripe shape formed on one of the bonding metal layers of the first semiconductor chip and the second semiconductor chip, and a plurality of island patterns formed on the other bonding metal layer of the first semiconductor chip and the second semiconductor chip and bonded to the link pattern.

Description

Technology Field

[0001] The present invention relates to semiconductor technology, and specifically to a semiconductor device having a shielding member. Background Technology

[0002] As part of efforts to increase integration density, a Peri Over Cell (POC) structure was proposed in which the memory cell array and the peripheral circuits for controlling the memory cell array are fabricated on different semiconductor chips by separating them, and the semiconductor chips are bonded together to connect the memory cell array and the peripheral circuits. The problem to be solved

[0003] Embodiments of the present invention may provide a semiconductor device having a shielding member. means of solving the problem

[0004] A semiconductor device according to one embodiment of the present invention may include: a first semiconductor chip comprising a memory cell array and a plurality of bit lines; a second semiconductor chip comprising a peripheral circuit and bonded to the first semiconductor chip; and a shielding member comprising a link pattern having a grid or stripe shape configured on one of the bonding metal layers of the first semiconductor chip and the second semiconductor chip, and a plurality of island patterns configured on the other bonding metal layer of the first semiconductor chip and the second semiconductor chip and bonded to the link pattern.

[0005] A semiconductor device according to one embodiment of the present invention may include: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip; and a shielding member comprising a link pattern having a grid or stripe shape formed on one of the bonding metal layers of the first semiconductor chip and the second semiconductor chip, and a plurality of island patterns formed on the other bonding metal layer of the first semiconductor chip and the second semiconductor chip and bonded to the link pattern. Effects of the invention

[0006] According to embodiments of the present invention, interference between bit lines and signal lines can be prevented, and bonding reliability between semiconductor chips can be ensured.

[0007] According to embodiments of the present invention, the utilization efficiency of the metal layer can be improved. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 3 and FIGS. 4 are exemplary plan views of a shielding member of a semiconductor device according to the present invention. Figure 5 is a plan view illustrating the link pattern of Figure 4 along with bit lines. FIG. 6 is a diagram showing the coupling capacitance between a shielding member and bit lines of a semiconductor device according to one embodiment of the present invention. FIG. 7 is a plan view illustrating an example of island patterns of a semiconductor device according to the present invention, together with bit lines. FIGS. 8 and 9 are exemplary plan views of a shielding member of a semiconductor device according to the present invention. FIG. 10 is a plan view showing an area in which bonding pads and a shielding member are arranged in a semiconductor device according to one embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 12 to 14 are plan views showing a situation in which a pad shift occurs in a semiconductor device according to the present invention. FIG. 15 is a schematic cross-sectional view of a semiconductor device different from the present invention. FIG. 16 is a block diagram schematically illustrating a memory system including a semiconductor device according to an embodiment of the present invention. FIG. 17 is a block diagram schematically illustrating a computing system including a semiconductor device according to an embodiment of the present invention. Specific details for implementing the invention

[0009] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0010] Furthermore, the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Additionally, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless specifically stated otherwise.

[0011] In addition, when interpreting the components in the embodiments of the present invention, they should be interpreted as including an error range even without separate explicit description.

[0012] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are used merely to distinguish the components from other components, and the essence, order, sequence, or number of the components are not limited by these terms. Furthermore, the components in the embodiments of the present invention are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0013] Where it is stated that one component is "connected," "combined," or "joined" to another component, it should be understood that while the component may be directly connected or joined to the other component, another component may be "interposed" between the components, or that the components may be "connected," "combined," or "joined" through other components. In the case of descriptions of positional relationships, for example, where the positional relationship between two parts is described using expressions such as "on," "above," "below," or "next to," one or more other parts may be located between the two parts unless "immediately" or "directly" is used.

[0014] In addition, the features (configurations) in the embodiments of the present invention may be combined, combined, or separated from one another, either partially or wholly, and may technically enable various interlocking and driving mechanisms; each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0015] Embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0016] FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the present invention.

[0017] Referring to FIG. 1, a semiconductor device (100) according to one embodiment of the present invention may include a memory cell array (110) and a peripheral circuit (120). The peripheral circuit (120) may include a row decoder (X-DEC, 121), a page buffer circuit (122), and other peripheral circuits. Other peripheral circuits may include control logic (123), a voltage generator (124), a column decoder (125), and an input / output circuit (IO Circuit, 126), etc.

[0018] The memory cell array (110) may include a plurality of memory blocks (BLK). Although not illustrated, each memory block (BLK) may include a plurality of pages. A memory block (BLK) may be the basic unit of an erase operation, and a page may be the basic unit of a read operation.

[0019] The memory cell array (110) can be connected to a row decoder (121) through a plurality of row lines (RL) and to a page buffer circuit (122) through a plurality of bit lines (BL). The row lines (RL) may include drain select lines, word lines, and source select lines.

[0020] A memory cell array (110) may include a plurality of memory cells disposed in regions where a plurality of bit lines (BL) and a plurality of word lines intersect. A memory cell may be a volatile memory cell that loses stored data when the supplied power is cut off, or a non-volatile memory cell that retains stored data even when the supplied power is cut off. For example, if the memory cell is a volatile memory cell, the semiconductor device (100) may be a DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), mobile DRAM, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power DDR) SDRAM, GDDR (Graphic DDR) SDRAM, or RDRAM (Rambus Dynamic Random Access Memory), etc. When the memory cell is a non-volatile memory cell, the semiconductor device (100) may be an EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), or FRAM (Ferroelectric Random Access Memory), etc. Additionally, the semiconductor device (100) may be a hybrid memory that includes both volatile memory cells and non-volatile memory cells.

[0021] A memory cell may be a single-level cell (SLC) that stores 1 bit of data or a multi-level cell (MLC) that can store 2 bits or more of data. A multi-level cell can store 2 bits of data, 3 bits of data, 4 bits of data, etc. A memory cell array (110) may include at least one of a single-level cell and a multi-level cell.

[0022] The row decoder (121) can select a memory block (BLK) in response to a row address (RADD) from the control logic (123). The row decoder (121) can transmit an operating voltage (Vop) from the voltage generator (124) to the row lines (RL) of the selected memory block (BLK).

[0023] The page buffer circuit (122) may include a plurality of page buffers (PB) connected to a plurality of bit lines (BL). The page buffer circuit (122) may be connected to an input / output circuit (126) through data lines (DL). The page buffer circuit (122) may receive a page buffer control signal (PBCON) from a control logic (123) and may transmit and receive a data signal (DATA) to and from the input / output circuit (126). The page buffer circuit (122) may control the bit line (BL) in response to the page buffer control signal (PBCON). For example, the page buffer circuit (122) may detect data stored in the memory cells of the memory cell array (110) by detecting the signal of the bit line (BL) of the memory cell array (110) in response to the page buffer control signal (PBCON), and may transmit a data signal (DATA) to the input / output circuit (126) according to the detected data. The page buffer circuit (122) can apply a signal to a bit line (BL) based on a data signal (DATA) received from an input / output circuit (126) in response to a page buffer control signal (PBCON), and accordingly, can write data to a memory cell of a memory cell array (110). The page buffer circuit (122) can write data to a memory cell connected to an activated word line or read data from therein.

[0024] The control logic (123) can output a voltage control signal (VCON) and a page buffer control signal (PBCON) in response to a command signal (CMD) input through the input / output circuit (126). The control logic (123) can output a row address signal (RADD) and a column address signal (CADD) in response to an address signal (ADD) input through the input / output circuit (126).

[0025] The voltage generator (124) can generate various voltages required by the semiconductor device (100), including an operating voltage (Vop) provided to the low lines (RL) in response to a voltage control signal (VCON) from the control logic (123). For example, the voltage generator (124) can be configured to generate various levels of program voltages, pass voltages, lead voltages, and erase voltages in response to a voltage control signal (VCON).

[0026] The column decoder (125) can generate a column selection signal (CS) in response to a column address (CADD) received from the control logic (123). For example, the column decoder (125) can generate a column selection signal (CS) corresponding to the column address (CADD) so that a portion of the data selected by the column address (CADD) among the data of each page buffer (PB) can be transmitted to the input / output circuit (126).

[0027] The input / output circuit (126) can receive a command signal (CMD), an address signal (ADD), and a control signal (CTRL) from outside the semiconductor device (100), and can transmit and receive data (DATA) with a device outside the semiconductor device (100), such as a memory controller.

[0028] Hereinafter, in the attached drawings, two directions parallel to and intersecting each other on the upper surface of the substrate will be defined as the first direction (FD) and the second direction (SD), respectively, and a direction protruding vertically from the upper surface of the substrate will be defined as the vertical direction (VD). The first direction (FD) may correspond to the direction of extension of bit lines or the direction of arrangement of row lines, and the second direction (SD) may correspond to the direction of arrangement of bit lines or the direction of extension of row lines. The first direction (FD) and the second direction (SD) may intersect substantially perpendicularly to each other. In the drawings, directions indicated by arrows and opposite directions represent the same direction.

[0029] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0030] Referring to FIG. 2, a semiconductor device according to one embodiment of the present invention may include: a first semiconductor chip (C1); a second semiconductor chip (C2) bonded to the first semiconductor chip (C1); and a shielding member (130) comprising a link pattern (131) configured on the bonding metal layer (M21) of the second semiconductor chip (C2) and a plurality of island patterns (132) configured on the bonding metal layer (M11) of the first semiconductor chip (C1) and bonded to the link pattern (131).

[0031] The first semiconductor chip (C1) is inverted vertically and bonded onto the second semiconductor chip (C2). In one embodiment, the first semiconductor chip (C1) and the second semiconductor chip (C2) may be bonded to each other at the wafer level. In another embodiment, the first semiconductor chip (C1) and the second semiconductor chip (C2) may be bonded to each other at the chip level.

[0032] The first semiconductor chip (C1) may include a first substrate (10) and a memory cell array (110) provided on the first substrate (10). The memory cell array (110) may include a plurality of electrode layers (20) and a plurality of interlayer insulating layers (22) alternately stacked on the first substrate (10), and a plurality of cell plugs (CP) penetrating the plurality of electrode layers (20) and the plurality of interlayer insulating layers (22).

[0033] The electrode layers (20) can form row lines. The row lines may include at least one source selection line, a plurality of word lines, and at least one drain selection line. A drain selection line and a source selection line may be disposed above and below the plurality of word lines, respectively.

[0034] The cell plug (CP) may extend to the first substrate (10) by penetrating a plurality of electrode layers (20) and a plurality of interlayer insulating layers (22) in the vertical direction (VD). Although not illustrated in detail, the cell plug (CP) may include a data storage layer and a channel layer. The channel layer of the cell plug (CP) may be connected to a bit line (BL) through a bit line contact (BLC).

[0035] A source select transistor may be configured in the portion where the source select line surrounds the cell plug (CP). Memory cells may be configured in the portions where the word lines surround the cell plug (CP). A drain select transistor may be configured in the portion where the drain select line surrounds the cell plug (CP). The source select transistor, memory cells, and drain select transistor arranged along a single cell plug (CP) may form a single cell string.

[0036] Although the present embodiment exemplarily shows a case where the memory cell array (110) is a three-dimensional stacked memory, the scope of the present invention is not limited thereto. The memory cell array (110) may be a two-dimensional memory in which the memory cells are arranged planarly on a single plane.

[0037] An internal metal layer (M12) and a bonding metal layer (M11) may be stacked sequentially on top of a memory cell array (110). A bit line (BL) may be formed in the internal metal layer (M12). FIG. 2 is a cross-sectional view taken along the first direction (FD), which is the extension direction of the bit line (BL). Although only one bit line is shown in FIG. 2, it should be understood that a plurality of bit lines (BL) are arranged along the second direction (SD).

[0038] A first bonding pad (PAD1) may be formed on the bonding metal layer (M11) of the first semiconductor chip (C1). Although only one first bonding pad (PAD1) connected to one bit line (BL) is shown in FIG. 2, it should be understood that multiple first bonding pads connected to multiple bit lines (BL) and multiple electrode layers (20) are formed on the bonding metal layer (M11).

[0039] An insulating layer (30) may be formed on the first substrate (10) to cover the memory cell array (110) and the internal metal layer (M12) and to expose the upper surface of the bonding metal layer (M11). The insulating layer (30) may, for example, be a multilayer structure in which a plurality of insulating materials are stacked. The upper surface of the insulating layer (30) in contact with the second semiconductor chip (C2) may be composed of oxide.

[0040] The second semiconductor chip (C2) may include a second substrate (12) and a peripheral circuit (120) provided on the second substrate (12). The peripheral circuit (120) may include a row decoder, a page buffer circuit, and other peripheral circuits as described with reference to FIG. 1. Other peripheral circuits may include control logic, a voltage generator, a column decoder, and an input / output circuit, etc.

[0041] An internal metal layer (M22) and a bonding metal layer (M21) may be sequentially stacked on top of the peripheral circuit (120). A plurality of signal lines (SL) and a ground line (GL) may be configured on the internal metal layer (M22). The signal lines (SL) serve to transmit signals necessary for the operation of the semiconductor device and may be electrically isolated from the shielding member (130). Some of the signal lines (SL) may be configured to overlap with the shielding member (130) in the vertical direction (VD).

[0042] A second bonding pad (PAD2) may be formed on the bonding metal layer (M21). The second bonding pad (PAD2) may be connected to a peripheral circuit (120) through contacts and wiring. The first bonding pad (PAD1) and the second bonding pad (PAD2) may be bonded to each other to form an electrical path connecting the memory cell array (110) of the first semiconductor chip (C1) and the peripheral circuit (120) of the second semiconductor chip (C2).

[0043] An insulating layer (40) may be formed on the second substrate (12) to cover the peripheral circuit (120) and the internal metal layer (M22) and to expose the upper surface of the bonding metal layer (M21). The insulating layer (40) may, for example, be a multilayer structure in which a plurality of insulating materials are stacked. The upper surface of the insulating layer (40) in contact with the first semiconductor chip (C1) may be composed of oxide.

[0044] The shielding member (130) may include a link pattern (131) configured in the bonding metal layer (M21) of the second semiconductor chip (C2) and a plurality of island patterns (132) configured in the bonding metal layer (M11) of the first semiconductor chip (C1) and bonded to the link pattern (131). The plurality of island patterns (132) are commonly bonded to the link pattern (131) and may be electrically connected to each other through the link pattern (131).

[0045] A ground voltage may be applied to the shielding member (130). For example, the link pattern (131) of the shielding member (130) may be connected to the ground line (GL) through a contact (CNT), and accordingly, the ground voltage of the ground line (GL) may be provided to the shielding member (130). As described below with reference to FIG. 10, the shielding member (130) may be placed in an area of ​​the cell region where bit lines (BL) are arrayed that is not utilized for the placement of bonding pads. Hereinafter, for convenience of explanation, the area where the shielding member (130) is placed will be defined as the shielding area.

[0046] The shielding member (130) can shield interference between the bit line (BL) and the signal lines (SL) in the shielding area to prevent the voltage of the bit line (BL) from changing due to the influence of the voltage loaded on the signal lines (SL).

[0047] The first semiconductor chip (C1) and the second semiconductor chip (C2) are bonded using a hybrid bonding method. Hybrid bonding includes oxide-to-oxide bonding and metal-to-metal bonding. When heat and pressure are applied while the first semiconductor chip (C1) and the second semiconductor chip (C2) are superimposed, oxide-to-oxide bonding proceeds in which the oxide of the insulating layer (30) of the first semiconductor chip (C1) and the oxide of the insulating layer (40) of the second semiconductor chip (C2) are bonded to each other. After oxide-to-oxide bonding has progressed to a certain extent, metal-to-metal bonding proceeds in which the bonding metal layer (M11) of the semiconductor chip (C1) and the bonding metal layer (M12) of the second semiconductor chip (C2) are bonded to each other.

[0048] In hybrid bonding, the oxide-oxide bonding ratio is directly related to bonding reliability. If the oxide-oxide bonding ratio is low, a gap may occur between the first semiconductor chip (C1) and the second semiconductor chip (C2), and a defect may occur where the first bonding pad (PAD1) and the second bonding pad (PAD2) are not connected. To ensure bonding reliability, the oxide-oxide bonding ratio must be above a certain standard value.

[0049] If the shielding member (130) is formed on the bonding metal layers (M11, M12), it has the advantage of not requiring the formation of a separate additional metal layer for the shielding member (130). However, the bonding reliability may be reduced as the oxide-oxide bonding ratio decreases due to the shielding member (130).

[0050] These embodiments can provide a method for configuring shielding members on bonding metal layers without causing a problem of reduced bonding reliability.

[0051] FIGS. 3 and FIGS. 4 are exemplary plan views of a shielding member of a semiconductor device according to the present invention, and FIG. 5 is a plan view showing the link pattern of FIG. 4 together with bit lines.

[0052] Referring to FIG. 3, a link pattern (131) and island patterns (132) of a shielding member (130) are arranged in a shielding area. A plurality of island patterns (132) may be arranged two-dimensionally with spacing between them. For example, the island patterns (132) may be arranged in a matrix form, forming a plurality of rows along a first direction (FD) and a plurality of columns along a second direction (SD).

[0053] The link pattern (131) may have a grid-like planar structure. For example, the link pattern (131) may include a plurality of first lines (vertical lines) that extend in a first direction (FD), which is the direction in which bit lines extend, and a plurality of second lines (horizontal lines) that extend in a second direction (SD), which is the direction in which bit lines are arranged, and intersect with the plurality of first lines. Island patterns (132) may be bonded to each of the intersection points where the first lines and the second lines intersect each other. The link pattern (131) may be configured so that the intersection points of the lines constituting the link pattern (131) match the island patterns (132). The grid-like link pattern (131) may include a plurality of openings (OP). Oxide-oxide bonding is formed in an area where the link pattern (131) and / or island patterns (132) are not placed. Oxide-oxide bonding in the form of isolated islands corresponding to multiple openings (OP) is distributed throughout the entire shielding area.

[0054] Referring to FIGS. 4 and 5, the link pattern (131) may have a striped shape comprising a plurality of lines (131A-131D) arranged parallel to each other at regular intervals. For example, the plurality of lines (131A-131D) may be extended in a second direction (SD), which is the direction in which bit lines (BL) are arranged, and may be arranged along a first direction (FD), which is the direction in which bit lines (BL) are extended. At least two island patterns (132) may be bonded to each of the lines (131A-131D) of the link pattern (131). Oxide-oxide bonding is formed between the lines (131A-131D) of the link pattern (131). The striped oxide-oxide bonding is distributed over the entire shielding area.

[0055] FIG. 6 is a diagram showing the coupling capacitance between the shielding member and bit lines of a semiconductor device according to the present invention, and FIG. 7 is a plan view showing an example of island patterns of a semiconductor device according to the present invention together with bit lines.

[0056] Referring to FIG. 6, coupling capacitance is generated in the portion where the bit line (BL) and the shielding member (130) overlap in the vertical direction (VD). As is known, the coupling capacitance is inversely proportional to the distance between the electrodes. The distance between the shielding member (130) and the bit line (BL) varies depending on the presence or absence of island patterns (132). In the portion where the island pattern (132) is present, the distance between the shielding member (130) and the bit line (BL) is narrow, and in the portion where the island pattern (132) is not present, the distance between the shielding member (130) and the bit line (BL) is wide. Accordingly, the coupling capacitance value (CAP1) in the part where the island pattern (132) exists becomes larger than the coupling capacitance value (CAP2) in the part where the island pattern (132) does not exist, and the bit line (BL) will have a coupling capacitance value that increases proportionally to the number of overlapping island patterns (132).

[0057] If the number of overlapping island patterns (132) is different, a coupling capacitance deviation occurs between bit lines (BL), and accordingly, the distribution change of memory cells connected to bit lines (BL) may increase.

[0058] Referring to FIG. 7, the island patterns (132) of the odd-numbered rows and the island patterns (132) of the even-numbered rows can be configured to be offset from each other in the second direction (SD), which is the row direction, so that the island patterns (132) of the odd-numbered rows overlap with some bit lines (BL) in the vertical direction (VD) and the island patterns (132) of the even-numbered rows overlap with the remaining bit lines (BL) in the vertical direction (VD). In this case, the number of island patterns (132) that overlap with the bit lines (BL) becomes constant, thereby reducing the deviation of the coupling capacitance between the bit lines (BL) and reducing the change in cell distribution.

[0059] FIGS. 8 and 9 are exemplary plan views of a shielding member of a semiconductor device according to the present invention, showing the structure of a shielding member when island patterns of odd-numbered rows and island patterns of even-numbered rows are offset from each other in the row direction.

[0060] Referring to FIG. 8, the link pattern (131) may have a grid-like planar structure. In order for the first lines (vertical lines) and the second lines (horizontal lines) to intersect each other at the intersection points, the first line of the link pattern (131) may be configured to have a short length connecting two adjacent second lines.

[0061] The link pattern (131) includes a plurality of openings (OP). The openings (OP) are arranged in a plurality of rows, such that the odd-numbered openings (OP) and the openings (OP) in the even-numbered rows are offset from each other in the row direction. Oxide-oxide bonding in the form of isolated islands corresponding to the plurality of openings (OP) is distributed throughout the shielding area.

[0062] Referring to FIG. 9, the link pattern (131) may have a striped shape comprising a plurality of lines (131A-131D) arranged parallel to each other at regular intervals. For example, the lines (131A-131D) of the link pattern (131) may be extended in a second direction (SD), which is the direction in which bit lines (BL) are arranged, and may be arranged along a first direction (FD), which is the direction in which bit lines (BL) are extended. A plurality of island patterns (132) may be bonded to each of the lines (131A-131D) of the link pattern (131). Oxide-oxide bonding is formed between the lines (131A-131D) of the link pattern (131). The striped oxide-oxide bonding may be distributed over the entire shielding area.

[0063] FIG. 10 is a plan view showing an area in which bonding pads and a shielding member are arranged in a semiconductor device according to one embodiment of the present invention.

[0064] Referring to FIG. 10, a semiconductor device according to one embodiment of the present invention may include a plurality of cell regions (CR) and a peripheral region (PR) outside the cell regions (CR). Although not illustrated, a memory cell array may be disposed in each of the cell regions (CR) of a first semiconductor chip (C1). A page buffer circuit may be disposed in each of the cell regions (CR) of a second semiconductor chip (C2). A row decoder may be disposed in a portion of the peripheral region (PR) of the second semiconductor chip (C2) that is adjacent to the cell region (CR) in the second direction (SD).

[0065] A semiconductor device according to one embodiment of the present invention may have a multi-plane structure including a plurality of planes. A first semiconductor chip (C1) may include a plurality of memory cell arrays included in each of the plurality of planes, and a second semiconductor chip (C2) may include a plurality of page buffer circuits included in each of the plurality of planes and a plurality of row decoders included in each of the plurality of planes.

[0066] FIG. 10 shows a 4-plane structure in which four cell regions (CR) are arranged in a 2x2 matrix form. Although the embodiment described with reference to FIG. 10 shows a case where the semiconductor device is a multi-plane structure, the semiconductor device may also be a single-plane structure including one plane.

[0067] First and second bonding pads (PAD1, PAD2) may be placed in the cell region (CR) and the peripheral region (PR). The first and second bonding pads (PAD1, PAD2) connecting multiple word lines (WL) and the row decoder may be placed in the peripheral region (PR) in a part adjacent to the cell region (CR) in the second direction (SD).

[0068] The cell region (CR) may include a bonding region and a shielding region. First and second bonding pads (PAD1, PAD2) connecting a plurality of bit lines (BL) and a page buffer circuit may be disposed in the bonding region. The shielding region is an area not used for the placement of the first and second bonding pads (PAD1, PAD2), and a shielding member (130) may be disposed in the shielding region.

[0069] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0070] In the embodiments described above with reference to FIGS. 2 to 10, the link pattern (131) of the shielding member (130) is configured on the second semiconductor chip (C2) and the island patterns (132) of the shielding member (130) are configured on the first semiconductor chip (C1), but this is not limited thereto.

[0071] As illustrated in FIG. 11, the link pattern (131) of the shielding member (130) may be configured on the first semiconductor chip (C1), and the island patterns (132) of the shielding member (130) may be configured on the second semiconductor chip (C2).

[0072] FIGS. 12 to 14 are plan views showing a situation in which a pad shift occurs in a semiconductor device according to the present invention.

[0073] As described with reference to FIG. 2, a plurality of electrode layers (20), a plurality of interlayer insulating layers (22), and metal layers (M11, M21) are deposited on a first substrate (10) of a first semiconductor chip (C1). These material layers deposited on the first substrate (10) have different stresses than the first substrate (10), and as a result, a stress imbalance may occur. When a stress imbalance occurs, the first substrate (10) may deform or bend to reach equilibrium stress. Such deformation or bending may cause difficulties in subsequent processes. For example, the first bonding pad (PAD1) and island patterns (132) of the first semiconductor chip (C1) may be bonded in a shifted state along the bending direction at a predetermined position.

[0074] FIGS. 12 and 14 show the case where the island patterns (132) are bonded in a state shifted in the second direction (SD) from a predetermined position (dotted line portion), and FIG. 13 shows the case where the island patterns (132) are bonded in a state shifted in the first direction (FD) from a predetermined position (dotted line portion).

[0075] Referring to FIGS. 12 and 13, the link pattern (131) is configured in a grid shape, and the island pattern (132) is configured to match the intersection points where the lines constituting the link pattern (131) intersect, so that even if the island patterns (132) are bonded while shifted in the second direction (SD) or the first direction (FD) at a predetermined position, the area of ​​the oxide-oxide bonding is not reduced.

[0076] Referring to FIG. 14, the link pattern (131) is configured in a striped shape including multiple lines extending in a second direction (SD), and the island patterns (132) are arranged in multiple rows that match the lines of the link pattern (131), so that the area of ​​the oxide-oxide bonding is not reduced even if the island patterns (132) are bonded while shifted in the second direction (SD) at a predetermined position.

[0077] Although the embodiments described herein with reference to the drawings show cases where a plurality of lines constituting the link pattern (131) are extended in a second direction (SD), this is not limited thereto. The structure of a previously manufactured semiconductor device may be observed, and based on the results, the pad shift direction of a semiconductor device to be manufactured thereafter may be predicted, and the lines of the link pattern (131) may be configured to have a shape that extends in the same direction as the predicted pad shift direction.

[0078] Although the embodiments described herein with reference to the drawings show a case where the first semiconductor chip is a memory chip including a memory cell array and the second semiconductor chip is a peripheral chip including a peripheral circuit that controls the operation of the memory cell array, the types of the first and second semiconductor chips are not limited thereto.

[0079] FIG. 15 is a schematic diagram showing a semiconductor device different from the present invention.

[0080] Referring to FIG. 15, the link pattern (131) is separated into the same number as the island patterns (132) and bonded to each of the island patterns (132). In this case, since the ground line (GL) must be configured to overlap all the island patterns (132) in the vertical direction (VD) to apply the ground voltage, the occupied area of ​​the ground line (GL) increases, and thus the utilization efficiency of the metal layer decreases.

[0081] Referring again to FIGS. 2 through 14, according to an embodiment of the present invention, the link pattern (131) is configured in a grid or stripe shape, and at least two island patterns (132) are connected to each other through the link pattern (131), so the ground line (GL) does not need to be configured to overlap with all island patterns (132). That is, the ground line (GL) can be non-overlapping with at least one of the plurality of island patterns (132) in the vertical direction (VD). Therefore, the area of ​​the ground line (GL) can be reduced, thereby increasing the utilization efficiency of the metal layer.

[0082] In summary, according to the embodiments, the ratio of oxide-oxide bonding can be prevented from becoming excessively low to the extent that it causes a decrease in bonding reliability between semiconductor chips due to the shielding member, thereby preventing interference between bit lines and signal lines while ensuring bonding reliability between semiconductor chips.

[0083] FIG. 16 is a block diagram schematically illustrating a memory system including a semiconductor device according to an embodiment of the invention.

[0084] Referring to FIG. 16, a memory system (600) according to an embodiment of the present invention may include a non-volatile memory device (610) and a memory controller (620).

[0085] The non-volatile memory device (610) is composed of the semiconductor device described above and can be operated in the manner described above. A memory controller (620) will be configured to control the non-volatile memory device (610). By combining the non-volatile memory device (610) and the memory controller (620), it may be provided as a memory card or a solid-state disk (SSD). The SRAM (621) is used as the operating memory of the processing unit (622). The processing unit (622) performs various control operations for data exchange of the memory controller (620).

[0086] The host interface (623) is equipped with a data exchange protocol of a host connected to the memory system (600). The error correction block (624) detects and corrects errors included in data read from the non-volatile memory device (610). The memory interface (625) interfaces with the non-volatile memory device (610) of the present invention.

[0087] Although not illustrated in the drawings, it is obvious to those skilled in the art that the memory system (600) according to the present invention may further be provided with a ROM (not illustrated) for storing code data for interfacing with a host. The non-volatile memory device (610) may be provided as a multi-chip package composed of a plurality of flash memory chips.

[0088] The memory system (600) of the present invention described above can be provided as a highly reliable storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of the present invention may be provided in a memory system such as a semiconductor disk device (Solid State Disk: hereinafter SSD) which is currently being actively researched. In this case, the memory controller (620) will be configured to communicate with an external entity (e.g., a host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, and IDE (Integrated Drive Electronics).

[0089] FIG. 17 is a block diagram schematically showing a computing system including a semiconductor device according to an embodiment of the present invention.

[0090] Referring to FIG. 17, a computing system (700) according to the present invention may include a memory system (710), a microprocessor (720), RAM (730), a user interface (740), and a modem (750), such as a baseband chipset, electrically connected to a system bus (760). If the computing system (700) according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system (700) will be additionally provided. Although not shown in the drawings, it is obvious to those skilled in the art that the computing system (700) according to the present invention may further be provided with an application chipset, a camera image processor (CIS), mobile DRAM, etc. The memory system (710) may be configured, for example, as a Solid State Drive / Disk (SSD) that uses non-volatile memory to store data. Alternatively, the memory system (710) may be provided as a fusion flash memory (e.g., one-NAND flash memory).

[0091] The embodiments of the present invention described above are not limited to implementation through devices and methods, but may also be implemented through a program that realizes a function corresponding to the configuration of the embodiments of the present invention or a recording medium on which such a program is recorded. Such implementation can be easily achieved by a person skilled in the art to which the present invention pertains, based on the description of the embodiments described above.

[0092] Although the detailed description of the present invention described above has been explained with reference to embodiments of the invention, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

Claims

Claim 1 A semiconductor device characterized by comprising: a first semiconductor chip including a memory cell array and a plurality of bit lines; a second semiconductor chip including peripheral circuits and bonded to the first semiconductor chip; and a shielding member comprising a link pattern in the form of a grid or stripes configured on one of the bonding metal layers of the first semiconductor chip and the second semiconductor chip, and a plurality of island patterns configured on the other bonding metal layer of the first semiconductor chip and the second semiconductor chip, arranged in a plurality of rows along the direction in which the plurality of bit lines extend and bonded to the link pattern. Claim 2 A semiconductor device according to claim 1, characterized in that a ground voltage is applied to the shielding member. Claim 3 A semiconductor device according to claim 1, further comprising a ground line connected to the shielding member and configured in the inner metal layer between the bonding metal layer of the second semiconductor chip and the peripheral circuit. Claim 4 A semiconductor device according to paragraph 3, characterized in that the ground line is configured to be non-overlapping with at least one of the plurality of island patterns in a vertical direction orthogonal to the bonding metal layers. Claim 5 A semiconductor device according to claim 1, characterized in that one of the plurality of island patterns is electrically connected to another island pattern through the link pattern. Claim 6 A semiconductor device according to claim 1, characterized in that the island patterns of the odd-numbered rows and the island patterns of the even-numbered rows are offset from each other in the row direction such that the island patterns of the odd-numbered rows overlap with some of the bit lines among the plurality of bit lines and the island patterns of the even-numbered rows overlap with the remaining other bit lines. Claim 7 A semiconductor device according to claim 1, wherein the grid-shaped link pattern is composed of a plurality of first lines extending in the direction in which the plurality of bit lines extend and a plurality of second lines extending in the direction in which the plurality of bit lines are arranged intersecting each other. Claim 8 A semiconductor device according to claim 7, wherein the link pattern is configured such that the intersection points where the plurality of first lines and the plurality of second lines intersect are each matched to the plurality of island patterns. Claim 9 A semiconductor device according to claim 1, characterized in that the lines of the striped link pattern are extended in the direction in which the plurality of bit lines are arranged. Claim 10 A semiconductor device characterized by comprising: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip; and a shielding member comprising a link pattern in the form of a grid or stripes formed on one of the bonding metal layers of the first semiconductor chip and the second semiconductor chip, and a plurality of island patterns formed on the other bonding metal layer of the first semiconductor chip and the second semiconductor chip, arranged in a plurality of rows along the direction in which a plurality of bit lines are extended and bonded to the link pattern. Claim 11 A semiconductor device according to claim 10, characterized in that a ground voltage is applied to the shielding member. Claim 12 A semiconductor device according to claim 10, further comprising a ground line configured in the internal metal layer of the second semiconductor chip and connected to the shielding member. Claim 13 A semiconductor device according to claim 10, characterized in that one of the plurality of island patterns is electrically connected to another island pattern through the link pattern. Claim 14 A semiconductor device according to claim 10, wherein the grid-shaped link pattern is configured such that the intersection points where the lines constituting the link pattern intersect each other are matched to the plurality of island patterns.

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