2 terminal based 3D random access memory including select transisor

Abstract

A two-terminal based three-dimensional random access memory including a select transistor is disclosed. According to one embodiment, the two-terminal based three-dimensional random access memory may include: gate electrodes stacked and spaced apart in the vertical direction while extending horizontally on a substrate; and vertical structures extending in the vertical direction through the gate electrodes—each of which includes a data storage pattern, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion.

Description

Technology Field

[0001] The following embodiments relate to a two-terminal based three-dimensional random access memory including a select transistor, a method of operation thereof, and a method of manufacturing thereof. Background Technology

[0002] Ferroelectric-based memory supporting byte-level random access has begun to be implemented in a three-dimensional structure to secure storage space.

[0003] However, since the gate electrodes of a three-dimensional ferroelectric-based memory are vertically spaced and stacked, they have a line shape, so memory cell strings penetrating the line-shaped gate electrodes in the vertical direction cannot be formed in high density.

[0004] Accordingly, as a technology to improve the integration density of memory cell strings is required, a 3D random access memory structure that supports terminal-based random access while improving the integration density of memory cell strings has been proposed.

[0005] However, since this three-dimensional random access memory has a structure in which multiple memory cell strings share the bit line horizontal portion, when memory is operated, the voltage for memory operation is applied through the bit line horizontal portion not only to the selected memory cell string containing the target memory cell that is the target of memory operation but also to the unselected memory cell string, resulting in a problem where parasitic capacitance occurs in the unselected memory cell string.

[0006] Therefore, a technology to solve the described problem needs to be proposed. The problem to be solved

[0008] One embodiment proposes a two-terminal-based three-dimensional random access memory having a structure in which each gate electrode is formed in the form of a plate extending in the horizontal direction, and vertical structures extending in the vertical direction through the gate electrodes form an array consisting of a plurality of columns and rows on a horizontal plane, in order to achieve the technical challenge of improving the integration density of a memory cell string.

[0009] At this time, one embodiment proposes a two-terminal-based three-dimensional random access memory in which vertical structures are arranged offset from each other on a horizontal plane to further improve the integration density of the memory cell string.

[0010] In particular, one embodiment proposes a two-terminal based three-dimensional random access memory having a structure that includes a select transistor to prevent the application of a voltage for memory operation to a non-selected memory cell string, so as to prevent parasitic capacitance from occurring in a non-selected memory cell string as a voltage for memory operation is applied to a non-selected memory cell string.

[0011] Here, some embodiments propose a two-terminal based three-dimensional random access memory that uses a select transistor to pre-charge a selected memory cell string during a read operation.

[0012] However, the technical problems that the present invention aims to solve are not limited to the above problems and can be expanded in various ways without departing from the technical concept and scope of the present invention. means of solving the problem

[0013] According to one embodiment, a two-terminal-based three-dimensional random access memory may include: gate electrodes that are formed extending horizontally on a substrate and are spaced apart vertically and stacked; and vertical structures that penetrate the gate electrodes and extend in the vertical direction—each of the vertical structures comprising a data storage pattern, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion.

[0014] According to one aspect, the selection transistor may be characterized in that, during memory operation for a target memory cell, voltage is applied only to a selected vertical structure that includes the target memory cell among the vertical structures, and the voltage is not applied to at least one unselected vertical structure that is connected to the same bit line horizontal portion as the selected vertical structure among the unselected vertical structures that do not include the target memory cell.

[0015] According to another aspect, the selection transistor may be characterized as being used to prevent parasitic capacitance from occurring in at least one unselected vertical structure.

[0016] According to another aspect, the selection transistor may be characterized by being used to pre-charge a selected vertical structure containing the target memory cell among the vertical structures during a read operation on the target memory cell.

[0017] According to another aspect, the selection transistor may be characterized by being turned on or turned off according to the control of the gate electrode corresponding to the selection transistor among the gate electrodes.

[0018] According to another aspect, the selection transistor may be characterized by being formed of a semiconductor material that selectively forms a channel depending on the applied voltage.

[0019] According to another aspect, the selection transistor may be characterized by being formed by selectively forming the channel while simultaneously doping it with impurities to improve contact resistance with the bit line vertical portion.

[0020] According to another aspect, each of the vertical structures may further include a dielectric pattern disposed on top of the data storage pattern to correspond to the selection transistor.

[0021] According to another aspect, among the vertical structures, the vertical structures placed in the same row in an array consisting of multiple columns and rows on a horizontal plane may be characterized by being connected to each other's different bit line horizontal parts.

[0022] According to one embodiment, a memory operation method of a two-terminal-based three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction on a substrate and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of which includes a data storage pattern, a bit line vertical portion, and a selection transistor disposed above the bit line vertical portion—may include the steps of: applying a voltage to a bit line horizontal portion connected to a selected vertical structure among the vertical structures that includes a target memory cell to be subject to memory operation; turning on a selection transistor of the selected vertical structure so that the voltage is applied to the selected vertical structure; and turning off a selection transistor of at least one unselected vertical structure so that the voltage is not applied to at least one unselected vertical structure among the unselected vertical structures that do not include the target memory cell and is connected to the same bit line horizontal portion as the selected vertical structure.

[0023] According to one aspect, the step of turning off may be characterized by preventing parasitic capacitance from occurring in the at least one unselected vertical structure by turning off the selection transistor of the at least one unselected vertical structure.

[0024] According to another aspect, the memory operation method of the above-described two-terminal-based three-dimensional random access memory may further include the step of pre-charging the selected vertical structure using a selection transistor of the selected vertical structure during the read operation when the memory operation is a read operation for the target memory cell.

[0025] According to one embodiment, a method for manufacturing a two-terminal-based three-dimensional random access memory may include: preparing a semiconductor structure comprising stacked gate electrodes that are spaced apart in the vertical direction and formed extending in the horizontal direction on a substrate; and forming vertical structures that penetrate the gate electrodes in the vertical direction—each of which comprises a data storage pattern, a bit line vertical portion, and a selection transistor disposed above the bit line vertical portion.

[0026] According to one embodiment, a method for manufacturing a two-terminal-based three-dimensional random access memory may include: preparing a semiconductor structure comprising sacrificial layers that are formed extending in a horizontal direction on a substrate and spaced apart in a vertical direction and stacked; forming vertical structures that extend through the sacrificial layers in the vertical direction—each of which comprises a data storage pattern, a bit line vertical portion, and a selection transistor disposed above the bit line vertical portion—and removing the sacrificial layers to form gate electrodes in the removed spaces.

[0027] According to one embodiment, a two-terminal-based three-dimensional random access memory may comprise: gate electrodes that are formed extending in a horizontal direction on a substrate and are spaced apart in a vertical direction and stacked—each of which is formed extending in a different length in the horizontal direction so as to implement a step structure at the upper end of the gate electrodes in the horizontal direction—and vertical structures that penetrate the gate electrodes and extend in the vertical direction—each of which includes a data storage pattern, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion—and each of which is formed extending in a different length to satisfy a length condition that prevents a delay from occurring when a voltage is applied to each of the gate electrodes.

[0028] According to one aspect, each of the gate electrodes may be characterized by satisfying the length condition through the step structure implemented at the end of the gate electrodes in the horizontal direction and the additional step structure implemented at the opposite end of the end of the gate electrodes in the horizontal direction. Effects of the invention

[0029] One embodiment proposes a two-terminal-based three-dimensional random access memory having a structure in which each gate electrode is formed in the shape of a plate extending in the horizontal direction, and vertical structures extending in the vertical direction through the gate electrodes form an array consisting of multiple columns and rows on a horizontal plane, thereby achieving the technical objective of improving the integration density of memory cell strings.

[0030] At this time, one embodiment can further improve the integration density of the memory cell string by proposing a two-terminal-based three-dimensional random access memory in which vertical structures are arranged offset from each other on a horizontal plane.

[0031] In particular, one embodiment proposes a two-terminal-based three-dimensional random access memory having a structure including a select transistor that prevents a voltage for memory operation from being applied to a non-selected memory cell string, thereby preventing parasitic capacitance from occurring in a non-selected memory cell string as a voltage for memory operation is applied to a non-selected memory cell string.

[0032] Here, some embodiments may propose a two-terminal based three-dimensional random access memory that uses a select transistor to pre-charge a selected memory cell string during a read operation.

[0033] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0034] FIG. 1 is a simplified circuit diagram illustrating a two-terminal-based three-dimensional random access memory according to one embodiment. FIGS. 2a and 2b are plan views illustrating a two-terminal-based three-dimensional random access memory according to one embodiment. FIG. 3 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory according to one embodiment, corresponding to the cross-section of FIG. 2a cut along the line A-A'. FIG. 4 is a plan view illustrating a two-terminal-based three-dimensional random access memory according to another embodiment. FIG. 5 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory according to another embodiment, corresponding to the cross-section of FIG. 4 cut along line A-A'. FIG. 6 is a flowchart illustrating a memory operation method of a two-terminal-based three-dimensional random access memory according to one embodiment. FIG. 7 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory to explain the memory operation method of a two-terminal-based three-dimensional random access memory according to one embodiment. FIG. 8 is a flowchart illustrating a method for manufacturing a two-terminal-based three-dimensional random access memory according to one embodiment. FIGS. 9a to 9j are cross-sectional views illustrating a two-terminal-based three-dimensional random access memory to explain a method for manufacturing a two-terminal-based three-dimensional random access memory according to one embodiment. FIG. 10 is a flowchart illustrating a method for manufacturing a two-terminal-based three-dimensional random access memory according to another embodiment. FIGS. 11a to 11l are cross-sectional views illustrating a two-terminal-based three-dimensional random access memory to explain a method for manufacturing a two-terminal-based three-dimensional random access memory according to another embodiment. FIG. 12 is a schematic perspective view illustrating an electronic system including a two-terminal-based three-dimensional random access memory according to one embodiment. Specific details for implementing the invention

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or restricted by the embodiments. Also, the same reference numerals in each drawing indicate the same components.

[0036] Furthermore, the terminology used in this specification is used to appropriately describe preferred embodiments of the present invention, and may vary depending on the intent of the viewer or operator, or the conventions of the field to which the present invention belongs. Accordingly, the definitions of these terms should be based on the content throughout this specification. For example, in this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Also, the terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Additionally, although terms such as "first," "second," etc., are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment.

[0037] Furthermore, it should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the technical spirit and scope of the present invention in relation to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components within each presented category of embodiments may be changed without departing from the technical spirit and scope of the present invention.

[0038] Hereinafter, with reference to the drawings, a two-terminal based three-dimensional random access memory having a structure in which each gate electrode is formed in the shape of a plate extending in the horizontal direction, and vertical structures extending in the vertical direction through the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane, a method of operation thereof, and a method of manufacturing thereof will be described in detail.

[0040] FIG. 1 is a simplified circuit diagram illustrating a two-terminal-based three-dimensional random access memory according to one embodiment.

[0041] Referring to FIG. 1, a three-dimensional random access memory according to one embodiment comprises a plurality of memory cell strings (CSTR; hereinafter, cell) disposed between a first terminal composed of a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and a second terminal composed of a plurality of word lines (WL1, 2, ↳, WLn-1, WLn). It may include strings.

[0042] The bit line horizontal portions (BLH) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a rectangular coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0043] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit line horizontal portions (BLH). Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and a plurality of bit line vertical portions (BLV) may be connected in parallel to each of the bit line horizontal portions (BLH).

[0044] Cell strings (CSTRs) can be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may include memory cell transistors (MCTs) arranged corresponding to word lines (WL1, WL2, ..., WLn-1, WLn) and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each memory cell transistor (MCT) may include a data storage element.

[0045] More specifically, a cell string (CSTR) may be composed of a select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and multiple memory cell transistors (MCTs) at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCTs) may be connected in series while arranged along a third direction (D3).

[0046] The select transistor (SST) can be controlled by the string select line (SSL), and the memory cell transistors (MCT) can be controlled by the word lines (WL1, WL2, ..., WLn-1, WLn).

[0047] Here, the gate electrode (EL-SSL) of the select transistor (SST) may be connected to the string select line (SSL) to be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be connected in common to one of the word lines (WL1, WL2, ..., WLn-1, WLn) to be in an equipotential state.

[0049] FIGS. 2a and 2b are plan views illustrating a two-terminal-based three-dimensional random access memory according to one embodiment, and FIG. 3 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory according to one embodiment, corresponding to the cross-section of FIG. 2a cut along the line A-A'.

[0050] The substrate may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0051] Stacked structures (ST) may be disposed on a substrate (SUB). The stacked structures (ST) may be formed extending in a first direction (D1) and arranged two-dimensionally along a second direction (D2). Additionally, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0052] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating films (ILD) alternately stacked in a vertical direction perpendicular to the upper surface of the substrate (SUB) (e.g., third direction (D3)). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surface of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction refers to the third direction (D3) or the reverse direction of the third direction (D3).

[0053] Referring again to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1, 2, , WLn-1, WLn) stacked in order on the substrate (SUB).

[0054] Each gate electrode (EL) may be formed in the shape of a plate extending in a first direction (D1) and also extending in a second direction (D2), and may have substantially the same thickness in a third direction (D3). Hereinafter, thickness refers to the thickness in the third direction (D3). Each gate electrode (EL) may be formed from a conductive material. For example, each gate electrode (EL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each gate electrode (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0055] One of the upper or lower ends of each of the stacked structures (ST) may have a stepwise structure (SS) along the first direction (D1) as illustrated in FIG. 2b. More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the gate electrode located at the top of the gate electrodes (EL) may have the shortest length in the first direction (D1) and the greatest distance from the substrate (SUB) in the third direction (D3). On the other hand, the gate electrode located at the bottom of the gate electrodes (EL) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3).

[0056] Accordingly, the regions corresponding to the step structure (SS) in each of the gate electrodes (EL) can all be exposed toward the top, and a plug (not shown) connected to each of the gate electrodes (EL) can be formed to contact the region corresponding to the step structure (SS) in each of the gate electrodes (EL) in a vertical direction.

[0057] At this time, if the length along the first direction (D1) of each of the stacked structures (ST) becomes excessively long, a delay in the voltage applied through the gate electrodes (EL) may occur.

[0058] To prevent this, the remaining end located opposite to one of the upper and lower ends of each of the stacked structures (ST) that has a step structure may also have an additional step structure (Small stepwise structure; SSS). The location where the additional step structure (SSS) is formed can be determined so that the length along the first direction (D1) of each of the stacked structures (ST) is adjusted to an appropriate length such that no delay occurs in the voltage applied through the gate electrodes (EL).

[0059] That is, each of the gate electrodes (EL) can be extended to different lengths to satisfy a length condition that prevents a delay from occurring when voltage is applied to each of the gate electrodes (EL) (e.g., a length condition in which the memory cell region where vertical structures (SS) are formed (the remaining region excluding the region corresponding to the step structure (SS)) is 50 μm or less). Such a length condition can be satisfied depending on the location where the step structure (SS) and additional step structure (SSS) are each formed at the upper horizontal end of the gate electrodes (EL), so that the 3D random access memory can implement the step structure (SS) and additional step structure (SSS) at appropriate locations on the gate electrodes (EL) that satisfy the described length condition.

[0060] Each interlayer insulating film (ILD) is depicted as having the same thickness, but is not limited thereto and may have different thicknesses. For example, the bottom and top interlayer insulating films (ILD) may have a smaller thickness than other interlayer insulating films (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating film (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating films (ILD) may be formed of an insulating material to provide insulation between the gate electrodes (EL). For example, the interlayer insulating films (ILD) may be formed of silicon oxide.

[0061] A plurality of holes (H) penetrating parts of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 1, extending in a third direction (D3) while connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by the lower surface of each part of the vertical structures (VS) coming into contact with the upper surface of the substrate (SUB), but is not limited to or restricted thereto and may also be achieved by being embedded inside the substrate (SUB). When a part of each of the vertical structures (VS) is embedded inside the substrate (SUB), the lower surface of the vertical structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

[0062] Columns of vertical structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL). For example, as shown in FIG. 2a, 12 vertical structures (VS) may penetrate one of the stacked structures (ST) by forming 6 columns and 4 rows. However, the number of vertical structures (VS) forming the array is not limited to or restricted therefrom.

[0063] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL) formed in the shape of a plate, the 3D random access memory can have a structure in which the integration density of the memory cell string is improved.

[0064] At this time, vertical structures (VS) included in an adjacent pair of columns may be shifted to form different rows on a horizontal plane and arranged so as to be offset from each other. For example, vertical structures (VS) included in the first column may be arranged in the first and third rows, and vertical structures (VS) included in the second column may be arranged in the second and fourth rows, and vertical structures (VS) included in the second column may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0065] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical structures (VS) as having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they go toward the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0066] These vertical structures (VS) may correspond to the cell strings (CSTR) shown in Fig. 1.

[0067] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a select transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top open, the bit line vertical portion (BLV) may have a shape that fills the space from the bottom to a certain height within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP), and the select transistor (SST) may have a shape that fills the space from the top to a certain depth within the inner space of the data storage pattern (DSP) while being wrapped on the outside by the data storage pattern (DSP). That is, the select transistor (SST) may be positioned above the bit line vertical portion (BLV) by being located at the top of the inner space of the data storage pattern (DSP).

[0068] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can come into contact with the side walls of the gate electrodes (EL) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL-WL) can be configured to form memory cells in which memory operations (including write operations such as program operations and erase operations, and read operations) are performed by the voltage applied through the gate electrodes (EL-WL) and the voltage applied to the bit line vertical portion (BLV). Hereinafter, the statement that voltage is applied to the bit line vertical portion (BLV) means that voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0069] The memory cells correspond to the memory cell transistors (MCTs) shown in FIG. 1. For this purpose, the data storage pattern (DSP) may be a data storage element that generates a polarization phenomenon by the voltage applied through the gate electrodes (EL-WL) and the voltage applied to the bit line vertical portion (BLV) to represent a data value as a voltage, current, or resistance change corresponding to the polarization state of the charges.

[0070] Hereinafter, as a ferroelectric material constituting a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr, or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx, or InOx may be used.

[0071] Although the drawing shows the data storage pattern (DSP) extending in a vertical direction (e.g., the third direction (D3)), it is not limited to or restricted thereto and may have a structure that is spaced apart and arranged only in regions corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0072] The lower surface of the data storage pattern (DSP) can be located at a lower level than the lower surface of the lowest of the gate electrodes (EL-WL) and can be formed to be in contact with the substrate (SUB).

[0073] The bit line vertical portion (BLV) can be connected to each bit line horizontal portion (BLH) located above the vertical structures (VS) via a select transistor (SST) while being included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) can be in contact with the bit line horizontal portion (BLH) via the upper select transistor (SST), and the upper surface of the select transistor (SST) can be substantially co-planar with the data storage pattern (DSP).

[0074] At this time, at least two bit line horizontal parts (BLH) are located at the same height above the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) positioned at a position offset from the center of each of the vertical structures (VS) to be connected to each of the different bit line horizontal parts (BLH). That is, the vertical structures (VS) arranged in the same row in the array may be connected to each of the different bit line horizontal parts (BLH) through the bit line plug (BLPG) positioned at a position offset from the center of each of the vertical structures (VS).

[0075] The bit line vertical portion (BLV) may be formed of a conductive material comprising at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.).

[0076] The lower surface of the bit line vertical portion (BLV) may be located at a lower level than the lower surface of the lowest of the gate electrodes (EL) and may be spaced apart from the substrate (SUB) by a certain amount. However, it is not limited to or restricted therefrom.

[0077] The select transistor (SST) can be configured to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH) while positioned above the bit line vertical portion (BLV).

[0078] More specifically, the select transistor (SST) can serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) containing a target memory cell that is the target of memory operation among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not contain a target memory cell.

[0079] For example, the select transistor (SST) can be used to ensure that, during memory operation for a target memory cell, the operating voltage is applied only to the selected vertical structure (Sel VS) among the vertical structures (VS) connected to the same bit line horizontal portion (BLH), and the operating voltage is not applied to at least one unselected vertical structure (Unsel VS). In this way, the select transistor (SST) can prevent parasitic capacitance from occurring in at least one unselected vertical structure (Unsel VS) by ensuring that the operating voltage is not applied to at least one unselected vertical structure (Unsel VS).

[0080] To this end, the select transistor (SST) may be formed from a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel depending on the applied voltage. For example, the select transistor (SST) may be formed by doping it with an impurity (N-type impurity) to selectively form a channel while simultaneously improving contact resistance with the bit line vertical portion (BLV) or the bit line horizontal portion (BLH).

[0081] The described select transistor (SST) can be used not only as a selector but also to pre-charge a vertical structure (VS). Specifically, the select transistor (SST) can be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) during a read operation on the target memory cell.

[0082] Such a selection transistor (SST) is turned on or turned off according to the control of the corresponding gate electrode (EL-SSL), and can enable or disable the included vertical structure (VS).

[0083] The vertical structures (VS) are not limited to or restricted to the structures described above and may have structures that further include a dielectric pattern (DP). A detailed description thereof will be provided with reference to Figures 4 and 5 below.

[0084] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench to separate the adjacent stacked structures (ST). For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0085] A capping insulating film (CAP) may be provided on the stacked structures (ST) and vertical structures (VS). The capping insulating film (CAP) may cover the upper surface of the uppermost of the interlayer insulating films (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating films (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0086] Bit line horizontal portions (BLH) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending a conductive material along the second direction (D2) while being spaced apart from each other along the first direction (D2). The conductive material constituting the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0087] The three-dimensional random access memory described above is not limited to or restricted to the described structure, and can be implemented in various structures based on a vertical structure (VS) including a select transistor (SST) according to an implementation example.

[0088] As described, the three-dimensional random access memory can perform memory operations in response to a voltage applied between a first terminal consisting of bit line horizontal portions (BLH) and bit line vertical portions (BLV) and a second terminal consisting of gate electrodes (EL).

[0089] In particular, the three-dimensional random access memory can perform memory operations on the selected target memory cell by using a select transistor (SST) to turn on (activate) only the selected vertical structure (Sel VS) containing the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) and turning off (deactivate) at least one unselected vertical structure (Unsel VS), and in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL) among the gate electrodes (EL).

[0090] A detailed description of the memory operation method of a three-dimensional random access memory and the manufacturing method thereof will be described with reference to Figures 6, 7, 8, 9a to 9j, 10, 11a to 11l below.

[0092] FIG. 4 is a plan view illustrating a two-terminal-based three-dimensional random access memory according to another embodiment, and FIG. 5 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory according to another embodiment, corresponding to the cross section cut along line A-A' of FIG. 4.

[0093] A two-terminal-based three-dimensional random access memory according to another embodiment has the same structure as the two-terminal-based three-dimensional random access memory described with reference to FIGS. 2a to 3, but is differentiated from the one described with reference to FIGS. 2a to 3 in that the vertical structures (VS) further include a dielectric pattern (DP).

[0094] The dielectric pattern (DP) is a component placed on top of the data storage pattern (DSP) to correspond to the select transistor (SST), and in the case where the data storage pattern (DSP) is formed to extend to a height corresponding to the select transistor (SST) (structure described above with reference to FIGS. 2a to 3), it plays a role in solving the problem of polarization occurring in the part of the data storage pattern (DSP) corresponding to the select transistor (SST) during the process in which the select transistor (SST) is controlled by the string select line (SSL).

[0095] That is, as the dielectric pattern (DP) is included in each of the vertical structures (VS), a structure can be implemented in which the dielectric pattern (DP) is located at a height corresponding to the select transistor (SST).

[0097] FIG. 6 is a flowchart illustrating a memory operation method of a two-terminal-based three-dimensional random access memory according to one embodiment, and FIG. 7 is a cross-sectional view illustrating a two-terminal-based three-dimensional random access memory to explain the memory operation method of a two-terminal-based three-dimensional random access memory according to one embodiment.

[0098] The memory operation method described below is based on the premise that it is performed by a three-dimensional random access memory of the structure described above with reference to FIGS. 1 to 5.

[0099] In step (S610), the three-dimensional random access memory can apply an operating voltage to a bit line horizontal portion (BLH) connected to a selected vertical structure (Sel VS) that includes a target memory cell among the vertical structures (VS) that is the target of memory operation.

[0100] In step (S620), the three-dimensional random access memory can turn on the select transistor (SST) of the selected vertical structure (Sel VS) so that an operating voltage is applied to the selected vertical structure (Sel VS).

[0101] Turning on the selection transistor (SST) of the selected vertical structure (Sel VS) can be achieved by applying a turn-on voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of the selected vertical structure (Sel VS).

[0102] In step (S630), the three-dimensional random access memory can turn off the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) so that an operating voltage is not applied to at least one unselected vertical structure (Unsel VS) connected to the same bit line horizontal portion (BLH) as the selected vertical structure (Sel VS) among the unselected vertical structures (Unsel VS) that do not include the target memory cell.

[0103] Turning off the select transistor (SST) of the unselected vertical structure (Unsel VS) can be achieved by floating the gate electrode (EL-SSL) corresponding to the select transistor (SST) of the unselected vertical structure (Unsel VS) or by applying a turn-off voltage.

[0104] In this way, the 3D random access memory can prevent parasitic capacitance from occurring in at least one unselected vertical structure (Unsel VS) by turning off the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) so that an operating voltage is not applied to at least one unselected vertical structure (Unsel VS) in step (S630).

[0105] Although not illustrated as a separate step in the drawing, the 3D random access memory can pre-charge the selected vertical structure (Sel VS) by using the selection transistor (SST) of the selected vertical structure (Sel VS) during the read operation when the memory operation is a read operation on the target memory cell.

[0106] With only the vertical structure (Sel VS) selected by steps (S620 to S630) turned on, the three-dimensional random access memory can perform memory operation for the target memory cell by applying an operating voltage to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and applying a ground voltage (ground bias; e.g., 0V) to the selected gate electrode (Sel EL-WL) among the gate electrodes (EL-WL) corresponding to the target memory cell (floating each of the unselected gate electrodes (Unsel EL-WL) excluding the selected gate electrode (Sel EL-WL) among the gate electrodes (EL-WL).

[0107] Here, the memory operation may include a first write operation (program operation) for writing data of "1", a second write operation (erase operation) for writing data of "0", and a read operation for sensing data written in the target memory cell (sensing the polarization state of the data storage pattern (DSP) corresponding to the target memory cell).

[0108] For example, regarding the first write operation, the 3D random access memory applies a positive write operation voltage (+V) to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). WRITE1 ; For example, by applying 5V) and applying a ground voltage (Ground bias; for example, 0V) to the selected gate electrode (Sel EL-WL), the amount of write operation voltage (+V) applied to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) is WRITE1 In response to a ground voltage (ground bias; e.g., 0V) applied to the selected gate electrode (Sel EL-WL), a first write operation (a programming operation to write data of "1") can be performed on the target memory cell.

[0109] For example, regarding the second write operation, the 3D random access memory applies a negative write operation voltage (-V) to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). WRITE0 ; for example, -5V) is applied, and by applying a ground voltage (Ground bias; for example, 0V) to the selected gate electrode (Sel EL-WL), a negative write operation voltage (-V) applied to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) is applied. WRITE0 In response to a ground voltage (Ground bias; e.g., 0V) applied to the selected gate electrode (Sel EL-WL), a second write operation (an erase operation that writes data of "0") to the target memory cell can be performed.

[0110] For example, regarding a read operation, a 3D random access memory applies a read operation voltage (V) to the bit line vertical portion (BLV) of a selected vertical structure (Sel VS). READ By applying ) and applying a ground voltage (Ground bias; e.g., 0V) to the selected gate electrode (Sel EL-WL), the read operation voltage (V) applied to the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) is READ A read operation on the target memory cell can be performed in response to a ground voltage (ground bias; e.g., 0V) applied to the selected gate electrode (Sel EL-WL).

[0112] FIG. 8 is a flowchart illustrating a method for manufacturing a two-terminal-based three-dimensional random access memory according to one embodiment, and FIGS. 9a to 9j are cross-sectional views illustrating a two-terminal-based three-dimensional random access memory to explain a method for manufacturing a two-terminal-based three-dimensional random access memory according to one embodiment.

[0113] The manufacturing method described below is intended for manufacturing a three-dimensional random access memory of the structure described above with reference to FIGS. 1 to 3, and is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0114] In step (S810), the manufacturing system can prepare a semiconductor structure (SEMI-STR). Here, the semiconductor structure (SEM-STR) may include gate electrodes (EL) formed in the shape of a plate extending horizontally on a substrate (SUB) and stacked while being spaced vertically apart, and interlayer insulating layers (ILD) interposed between the gate electrodes (EL).

[0115] In step (S820), the manufacturing system can extend vertical structures (VS) that penetrate the gate electrodes (EL) in a vertical direction so that the vertical structures (VS) form an array composed of multiple columns and rows on a horizontal plane—each of the vertical structures (VS) includes a data storage pattern (DSP), a bit line vertical portion (BLV), and a select transistor (SST) positioned on top of the bit line vertical portion (BLV).

[0116] More specifically, the manufacturing system may form a plurality of holes (H) that form an array consisting of a plurality of columns and rows on a semiconductor structure (SEM-STR) as shown in FIG. 9a, extend a data storage pattern (DSP) on the inner wall of the holes (H) as shown in FIG. 9b, and extend a bit line vertical portion (BLV) on the inner wall of the data storage pattern (DSP) as shown in FIG. 9c. Subsequently, the manufacturing system may etch and remove an area corresponding to the uppermost gate electrode (EL-SSL) in the bit line vertical portion (BLV) as shown in FIG. 9d, and form a selective transistor (SST) with a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel according to the voltage applied to the etched and removed space as shown in FIG. 9e and 9f.

[0117] The manufacturing method described above is described as manufacturing a three-dimensional random access memory with a structure that does not include a dielectric pattern (DP), but is not limited to or restricted thereto, and a three-dimensional random access memory with a structure that includes a dielectric pattern (DP) can also be manufactured.

[0118] When manufacturing a three-dimensional random access memory having a structure including a dielectric pattern (DP), the manufacturing system can, after the processes of FIGS. 9a to 9c described above, etch and remove the region corresponding to the uppermost gate electrode (EL-SSL) in each of the bit line vertical portion (BLV) and the data storage pattern (DSP) as shown in FIG. 9g, fill the etched and removed space with a dielectric material that forms the dielectric pattern (DP) as shown in FIG. 9h, and then etch and remove the vertical region corresponding to the bit line vertical portion (BLV) from the filled dielectric material as shown in FIG. 9i, thereby forming a selective transistor (SST) with a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel according to the voltage applied to the etched and removed space as shown in FIG. 9j.

[0119] Although not described as a separate step, the manufacturing system may extend and form bit line horizontal portions (BLH) horizontally on top of the vertical structures (VS) after step (S820). In this process, the manufacturing system may connect the bit line vertical portions (BLV) included in each of the vertical structures (VS) to each of the bit line horizontal portions (BLH) through bit line plugs (BLPG).

[0120] The manufacturing method described above is a gate-first process method; however, in addition to the gate-first process method, the manufacturing system may also utilize a gate replacement process method. A detailed explanation regarding this will be provided below.

[0122] FIG. 10 is a flowchart illustrating a method for manufacturing a two-terminal-based three-dimensional random access memory according to another embodiment, and FIG. 11a to 11l are cross-sectional views illustrating a two-terminal-based three-dimensional random access memory to explain a method for manufacturing a two-terminal-based three-dimensional random access memory according to another embodiment.

[0123] The manufacturing method described below is for manufacturing a three-dimensional random access memory of the structure described above with reference to FIGS. 1 to 3, and is based on the premise that it is performed by an automated and mechanized manufacturing system, and may utilize a gate replacement process method.

[0124] Referring to FIG. 10, in step (S1010), the manufacturing system can prepare a semiconductor structure (SEMI-STR). Here, the semiconductor structure (SEM-STR) may include sacrificial layers (SAC) stacked and spaced vertically while being formed in the shape of a plate extending horizontally on a substrate (SUB), and interlayer insulating layers (ILD) interposed between the sacrificial layers (SAC).

[0125] In step (S1020), the manufacturing system can extend and form vertical structures (VS) that penetrate the sacrificial layers (SAC) in a vertical direction so that the vertical structures (VS) form an array composed of multiple columns and rows on a horizontal plane—each of the vertical structures (VS) includes a data storage pattern (DSP), a bit line vertical portion (BLV), and a select transistor (SST) positioned on top of the bit line vertical portion (BLV).

[0126] In step (S1030), the manufacturing system can remove the sacrificial layers (SAC) to form gate electrodes (EL) in the removed spaces.

[0127] More specifically, the manufacturing system may form a plurality of holes (H) that form an array consisting of a plurality of columns and rows on a semiconductor structure (SEM-STR) as shown in FIG. 11a, extend a data storage pattern (DSP) on the inner wall of the holes (H) as shown in FIG. 11b, and extend a bit line vertical portion (BLV) on the inner wall of the data storage pattern (DSP) as shown in FIG. 11c. Then, the manufacturing system may etch and remove an area corresponding to the uppermost sacrificial layer (SAC) in the bit line vertical portion (BLV) as shown in FIG. 11d, and form a selective transistor (SST) with a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel depending on the voltage applied to the etched and removed space as shown in FIG. 11e and FIG. 11f. After that, the manufacturing system can remove the sacrificial layers (SAC) as shown in FIG. 11g, and then form gate electrodes (EL) in the spaces where the sacrificial layers (SAC) were removed as shown in FIG. 11h.

[0128] When manufacturing a three-dimensional random access memory having a structure including a dielectric pattern (DP), the manufacturing system can, after the processes of FIGS. 11a to 11d described above, etch and remove a region corresponding to the uppermost sacrificial layer (SAC) in each of the bit line vertical portion (BLV) and the data storage pattern (DSP) as shown in FIG. 11i, fill the etched and removed space with a dielectric material forming the dielectric pattern (DP) as shown in FIG. 11j, and then etch and remove a vertical region corresponding to the bit line vertical portion (BLV) from the filled dielectric material as shown in FIG. 11k, thereby forming a selective transistor (SST) with a semiconductor material (e.g., polycrystalline silicon or oxide semiconductor material, etc.) that selectively forms a channel according to the voltage applied to the etched and removed space as shown in FIG. 11l. After that, the manufacturing system can complete the formation of gate electrodes (EL) by performing the processes of FIGS. 11g and 11h described above.

[0129] Although not described as a separate step, the manufacturing system may extend and form bit line horizontal portions (BLH) horizontally on top of the vertical structures (VS) after step (S1030). In this process, the manufacturing system may connect the bit line vertical portions (BLV) included in each of the vertical structures (VS) to each of the bit line horizontal portions (BLH) through bit line plugs (BLPG).

[0131] FIG. 12 is a schematic perspective view illustrating an electronic system including a two-terminal-based three-dimensional random access memory according to one embodiment.

[0132] Referring to FIG. 12, an electronic system (1200) including a three-dimensional random access memory according to embodiments may include a main board (1201), a controller (1202) mounted on the main board (1201), one or more semiconductor packages (1203) and a DRAM (1204).

[0133] The semiconductor package (1203) and DRAM (1204) can be connected to the controller (1202) by wiring patterns (1205) provided on the main board (1201).

[0134] The main board (1201) may include a connector (1206) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1206) may vary depending on the communication interface between the electronic system (1200) and the external host.

[0135] The electronic system (1200) can communicate with an external host according to any one of the interfaces, for example, USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). The electronic system (1200) can operate by power supplied from an external host, for example, through a connector (1206). The electronic system (1200) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to a controller (1202) and a semiconductor package (1203).

[0136] The controller (1202) can write data to the semiconductor package (1203) or read data from the semiconductor package (1203), and can improve the operating speed of the electronic system (1200).

[0137] The DRAM (1204) may be a buffer memory to mitigate the speed difference between the semiconductor package (1203), which is a data storage space, and an external host. The DRAM (1204) included in the electronic system (1200) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (1203). When the electronic system (1200) includes the DRAM (1204), the controller (1202) may further include a DRAM controller for controlling the DRAM (1204) in addition to the NAND controller for controlling the semiconductor package (1203).

[0138] A semiconductor package (1203) may include first and second semiconductor packages (1203a, 1203b) spaced apart from each other. The first and second semiconductor packages (1203a, 1203b) may each be a semiconductor package including a plurality of semiconductor chips (1220). Each of the first and second semiconductor packages (1203a, 1203b) may include a package substrate (1210), semiconductor chips (1220) on the package substrate (1210), adhesive layers (1230) disposed on the lower surface of each of the semiconductor chips (1220), connection structures (1240) electrically connecting the semiconductor chips (1220) and the package substrate (1210), and a molding layer (1250) covering the semiconductor chips (1220) and the connection structures (1240) on the package substrate (1210).

[0139] The package substrate (1210) may be a printed circuit board including package upper pads (1211). Each semiconductor chip (1220) may include input / output pads (1221). Each semiconductor chip (1220) may include the three-dimensional random access memory described above with reference to FIGS. 1 to 11. More specifically, each semiconductor chip (1220) may include gate stacking structures (1222) and memory structures (1223). The gate stacking structures (1222) may correspond to the stacking structures (ST) described above, and the memory structures (1223) may correspond to the vertical structures (VS) described above.

[0140] The connection structures (1240) may be, for example, bonding wires that electrically connect the input / output pads (1221) and the package upper pads (1211). Accordingly, in each of the first and second semiconductor packages (1203a, 1203b), the semiconductor chips (1220) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (1211) of the package substrate (1210). According to embodiments, in each of the first and second semiconductor packages (1203a, 1203b), the semiconductor chips (1220) may be electrically connected to each other by through-silicon vias instead of the bonding wire connection structures (1240).

[0141] Unlike what is described, the controller (1202) and the semiconductor chips (1220) may be included in a single package. The controller (1202) and the semiconductor chips (1220) may be mounted on a separate interposer substrate other than the main substrate (1201), and the controller (1202) and the semiconductor chips (1220) may be connected to each other by wiring provided on the interposer substrate.

[0143] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0144] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A two-terminal based three-dimensional random access memory comprises: gate electrodes formed extending horizontally on a substrate and stacked while being spaced apart in the vertical direction; and vertical structures formed extending vertically through the gate electrodes—each of which has a segmented structure formed of a ferroelectric material and includes a data storage pattern, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion, wherein memory cells are configured in regions corresponding to the gate electrodes on the data storage pattern—the memory cells have a structure that is spaced apart from each other through the segmented structure of the data storage pattern and is connected horizontally to the bit line vertical portion, and the two-terminal based three-dimensional random access memory is characterized by implementing a Metal-Ferroelectric-Metal (MFM) structure in the regions corresponding to the gate electrodes, the gate electrodes, the ferroelectric material, and the bit line vertical portion. Claim 2 A two-terminal based three-dimensional random access memory according to claim 1, wherein the selection transistor is used to apply voltage only to a selected vertical structure containing the target memory cell among the vertical structures during a memory operation for the target memory cell, and to prevent the voltage from being applied to at least one unselected vertical structure connected to the same bit line horizontal portion as the selected vertical structure among the unselected vertical structures that do not contain the target memory cell. Claim 3 A two-terminal based three-dimensional random access memory according to claim 2, characterized in that the selection transistor is used to prevent parasitic capacitance from occurring in at least one unselected vertical structure. Claim 4 A two-terminal based three-dimensional random access memory according to claim 1, characterized in that the selection transistor is used to pre-charge a selected vertical structure including the target memory cell among the vertical structures during a read operation for the target memory cell. Claim 5 A two-terminal based three-dimensional random access memory according to claim 1, wherein the selection transistor is turned on or turned off according to the control of the gate electrode corresponding to the selection transistor among the gate electrodes. Claim 6 A two-terminal based three-dimensional random access memory according to claim 1, wherein the selection transistor is formed of a semiconductor material that selectively forms a channel according to an applied voltage. Claim 7 A two-terminal based three-dimensional random access memory according to claim 6, wherein the selection transistor is formed by selectively forming the channel while simultaneously doping it with impurities to improve contact resistance with the bit line vertical portion. Claim 8 A two-terminal based three-dimensional random access memory according to claim 1, wherein each of the vertical structures further comprises a dielectric pattern disposed on top of the data storage pattern to correspond to the selection transistor. Claim 9 A two-terminal based three-dimensional random access memory according to claim 1, wherein the vertical structures placed in the same row in an array composed of multiple columns and rows on a horizontal plane among the vertical structures are each connected to different bit line horizontal portions. Claim 10 A memory operation method for a two-terminal based three-dimensional random access memory comprising: gate electrodes formed extending horizontally on a substrate and spaced apart in a vertical direction and stacked; and vertical structures formed extending vertically and penetrating the gate electrodes—each of which includes a data storage pattern formed of a ferroelectric material, a bit line vertical portion, and a selection transistor disposed above the bit line vertical portion, wherein memory cells are configured in regions corresponding to the gate electrodes on the data storage pattern— wherein the memory cells are spaced apart from each other through the segmented structure of the data storage pattern and have a structure connected horizontally to the bit line vertical portion, the method comprising: a step of applying a voltage to a bit line horizontal portion connected to a selected vertical structure including a target memory cell among the vertical structures that is the target of memory operation; and a step of turning on a selection transistor of the selected vertical structure so that the voltage is applied to the selected vertical structure. A memory operation method of a two-terminal based three-dimensional random access memory, comprising the step of turning off a selection transistor of at least one unselected vertical structure so that the voltage is not applied to at least one unselected vertical structure connected to the same bit line horizontal portion as the selected vertical structure among the unselected vertical structures that do not include the target memory cell, and wherein the two-terminal based three-dimensional random access memory implements a Metal-Ferroelectric-Metal (MFM) structure in regions corresponding to the gate electrodes, the gate electrodes, the ferroelectric material, and the bit line vertical portion. Claim 11 A memory operation method of a two-terminal-based three-dimensional random access memory, wherein, in claim 10, the step of turning off is a step of preventing parasitic capacitance from occurring in the at least one unselected vertical structure by turning off the selection transistor of the at least one unselected vertical structure. Claim 12 A memory operation method of a two-terminal-based three-dimensional random access memory, characterized in that, in the case where the memory operation is a read operation for the target memory cell, the method further includes the step of pre-charging the selected vertical structure using a selection transistor of the selected vertical structure during the read operation. Claim 13 A method for manufacturing a two-terminal-based three-dimensional random access memory comprises: a step of preparing a semiconductor structure including stacked gate electrodes that are formed extending in a horizontal direction on a substrate and spaced apart in a vertical direction; and a step of extending and forming vertical structures penetrating the gate electrodes in the vertical direction—each of the vertical structures having a segmented structure spaced apart from each other only in regions corresponding to the gate electrodes and including a data storage pattern formed of a ferroelectric material, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion, wherein memory cells are configured in regions corresponding to the gate electrodes on the data storage pattern, and the memory cells have a structure spaced apart from each other through the segmented structure of the data storage pattern and connected in a horizontal direction to the bit line vertical portion—the two-terminal-based three-dimensional random access memory is characterized by implementing a Metal-Ferroelectric-Metal (MFM) structure in the regions corresponding to the gate electrodes, the gate electrodes, the ferroelectric material, and the bit line vertical portion. Claim 14 A method for manufacturing a two-terminal-based three-dimensional random access memory comprises: a step of preparing a semiconductor structure including stacked sacrificial layers that are spaced apart in the vertical direction and formed extending in the horizontal direction on a substrate; and a step of extending and forming vertical structures penetrating the sacrificial layers in the vertical direction—each of the vertical structures having a segmented structure spaced apart from each other only in regions corresponding to gate electrodes, and including a data storage pattern formed of a ferroelectric material, a bit line vertical portion, and a select transistor disposed above the bit line vertical portion, wherein memory cells are configured in regions corresponding to the gate electrodes on the data storage pattern, and the memory cells have a structure spaced apart from each other through the segmented structure of the data storage pattern and connected in the horizontal direction to the bit line vertical portion. A method for manufacturing a two-terminal based three-dimensional random access memory, comprising the step of removing the sacrificial layers to form the gate electrodes in the removed spaces, wherein the two-terminal based three-dimensional random access memory implements a Metal-Ferroelectric-Metal (MFM) structure in regions corresponding to the gate electrodes, wherein the gate electrodes, the ferroelectric material, and the bit line vertical portions. Claim 15 In a two-terminal-based three-dimensional random access memory, gate electrodes are formed extending in a horizontal direction on a substrate and stacked while being spaced apart in a vertical direction—each of the gate electrodes is formed extending with a different length in the horizontal direction so as to implement a step structure at the upper end of the gate electrodes in the horizontal direction—; A two-terminal based three-dimensional random access memory comprising: vertical structures formed extending in the vertical direction and penetrating the gate electrodes—each of which has a segmented structure spaced apart from each other only in regions corresponding to the gate electrodes and includes a data storage pattern formed of a ferroelectric material, a bit line vertical portion, and a selection transistor disposed above the bit line vertical portion, and configuring memory cells in regions corresponding to the gate electrodes on the data storage pattern—each of which the gate electrodes are formed extending with different lengths satisfying a length condition that prevents a delay from occurring when a voltage is applied to each of the gate electrodes, and the memory cells have a structure spaced apart from each other through the segmented structure of the data storage pattern and connected in the horizontal direction to the bit line vertical portion, wherein the two-terminal based three-dimensional random access memory implements a Metal-Ferroelectric-Metal (MFM) structure in the regions corresponding to the gate electrodes, the gate electrodes, the ferroelectric material, and the bit line vertical portion. Claim 16 A two-terminal based three-dimensional random access memory according to claim 15, wherein each of the gate electrodes satisfies the length condition through the step structure implemented at the end of the gate electrodes in the horizontal direction and the additional step structure implemented at the opposite end of the end of the gate electrodes in the horizontal direction.

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