Backgate wiring manufacturing method

Abstract

A method for manufacturing back gate wiring is disclosed. According to one embodiment, the method for manufacturing back gate wiring may include the steps of exposing one end of each of the vertical channel structures, sequentially forming a common source and a separating insulating layer to contact the exposed side of each of the vertical channel structures, and forming back gate wiring on the vertical channel structures to contact the back gate of each of the vertical channel structures.

Description

Technology Field

[0001] The following embodiments describe a method for manufacturing back gate wiring in a three-dimensional flash memory structure including a back gate. Background Technology

[0002] Flash memory devices are electrically programmable and eraseable read-only memory (EEPROM) that controls data input and output electrically through FN tunneling (Fowler-Nordheim tunneling) or thermionic electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In these flash memory devices, it is required to increase the integration density to meet the excellent performance and low cost demanded by consumers, so a three-dimensional structure in which memory cell transistors are arranged in a vertical direction to form a memory cell string has been proposed.

[0004] In relation to such 3D flash memory, ensuring cell characteristics and reliability that degrade with increasing stacking in the vertical direction is emerging as a major issue.

[0005] Accordingly, a structure including a back gate in the internal space of a vertical channel pattern was proposed, and regarding the manufacturing of back gate wiring connecting the back gate, a method was proposed in which a hole in contact with the back gate is formed using a photomask, the vertical portion of the back gate wiring is filled into the hole, and a horizontal portion connected to the vertical portion of the back gate wiring is formed.

[0006] However, the described back gate wiring manufacturing process has the disadvantage of increasing process complexity and cost due to the requirement of a photomask-based process for forming holes in contact with the back gate, and the problem of difficulty in filling the vertical portions of the back gate wiring into the holes due to scaling for improved integration density.

[0007] Therefore, through the following embodiments, it is necessary to propose a technology that solves the disadvantages and problems of the existing back gate wiring manufacturing process. The problem to be solved

[0009] One embodiment proposes a back gate wiring manufacturing method using a recess process based on an Xtacking technique that flips a semiconductor structure, with the aim of achieving a technical objective that is applicable regardless of scaling for improved integration density while promoting process simplification by lowering process complexity and cost.

[0010] At this time, one embodiment proposes a back gate wiring manufacturing method that prevents vertical channel patterns from being recessed together during the recess process.

[0011] In addition, one embodiment proposes a method for manufacturing back gate wiring that also forms a source along with the back gate wiring.

[0012] In addition, one embodiment proposes a method for manufacturing back gate wiring that prevents a short circuit between the source and the back gate wiring.

[0013] In addition, some embodiments propose a method for manufacturing back gate wiring that implements back gate wiring in various forms.

[0014] However, the technical problems that the present invention aims to solve are not limited to the above problems and can be expanded in various ways without departing from the technical concept and scope of the present invention. means of solving the problem

[0015] According to one embodiment, a method for manufacturing back gate wiring may include: preparing a semiconductor structure comprising: gate electrodes formed extending in a horizontal direction and stacked while spaced apart from each other in a vertical direction; and vertical channel structures formed extending in the vertical direction through the gate electrodes—each of which includes a vertical channel pattern formed extending in the vertical direction, a data storage pattern formed in contact with the outer wall of the vertical channel pattern, and a back gate formed extending in the vertical direction within the inner space of the vertical channel pattern; recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; sequentially forming a common source and a separation insulating layer to contact the exposed side of each of the vertical channel structures; and forming back gate wiring on the vertical channel structures to contact the back gate of each of the vertical channel structures.

[0016] According to another embodiment, a method for manufacturing back gate wiring may include: preparing a semiconductor structure comprising: sacrificial layers formed extending in a horizontal direction and stacked while spaced apart from each other in a vertical direction; and vertical channel structures formed extending in the vertical direction through the sacrificial layers—each of which includes a vertical channel pattern formed extending in the vertical direction, a data storage pattern formed in contact with the outer wall of the vertical channel pattern, and a back gate formed extending in the vertical direction within the inner space of the vertical channel pattern; recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; sequentially forming a common source and a separating insulating layer to contact the exposed side of each of the vertical channel structures; forming back gate wiring on the vertical channel structures to contact the back gate of each of the vertical channel structures; and removing the sacrificial layers to form gate electrodes in the spaces where the sacrificial layers have been removed.

[0017] According to one aspect, the preparing step may be characterized as a step of preparing the semiconductor structure in which a capping film is formed in a region corresponding to the back gate among the exposed ends of each of the vertical channel structures.

[0018] According to another aspect, the capping film may be characterized by being formed of a material or composition different from the common source to prevent the region corresponding to the back gate among the exposed ends of each of the vertical channel structures from being recessed together when a portion of the common source is recessed during the step of sequentially forming the common source and the separating insulating layer.

[0019] According to another aspect, the step of sequentially forming the common source and the separating insulating layer may be characterized by comprising: forming the common source to contact the exposed side of the vertical channel pattern in each of the vertical channel structures in response to the recessing of the semiconductor structure in which a region corresponding to the data storage pattern among the exposed ends of each of the vertical channel structures is recessed; recessing a portion of the common source and the region corresponding to the vertical channel pattern so that a back gate insulating film interposed between the vertical channel pattern and the back gate is exposed at the exposed end of each of the vertical channel structures; and forming the separating insulating layer on the common source to contact the exposed side of the back gate insulating film in each of the vertical channel structures.

[0020] According to another aspect, the step of forming the back gate wiring may be characterized by including either a step of forming the back gate wiring in the form of a plate or a step of forming the back gate wiring in the form of a line.

[0021] According to another aspect, the back gate wiring formed in the line shape may be characterized by connecting the back gates of each of the vertical channel structures included in the same row or column among the vertical channel structures.

[0022] According to another aspect, the horizontal portion of the back gate wiring formed in the line shape may be characterized by being shared by vertical channel structures included in adjacent rows or columns among the vertical channel structures.

[0023] According to another aspect, the step of sequentially forming the common source and the separating insulating layer may be characterized by including either a step of forming the common source in a plate shape or a step of forming the common source in a line shape.

[0024] According to another aspect, the common source formed in the line shape may be characterized by connecting the vertical channel patterns of each of the vertical channel structures included in the same row or column among the vertical channel structures.

[0025] According to another aspect, the common source formed in the line shape may be characterized by being shared by vertical channel structures included in adjacent rows or columns among the vertical channel structures.

[0026] According to another aspect, the step of sequentially forming the common source and the separating insulating layer may be characterized by including the step of forming the separating insulating layer on one side of the common source to prevent a short circuit between the common source and the back gate wiring as the back gate wiring comes into direct contact with one side of the common source.

[0027] According to one embodiment, a three-dimensional flash memory may include: gate electrodes formed to extend in a horizontal direction and stacked while spaced apart from each other in a vertical direction; vertical channel structures formed to extend in the vertical direction through the gate electrodes—each of the vertical channel structures comprising a vertical channel pattern formed to extend in the vertical direction, a data storage pattern formed in contact with the outer wall of the vertical channel pattern, and a back gate formed to extend in the vertical direction within the inner space of the vertical channel pattern—; a common source formed to contact the lower side of each of the vertical channel structures; a separating insulating layer formed below the common source; and back gate wiring formed below the vertical channel structures and below the separating insulating layer to contact the back gate of each of the vertical channel structures.

[0028] According to one aspect, the common source is characterized by being formed to contact the lower side of the vertical channel pattern in each of the vertical channel structures, and the separating insulating layer is characterized by being formed to contact the lower side of the back gate insulating film interposed between the vertical channel pattern and the back gate in each of the vertical channel structures. Effects of the invention

[0029] One embodiment proposes a back gate wiring manufacturing method using a recess process based on an X-tacking technique that flips a semiconductor structure, thereby reducing process complexity and cost to promote process simplification, while simultaneously achieving a technical effect applicable regardless of scaling for integration density improvement.

[0030] At this time, one embodiment may propose a back gate wiring manufacturing method that prevents vertical channel patterns from being recessed together during the recess process.

[0031] In addition, one embodiment may propose a method for manufacturing back gate wiring that also forms a source together with the back gate wiring.

[0032] In addition, one embodiment may propose a method for manufacturing back gate wiring that prevents a short circuit between the source and the back gate wiring.

[0033] In addition, some embodiments may propose a method for manufacturing back gate wiring that implements back gate wiring in various forms.

[0034] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0035] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to embodiments. FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment. FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'. FIG. 4 is a flowchart illustrating a method for manufacturing back gate wiring in a three-dimensional flash memory according to one embodiment. FIGS. 5a to 5g are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the back gate wiring manufacturing method illustrated in FIG. 4. FIGS. 6a to 6e are cross-sectional views illustrating the structure of a three-dimensional flash memory including a capping film to explain the back gate wiring manufacturing method illustrated in FIG. 4. FIGS. 7a to 7g are plan views illustrating the structure of a three-dimensional flash memory in which the back gate wiring and the common source are each formed in the form of a plate to explain the back gate wiring manufacturing method illustrated in FIG. 4. FIGS. 8 and 9 are plan views illustrating the structure of a three-dimensional flash memory in which a common source is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 4. FIGS. 10 and 11 are plan views illustrating the structure of a three-dimensional flash memory in which the back gate wiring is formed in a line shape to explain the back gate wiring manufacturing method illustrated in FIG. 4. FIG. 12 is a flowchart illustrating a method for manufacturing back gate wiring in a three-dimensional flash memory according to another embodiment. FIG. 13 is a schematic perspective view illustrating an electronic system including a three-dimensional flash memory according to embodiments. Specific details for implementing the invention

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or restricted by the embodiments. Also, the same reference numerals in each drawing indicate the same components.

[0037] Furthermore, the terminology used in this specification is used to appropriately describe preferred embodiments of the present invention, and may vary depending on the intent of the viewer or operator, or the conventions of the field to which the present invention belongs. Accordingly, the definitions of these terms should be based on the content throughout this specification. For example, in this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Also, the terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Additionally, although terms such as "first," "second," etc., are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment.

[0038] Furthermore, it should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the technical spirit and scope of the present invention in relation to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components within each presented category of embodiments may be changed without departing from the technical spirit and scope of the present invention.

[0039] Hereinafter, with reference to the drawings, a method for manufacturing back gate wiring using a recess process based on the Xtacking technique, which flips a semiconductor structure, is described in detail in order to achieve the technical objectives and effects applicable regardless of scaling for improved integration density, while simultaneously promoting process simplification by reducing process complexity and cost.

[0041] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to embodiments.

[0042] Referring to FIG. 1, an array of three-dimensional flash memory according to one embodiment may include a common source (CS), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source (CS) and the bit lines (BL0, BL1, BL2).

[0043] Bit lines (BL0, BL1, BL2) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a Cartesian coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0044] Multiple cell strings (CSTR) can be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) can be connected to a common source (CS) while provided between the bit lines (BL0, BL1, BL2) and a common source (CS).

[0045] At this time, the common source (CS) may be implemented in a plate form so as to be shared by cell strings (CSTRs) constituting the array, but is not limited to or restricted thereto and may be implemented in a line form so as to be shared only by cell strings (CSTRs) included in the same row or column. When the common source (CS) is implemented in a line form, multiple common sources (CS) may be provided, and multiple common sources (CS) may be arranged two-dimensionally, spaced apart from each other along the second direction (D2) while extending in the first direction (D1). The same electrical voltage may be applied to the multiple common sources (CS), but is not limited to or restricted thereto and different voltages may be applied by each of the multiple common sources (CS) being electrically controlled independently.

[0046] Cell strings (CSTRs) may be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may be composed of a ground select transistor (GST) connected to a common source (CS), first and second string select transistors (SST1, SST2) connected in series and connected to bit lines (BL0, BL1, BL2), memory cell transistors (MCTs) connected in series and positioned between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2), and an erase control transistor (ECT). Additionally, each memory cell transistor (MCT) may include a data storage element.

[0047] For example, each cell string (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, not limited thereto, each cell string (CSTR) may include a single string select transistor. As another example, the ground select transistor (GST) in each cell string (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0048] A cell string (CSTR) may be composed of multiple memory cell transistors (MCTs) at different distances from a common source (CS). That is, the memory cell transistors (MCTs) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source (CS). Each cell string (CSTR) may further include dummy cell transistors (DMCs) connected between the first string select transistor (SST1) and the highest of the memory cell transistors (MCTs), and between the ground select transistor (GST) and the lowest of the memory cell transistors (MCTs), respectively. The dummy cell transistors (DMCs) may be omitted depending on the implementation.

[0049] According to an embodiment, the first string select transistor (SST1) can be controlled by the first string select lines (SSL1-1, SSL1-2, SSL1-3), and the second string select transistor (SST2) can be controlled by the second string select lines (SSL2-1, SSL2-2, SSL2-3). Memory cell transistors (MCT) can each be controlled by a plurality of word lines (WL0-WLn), and dummy cell transistors (DMC) can each be controlled by a dummy word line (DWL). The ground select transistor (GST) can be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) can be controlled by the erase control line (ECL). The erase control transistor (ECT) can be provided in multiple numbers. A common source (CS) can be connected in common to the sources of the erase control transistors (ECT).

[0050] Here, the dummy word line (DWL) can also be omitted, just like the dummy cell transistors (DMC).

[0051] The gate electrodes of memory cell transistors (MCTs) provided at substantially the same distance from the common source (CS) may be connected in common to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. However, without being limited to this, even if the gate electrodes of memory cell transistors (MCTs) are provided at substantially the same level from the common source (CS), the gate electrodes provided in different rows or columns may be controlled independently.

[0052] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3) may be extended along a first direction (D1) and spaced apart from each other in a second direction (D2) and arranged two-dimensionally. However, without being limited to or restricted thereto, each of the ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3) may be implemented in the form of a plate and shared by cell strings (CSTR) constituting the array.

[0053] Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from a common source (CS) can be electrically isolated from each other.

[0054] Additionally, erase control transistors (ECTs) of different cell strings (CSTRs) can be controlled by a common erase control line (ECL). The erase control transistors (ECTs) may cause gate-induced drain leakage (GIDL) during the erase operation of the memory cell array. In some embodiments, during the erase operation of the memory cell array, an erase voltage may be applied to bit lines (BL0, BL1, BL2) and / or a common source (CS), and gate-induced leakage current may occur in the string select transistor (SST) and / or erase control transistors (ECTs).

[0055] Additionally, back gates (BG) connected to each cell string (CSTR) in the array of three-dimensional flash memory are omitted from the drawing, but each back gate (BG) can be electrically connected to memory cell transistors (MCT) within each string (CSTR). That is, back gates (BG) can be provided corresponding to the cell strings (CSTR). A detailed explanation of this will be provided below.

[0057] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment, and FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section cut along the line A-A' of FIG. 2.

[0058] Referring to the drawings, the laminated structure (ST) may be formed to extend in a first direction (D1) and a second direction (D2). Although the drawings show a single laminated structure (ST), it is not limited to or restricted thereto, and multiple structures may be provided and arranged two-dimensionally spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0059] The stacked structure (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., third direction (D3)). The stacked structure (ST) may have a substantially flat top surface. Hereinafter, the vertical direction means the third direction (D3) or the reverse direction of the third direction (D3).

[0060] Although omitted in the drawing, the stacked structure (ST) may exist in a state disposed on the substrate (SUB) prior to the formation of the common source (CS) and back gate wiring (BGW). That is, the stacked structure (ST) may be manufactured by alternately stacking gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) may be removed during the process of forming the common source (CS) and back gate wiring (BGW), so that the substrate (SUB) may not be included.

[0061] The substrate (SUB) used in the manufacturing process of the stacked structure (ST) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0062] Referring again to FIG. 1, each gate electrode (EL1, EL2, EL3) may be one of an erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) stacked in order along the direction from bottom to top.

[0063] Each of the gate electrodes (EL1, EL2, EL3) may have a substantially identical thickness in the third direction (D3) while being formed extending in the first direction (D1). Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0064] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each shown and described in singular form, this is exemplary and not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in plurality as needed. The first gate electrode (EL1) may correspond to any one of the ground select lines (GSL0, GSL1, GLS2) shown in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) shown in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) of FIG. 1 or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3).

[0065] Although not illustrated, the end of the stacked structure (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structure (ST) may decrease in length in the first direction (D1) as they move from the bottom to the top. The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the largest distance from the bottom along the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the smallest distance from the bottom along the third direction (D3). Due to the stepped structure, the thickness of the stacked structure (ST) can decrease as it moves away from the outermost one of the vertical channel structures (VS) described later, and the sidewalls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at regular intervals along the first direction (D1) in a planar view.

[0066] However, not limited to or restricted thereto, the end of the laminated structure (ST) may have a stepped structure along the second direction (D2).

[0067] Each of the interlayer insulating layers (ILD) may have a different thickness. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating layer (ILD) may have different thicknesses or all be set to the same thickness depending on the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material to provide insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0068] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) are stacked and spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0069] A plurality of channel holes (CH) penetrating a portion of the stacked structure (ST) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 1, extending in a third direction (D3) while connected to a common source (CS). The connection of the vertical channel structures (VS) to the common source (CS) may be achieved by the lower surface of each portion of the vertical channel structures (VS) coming into contact with the upper surface of the common source (CS).

[0070] Columns of vertical channel structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as shown in FIG. 2, 15 vertical channel structures (VS) may penetrate the stacked structure (ST) in 6 columns and 5 rows. However, the number of vertical channel structures (VS) forming the array is not limited to or restricted therefrom.

[0071] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL1, EL2, EL3) formed in the shape of a plate, the 3D flash memory can have a structure in which the integration density of the memory cell string is improved.

[0072] In particular, unlike conventional structures where the common source (CS) and its wiring are contained within the stacked structure (ST), memory density can be improved as they are located at the bottom of the stacked structure (ST).

[0073] At this time, vertical channel structures (VS) included in an adjacent pair of columns may be arranged so as to be offset from each other by being shifted to form different rows on a horizontal plane. For example, vertical channel structures (VS) included in the first column may be arranged in the first row, the third row, and the third row, and vertical channel structures (VS) included in the second column may be arranged in the second row and the fourth row, and vertical channel structures (VS) included in an adjacent pair of columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical channel structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0074] Each of the vertical channel structures (VS) may be formed to extend in a third direction (D3) from the bottom toward the top. Although the drawings show that each of the vertical channel structures (VS) has a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases toward the first direction (D1) and the second direction (D2) as they move toward the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0075] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a back gate (BG), and a capping layer (CAP-L). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with the bottom open, and the back gate (BG) may have a shape that fills the inner space of the vertical channel pattern (VCP).

[0076] The data storage pattern (DSP) covers the inner wall of each channel hole (CH), surrounds the outer wall of the vertical channel pattern (VCP) on the inside, and can contact the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the second gate electrodes (EL2), together with the regions of the vertical channel pattern (VCP) corresponding to the second gate electrodes (EL2), can form memory cells in which memory operations (program operation, read operation, or erase operation) are performed by the voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) shown in FIG. 1.

[0077] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by the voltage applied through the second gate electrodes (EL2) or by maintaining the state of the electrons (e.g., the polarization state of the charges). For example, an ONO (tunnel oxide-charge storage nitride-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent binary data values ​​or multi-valued data values ​​based on changes in trapped charges or holes, or binary data values ​​or multi-valued data values ​​based on changes in the state of the charges.

[0078] Although it has been described that the data storage pattern (DSP) is connected in a vertical direction and extended, it is not limited to or restricted thereto and may be segmented into multiple parts and formed only in the portions corresponding to the second gate electrodes (EL), thereby configuring memory cells together with the regions corresponding to the second gate electrodes (EL2) among the vertical channel pattern (VCP).

[0079] A vertical channel pattern (VCP) is a component that supplies electrons or holes to transfer charge to a data storage pattern (DSP), and can be formed by covering the inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage and extending in a vertical direction (e.g., a third direction (D3)). More specifically, the vertical channel pattern (VCP) can perform memory operations in response to voltage applied by a bit line (BL), a common source (CS), a back gate (BG), and gate electrodes (EL1, EL2, EL3). To this end, the vertical channel pattern (VCP) can be formed of, for example, single-crystalline silicon or polycrystalline silicon.

[0080] The upper surface of the vertical channel pattern (VCP) may be located at a higher level than the upper surface of the uppermost of the second gate electrodes (EL2). More specifically, the upper surface of the vertical channel pattern (VCP) may be located between the upper and lower surfaces of the third gate electrode (EL3). The lower surface of the vertical channel pattern (VCP) may be co-planar with the upper surface of the common source (CS) (i.e., the lower surface of the lowest of the interlayer insulating layers (ILD)).

[0081] The back gate (BG) can be formed to be in contact with the vertical channel pattern (VCP) while being partially wrapped by it. For example, the back gate (BG) can be formed to extend vertically (e.g., in the third direction (D3)) within the inner space of the vertical channel pattern (VCP).

[0082] Here, the back gate (BG) can be formed to apply a voltage for memory operation to a vertical channel pattern (VCP). To this end, the back gate (BG) can be formed from a conductive material comprising at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). In addition to the described metal material, the back gate (BG) may comprise at least one of all metal materials that can be formed by ALD.

[0083] Additionally, a back gate insulating film (BG-INS) may be formed and interposed between the back gate (BG) and the vertical channel pattern (VCP), extending in a vertical direction (e.g., a third direction (D3)). Accordingly, the back gate insulating film (BG-INS) prevents the back gate (BG) from coming into direct contact with the vertical channel pattern (VCP). The back gate insulating film (BG-INS) may be formed of an insulating material such as silicon oxide, similar to the interlayer insulating layers (ILD). However, the back gate insulating film (BG-INS) may be omitted depending on the implementation example.

[0084] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to the channels of the erase control transistor (ECT), the first and second string select transistors (SST1, SST2), the ground select transistor (GST), and the memory cell transistors (MCT).

[0085] Back gates (BG) included in each of the vertical channel structures (VS) can be electrically connected to each other by back gate wiring (BGW). Accordingly, the back gate wiring (BGW) can be formed of a conductive material comprising at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), similar to the back gate (BG).

[0086] Although the drawing illustrates that the back gate wiring (BGW) is implemented in the form of a plate to connect the back gate (BG) of each of the vertical channel structures (VS) constituting the array, it is not limited to or restricted thereto and may also be implemented in the form of a line. In such cases, the back gate wiring (BGW) may be implemented to connect the back gate (BG) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the back gate wiring (BGW) may be shared not only by the vertical channel structures (VS) included in the same row or column but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the back gates (BG) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns to each other. A detailed explanation thereof will be provided below.

[0087] The common source (CS) is a component corresponding to the common source (CS) of FIG. 1 and can be electrically connected to the vertical channel structures (VS) through the vertical channel pattern (VCP). More specifically, the common source (CS) may be formed to contact the lower side of the vertical channel pattern (VCP) of each of the vertical channel structures (VS) as formed by the manufacturing method described below. However, without being limited to this, the common source (CS) may also be formed to contact the lower side of the data storage pattern (DSP).

[0088] Likewise, the common source (CS) may be formed of a conductive material comprising at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) so as to enable voltage application to the vertical channel structures (VS).

[0089] Although the drawing illustrates a common source (CS) being implemented in the form of a plate to connect the vertical channel patterns (VCP) of each of the vertical channel structures (VS) constituting the array, it is not limited to or restricted thereto and may also be implemented in the form of a line. In such cases, the common source (CS) may be implemented to connect the vertical channel patterns (VCP) of each of the vertical channel structures (VS) included in the same row or column among the vertical channel structures (VS). Furthermore, the common source (CS) may be shared not only by the vertical channel structures (VS) included in the same row or column but also by the vertical channel structures (VS) included in adjacent rows or columns, thereby connecting the vertical channel patterns (VCP) included in each of the vertical channel structures (VS) included in the same row or column and the vertical channel structures (VS) included in adjacent rows or columns. A detailed explanation thereof will be provided below.

[0090] A separating insulating layer (S-INS-L) may be interposed between the common source (CS) and the back gate wiring (BGW). Accordingly, a short circuit between the back gate wiring (BGW) and the common source (CS) caused by the back gate wiring (BGW) directly contacting one side of the common source (CS) can be prevented by the separating insulating layer (S-INS-L).

[0091] The separation insulating layer (S-INS-L) can be formed to contact the lower side of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS) as it is formed by the manufacturing method described below.

[0092] A capping layer (CAP-L) may be provided on the upper surface of the vertical channel pattern (VCP). The capping layer (CAP-L) may be connected to the upper surface of the vertical channel pattern (VCP). The sidewalls of the capping layer (CAP-L) may be surrounded by a data storage pattern (DSP). The upper surface of the capping layer (CAP-L) may be substantially co-planar with the upper surface of the stacked structure (ST) (i.e., the upper surface of the uppermost of the interlayer insulating layers (ILD). The lower surface of the capping layer (CAP-L) may be located at a lower level than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP-L) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP-L) may overlap horizontally with the third gate electrode (EL3).

[0093] The capping layer (CAP-L) can be formed of a material having a contact resistance lower than the contact resistance that the vertical channel pattern (VCP) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP-L) can reduce the contact resistance between the bit line (BL) and the vertical channel pattern (VCP) described later. However, depending on the implementation example, the capping layer (CAP-L) may be omitted.

[0094] A capping insulating film (CAP-INS) may be provided on the stacked structure (ST) and the vertical channel structures (VS). The capping insulating film (CAP-INS) may cover the upper surface of the uppermost of the interlayer insulating layers (ILD) and the upper surface of the capping layer (CAP-L). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP-L) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0095] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of the plurality of bit lines (BL0, BL1, BL2) shown in FIG. 1 and may be formed by extending a conductive material along a second direction (D2). The conductive material constituting the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0096] A bit line (BL) can be electrically connected to vertical channel structures (VS) through a bit line contact plug (BLPG). Here, being connected to the vertical channel structures (VS) means being connected to a vertical channel pattern (VCP) included in the vertical channel structures (VS).

[0097] A three-dimensional flash memory according to one embodiment is not limited to or restricted to the described structure, and can be implemented in various structures on the premise that it includes gate electrodes (EL1, EL2, EL3) to which a voltage for memory operation is applied, a bit line (BL), a common source (CS), a vertical channel pattern (VCP), a data storage pattern (DSP), a back gate (BG), and a back gate wiring (BGW) according to an example of implementation.

[0098] Additionally, the 3D flash memory may be a hybrid bonding-based 3D flash memory in which two structures having the structure shown in FIG. 3 are prepared and then the two structures are bonded facing each other based on a bit line (BL). However, it may also be a hybrid bonding-based 3D flash memory in which two structures are bonded facing each other based on a back gate wiring (BGW), without being limited to or restricted to this.

[0099] The following describes a method for manufacturing a back gate wiring (BGW) in a three-dimensional flash memory of the described structure.

[0101] FIG. 4 is a flowchart illustrating a method for manufacturing back gate wiring in a three-dimensional flash memory according to one embodiment, FIG. 5a to 5g are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the method for manufacturing back gate wiring illustrated in FIG. 4, FIG. 6a to 6e are cross-sectional views illustrating the structure of a three-dimensional flash memory when a capping film is included to explain the method for manufacturing back gate wiring illustrated in FIG. 4, FIG. 7a to 7g are plan views illustrating the structure of a three-dimensional flash memory when the back gate wiring and the common source are each formed in a plate shape to explain the method for manufacturing back gate wiring illustrated in FIG. 4, FIG. 8 to 9 are plan views illustrating the structure of a three-dimensional flash memory when the common source is formed in a line shape to explain the method for manufacturing back gate wiring illustrated in FIG. 4, FIG. 10 to 11 are plan views illustrating the structure of a three-dimensional flash memory when the back gate wiring is formed in a line shape to explain the method for manufacturing back gate wiring illustrated in FIG. 4.

[0102] The three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 3, and the manufacturing method described below is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0103] In addition, through the drawings below, a method for manufacturing back gate wiring based on a semiconductor structure (SEMI-STR) prior to the creation of capping insulating films (CAP-INS), bit line contact plugs (BLPG), and bit lines (BL) is described.

[0104] In step (S410), the manufacturing system can prepare a semiconductor structure (SEMI-STR) as shown in FIG. 5a and FIG. 7a.

[0105] Here, the semiconductor structure (SEMI-STR) may include gate electrodes (EL1, EL2, EL3) that are formed extending in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and stacked while spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed extending in a vertical direction (e.g., a third direction (D3)) through the gate electrodes (EL1, EL2, EL3). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) formed extending in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) formed in contact with the outer wall of the vertical channel pattern (VCP), and a back gate (BG) formed extending in a vertical direction (e.g., a third direction (D3)) in the inner space of the vertical channel pattern (VCP).

[0106] The semiconductor structure (SEMI-STR) is prepared by being manufactured through the conventional manufacturing processes of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), respectively, and then flipped by the X-tacking technique, and a detailed explanation thereof will be omitted.

[0107] As described above, a back gate wiring manufacturing method is performed during the process of manufacturing a hybrid bonding-based 3D flash memory. In step (S410), another semiconductor structure (SEMI-STR) may already be bonded to the lower surface of the semiconductor structure (SEMI-STR) prepared (when upper structures such as bit lines (BL) are all manufactured on each of the semiconductor structures (SEMI-STR)) or may be bonded after the steps described later (S420 to S440) (when upper structures such as bit lines (BL) are not manufactured on each of the semiconductor structures (SEMI-STR)).

[0108] In step (S410), when the semiconductor structure (SEMI-STR) is prepared, a CMP process may be performed on one side of the semiconductor structure (SEMI-STR) (the side on which the subsequent step (S420) is to be performed).

[0109] At this time, when a portion of the common source (CS) is recessed in the step (S430) described later, the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS) may be recessed together. Accordingly, in step (S410), the manufacturing system may prepare a semiconductor structure (SEMI-STR) in which a capping film (CAP) is formed on the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS), as illustrated in FIG. 6a. For example, the capping film (CAP) may be formed of a material or composition different from the common source (CS) to prevent the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS) from being recessed together when a portion of the common source (CS) is recessed in step (S430).

[0110] In step (S420), the manufacturing system can recess the semiconductor structure (SEMI-STR) so that one end of each of the vertical channel structures (VS) is exposed on one side of the semiconductor structure (SEMI-STR), as illustrated in FIGS. 5b, FIGS. 7b, and FIGS. 6b.

[0111] Here, one side of the semiconductor structure (SEMI-STR) is recessed so that the bottommost interlayer insulating layer (ILD) included in the semiconductor structure (SEMI-STR), excluding the vertical channel structures (VS) (since the semiconductor structure (SEMI-STR) is prepared by flipping it over using the X-tacking technique), is removed.

[0112] Additionally, as one side of the semiconductor structure (SEMI-STR) is recessed, the area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) may be recessed. However, this is not limited to or restricted thereto.

[0113] In step (S430), the manufacturing system can sequentially form a common source (CS) and a separate insulating layer (S-INS-L) to contact the exposed side of each of the vertical channel structures (VS).

[0114] More specifically, the manufacturing system comprises: a first step of forming a common source (CS) to contact the exposed side of a vertical channel pattern (VCP) in each of the vertical channel structures (VS) as illustrated in FIGS. 5c, 7c, and 6c; a second step of recessing a portion of the common source (CS) and a region corresponding to the vertical channel pattern (VCP) so that a back gate insulating film (BG-INS) is exposed at one exposed end of each of the vertical channel structures (VS) as illustrated in FIGS. 5d, 7d, and 6d; a third step of forming a separating insulating layer (S-INS-L) on the common source (CS) to contact the exposed side of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS) as illustrated in FIGS. 5e, 7e, and 6e; and a portion of the separating insulating layer (S-INS-L) so that the back gate (BG) of each of the vertical channel structures (VS) is exposed as illustrated in FIGS. 5f and 7f. Step (S430) can be performed through the fourth step of CMP (Chemical mechanical polishing).

[0115] The described first step corresponds to the case where, in step (S420), one side of the semiconductor structure (SEMI-STR) is recessed and, at the same time, the region corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is recessed; however, if the region corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is not recessed in step (S420), the step may be executed as a step of forming a common source (CS) to contact the exposed side of the data storage pattern (DSP) in each of the vertical channel structures (VS). In this case, the second step may be executed such that, at the same time, a portion of the common source (CS) is recessed and, the region corresponding to the data storage pattern (DSP) and the region corresponding to the vertical channel pattern (VCP) are recessed together so that the back gate insulating film (BG-INS) is exposed in the exposed end of each of the vertical channel structures (VS).

[0116] The described fourth step can be performed by CMPing one end of each of the vertical channel structures (VS) together with a portion of the separating insulating layer (S-INS-L) so that, when each of the vertical channel structures (VS) includes a capping film (CAP) as illustrated in FIGS. 6a to 6e, the capping film (CAP) is removed to expose the back gate (BG).

[0117] In the process of forming the common source (CS) and the separated insulating layer (S-INS-L), respectively, conventional deposition processes such as ALD and CVD can be used.

[0118] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) and the common source (CS) described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) caused by the back gate wiring (BGW) directly contacting one side of the common source (CS).

[0119] In FIGS. 5c, 7c, 6c, 5d, 7d, and 6d, the common source (CS) is shown as being formed in a plate shape, but is not limited thereto and may be formed in a line shape as shown in FIGS. 8 and 9. That is, in step (S430), the manufacturing system can form the common source (CS) in a plate shape or a line shape.

[0120] When a common source (CS) is formed in the form of a line, the common source (CS) can be configured to connect the vertical channel patterns (VCP) of each vertical channel structure (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) can be formed corresponding to each column in an array of vertical channel structures (VS) as shown in FIG. 8, thereby connecting the vertical channel patterns (VCP) of each vertical channel structure (VS) included in the same column.

[0121] However, not limited to or restricted thereto, when the common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed in correspondence with the space between columns in an array of vertical channel structures (VS) as shown in FIG. 9, thereby connecting the vertical channel patterns (VCP) of each vertical channel structure (VS) included in adjacent columns to the left and right.

[0122] In step (S440), the manufacturing system can form back gate wiring (BGW) on the vertical channel structures (VS) so as to contact the back gate (BG) of each of the vertical channel structures (VS) as illustrated in FIG. 5g and FIG. 7g.

[0123] In FIG. 5g and FIG. 7g, the back gate wiring (BGW) is shown as being formed in a plate shape, but is not limited thereto and may be formed in a line shape as shown in FIG. 10 or FIG. 11. That is, in step (S440), the manufacturing system can form the back gate wiring (BGW) in a plate shape or a line shape.

[0124] When the back gate wiring (BGW) is formed in the form of a line, the back gate wiring (BGW) can be configured to connect the back gates (BG) of each vertical channel structure (VS) included in the same row or column among the vertical channel structures (VS). For example, the back gate wiring (BGW) can be formed corresponding to each column in an array of vertical channel structures (VS) as shown in FIG. 10, thereby connecting the back gates (BG) of each vertical channel structure (VS) included in the same column.

[0125] However, not limited to or restricted thereto, when the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the back gate wiring (BGW) may be formed in correspondence with the space between columns in an array of vertical channel structures (VS) as shown in FIG. 11, thereby connecting the back gates (BG) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0126] In the drawings above, when the common source (CS) and back gate wiring (BGW) are configured in a line form, they are shown as being formed in a direction orthogonal to the bit lines (BL) on the horizontal plane, but they are not limited to or restricted thereto and may also be formed in a direction parallel to the bit lines (BL) on the horizontal plane. Since this only requires rotating the formation direction by 90 degrees, a detailed explanation will be omitted.

[0127] In addition, although the above back gate wiring (BGW) manufacturing method has been described as using a gate-first process based on a semiconductor structure (SEMI-STR) in which gate electrodes (EL1, EL2, EL3) are formed first, it is not limited thereto and may also use a gate replacement process based on a semiconductor structure (SEMI-STR) that includes sacrificial layers (SAC) corresponding to spaces where gate electrodes (EL1, EL2, EL3) are to be formed later. A detailed description thereof will be provided with reference to FIG. 12.

[0129] FIG. 12 is a flowchart illustrating a method for manufacturing back gate wiring in a three-dimensional flash memory according to another embodiment.

[0130] The three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 3, and the manufacturing method described below is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0131] In addition, the manufacturing method described below is similar to the manufacturing method described above with reference to FIG. 4, but is characterized by using a gate replacement process based on a semiconductor structure (SEMI-STR) that includes sacrificial layers (SAC) corresponding to spaces where gate electrodes (EL1, EL2, EL3) are later formed.

[0132] In step (S1210), the manufacturing system can prepare a semiconductor structure (SEMI-STR).

[0133] Here, the semiconductor structure (SEMI-STR) may include sacrificial layers (SAC) that are formed extending in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and stacked spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and vertical channel structures (VS) that are formed extending in a vertical direction (e.g., a third direction (D3)) through the sacrificial layers (SAC). Each of the vertical channel structures (VS) may include a vertical channel pattern (VCP) formed extending in a vertical direction (e.g., a third direction (D3)) as described above, a data storage pattern (DSP) formed in contact with the outer wall of the vertical channel pattern (VCP), and a back gate (BG) formed extending in a vertical direction (e.g., a third direction (D3)) within the inner space of the vertical channel pattern (VCP).

[0134] The semiconductor structure (SEMI-STR) is prepared by being manufactured through the conventional manufacturing processes of the gate electrodes (EL1, EL2, EL3), interlayer insulating layers (ILD), and vertical channel structures (VS), respectively, and then flipped by the X-tacking technique, and a detailed explanation thereof will be omitted.

[0135] As described above, a back gate wiring manufacturing method is performed during the process of manufacturing a hybrid bonding-based 3D flash memory. In step (S1210), another semiconductor structure (SEMI-STR) may already be bonded to the lower surface of the semiconductor structure (SEMI-STR) prepared in step (S1210) (when upper structures such as bit lines (BL) are all manufactured on each of the semiconductor structures (SEMI-STR)) or may be bonded after the steps described later (S1220 to S1250) (when upper structures such as bit lines (BL) are not manufactured on each of the semiconductor structures (SEMI-STR)).

[0136] In step (S1210), when the semiconductor structure (SEMI-STR) is prepared, a CMP process may be performed on one side of the semiconductor structure (SEMI-STR) (the side on which the subsequent step (S1220) is to be performed).

[0137] At this time, when a portion of the common source (CS) is recessed in the step (S1230) described later, the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS) may be recessed together. Accordingly, in step (S1210), the manufacturing system may prepare a semiconductor structure (SEMI-STR) in which a capping film (CAP) is formed on the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS). For example, the capping film (CAP) may be formed of a material or composition different from the common source (CS) to prevent the region corresponding to the back gate (BG) among the exposed ends of each of the vertical channel structures (VS) from being recessed together when a portion of the common source (CS) is recessed in step (S1230).

[0138] In step (S1220), the manufacturing system can recess the semiconductor structure (SEMI-STR) so that one end of each of the vertical channel structures (VS) is exposed on one side of the semiconductor structure (SEMI-STR).

[0139] Here, one side of the semiconductor structure (SEMI-STR) is recessed so that the bottommost interlayer insulating layer (ILD) included in the semiconductor structure (SEMI-STR), excluding the vertical channel structures (VS) (since the semiconductor structure (SEMI-STR) is prepared by flipping it over using the X-tacking technique), is removed.

[0140] Additionally, as one side of the semiconductor structure (SEMI-STR) is recessed, the area corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) may be recessed. However, this is not limited to or restricted thereto.

[0141] In step (S1230), the manufacturing system can sequentially form a common source (CS) and a separate insulating layer (S-INS-L) to contact the exposed side of each of the vertical channel structures (VS).

[0142] More specifically, the manufacturing system can perform step (S1230) through a first step of forming a common source (CS) to contact the exposed side of a vertical channel pattern (VCP) in each of the vertical channel structures (VS); a second step of recessing a portion of the common source (CS) and a region corresponding to the vertical channel pattern (VCP) so that a back gate insulating film (BG-INS) is exposed at one end of each of the vertical channel structures (VS); a third step of forming a separating insulating layer (S-INS-L) on the common source (CS) to contact the exposed side of the back gate insulating film (BG-INS) in each of the vertical channel structures (VS); and a fourth step of chemical mechanical polishing (CMP) a portion of the separating insulating layer (S-INS-L) so that the back gate (BG) of each of the vertical channel structures (VS) is exposed.

[0143] The described first step corresponds to a case where, in step (S1220), one side of the semiconductor structure (SEMI-STR) is recessed and, at the same time, the region corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is recessed; however, if the region corresponding to the data storage pattern (DSP) among the exposed ends of each of the vertical channel structures (VS) is not recessed in step (S1220), the step may be executed as a step of forming a common source (CS) to contact the exposed side of the data storage pattern (DSP) in each of the vertical channel structures (VS). In this case, the second step may be executed such that, at the same time, a portion of the common source (CS) is recessed and, the region corresponding to the data storage pattern (DSP) and the region corresponding to the vertical channel pattern (VCP) are recessed together so that the back gate insulating film (BG-INS) is exposed in the exposed end of each of the vertical channel structures (VS).

[0144] The described fourth step can be performed by CMPing one end of each of the vertical channel structures (VS) together with a portion of the separation insulating layer (S-INS-L) so that, if each of the vertical channel structures (VS) includes a capping film (CAP), the capping film (CAP) is removed to expose the back gate (BG).

[0145] In the process of forming the common source (CS) and the separated insulating layer (S-INS-L), respectively, conventional deposition processes such as ALD and CVD can be used.

[0146] The isolation insulating layer (S-INS-L) is a component interposed between the back gate wiring (BGW) and the common source (CS) described later, and can prevent a short circuit between the back gate wiring (BGW) and the common source (CS) caused by the back gate wiring (BGW) directly contacting one side of the common source (CS).

[0147] The common source (CS) can be formed not only in the form of a plate but also in the form of a line. That is, in step (S1230), the manufacturing system can form the common source (CS) in the form of a plate or a line.

[0148] When a common source (CS) is formed in the form of a line, the common source (CS) can be configured to connect the vertical channel patterns (VCP) of each vertical channel structure (VS) included in the same row or column among the vertical channel structures (VS). For example, the common source (CS) can be formed corresponding to each column in an array of vertical channel structures (VS) to connect the vertical channel patterns (VCP) of each vertical channel structure (VS) included in the same column.

[0149] However, not limited to or restricted thereto, when a common source (CS) is formed in a line shape, the common source (CS) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the common source (CS) may be formed corresponding to the space between columns in an array of vertical channel structures (VS) to connect the vertical channel patterns (VCP) of each vertical channel structure (VS) included in adjacent columns to the left and right.

[0150] In step (S1240), the manufacturing system can form back gate wiring (BGW) on the vertical channel structures (VS) so as to contact the back gate (BG) of each of the vertical channel structures (VS).

[0151] The back gate wiring (BGW) can be formed not only in the form of a plate but also in the form of a line. That is, in step (S1240), the manufacturing system can form the back gate wiring (BGW) in the form of a plate or a line.

[0152] When the back gate wiring (BGW) is formed in the form of a line, the back gate wiring (BGW) can be configured to connect the back gates (BG) of each vertical channel structure (VS) included in the same row or column among the vertical channel structures (VS). For example, the back gate wiring (BGW) can be formed corresponding to each column in an array of vertical channel structures (VS) to connect the back gates (BG) of each vertical channel structure (VS) included in the same column.

[0153] However, not limited to or restricted thereto, when the back gate wiring (BGW) is formed in a line shape, the back gate wiring (BGW) may be configured to be shared by vertical channel structures (VS) included in adjacent rows or columns among the vertical channel structures (VS). For example, the back gate wiring (BGW) may be formed corresponding to the space between columns in an array of vertical channel structures (VS) to connect the back gates (BG) of each of the vertical channel structures (VS) included in adjacent columns to the left and right.

[0154] In step (S1250), the manufacturing system can remove the sacrificial layers (SAC) to form gate electrodes (EL1, EL2, EL3) in the spaces where the sacrificial layers (SAC) have been removed. The removal of the sacrificial layers (SAC) can be performed through a trench or hole for a gate replacement process formed on one side of the semiconductor structure (SEMI-STR). Since the gate replacement process can be performed using the existing method, a detailed description thereof will be omitted.

[0155] Similar to the manufacturing method described above through FIG. 4, when the common source (CS) and back gate wiring (BGW) are configured in the form of lines, they can be formed not only in a direction orthogonal to the bit lines (BL) on the horizontal plane, but also in a direction parallel to the bit lines (BL) on the horizontal plane. Since this only requires rotating the formation direction by 90 degrees, a detailed description will be omitted.

[0157] FIG. 13 is a schematic perspective view illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0158] Referring to FIG. 13, an electronic system (1300) including a three-dimensional flash memory according to embodiments may include a main board (1301), a controller (1302) mounted on the main board (1301), one or more semiconductor packages (1303) and a DRAM (1304).

[0159] The semiconductor package (1303) and DRAM (1304) can be connected to the controller (1302) by wiring patterns (1305) provided on the main board (1301).

[0160] The main board (1301) may include a connector (1306) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1306) may vary depending on the communication interface between the electronic system (1300) and the external host.

[0161] The electronic system (1300) can communicate with an external host according to any one of the interfaces, for example, USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). The electronic system (1300) can operate by power supplied from an external host, for example, through a connector (1306). The electronic system (1300) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to a controller (1302) and a semiconductor package (1303).

[0162] The controller (1302) can write data to the semiconductor package (1303) or read data from the semiconductor package (1303), and can improve the operating speed of the electronic system (1300).

[0163] The DRAM (1304) may be a buffer memory to mitigate the speed difference between the semiconductor package (1303), which is a data storage space, and an external host. The DRAM (1304) included in the electronic system (1300) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (1303). When the electronic system (1300) includes the DRAM (1304), the controller (1302) may further include a DRAM controller for controlling the DRAM (1304) in addition to the NAND controller for controlling the semiconductor package (1303).

[0164] A semiconductor package (1303) may include first and second semiconductor packages (1303a, 1303b) spaced apart from each other. The first and second semiconductor packages (1303a, 1303b) may each be a semiconductor package including a plurality of semiconductor chips (1320). Each of the first and second semiconductor packages (1303a, 1303b) may include a package substrate (1310), semiconductor chips (1320) on the package substrate (1310), adhesive layers (1330) disposed on the lower surface of each of the semiconductor chips (1320), connection structures (1340) electrically connecting the semiconductor chips (1320) and the package substrate (1310), and a molding layer (1350) covering the semiconductor chips (1320) and the connection structures (1340) on the package substrate (1310).

[0165] The package substrate (1310) may be a printed circuit board including package upper pads (1311). Each semiconductor chip (1320) may include input / output pads (1321). Each semiconductor chip (1320) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 3. More specifically, each semiconductor chip (1320) may include a gate stacking structure (1322) and memory channel structures (1323). The memory channel structures (1323) may correspond to the vertical channel structures (VS) described above.

[0166] The connection structures (1340) may be, for example, bonding wires that electrically connect the input / output pads (1321) and the package upper pads (1311). Accordingly, in each of the first and second semiconductor packages (1303a, 1303b), the semiconductor chips (1320) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (1311) of the package substrate (1310). According to embodiments, in each of the first and second semiconductor packages (1303a, 1303b), the semiconductor chips (1320) may be electrically connected to each other by through-silicon vias instead of the bonding wire connection structures (1340).

[0167] Unlike what is described, the controller (1302) and the semiconductor chips (1320) may be included in a single package. The controller (1302) and the semiconductor chips (1320) may be mounted on a separate interposer substrate different from the main substrate (1301), and the controller (1302) and the semiconductor chips (1320) may be connected to each other by wiring provided on the interposer substrate.

[0169] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0170] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A step of preparing a semiconductor structure comprising: gate electrodes formed extending in a horizontal direction and stacked while spaced apart from each other in a vertical direction; and vertical channel structures formed extending in the vertical direction through the gate electrodes—each of which includes a vertical channel pattern formed extending in the vertical direction, a data storage pattern formed in contact with the outer wall of the vertical channel pattern, and a back gate formed extending in the vertical direction within the inner space of the vertical channel pattern; a step of recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; and a step of sequentially forming a common source and a separation insulating layer to contact the exposed side of each of the vertical channel structures. A method for manufacturing back gate wiring, comprising the step of forming back gate wiring on vertical channel structures so as to contact the back gate of each of the vertical channel structures, wherein the step of forming the back gate wiring is characterized in that the back gate wiring is formed so as to directly contact the back gate on the plane of the vertical channel structures exposed through the common source and the separation insulation layer, such that the plane of the vertical channel structures is positioned at a height that penetrates the common source and the separation insulation layer, as each of the common source and the separation insulation layer contacts the exposed side of each of the vertical channel structures. Claim 2 A step of preparing a semiconductor structure comprising: sacrificial layers formed extending in a horizontal direction and stacked while spaced apart from each other in a vertical direction; and vertical channel structures formed extending in the vertical direction through the sacrificial layers—each of which includes a vertical channel pattern formed extending in the vertical direction, a data storage pattern formed in contact with the outer wall of the vertical channel pattern, and a back gate formed extending in the vertical direction within the inner space of the vertical channel pattern; a step of recessing the semiconductor structure so that one end of each of the vertical channel structures is exposed on one side of the semiconductor structure; a step of sequentially forming a common source and a separation insulating layer to contact each of the exposed sides of each of the vertical channel structures; and a step of forming back gate wiring on the vertical channel structures to contact the back gate of each of the vertical channel structures. A method for manufacturing back gate wiring, comprising the step of removing the sacrificial layers to form gate electrodes in the spaces where the sacrificial layers have been removed, wherein the step of forming the back gate wiring is characterized by forming the back gate wiring so as to directly contact the back gate on the plane of the vertical channel structures exposed through the common source and the separating insulating layer, such that the common source and the separating insulating layer each contact the exposed side of each of the vertical channel structures, and the plane of the vertical channel structures is located at a height that penetrates the common source and the separating insulating layer. Claim 3 A method for manufacturing a back gate wiring, characterized in that, in either claim 1 or 2, the preparing step is the step of preparing a semiconductor structure in which a capping film is formed in a region corresponding to the back gate among the exposed ends of each of the vertical channel structures. Claim 4 A method for manufacturing a back gate wiring according to claim 3, wherein the capping film is formed of a material or composition different from the common source to prevent the region corresponding to the back gate among the exposed ends of each of the vertical channel structures from being recessed together when a portion of the common source is recessed in the step of sequentially forming the common source and the separating insulating layer. Claim 5 A method for manufacturing back gate wiring according to either claim 1 or 2, wherein the step of sequentially forming the common source and the separating insulating layer comprises: forming the common source to contact the exposed side of the vertical channel pattern in each of the vertical channel structures in response to the recessing of the semiconductor structure in which the region corresponding to the data storage pattern among the exposed ends of each of the vertical channel structures is recessed; recessing the region corresponding to the vertical channel pattern and a part of the common source so that a back gate insulating film interposed between the vertical channel pattern and the back gate is exposed at the exposed ends of each of the vertical channel structures; and forming the separating insulating layer on the common source to contact the exposed side of the back gate insulating film in each of the vertical channel structures. Claim 6 A method for manufacturing a back gate wiring, characterized in that, in either claim 1 or claim 2, the step of forming the back gate wiring comprises one of the steps of: forming the back gate wiring in a plate shape; or forming the back gate wiring in a line shape. Claim 7 A method for manufacturing back gate wiring according to claim 6, wherein the back gate wiring formed in the line shape connects the back gates of each of the vertical channel structures included in the same row or column among the vertical channel structures. Claim 8 A method for manufacturing back gate wiring according to claim 7, wherein the horizontal portion of the back gate wiring formed in the line shape is shared by vertical channel structures included in adjacent rows or columns among the vertical channel structures. Claim 9 A method for manufacturing back gate wiring according to either claim 1 or 2, wherein the step of sequentially forming the common source and the separated insulating layer comprises the step of forming the common source in a plate shape; or the step of forming the common source in a line shape. Claim 10 A method for manufacturing back gate wiring according to claim 9, wherein the common source formed in the line shape connects the vertical channel patterns of each of the vertical channel structures included in the same row or column among the vertical channel structures. Claim 11 A method for manufacturing back gate wiring according to claim 10, wherein the common source formed in the line shape is shared by vertical channel structures included in adjacent rows or columns among the vertical channel structures. Claim 12 A method for manufacturing a back gate wiring according to either claim 1 or 2, wherein the step of sequentially forming the common source and the separating insulating layer includes the step of forming the separating insulating layer on one side of the common source to prevent a short circuit between the common source and the back gate wiring caused by the back gate wiring directly contacting one side of the common source. Claim 13 delete Claim 14 delete

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