Neuromorphic memory element simultaneously implementing volatile and non-volatile feature for emulation of neuron and synapse

Abstract

A neuromorphic memory device according to the present invention may include a first electrode, a second electrode, a first thin film layer disposed adjacent to the first electrode between the first electrode and the second electrode and performing a volatile storage function based on a voltage difference between the first electrode and the second electrode to mimic the plasticity of a neuron, and a second thin film layer disposed between the first thin film layer and the second electrode and performing a non-volatile storage function to mimic the plasticity of a synapse.

Description

Technology Field

[0001] The present invention relates to a neuromorphic memory device, and more specifically, to a neuromorphic memory device that simultaneously implements volatile and non-volatile characteristics for mimicking neurons and synapses. Background Technology

[0002] With the advent of the Big Data era, the demand for the computation, processing, and storage of vast amounts of data is increasing explosively. In computer systems, the traditional Von Neumann architecture separates the Central Processing Unit (CPU), which processes and computes data, from Memory, which stores the completed data. Consequently, bottlenecks and energy consumption arising from the data exchange process between the CPU and Memory—resulting from the increase in data volume in the Big Data era—are emerging as critical issues that must be resolved.

[0003] As a solution to the problems of these existing computer systems, there is a growing movement to implement systems that mimic the human brain, which is called neuromorphic computing. Among neuromorphic computing, deep neural networks, unlike conventional von Neumann computing, require synapses with specific synaptic weights connected in parallel and neurons that pass them to the next synapse. By performing computations based on this, accurate and fast learning and reasoning can be achieved with efficient energy consumption.

[0004] Research on such deep neural networks has mostly been conducted using software to process data. However, to realize true ultra-low-power neuromorphic computing, suitable hardware is indispensable, and it is necessary to secure synapse and neuron devices that are capable of parallel computation and energy efficient from the device stage. The problem to be solved

[0005] The present invention aims to solve the aforementioned problems, and the objective of the present invention is to provide a neuromorphic memory device that simultaneously implements volatile and non-volatile characteristics within a single device for mimicking neurons and synapses. means of solving the problem

[0006] A neuromorphic memory device according to the present invention may include: a first electrode; a second electrode; a first thin film layer disposed adjacent to the first electrode between the first electrode and the second electrode, which performs a volatile storage function based on a voltage difference between the first electrode and the second electrode to mimic the plasticity of a neuron; and a second thin film layer disposed between the first thin film layer and the second electrode, which performs a non-volatile storage function to mimic the plasticity of a synapse.

[0007] In addition, the first thin film layer forms a filament based on the magnitude of the voltage applied between the first electrode and the second electrode, and the second thin film layer can undergo a phase change based on the voltage pulse applied between the first electrode and the second electrode.

[0008] In addition, the first thin film layer can form the filament when the voltage applied between the first electrode and the second electrode becomes higher than the threshold voltage, and can decompose the filament when the voltage applied between the first electrode and the second electrode becomes lower than the threshold voltage.

[0009] Additionally, the second thin film layer may undergo a phase change to a crystalline state when a setting signal having a first size and a first width is applied between the first electrode and the second electrode, and may undergo a phase change to an amorphous state when a reset signal having a second size larger than the first size and a second width smaller than the first width is applied between the first electrode and the second electrode.

[0010] In addition, when a capacitor is connected in parallel to the first electrode and the second electrode, the formation or decomposition rate of the filament may vary based on the phase change state of the second thin film layer.

[0011] In addition, the phase change rate of the second thin film layer may vary depending on whether the filament is formed in the first thin film layer when a capacitor is connected in parallel to the first electrode and the second electrode.

[0012] In addition, if the filament is not formed in the first thin film layer and the first thin film layer is in an amorphous state, the first thin film layer and the second thin film layer may have a first resistance state.

[0013] In addition, if the filament is not formed in the first thin film layer and the first thin film layer is in a crystalline state, the first thin film layer and the second thin film layer may have a second resistance state lower than the first resistance state.

[0014] In addition, if the filament is formed in the first thin film layer and the first thin film layer is in an amorphous state, the first thin film layer and the second thin film layer may have a third resistance state lower than the first resistance state.

[0015] In addition, when the filament is formed in the first thin film layer and the first thin film layer is in a crystalline state, the first thin film layer and the second thin film layer may have a fourth resistance state lower than the second resistance state and the third resistance state.

[0016] A neuromorphic memory device according to the present invention may include: a first electrode; a second electrode; a threshold switching portion stacked on the first electrode and turned on or turned off based on the magnitude of the voltage between the first electrode and the second electrode; and a phase change memory portion stacked between the first electrode and the threshold switching portion and undergoing a phase change based on a voltage pulse applied between the first electrode and the second electrode.

[0017] In addition, the threshold switching portion can be formed as a thin film by doping silver (Ag) into silicon dioxide (SiO2).

[0018] In addition, the threshold switching portion can form a silver filament and lower the resistance when the voltage applied between the first electrode and the second electrode becomes higher than the threshold voltage.

[0019] In addition, the above phase change memory portion may include GST or AIST.

[0020] In addition, the phase change memory portion may undergo a phase change from an amorphous state to a crystalline state based on the voltage pulse, thereby lowering the resistance.

[0021] In addition, the threshold switching portion may have two resistance states based on the magnitude of the voltage between the first electrode and the second electrode, and the phase change memory portion may have two resistance states based on the phase change state.

[0022] In addition, the first electrode may be formed of gold (Au).

[0023] In addition, the second electrode may be formed of a tungsten titanium compound.

[0024] A neuromorphic memory device according to the present invention may include: a first electrode; a second electrode; a threshold switching portion stacked on the first electrode and turned on or turned off based on the magnitude of the voltage between the first electrode and the second electrode; and a resistance change memory portion stacked between the first electrode and the threshold switching portion and having a resistance that changes based on the voltage applied between the first electrode and the second electrode.

[0025] In addition, the threshold switching portion is formed by doping copper (Cu) into an oxide, and the resistance change memory portion may include a ferroelectric tunnel junction (FTJ) device or a magnetic random access memory (MRAM) using a ferroelectric material. Effects of the invention

[0026] According to the present invention, volatile and non-volatile characteristics can be simultaneously realized within a single neuromorphic memory device, thereby simultaneously mimicking neuronal plasticity and synaptic plasticity. Brief explanation of the drawing

[0027] FIG. 1 is a drawing showing a neuromorphic memory device according to one embodiment. Figure 2 is a three-dimensional diagram showing the neuromorphic memory device of Figure 1. FIG. 3 is a diagram comparing the operation of a neuron of a brain cell according to one embodiment with the operation of the first thin film layer of FIG. 1. FIG. 4 is a diagram comparing the operation of a synapse of a brain cell according to one embodiment with the operation of the second thin film layer of FIG. 1. Figure 5 is a graph showing the voltage and current (or resistance state) between the first electrode and the second electrode according to the state change of the first thin film layer of Figure 1. Figure 6 is a graph showing the voltage and current (or resistance state) between the first electrode and the second electrode according to the state change of the second thin film layer of Figure 1. Figure 7 is a graph showing the resistance state of the neuromorphic memory device of Figure 1. Figure 8 is a diagram showing the states of the neuromorphic memory device of Figure 1 corresponding to the graph of Figure 7. FIG. 9 is a diagram showing a circuit including the neuromorphic memory element of FIG. 1 for verifying the characteristic simulation of a neuron. Figure 10 shows graphs representing the simulation of neuron characteristics identified by the circuit of Figure 9. FIG. 11 is a diagram illustrating the learning process of a general spiking neural network (SNN) according to one embodiment. FIG. 12 is a diagram showing the learning process of a neuromorphic memory array composed of the neuromorphic memory elements of FIG. 1. FIG. 13 is a diagram showing the fabrication process of the neuromorphic memory device of FIG. 1. Specific details for implementing the invention

[0028] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0029] FIG. 1 is a drawing showing a neuromorphic memory device according to one embodiment. Referring to FIG. 1, the neuromorphic memory device (100) may include a first electrode (110), a first thin film layer (120), a second thin film layer (130), and a second electrode (140).

[0030] According to one embodiment, the first electrode (110), the first thin film layer (120), the second thin film layer (130), and the second electrode (140) may be formed by stacking. For example, the first thin film layer (120) and the second thin film layer (130) may be stacked between the first electrode (110) and the second electrode (140). The first thin film layer (120) may be stacked between the first electrode (110) and the second thin film layer (130) so as to be adjacent to the first electrode (110). The second thin film layer (130) may be stacked between the first thin film layer (120) and the second electrode (140) so as to be adjacent to the second electrode (140).

[0031] According to one embodiment, the first thin film layer (120) may be formed to mimic the plasticity of neurons among human brain cells. For example, the first thin film layer (120) may form a filament between the second thin film layer (130) and the first electrode (110) depending on the voltage between the first electrode (110) and the second electrode (140). If no voltage is applied between the first electrode (110) and the second electrode (140), the first thin film layer (120) may have an initial state in which no filament is formed. If a voltage exceeding a specified voltage (e.g., threshold voltage) is applied between the first electrode (110) and the second electrode (140), the first thin film layer (120) may form a filament. When a voltage lower than a specified voltage is applied between the first electrode (110) and the second electrode (140), the filaments of the first thin film layer (120) can return to their initial state. Accordingly, the first thin film layer (120) has the characteristics of a volatile memory and can operate as a threshold switch that turns on or off depending on the threshold voltage. Additionally, the strength of the filaments of the first thin film layer (120) can vary based on the frequency of voltage application between the first electrode (110) and the second electrode (140). The filaments of the first thin film layer (120) can form more quickly if a voltage higher than the threshold voltage has previously been applied between the first electrode (110) and the second electrode (140). Thus, the first thin film layer (120) can mimic the plasticity of a neuron that performs interval jumps according to excitation.

[0032] According to one embodiment, the second thin film layer (130) may be formed to mimic the plasticity of synapses among human brain cells. For example, the second thin film layer (130) may include a phase change material. The second thin film layer (130) may be heated by a voltage pulse transmitted through a filament of the first thin film layer (120) and undergo a phase change between amorphous and crystalline. Accordingly, the resistance of the second thin film layer (130) may increase or decrease due to the phase change, and may mimic a change in the connection strength of synapses based on the increase or decrease in resistance.

[0033] FIG. 2 is a three-dimensional drawing of the neuromorphic memory device of FIG. 1. Referring to FIG. 2, the neuromorphic memory device (100) may include a first electrode (110), a first thin film layer (120), a second thin film layer (130), and a second electrode (140).

[0034] According to one embodiment, the first electrode (110) may be composed of a metal material on which the first thin film layer (120) can be deposited. For example, the first electrode (110) may be composed of gold (Au). For example, the first electrode (110) may be formed with a thickness of 35 to 45 nm.

[0035] According to one embodiment, the first thin film layer (120) may include a threshold switching element. For example, the first thin film layer (120) may be composed of an electrochemical metallization-based volatile memristor element. The first thin film layer (120) may be formed by doping silver (Ag) into a silicon dioxide (SiO2) matrix (e.g., Ag:SiO2). For example, the first thin film layer (120) may include a source layer (121) and a doping layer (122). The source layer (121) may allow the doping layer (122) to adhere well to the first electrode (110). The source layer (121) may be formed with a thickness of 1 to 10 nm. Alternatively, the source layer (121) may be formed with a thickness of 10 to 100 nm when used as an electrode. The doping layer (122) may be formed with a thickness of 5 to 50 nm. The doping layer (122) may contain silver (Ag) in a ratio of 5 to 30%. The ratio of silver (Ag) in the doping layer (122) may be adjusted according to the thickness of the doping layer (122) or voltage conditions used, etc.

[0036] According to one embodiment, the first thin film layer (120) may be formed by doping various oxides. For example, the oxide of the first thin film layer (120) may include HfO2, MgO2, or WO3. The first thin film layer (120) may be formed by doping copper (Cu) into the oxide.

[0037] According to one embodiment, the first thin film layer (120) can perform a threshold switching operation. For example, the first thin film layer (120) can form a filament (123) based on the voltage between the first electrode (110) and the second electrode (140). The filament (123) can be formed when the voltage between the first electrode (110) and the second electrode (140) exceeds a threshold voltage. When the voltage between the first electrode (110) and the second electrode (140) drops below the threshold voltage, the filament (123) can return to a molecular state. Thus, the first thin film layer (120) can operate as a volatile memory. The time for the filament (123) to be formed can be shortened as the number of times the voltage between the first electrode (110) and the second electrode (140) exceeds the threshold voltage increases.

[0038] According to one embodiment, the second thin film layer (130) may include a phase change memory element. For example, the second thin film layer (130) may be composed of a GST (Ge, Sb, Te) phase change material. Ge, Sb, and Te included in the second thin film layer (130) may be composed in various ratios. Alternatively, the second thin film layer (130) may include a phase change memory such as AIST (Ag, In, Sb, Te), etc. Ag, In, Sb, and Te included in the second thin film layer (130) may be composed in various ratios.

[0039] According to one embodiment, the second thin film layer (130) may include various non-volatile memristor devices. For example, the second thin film layer (130) may include a resistance change memory, a ferroelectric tunnel junction (FTJ) device using a ferroelectric material, or a magnetic random access memory (MRAM).

[0040] According to one embodiment, the phase change of the second thin film layer (130) can be achieved by heating through an electrical pulse between the first electrode (110) and the second electrode (140). For example, the second thin film layer (130) can be heated by a voltage pulse transmitted through the filament (123) of the first thin film layer (120) to undergo a phase change between amorphous and crystalline. Accordingly, the resistance of the second thin film layer (130) can increase or decrease due to the phase change, and can simulate a change in the connection strength of a synapse based on the increase or decrease in resistance.

[0041] According to one embodiment, the second electrode (140) may be composed of a metal material that can be deposited on the second thin film layer (130). For example, the second electrode (140) may include a tungsten titanium compound (e.g., TiW). For example, the second electrode (140) may be formed with a thickness of 35 to 45 nm.

[0042] FIG. 3 is a diagram comparing the operation of a neuron of a brain cell according to one embodiment with the operation of the first thin film layer of FIG. 1. Referring to FIG. 3, the first operation (11) and the second operation (12) may represent the operation of a neuron (1201) contained in a human brain cell. The third operation (21) and the fourth operation (22) may represent the operation of the first thin film layer (120) of FIG. 1.

[0043] According to one embodiment, when a random stimulus is input, the neuron (1201) can perform a first action (11) according to intrinsic excitability. When the same stimulus is repeated, the neuron (1201) can perform a second action (12) according to potentialiation of excitability. That is, when the same stimulus is repeated, the nerve transmission speed of the neuron (1201) can be increased.

[0044] According to one embodiment, in a first state (120A) (e.g., initial state) where the voltage (V) between the first electrode (110) and the second electrode (140) is lower than the threshold voltage (Vth), the first thin film layer (120) may not form a filament (123). In a second state (120B) where the voltage (V) between the first electrode (110) and the second electrode (140) is higher than the threshold voltage (Vth), the first thin film layer (120) may form a filament (123) (or silver filament). When the voltage (V) between the first electrode (110) and the second electrode (140) becomes lower than the threshold voltage (Vth) and returns to the first state (120A), the filament (123) of the first thin film layer (120) may be separated again.

[0045] According to one embodiment, when a neuromorphic memory element (100) and a capacitor are connected in parallel, the first thin film layer (120) may exhibit a third operation (21) and a fourth operation (22). For example, in a random state where the voltage (V) between the first electrode (110) and the second electrode (140) is maintained at a first state (120A) that is lower than the threshold voltage (Vth) for a certain period of time, when the voltage (V) between the first electrode (110) and the second electrode (140) becomes higher than the threshold voltage (Vth), the first thin film layer (120) may exhibit a tonic busting operation such as the third operation (21). The third operation (21) of the first thin film layer (120) may correspond to the first operation (11) of the neuron (1201). When a second state (120B) in which the voltage (V) between the first electrode (110) and the second electrode (140) becomes higher than the threshold voltage (Vth) is repeated, the first thin film layer (120) may exhibit a tonic spiking action as in the fourth action (22). The fourth action (24) of the first thin film layer (120) may correspond to the second action (12) of the neuron (1201). Thus, the first thin film layer (120) can mimic the plasticity of a human neuron.

[0046] FIG. 4 is a diagram comparing the operation of a synapse of a brain cell according to one embodiment with the operation of the second thin film layer of FIG. 1. Referring to FIG. 4, the first operation (31) may represent the operation between synapses (1301, 1302) contained in a human brain cell. The second operation (32) may represent the operation of the second thin film layer (130) of FIG. 1. A synapse is an information transmission terminal between nerve cells. It is a site of interaction between the intracellular molecular network and the layer known as the nerve cell network. Plastic changes in synaptic transmission efficiency are the substance of information processing in the brain. Ca ions, which are major intracellular information carriers, play an important role in synaptic plasticity, and synaptic transmission efficiency can ultimately be adjusted by controlling the electrochemical properties of neurotransmitter receptor molecules, the number of molecules, or the release mechanism of neurotransmitters.

[0047] Synaptic plasticity refers to the dynamic control and change in the transmission efficiency of chemical signals at synapses, and it is the most fundamental function for realizing information processing in the brain. Neurotransmitters are dynamically regulated at release mechanisms and receptors. Synaptic transmission efficiency consists of two factors: changes in the number of synaptic sites and changes in miniature synaptic currents (mPSCs) at a single synaptic site. If the number of synaptic sites connected to the axon increases, the amplitude of the induced postsynaptic current, which is generated by stimulating the presynaptic cell, increases proportionally to the increase in synaptic sites. Micropostsynaptic currents are typically interpreted to predict the behavior of these factors. When an action potential inhibitor is added to an extracellular recording solution, the induced postsynaptic current disappears due to presynaptic firing, and a micropostsynaptic current (approximately tens of pA) is observed. It is presumed that the change in the amplitude of micropostsynaptic currents due to plastic changes indicates a change in sensitivity to glutamate at a single synaptic site. Conversely, changes in the frequency of microsynaptic postsynaptic currents are thought to indicate changes in the number of synaptic sites or an increase in the probability of neurotransmitter release. However, in reality, detailed interpretation is difficult using this method alone because it requires assumptions regarding various parameters. Synaptic plasticity includes short-term potentiation (STP), short-term depression (STD), long-term potentiation (LTP), and long-term depression (LTD).

[0048] According to one embodiment, two adjacent synapses (e.g., a first synapse (1301) and a second synapse (1302)) may be connected via a neurotransmitter (1303). For example, a neurotransmitter (1303) may be released from the terminal of the first synapse (1301), and a receptor at the second synapse (1302) may receive the neurotransmitter (1303), thereby transmitting a signal between the two synapses. The strength of the connection between the two synapses may be determined by the concentration of the neurotransmitter (1303). The strength of the connection between the two synapses may appear as in the first operation (31) depending on the concentration of the neurotransmitter (1303).

[0049] According to one embodiment, the connection strength of the second thin film layer (130) can be determined based on the phase change state of the second thin film layer (130). For example, the phase change state of the second thin film layer (130) can be determined based on a pulse signal input between the first electrode (110) and the second electrode (140). When a setting signal (SET) with a small voltage magnitude and large amplitude is input between the first electrode (110) and the second electrode (140), the second thin film layer (130) can undergo a phase change from an amorphous state (130A) to a crystalline state (130B). When a reset signal (RESET) with a large voltage magnitude and small amplitude is input between the first electrode (110) and the second electrode (140), the second thin film layer (130) can undergo a phase change from a crystalline state (130B) to an amorphous state (130A). The second operation (32) of the second thin film layer (130) may exhibit a similar aspect to the first operation (31) of the synapses (1301, 1302). Thus, the second thin film layer (130) can mimic the plasticity of human synapses.

[0050] According to one embodiment, the second thin film layer (130) can mimic the spike-timing-dependent plasticity (STDP), which is a representative long-term plasticity of a synapse. The second thin film layer (130) can implement the symmetric Hebbian learning rule among STDPs. The second thin film layer (130) can mimic the paired-pulse facilitation (PPF), which is a representative short-term plasticity of a synapse.

[0051] FIG. 5 is a graph showing the voltage and current (or resistance state) between the first electrode and the second electrode according to the state change of the first thin film layer of FIG. 1. Referring to FIG. 1 to FIG. 5, the formation of a filament in the first thin film layer (120) can be determined according to the voltage between the first electrode (110) and the second electrode (140).

[0052] According to one embodiment, in the first section (41), the voltage (V) between the first electrode (110) and the second electrode (140) is lower than the threshold voltage (Vth), and while the voltage (V) between the first electrode (110) and the second electrode (140) increases, the current between the first electrode (110) and the second electrode (140) hardly increases, and the first thin film layer (120) can maintain a first state (120A) (e.g., initial state). In the second section (42), the voltage (V) between the first electrode (110) and the second electrode (140) exceeds a threshold voltage (Vth) (e.g., V1), and even if the voltage (V) between the first electrode (110) and the second electrode (140) increases only slightly, the current between the first electrode (110) and the second electrode (140) increases significantly, and the first thin film layer (120) can form a filament (123) and transition to the second state (120B). In the third section (43), while the voltage (V) between the first electrode (110) and the second electrode (140) increases, the current between the first electrode (110) and the second electrode (140) does not increase again, and the first thin film layer (120) can maintain the second state (120B).

[0053] According to one embodiment, in the fourth section (44), while the voltage (V) between the first electrode (110) and the second electrode (140) decreases, the current between the first electrode (110) and the second electrode (140) hardly decreases, and the first thin film layer (120) can maintain the second state (120B). In the fifth section (45), while the voltage (V) between the first electrode (110) and the second electrode (140) decreases, the current between the first electrode (110) and the second electrode (140) decreases rapidly, and the first thin film layer (120) switches to the first state (120A), and the filament (123) can be decomposed. Depending on the increase or decrease in the voltage (V) between the first electrode (110) and the second electrode (140), the voltage and current of the first thin film layer (120) change as shown in the graph of FIG. 5, and accordingly, the first thin film layer (120) can repeatedly switch between the first state (120A) and the second state (120B). Thus, the first thin film layer (120) can operate like a volatile memory based on the voltage (V) between the first electrode (110) and the second electrode (140).

[0054] FIG. 6 is a graph showing the voltage and current (or resistance state) between the first electrode and the second electrode according to the state change of the second thin film layer of FIG. 1. Referring to FIG. 1 to 4 and FIG. 6, the phase change state of the second thin film layer (130) can be determined according to the voltage pulse applied between the first electrode (110) and the second electrode (140).

[0055] According to one embodiment, in the first section (51), the second thin film layer (130) may have an amorphous state (130A). In the first section (51), the second thin film layer (130) may have a high resistance value. In the second section (52), when a set signal (SET) is applied between the first electrode (110) and the second electrode (140), the second thin film layer (130) may be switched to a crystalline state (130B). In the second section (52) and the third section (53), even if the voltage (V) between the first electrode (110) and the second electrode (140) increases only slightly, the current between the first electrode (110) and the second electrode (140) increases significantly and can follow the voltage and current graph of the crystalline state (130B).

[0056] According to one embodiment, in the fourth section (54), the voltage and current of the second thin film layer (130) may move along the graph of the voltage and current of the crystalline state (130B). The resistance of the second thin film layer (130) in the crystalline state (130B) may be lower than the resistance of the second thin film layer (130) in the amorphous state (130A). Thus, in the crystalline state (130B), the voltage and current of the second thin film layer (130) may move along a one-dimensional straight line graph. Thus, the resistance of the second thin film layer (130) changes similarly to the operation of synapses (1301, 1302) according to the phase change state (e.g., amorphous state (130A) and crystalline state (130B)), and the second thin film layer (130) can mimic the plasticity of the synapses.

[0057] FIG. 7 is a graph showing the resistance state of the neuromorphic memory device of FIG. 1. FIG. 8 is a diagram showing the states of the neuromorphic memory device of FIG. 1 corresponding to the graph of FIG. 7. Referring to FIG. 7 and FIG. 8, the neuromorphic memory device (100) may have four resistance states (61, 62, 63, 64). In FIG. 7, the resistance state of the neuromorphic memory device (100) may show a form in which the resistance state of the first thin film layer (120) of FIG. 5 and the resistance state of the second thin film layer (130) of FIG. 6 interact in a complex manner. In FIG. 8, the neuromorphic memory device (100) can exhibit four physical state properties (e.g., first physical state (71), second physical state (72), third physical state (73) and fourth physical state (74)) depending on whether the first thin film layer (120) or the second thin film layer (130) is on or off.

[0058] According to one embodiment, in the first resistance state (61), the first thin film layer (120) may be in an off state (e.g., a first state (120A) in which no filament is formed), and the second thin film layer (130) may also be in an off state (e.g., an amorphous state (130A)). In the first resistance state (61), the neuromorphic memory device (100) may have a first physical state (71). In the second resistance state (62), the first thin film layer (120) may be in an on state (e.g., a second state (120B) in which a filament is formed), and the second thin film layer (130) may be in an off state. In the second resistance state (62), the neuromorphic memory device (100) may have a second physical state (72). In the third resistance state (63), the first thin film layer (120) may be in an off state, and the second thin film layer (130) may be in an on state (e.g., a crystalline state (130B)). In the third resistance state (63), the neuromorphic memory device (100) may have a third physical state (73). In the fourth resistance state (64), the first thin film layer (120) may be in an on state, and the second thin film layer (130) may also be in an on state. In the fourth resistance state (64), the neuromorphic memory device (100) may have a fourth physical state (74).

[0059] According to one embodiment, the neuromorphic memory device (100) can simultaneously (or in combination) implement a volatile resistance change of the first thin film layer (120) and a non-volatile resistance change of the second thin film layer (130). For example, the first thin film layer (120) may have two resistance states depending on whether a filament is formed. Additionally, the second thin film layer (130) may have two resistance states depending on whether a phase change occurs. Thus, the neuromorphic memory device (100) may have four resistance states. The first resistance state (61) may have the highest resistance because both the first thin film layer (120) and the second thin film layer (130) are in an off state (e.g., the first physical state (71)). The fourth resistance state (64) may have the lowest resistance because both the first thin film layer (120) and the second thin film layer (130) are in an on state (e.g., the fourth physical state (74)). The second resistance state (62) and the third resistance state (63) may have a resistance between the first resistance state (61) and the fourth resistance state (64). Since the second resistance state (62) is in the off state, the first resistance state (120) may have a higher resistance than the fourth resistance state (64) even if the second resistance state (62) is in the on state (e.g., second physical state (72)). Since the first resistance state (120) is in the off state even if the second resistance state (130) is in the on state, the third resistance state (63) may have a higher resistance than the fourth resistance state (64) even if the second resistance state (130) is in the on state (e.g., third physical state (73)).

[0060] As described above, even if the same voltage is applied between the first electrode (110) and the second electrode (140) of the neuromorphic memory device (100), the resistance state can be determined differently depending on the phase change state of the second thin film layer (130). In addition, since the operation of the first thin film layer (120) is maintained according to the magnitude of the voltage applied between the first electrode (110) and the second electrode (140), the neuromorphic memory device (100) can simultaneously implement volatile and non-volatile resistance changes in a single device. Accordingly, the neuromorphic memory device (100) can simultaneously mimic the characteristics of neurons and synapses.

[0061] FIG. 9 is a diagram showing a circuit including the neuromorphic memory element of FIG. 1 for verifying the characteristic simulation of a neuron. FIG. 10 is a graph showing the characteristic simulation of a neuron verified by the circuit of FIG. 9. Referring to FIG. 9 and FIG. 10, the neuromorphic memory element (100) can be connected in parallel between a capacitor (C1), a first node (n1), and a second node (n2).

[0062] According to one embodiment, an input current (Iin) is applied between a first node (n1) and a second node (n2), and an output voltage (Vout) between the two ends of the neuromorphic memory device (100) (e.g., the first node (n1) and the second node (n2)) can be measured. Through this output voltage (Vout), it can be confirmed that the neuromorphic memory device (100) mimics the firing and plasticity of a neuron. Referring to the first graph (81), the neuromorphic memory device (100) can mimic the tonic spiking characteristics of a neuron. Referring to the second graph (82), the neuromorphic memory device (100) can mimic the tonic bursting characteristics of a neuron. Referring to the third graph (83), the frequency of the neuromorphic memory device (100) can change according to the change in capacitance.

[0063] According to one embodiment, an input voltage (Vin) is applied between the first node (n1) and the second node (n2), and an output current (Iout) flowing between the two ends of the neuromorphic memory device (100) (e.g., the first node (n1) and the second node (n2)) can be measured. Referring to the fourth graph (84) and the fifth graph (85), the neuromorphic memory device (100) can simulate the integrator of the LIF (leaky-integrate and fire) model, which is a representative model of a neuron. Referring to the sixth graph (86), the neuromorphic memory device (100) can simulate the behavior according to the all-or-nothing principle of a neuron (e.g., all-or-nothing firing).

[0064] FIG. 11 is a diagram illustrating the learning process of a general spiking neural network (SNN) according to one embodiment. FIG. 12 is a diagram illustrating the learning process of a neuromorphic memory array composed of the neuromorphic memory elements of FIG. 1. Referring to FIG. 11, the spiking neural network (1100) may include a hidden memory (1110) and a synaptic memory (1120). The hidden memory (1110) may simulate the plasticity of a neuron, and the synaptic memory (1120) may simulate the plasticity of a synapse. When the hidden memory (1110) receives an input value (I(t)), it simulates the firing of a neuron and transmits it to the synaptic memory (1120), the synaptic memory (1120) outputs an output value (O(t)), and the synaptic memory (1120) may send feedback to the hidden memory (1110). Through this process, the spiking neural network (1100) can form a learning loop such as synaptic strengthening, increased likelihood of neuron firing, and re-strengthening of synapses due to neuron firing. Synaptic memory (1120) learns slowly during naive training, and then learns faster during retraining after a specified time has elapsed (e.g., forget time). This may be similar to the learning pattern of human brain cells.

[0065] Referring to FIG. 12, a neuromorphic memory device (100) can implement a spiking neural network (1100) in a single device. For example, a neuromorphic memory array (1200) can be formed by configuring a plurality of neuromorphic memory devices (100) into an array. In FIG. 12, as an example, the neuromorphic memory array (1200) may include neuromorphic memory devices (100) arranged in a 4x4 array.

[0066] According to one embodiment, the first learning result (91) and the second learning result (92) are the results of learning by inputting a learning pattern (90) into a neuromorphic memory array (1200). The first learning result (91) is the result of learning through naive learning. The second learning result (92) is the result of learning through re-learning. It can be seen that the neuromorphic memory array (1200) shows an improved learning speed during re-learning compared to naive learning, such as with a spiking neural network (1100).

[0067] FIG. 13 is a diagram showing the fabrication process of the neuromorphic memory device of FIG. 1. Referring to FIG. 13, the neuromorphic memory device (100) may have a two-terminal memristor crossbar structure.

[0068] According to one embodiment, the neuromorphic memory device (100) may have a combined form in which a volatile first thin film layer (120) and a non-volatile second thin film layer (130) are stacked without an intermediate electrode. For example, the first electrode (110) may be formed in a bar shape on a silicon substrate (101). The first electrode (110) may be formed of gold (Au) using e-beam lithography (EBL). Alternatively, the first electrode (110) may be formed by stacking gold (Au) and titanium (Ti). A first contact pad (110_1) may be formed at both ends of the first electrode (110). The first electrode pad (110_1) may be formed through photolithography. The first thin film layer (120) may be formed on the first electrode (110). The first thin film layer (120) can be formed by co-sputtering a silver (Ag) target and a silicon dioxide (SiO2) target to form a silicon dioxide thin film (Ag:SiO2) doped with silver (Ag). The second thin film layer (130) can be formed on the first thin film layer (120). The second thin film layer (130) can be formed by depositing GST using e-beam lithography (EBL). The second thin film layer (130) can be formed in a crossbar shape with respect to the first electrode (110). The second electrode (140) can be formed on the second thin film layer (130). The second electrode (140) can be formed by depositing a tungsten titanium compound (TiW) using e-beam lithography (EBL).

[0069] According to one embodiment, the neuromorphic memory device (100) can be formed with a size of several hundred nm or less. For example, the width of the first electrode (110) and the second electrode (140) can be determined according to conditions for the filament to be repeatedly formed in the first thin film layer (120). Additionally, the width of the first electrode (110) and the second electrode (140) can be determined based on the size of the region where the second thin film layer (130) undergoes a phase change through the filament of the first thin film layer (120). For example, the width of the first electrode (110) and the second electrode (140) can be formed with a size of 100 nm or less.

[0070] According to one embodiment, the thickness of each thin film of the neuromorphic memory device (100) may have little effect on the device characteristics. However, the thickness of the neuromorphic memory device (100) may be determined by considering external stress on the neuromorphic memory device (100). For example, the thickness of the first electrode (110) and the second electrode (140) may be formed to be 35 to 45 nm. The thickness of the source layer (e.g., source layer (121)) of the first thin film layer (120) may be formed to be 1 to 10 nm. Alternatively, the thickness of the source layer of the first thin film layer (120) may be formed to be 10 to 100 nm when the source layer is used as an electrode. The thickness of the doping layer (e.g., doping layer (122)) of the first thin film layer (120) may be formed to be 5 to 50 nm. The thickness of the second thin film layer (130) can be formed to be 5 to 200 nm.

[0071] The above description describes specific embodiments for implementing the present invention. In addition to the embodiments described above, the present invention may also include embodiments that can be simply modified or easily modified. Furthermore, the present invention may also include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of the present invention.

Claims

Claim 1 A neuromorphic memory device comprising: a first electrode; a second electrode; a first thin film layer disposed adjacent to the first electrode between the first electrode and the second electrode, and performing a volatile storage function based on a voltage difference between the first electrode and the second electrode to mimic the plasticity of a neuron; and a second thin film layer disposed between the first thin film layer and the second electrode, and performing a non-volatile storage function to mimic the plasticity of a synapse, wherein the first thin film layer forms or decomposes a filament based on the magnitude of a first voltage applied between the first electrode and the second electrode, and the strength of the filament changes based on the frequency in which a voltage greater than or equal to a threshold voltage is applied as the first voltage. Claim 2 In claim 1, when a voltage greater than or equal to the threshold voltage is applied as the first voltage after the filament has previously been formed and decomposed, the formation time of the filament is shortened, and the second thin film layer undergoes a phase change based on a voltage pulse applied between the first electrode and the second electrode, in a neuromorphic memory device. Claim 3 A neuromorphic memory device according to claim 1, wherein the first thin film layer forms the filament when the first voltage becomes higher than the threshold voltage and decomposes the filament when the first voltage becomes lower than the threshold voltage. Claim 4 A neuromorphic memory device according to claim 2, wherein the second thin film layer undergoes a phase change to a crystalline state when a setting signal having a first size and a first width is applied between the first electrode and the second electrode, and undergoes a phase change to an amorphous state when a reset signal having a second size larger than the first size and a second width smaller than the first width is applied between the first electrode and the second electrode. Claim 5 In paragraph 2, the first thin film layer is a neuromorphic memory device in which the formation or decomposition rate of the filament changes based on the phase change state of the second thin film layer when a capacitor is connected in parallel to the first electrode and the second electrode. Claim 6 In paragraph 2, the second thin film layer is a neuromorphic memory device in which the phase change rate varies based on whether the filament of the first thin film layer is formed when a capacitor is connected in parallel to the first electrode and the second electrode. Claim 7 In paragraph 2, a neuromorphic memory device in which the filament is not formed in the first thin film layer and the first thin film layer is in an amorphous state, and the first thin film layer and the second thin film layer have a first resistance state. Claim 8 In claim 7, a neuromorphic memory device in which, when the filament is not formed in the first thin film layer and the first thin film layer is in a crystalline state, the first thin film layer and the second thin film layer have a second resistance state lower than the first resistance state. Claim 9 In claim 8, a neuromorphic memory device wherein the filament is formed in the first thin film layer and the first thin film layer is in an amorphous state, and the first thin film layer and the second thin film layer have a third resistance state lower than the first resistance state. Claim 10 In claim 9, a neuromorphic memory device wherein the filament is formed in the first thin film layer and the first thin film layer is in a crystalline state, and the first thin film layer and the second thin film layer have a fourth resistance state lower than the second resistance state and the third resistance state.

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