Semiconductor device

Abstract

A semiconductor device according to one embodiment of the present invention comprises a PMOS transistor having a resistor element connected to a first power node that supplies a first power supply voltage, a gate terminal connected to a second power node that supplies a second power supply voltage smaller than the first power supply voltage, a source terminal connected to the resistor element, and a drain terminal that outputs a first current, and a diode-connected transistor, and a first NMOS transistor connected between the drain terminal of the PMOS transistor and the second power node.

Description

Technology Field

[0001] The present invention relates to a semiconductor device comprising a current source capable of supplying a constant current regardless of temperature change. Background Technology

[0003] Semiconductor devices capable of storing data are applied as data storage spaces in computers, smartphones, tablet PCs, and various other electronic devices. Semiconductor devices may include a current source that supplies the current required for operation, and the current output by this source can be affected by internal and external factors. For example, the current output by the source can be significantly affected by temperature, and consequently, the performance of the semiconductor device may vary depending on the temperature. To maintain consistent performance of the semiconductor device, it is necessary to supply a constant current that does not change with temperature. The problem to be solved

[0005] One of the objectives of the technical concept of the present invention is to increase the integration density and improve the performance of semiconductor devices by implementing a current source capable of outputting a constant current despite temperature changes without a bandgap reference. means of solving the problem

[0007] A semiconductor device according to one embodiment of the present invention comprises a PMOS transistor having a resistor element connected to a first power node that supplies a first power supply voltage, a gate terminal connected to a second power node that supplies a second power supply voltage smaller than the first power supply voltage, a source terminal connected to the resistor element, and a drain terminal that outputs a first current, and a diode-connected transistor, and a first NMOS transistor connected between the drain terminal of the PMOS transistor and the second power node.

[0009] A semiconductor device according to one embodiment of the present invention includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which peripheral circuits for driving the cell region are arranged, wherein the peripheral circuit region includes a current source, wherein the current source includes a resistor element, a PMOS transistor, and a first NMOS transistor connected by a diode, wherein the control terminal of the PMOS transistor receives a ground voltage, the input terminal of the PMOS transistor receives a power supply voltage greater than the ground voltage through the resistor element, and the output terminal of the PMOS transistor outputs current to the first NMOS transistor.

[0011] A semiconductor device according to one embodiment of the present invention includes a current source that outputs a constant current that does not change with temperature and a temperature sensor that detects the temperature using the constant current, wherein the current source includes a resistor element having a resistance value proportional to the temperature, a PMOS transistor having a threshold voltage inversely proportional to the temperature and connected to an equipotential terminal to which a control terminal supplies a ground voltage, and a current mirror circuit that mirrors the current of the PMOS transistor, and the temperature sensor detects the temperature based on the constant current output by the current source. Effects of the invention

[0013] According to one embodiment of the present invention, by inputting a ground voltage to the control terminal of a PMOS transistor, a current source that outputs a constant current despite temperature changes can be provided without a bandgap reference circuit. Therefore, since the bandgap reference circuit can be omitted, the integration density of the semiconductor device can be improved, and at the same time, the performance of the semiconductor device can be improved by implementing a current source that outputs a constant current despite temperature changes.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention. FIG. 2 is a graph provided to explain the operation of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a diagram briefly illustrating a part of the configuration of a circuit included in a semiconductor device according to one embodiment of the present invention. FIG. 4 is a diagram briefly illustrating a part of the configuration of a circuit included in a semiconductor device according to one embodiment of the present invention. FIG. 5 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention. FIG. 6 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention. FIG. 7 is a graph provided to explain the operation of a semiconductor device according to one embodiment of the present invention. FIG. 8 is a simplified block diagram of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a simplified diagram showing a semiconductor package including a semiconductor device according to one embodiment of the present invention. FIG. 10 is a simplified diagram showing a storage device including a semiconductor device according to one embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings.

[0019] FIG. 1 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention.

[0020] Referring to FIG. 1, a semiconductor device (1) according to one embodiment of the present invention may include a resistor element (R), a PMOS transistor (MP), a diode-connected first NMOS transistor (MN2), and a second NMOS transistor (MN2), etc.

[0021] One end of the resistor element (R) can be connected to a first power node that supplies a first power supply voltage (VCC). The other end of the resistor element (R) can be connected to one end of a PMOS transistor (MP). The gate terminal of the PMOS transistor (MP) can be connected to a second power node that supplies a second power supply voltage (GND). The magnitude of the second power supply voltage (GND) may be smaller than the magnitude of the first power supply voltage (VCC).

[0022] In one embodiment, the second power supply voltage (GND) may be a power supply voltage. By the second power supply voltage (GND) input to the gate terminal of the PMOS transistor (MP), the gate voltage of the PMOS transistor (MP) can be maintained at a state lower than the source voltage. Accordingly, the PMOS transistor (MP) can be maintained in a turn-on state.

[0023] The other end of the PMOS transistor (MP) can be connected to one end of the first NMOS transistor (MN1) and can output a first current (I1) that is substantially unchanged regardless of temperature change. For example, one end of the PMOS transistor (MP) may be a source terminal and the other end may be a drain terminal.

[0024] The performance of the semiconductor device (1) may be affected by internal and external factors, and may be particularly affected by temperature. For example, the resistance values ​​of the resistor elements included in the semiconductor device (1) may increase as the temperature increases, and the threshold voltage of the transistors may decrease as the temperature increases. Therefore, the current output by the current source included in the semiconductor device may change due to temperature changes, and the characteristics of the circuit that operates by receiving current from the current source may change along with the temperature.

[0025] For example, the current output from a current source can be input to a current-controlled oscillator. The current-controlled oscillator can output a clock signal determined by the current received from the current source. Therefore, if the current output from the current source changes due to temperature variations, the frequency of the clock signal output by the current-controlled oscillator may change unintentionally, which can lead to changes in the performance and / or power consumption of the semiconductor device. To address this issue, it is necessary to implement a current source capable of outputting a practically constant current regardless of temperature variations.

[0026] According to one embodiment of the present invention illustrated in FIG. 1, the resistance value of a resistor element (R) can increase in proportion to temperature, whereas the threshold voltage of a PMOS transistor (MP) can decrease as the temperature increases. In other words, the resistance value of the resistor element (R) can have a positive temperature coefficient (NTC), and the threshold voltage of the PMOS transistor (MP) can have a negative temperature coefficient (NTC).

[0027] In summary, as the temperature increases, the resistance value of the resistor element (R) increases and the threshold voltage of the PMOS transistor (MP) may decrease, and as the temperature decreases, the resistance value of the resistor element (R) decreases and the threshold voltage of the PMOS transistor (MP) may increase.

[0028] A first current (I1) may flow through the resistor element (R), and as previously explained, a first power node supplying a first power supply voltage (VCC) may be connected to one end of the resistor element (R). Accordingly, the voltage at the other end of the resistor element (R) can be defined as [VCC - I1 * R]. In the above equation, VCC may be the magnitude of the first power supply voltage (VCC), and I1 may be the magnitude of the first current (I1). R may be the resistance value of the resistor element (R).

[0029] Since the resistance value of the resistor element (R) changes in proportion to temperature, the voltage at the other end of the resistor element (R) may decrease as the temperature increases. Conversely, the voltage at the other end of the resistor element (R) may increase as the temperature decreases.

[0030] Meanwhile, a second power node supplying a second power voltage (GND) can be connected to the gate terminal of the PMOS transistor (MP). Accordingly, a constant second power voltage (GND) is supplied to the gate terminal of the PMOS transistor (MP), and the PMOS transistor (MP) can maintain a turned-on state.

[0031] The other end of the PMOS transistor can be connected to a diode-connected first NMOS transistor (MN1) and can output a first current (I1). The magnitude of the first current (I1) can be determined as shown in Equation 1.

[0032]

[0034] In mathematical formula 1 can be the carrier mobility of a PMOS transistor (MP), and can be the size of the capacitance present in the gate insulation layer of the PMOS transistor (MP). ε can be the channel length of the PMOS transistor (MP), and can be the channel width of the PMOS transistor (MP). can be the magnitude of the threshold voltage of the PMOS transistor (MP).

[0035] As mentioned above, since the resistance value of the resistor element (R) can have a characteristic proportional to temperature, in Equation 1 The value may increase as the temperature increases. In addition, since the threshold voltage of a PMOS transistor (MP) can have a characteristic inversely proportional to temperature, in Equation 1 The value can decrease as the temperature increases. Therefore, the size increases as the temperature increases. The size decreases as the temperature increases Since they cancel each other out in Equation 1, the magnitude of the first current (I1) can maintain a substantially constant value regardless of temperature change.

[0036] Accordingly, in one embodiment of the present invention, a current source capable of outputting a substantially constant current regardless of temperature change can be implemented without a bandgap reference circuit connected to the gate terminal of a PMOS transistor (MP). For example, the circuit area can be reduced by implementing the current source using a PMOS transistor (MP) having a gate terminal connected to a second power node that supplies a second power supply voltage (GND) instead of a bandgap reference circuit.

[0037] The first NMOS transistor (MN1) may be a diode-connected transistor in which the gate terminal and the drain terminal are connected to each other. The gate terminal of the first NMOS transistor (MN1) may be connected to the gate terminal of the second NMOS transistor (MN2), and the first and second NMOS transistors (MN1, MN2) may form a current mirror circuit. One end of the second NMOS transistor (MN2) may output a second current (I2), which is a mirrored current of the first current (I1), and the other end of the second NMOS transistor (MN2) may be connected to a second power node that supplies a second power supply voltage (GND).

[0038] The magnitude of the second current (I2) can be determined according to the magnitude of the first current (I1). Since the magnitude of the first current (I1) does not substantially change regardless of temperature change, the magnitude of the second current (I2) can also be maintained substantially constant regardless of temperature change. That is, the second current (I2) can have the characteristics of a constant current.

[0040] FIG. 2 is a graph provided to explain the operation of a semiconductor device according to one embodiment of the present invention.

[0041] Hereinafter, for convenience of explanation, the operation of a semiconductor device (1) according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2 together.

[0042] As described with reference to FIG. 1, the source terminal of the PMOS transistor (MP) can be connected to a resistor (R), and the resistance value of the resistor (R) can increase as the temperature increases. Therefore, the magnitude of the source voltage of the PMOS transistor (MP) can decrease as the temperature increases. For example, the magnitude of the source voltage applied to the source terminal of the PMOS transistor (MP) can be defined as [VCC-I1*R].

[0043] Meanwhile, the magnitude of the threshold voltage of the PMOS transistor (MP) can decrease as the temperature increases. Since the voltage at the gate terminal of the PMOS transistor (MP) is maintained at a substantially constant second power supply voltage (GND), as the threshold voltage of the PMOS transistor (MP) decreases due to the increase in temperature, the resistance of the PMOS transistor (MP) in the turn-on state can decrease as the temperature increases.

[0044] As the temperature increases, the source voltage of the PMOS transistor (MP) decreases, and at the same time, the resistance of the PMOS transistor (MP) decreases, so the change in the magnitude of the first current (I1) with respect to temperature can be minimized. In one embodiment, as shown in the graph of FIG. 2, the magnitude of the first current (I1) can be maintained substantially constant despite the change in temperature. Therefore, the first current (I1) can have constant current characteristics.

[0046] FIG. 3 is a diagram briefly illustrating a part of the configuration of a circuit included in a semiconductor device according to one embodiment of the present invention.

[0047] Referring to FIG. 3, a semiconductor device (2) according to one embodiment of the present invention may include a current source that supplies a current that does not substantially change with temperature. The current source may include a resistor element (R), a PMOS transistor (MP), a diode-connected first NMOS transistor (MN1), and a second NMOS transistor (MN2). The resistor element (R) may include a plurality of unit resistor elements (R1-Rn) and a plurality of unit switches (SW_R1-SW_Rn). For example, each of the plurality of unit resistor elements (R1-Rn) may have the same resistance value. However, depending on the embodiments, at least some of the plurality of unit resistor elements (R1-Rn) may have different resistance values.

[0048] The structure and operation of the PMOS transistor (MP), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) can be understood based on an embodiment described above with reference to FIG. 1.

[0049] Each of the plurality of unit resistor elements (R1-Rn) can be connected in parallel with each other, and each of the plurality of unit resistor elements (R1-Rn) can be connected to a plurality of unit switches (SW_R1-SW_Rn) that can be individually turned on and turned off. One end of each of the plurality of unit resistor elements (R1-Rn) can be connected to a first power node that supplies a first power supply voltage (VCC), and the other end can be connected to one end of a PMOS transistor (MP). For example, one end of the PMOS transistor (MP) can be a source terminal.

[0050] In one embodiment of the present invention illustrated in FIG. 3, the magnitude of the first current (I1) can be determined by the resistance value of a resistor element (R) determined according to the on / off status of each of the plurality of unit switches (SW_R1-SW_Rn). For example, as the resistance value of the resistor element (R) increases according to the on / off status of each of the plurality of unit switches (SW_R1-SW_Rn), the magnitude of the first current (I1) may decrease, and as the resistance value of the resistor element (R) decreases, the magnitude of the first current (I1) may increase.

[0051] In the design and / or manufacturing stage of the semiconductor device (2), the turn-on and turn-off of each of the unit switches (SW_R1-SW_Rn) connected to each of the plurality of unit resistor elements (R1-Rn) can be controlled so that the magnitude of the first current (I1) output by the PMOS transistor (MP) does not change with temperature. For example, as the number of unit switches turned on increases, the number of unit resistor elements connected between the first power node and the PMOS transistor (MP) among the plurality of unit resistor elements (R1-Rn) increases, so the resistance value of the resistor element (R) can be reduced.

[0052] For example, the resistance value of a resistor element (R) can be determined according to the change in threshold voltage of a PMOS transistor (MP) due to a change in temperature. For example, the greater the change in threshold voltage of the PMOS transistor (MP) due to a change in temperature, the number of unit switches turned on among the plurality of unit switches (SW_R1-SW_Rn) can be reduced, and the resistance value of the resistor element (R) can be determined to be large. On the other hand, the smaller the change in threshold voltage of the PMOS transistor (MP) due to a change in temperature, the number of unit switches turned on among the plurality of unit switches (SW_R1-SW_Rn) can be increased, and the resistance value of the resistor element (R) can be determined to be small.

[0053] In summary, the degree of change in the threshold voltage magnitude of the PMOS transistor (MP) due to temperature change may vary depending on the embodiments, and the on / off of the unit switches (SW_R1-SW_Rn) can be controlled in response to this degree of change to make the current supplied by the current source substantially constant.

[0055] FIG. 4 is a diagram briefly illustrating a part of the configuration of a circuit included in a semiconductor device according to one embodiment of the present invention.

[0056] A semiconductor device (3) according to one embodiment of the present invention may include a current source that supplies a current that does not substantially change with temperature. The current source may include a resistor element (R), a PMOS transistor (MP), a diode-connected first NMOS transistor (MN1), and a second NMOS transistor (MN2). The PMOS transistor (MP) may include a plurality of unit PMOS transistors (MP1-MPn) and a plurality of unit switches (SW_M1-SW_Mn). For example, each of the plurality of unit PMOS transistors (MP1-MPn) may have the same size as each other. However, depending on the embodiments, at least some of the plurality of unit PMOS transistors (MP1-MPn) may have different sizes.

[0057] The structure and operation of the resistor element (R), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) can be understood based on an embodiment described above with reference to FIG. 1.

[0058] Each of the plurality of unit PMOS transistors (MP1-MPn) can be connected in parallel with each other, and each of the plurality of unit PMOS transistors (MP1-MPn) can be connected to a plurality of unit switches (SW_M1-SW_Mn) that can be individually turned on and turned off. One end of each of the plurality of unit PMOS transistors (MP1-MPn) can be connected to one end of a resistor element (R), and the other end can be connected to one end of a first NMOS transistor (MN1). For example, one end of the PMOS transistor (MP) can be a source terminal, and the other end can be a drain terminal.

[0059] In one embodiment of the present invention illustrated in FIG. 4, the magnitude of the first current (I1) can be determined according to the number of unit switches turned on among the plurality of unit switches (SW_M1-SW_Mn). In other words, the magnitude of the first current (I1) can be determined according to the number of PMOS transistors actually connected to the resistor element (R) among the plurality of unit PMOS transistors (MP1-MPn). For example, the magnitude of the first current (I1) can increase as the number of unit PMOS transistors actually connected to the resistor element (R) increases. In the design and / or manufacturing stage of the semiconductor device (3), the turn-on and turn-off of each of the plurality of unit switches (SW_M1-SW_Mn) connected to each of the plurality of PMOS transistors (MP1-MPn) can be controlled so that the magnitude of the first current (I1) does not change with temperature. For example, as the number of unit switches turned on among the plurality of unit switches (SW_M1-SW_Mn) increases, the effect of reducing the resistance value between the resistor element (R) and the first NMOS transistor (MN1) can be obtained, and the magnitude of the first current (I1) can be increased.

[0060] In one embodiment, the turn-on and turn-off of each of the plurality of unit switches (SW_M1-SW_Mn) can be determined according to the resistance value of the resistor element (R). For example, if the resistance value of the resistor element (R) is large, the number of unit switches turned on among the plurality of unit switches (SW_M1-SW_Mn) can be reduced. On the other hand, if the resistance value of the resistor element (R) is small, the number of unit switches turned on among the plurality of unit switches (SW_M1-SW_Mn) can be increased.

[0062] FIG. 5 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention.

[0063] A semiconductor device (4) according to one embodiment of the present invention may include a current source that supplies a current having a substantially constant magnitude regardless of temperature change. The current source may include a resistor element (R), a PMOS transistor (MP), a diode-connected first NMOS transistor (MN1), and a second NMOS transistor (MN2).

[0064] A resistor element (R) may include a plurality of unit resistor elements (R1-Rn) and a plurality of unit switches (SW_R1-SW_Rn). The plurality of unit resistor elements (R1-Rn) may have the same resistance value, or some of the plurality of unit resistor elements (R1-Rn) may have different resistance values.

[0065] A PMOS transistor (MP) may include a plurality of unit PMOS transistors (MP1-MPn) and a plurality of unit switches (SW_M1-SW_Mn). The plurality of unit PMOS transistors (MP1-MPn) may have the same size as each other, or some of the plurality of unit PMOS transistors (MP1-MPn) may have different sizes.

[0066] The first NMOS transistor (MN1) and the second NMOS transistor (MN2) can provide a current mirror circuit. The structure and operation of the current mirror circuit can be understood based on an embodiment described above with reference to FIG. 1.

[0067] The structure and operation of a plurality of unit resistor elements (R1-Rn) and a plurality of unit switches (SW_R1-SW_Rn) connected to each of the unit resistor elements (R1-Rn) can be understood based on an embodiment described above with reference to FIG. 3.

[0068] The structure and operation of a plurality of unit PMOS transistors (MP1-MPn) and a plurality of unit switches (SW_M1-SW_Mn) connected to each of the plurality of PMOS transistors (MP1-MPn) can be understood based on an embodiment described above with reference to FIG. 4.

[0069] For example, in the design and / or manufacturing stage of a semiconductor device (4), the turn-on and turn-off of a plurality of unit switches (SW_R1-SW_Rn) connected to each of a plurality of unit resistor elements (R1-Rn) and a plurality of unit switches (SW_M1-SW_Mn) connected to each of a plurality of unit PMOS transistors (MP1-MPn) can be controlled so that the magnitude of the first current (I1) does not change according to temperature. For example, the turn-on and turn-off of each of the plurality of unit switches (SW_R1-SW_Rn) connected to each of a plurality of unit resistor elements (R1-Rn) can be controlled so that the change in the resistance value of the resistor element (R) according to the temperature change matches the change in the resistance value of the PMOS transistor (MP) according to the temperature change, and the turn-on and turn-off of each of the plurality of unit switches (SW_M1-SW_Mn) connected to each of a plurality of unit PMOS transistors (MP1-MPn) can be controlled.

[0071] FIG. 6 is a diagram briefly illustrating a partial configuration of a circuit included in a semiconductor device according to one embodiment of the present invention.

[0072] Referring to FIG. 6, a semiconductor device (5) according to one embodiment of the present invention may include a current source (6), a first current-controlled oscillator (11), a second current-controlled oscillator (12), a first arithmetic unit (21), and a second arithmetic unit (22). The current source (6) may include a resistor element (R), a PMOS transistor (MP), a diode-connected first NMOS transistor (MN1), and a second NMOS transistor (MN2).

[0073] For example, the current source (6) may be implemented according to at least one of the embodiments described with reference to FIGS. 1 to 5. Accordingly, the structure and operation of the current source (6) may be understood based on at least one of the embodiments described above with reference to FIGS. 1 to 5.

[0074] The first current control oscillator (11) can receive the second current (I2) output by the current source (6) and output the first signal (OUT1). For example, the magnitude of the first current (I1) input to the first NMOS transistor (MN1) within the current source (6) can be maintained substantially constant regardless of temperature change by means of a resistor element (R) having a resistance value that increases as the temperature increases and a PMOS transistor (MP) having a resistance value that decreases as the temperature increases. Therefore, the change in the magnitude of the first current (I1) due to temperature change can be minimized, and the first current (I1) having constant current characteristics can be generated.

[0075] Therefore, the magnitude of the second current (I2) can also be maintained substantially constant even when the temperature changes. Since the second current (I2) output by the current source (6) does not change substantially with temperature, the first signal (OUT1) output by the first current control oscillator (11) can also have a substantially constant characteristic despite temperature changes. For example, the first signal (OUT1) may be a clock signal having a predetermined first frequency, and the first frequency can be maintained substantially constant regardless of temperature changes.

[0076] The second current-controlled oscillator (12) outputs a second signal (OUT2), and the second signal (OUT2) may also be a clock signal having a predetermined second frequency. Unlike the first signal (OUT1), the second frequency of the second signal (OUT2) may vary with temperature. For example, the second frequency may increase as the temperature increases.

[0077] The first arithmetic unit (21) can receive a first signal (OUT1) and output a third signal (OUT3) to the second arithmetic unit (22). For example, the first arithmetic unit (21) may be a counter circuit and can determine the number of times the first signal (OUT1) of one cycle has been received from the first current-controlled oscillator (11) by counting the rising edge and / or falling edge of the first signal (OUT1). When the first arithmetic unit (21) receives the first signal (OUT1) of one cycle a predetermined reference number of times, it can output a third signal (OUT3) to the second arithmetic unit (22). For example, the third signal (OUT3) may be an enable signal that operates the second arithmetic unit (22) for a predetermined period. Since the first signal (OUT1) has a substantially constant frequency, the first arithmetic unit (21) can also output the third signal (OUT3) at substantially constant intervals.

[0078] The second arithmetic unit (22) can receive the second signal (OUT2) of one cycle N times during the enable period operated by the third signal (OUT3) (where N is a natural number). As the temperature increases, the frequency of the second signal (OUT2) may increase, and the number of times the second arithmetic unit (22) receives the second signal (OUT2) of one cycle during the enable period may increase. As previously explained, since the third signal (OUT3) can be substantially constant regardless of temperature, the enable period during which the second arithmetic unit (22) receives the second signal (OUT2) from the second current-controlled oscillator (12) can also be substantially constant regardless of temperature change.

[0079] The second arithmetic unit (22) can output a temperature code (TH Code) corresponding to the number of cycles included in the second signal (OUT2) received from the second current control oscillator (12) during the enable period operated by the third signal (OUT3). For example, as the temperature increases, the number of cycles included in the second signal (OUT2) received by the second arithmetic unit (22) during the enable period increases, and the temperature code (TH Code) can increase proportionally.

[0080] The circuit described with reference to FIG. 6 can operate as a temperature sensor that provides a temperature code (TH Code). As previously explained, since the temperature code (TH Code) changes according to the temperature change, the semiconductor device (5) can detect the temperature by referring to the temperature code (TH Code).

[0081] A temperature code (TH Code) can be used for the operation of a semiconductor device (5). For example, if the semiconductor device (5) is a memory device comprising a plurality of memory cells, the magnitude of the bias voltage input to the plurality of memory cells during the program operation, read operation, delete operation, etc. of the memory device can be determined differently according to the temperature code (TH Code).

[0083] FIG. 7 is a graph provided to explain the operation of a semiconductor device according to one embodiment of the present invention.

[0084] For example, the temperature code (TH Code) of the graph shown in FIG. 7 may be a signal output by the second arithmetic unit (22) in one embodiment shown in FIG. 6. Referring to FIG. 7, the temperature code (TH Code) may increase as the temperature increases. In each of the plurality of temperature ranges, the temperature code (TH Code) may have the same value, and whenever the temperature range is exceeded, the temperature code (TH Code) may increase by a certain unit in correspondence.

[0085] However, the pattern of change of the temperature code (TH Code) is not necessarily limited to this and may vary depending on the embodiment. For example, the temperature code (TH Code) may decrease as the temperature increases.

[0087] FIG. 8 is a simplified block diagram of a semiconductor device according to one embodiment of the present invention.

[0088] Referring to FIG. 8, the semiconductor device (100) may be a storage device based on a semiconductor element. The semiconductor device (100) may be a random access memory (RAM) device such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), SRAM (Static RAM), DDR SDRAM (Double Date Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), etc. The semiconductor device (100) may store data received via a data signal (DQ) or output data via a data signal (DQ) in response to an address signal (ADDR) and a control command signal (CMD) received from an external host (e.g., a central processing unit (CPU), an application processor (AP), or a system-on-chip (SoC)). The semiconductor device (100) may include a memory cell array (110), control logic (120), row decoder (130), column decoder (140), and input / output circuit (150), etc.

[0089] In the semiconductor device (100), the control logic (120), row decoder (130), column decoder (140), and input / output circuit (150) are placed in the peripheral circuit area, and the memory cell array (110) may be placed in the cell area. The placement and design of the cell area and the peripheral circuit area may vary depending on the type of semiconductor device (100).

[0090] A memory cell array (110) includes a plurality of memory cells, and the plurality of memory cells may be connected to a row decoder (130) and an input / output circuit (150) through a plurality of word lines (WL) and a plurality of bit lines (BL). Each of the plurality of memory cells may be located at a point where the plurality of word lines (WL) and the plurality of bit lines (BL) intersect. The plurality of memory cells may be arranged in a matrix form in the memory cell array (110), and each of the plurality of memory cells may include at least one memory element for storing data. For example, if the semiconductor device (100) is a DRAM, each of the plurality of memory cells may include a switch element and a cell capacitor. If the semiconductor device (100) is a NAND memory device, each of the plurality of memory cells may include a charge storage layer in which charge is trapped.

[0091] The control logic (120) can receive an address signal (ADDR) and a control command signal (CMD) from an external host. The address signal (ADDR) may include a row address pointing to a row in the memory cell array (110) and a column address pointing to a column in the memory cell array (110). For example, the row decoder (130) may select at least one of a plurality of word lines (WL) by referring to the row address, and the column decoder (140) may select at least one of a plurality of bit lines (BL) by referring to the column address. The input / output circuit (150) may output a data signal (DQ) read from the memory cell array (110).

[0092] The characteristics of the components included in the semiconductor device (100), including memory cells placed in the memory cell array (110), may be affected by temperature. Therefore, it is necessary for the semiconductor device (100) to detect temperature changes and operate in response to them. In the semiconductor device (100) according to one embodiment of the present invention, a current source that supplies a substantially constant current regardless of temperature changes may be placed in the peripheral circuit area. For example, the current source placed in the peripheral circuit area may be implemented according to at least one of the embodiments described above with reference to FIGS. 1 to 6.

[0093] For example, in the peripheral circuit area of ​​a semiconductor device (100) according to one embodiment of the present invention, a temperature sensor that outputs a temperature code that changes according to temperature may be disposed, including a current source, a current-controlled oscillator, and an arithmetic unit. According to an embodiment, at least one of the control logic (120), row decoder (130), column decoder (140), and input / output circuit (150) included in the peripheral circuit area may determine the magnitude of the bias voltage input to the memory cell array (110) differently by referring to the temperature code output by the temperature sensor.

[0095] FIG. 9 is a simplified diagram showing a semiconductor package including a semiconductor device according to one embodiment of the present invention.

[0096] Referring to FIG. 9, the semiconductor package (200) may include a plurality of memory chips (M1-Mn), a register chip (210), buffers (BF1-BFn), etc. Each of the plurality of memory chips (M1-Mn) may include a bank array, a row decoder, a sense amplifier circuit, a column decoder, and control logic, etc., and the bank array may include a plurality of memory cells.

[0097] The register chip (210) receives a command signal and an address signal from an external host and can control a plurality of memory chips (M1-Mn) according to the command signal and the address signal. The register chip (210) can select at least one of the plurality of memory chips (M1-Mn) by referring to the address signal and can control at least one of the plurality of memory chips (M1-Mn) to store data or output data according to the command signal.

[0098] In one embodiment, a plurality of buffer chips (BF1-BFn) may be assigned to each of the plurality of memory chips (M1-Mn). The plurality of buffer chips (BF1-BFn) are connected to a path where the plurality of memory chips (M1-Mn) input and output data, and can transfer data between the semiconductor package (200) and an external host.

[0099] Each of the plurality of memory chips (M1-Mn) may include a current source according to at least one of the embodiments described above with reference to FIGS. 1 to 6. For example, the characteristics of the plurality of memory cells included in the bank array in each of the plurality of memory chips (M1-Mn) may be affected by temperature. For example, by using a current source that supplies a substantially constant current regardless of temperature change, a temperature code corresponding to the current temperature can be accurately generated, and the plurality of memory cells can be controlled according to the temperature code. For example, the magnitude of the bias voltage input to the plurality of memory cells during the program operation, read operation, refresh operation, etc., of each of the plurality of memory chips (M1-Mn) may be determined differently depending on the temperature detected by the temperature sensor.

[0101] FIG. 10 is a simplified diagram showing a storage device including a semiconductor device according to one embodiment of the present invention.

[0102] Referring to FIG. 10, a storage device (300) including a semiconductor device according to one embodiment of the present invention may include a plurality of non-volatile memory devices (MC1-MCn), a power management device (310), and a controller (320), etc. Each of the plurality of non-volatile memory devices (MC1-MCn) may include a cell region where a memory cell array is arranged, and a peripheral circuit region that controls the memory cell array, etc. A plurality of memory cells may be arranged in a three-dimensional structure in the memory cell array of the cell region, and the peripheral circuit region may include control logic, a row decoder, a page buffer, an input / output circuit, etc.

[0103] The power management device (310), the controller (320), and the non-volatile memory devices (MC1-MCn) may be connected to each other by wiring patterns formed on the substrate (301). In exemplary embodiments, the storage device (300) may communicate with an external host according to any one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). For example, the storage device (300) according to one embodiment illustrated in FIG. 10 may have a form factor such as a 2.5-inch disk drive and may communicate with other external devices according to the SATA protocol.

[0104] The storage device (300) can be operated by an external power voltage and control commands transmitted by an external host. The power management device (310) of the storage device (300) may be a Power Management Integrated Circuit (PMIC) that generates internal power voltages necessary for the operation of the controller (320) and a plurality of non-volatile memory devices (MC1-MCn) using an external power voltage supplied by an external host.

[0105] The controller (320) can write data to a plurality of non-volatile memory devices (MC1-MCn), read data from a plurality of non-volatile memory devices (MC1-MCn), and exchange data with an external host. Each of the plurality of non-volatile memory devices (MC1-MCn) may be a NAND memory device, and the controller (320) may include a NAND controller and a memory interface, etc., for controlling the plurality of non-volatile memory devices (MC1-MCn). According to an embodiment, at least one of the plurality of non-volatile memory devices (MC1-MCn) may further include an interface chip that mediates communication with the controller (320).

[0106] At least one of the power management device (310), the controller (320), and the plurality of non-volatile memory devices (MC1-MCn) may include a current source according to at least one of the embodiments described above with reference to FIGS. 1 to 6. Similar to what was described above with reference to FIG. 9, the characteristics of the plurality of memory cells included in the plurality of non-volatile memory devices (MC1-MCn) may be affected by temperature. In one embodiment of the present invention, a temperature code indicating a temperature change may be generated using a current source that supplies a substantially constant current regardless of temperature change, and the plurality of non-volatile memory devices (MC1-MCn) may operate in response to the temperature code. For example, the magnitude of the bias voltage input to the memory cell array during program operation, read operation, delete operation, etc. of the plurality of non-volatile memory devices (MC1-MCn) may be determined differently depending on the temperature detected by the temperature sensor.

[0108] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0110] 1, 2, 3, 4, 5: Semiconductor device 6: Current source 11: First current-controlled oscillator 12: Second current-controlled oscillator 21: First operation unit 22: Second arithmetic unit 100: Semiconductor device 110: Memory cell array 120: Control logic 130: Low decoder 140: Column decoder 150: Input / Output Circuit 200: Semiconductor package 210: Register chip 300: Storage device 310: Power Management Unit 320: Controller MC: Memory chip TH Code: Temperature Code MP: PMOS transistor MN: NMOS transistor

Claims

Claim 1 A semiconductor device comprising: a resistor element connected to a first power node supplying a first power supply voltage; a PMOS transistor having a gate terminal connected to a second power node supplying a second power supply voltage smaller than the first power supply voltage, a source terminal connected to the resistor element, and a drain terminal outputting a first current; and a diode-connected transistor, wherein a first NMOS transistor connected between the drain terminal of the PMOS transistor and the second power node; wherein the second power supply voltage is a ground voltage. Claim 2 A semiconductor device according to claim 1, wherein the resistance value of the resistor element is proportional to the temperature, and the threshold voltage of the PMOS transistor is inversely proportional to the temperature. Claim 3 A semiconductor device according to claim 1, wherein the resistor element comprises a plurality of unit resistor elements connected in parallel with each other and a plurality of unit switches connected to the plurality of unit resistor elements, and the PMOS transistor comprises a plurality of unit PMOS transistors connected in parallel and a plurality of unit switches connected to the plurality of unit PMOS transistors. Claim 4 A semiconductor device according to claim 1, further comprising a second NMOS transistor, wherein the gate terminal of the first NMOS transistor is connected to the gate terminal of the second NMOS transistor, and the second NMOS transistor outputs a second current that is mirrored of the first current output by the PMOS transistor. Claim 5 A semiconductor device according to claim 4, further comprising a first current-controlled oscillator that receives the second current and outputs a first signal having a first frequency that does not change with temperature. Claim 6 A semiconductor device according to claim 5, further comprising: a first counter that receives the first signal and outputs a signal that does not change according to temperature; a second current-controlled oscillator that outputs a second signal having a second frequency that changes according to temperature; and a second counter that outputs a temperature code that changes according to temperature based on the signal output by the first counter and the second signal. Claim 7 A semiconductor device comprising: a cell region in which a plurality of memory cells are arranged; and a peripheral circuit region in which peripheral circuits for driving the cell region are arranged; wherein the peripheral circuit region includes a current source, the current source includes a resistor element, a PMOS transistor, and a diode-connected first NMOS transistor, wherein the control terminal of the PMOS transistor receives a ground voltage, the input terminal of the PMOS transistor receives a power supply voltage greater than the ground voltage through the resistor element, and the output terminal of the PMOS transistor outputs current to the first NMOS transistor. Claim 8 A semiconductor device according to claim 7, wherein the resistance value of the resistor element increases in proportion to the temperature, the threshold voltage of the PMOS transistor is inversely proportional to the temperature, the current source outputs a constant current, and further comprises a second NMOS transistor that forms a current mirror circuit with the first NMOS transistor, wherein the second NMOS transistor outputs a mirror current that mirrors the current output by the PMOS transistor. Claim 9 A semiconductor device according to claim 8, further comprising: a first current-controlled oscillator that outputs a first signal having a first frequency based on the mirror current; a second current-controlled oscillator that outputs a second signal having a second frequency that varies according to temperature; and an arithmetic unit that outputs a temperature code based on the first and second signals. Claim 10 A semiconductor device comprising: a current source that outputs a constant current that does not change with temperature; and a temperature sensor that detects the temperature using the constant current; wherein the current source comprises: a resistor element having a resistance value proportional to the temperature; a PMOS transistor having a threshold voltage inversely proportional to the temperature, wherein the control terminal receives a ground voltage as input; and a current mirror circuit that mirrors the current of the PMOS transistor; and wherein the temperature sensor detects the temperature based on the constant current output by the current source.

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