Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention may include: a substrate; a contact plug on the substrate; a lower electrode electrically connected to the contact plug and comprising a first electrode layer, a first buffer layer, and a second electrode layer sequentially stacked; a first support layer extending in a direction parallel to the substrate, which may be arranged to be in contact with the upper surface of the lower electrode and overlap with at least a portion of the lower electrode; a dielectric layer disposed on the lower electrode and the first support layer; and an upper electrode disposed on the dielectric layer. The lower electrode may include a first region having a first height that overlaps with the first support layer; and a second region having a second height that does not overlap with the first support layer and is smaller than the first height.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] In response to the demand for high integration and miniaturization of semiconductor devices, the size of capacitors in these devices is also becoming smaller. Accordingly, various studies are being conducted to optimize the structure of capacitors capable of storing information in Dynamic Random-Access Memory (DRAM).

[0004] delete Prior art literature

[65535] 1. U.S. Registered Patent Publication 8,441,100 B2 The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments may include: a substrate; a contact plug on the substrate; a lower electrode electrically connected to the contact plug and comprising a first electrode layer, a first buffer layer, and a second electrode layer sequentially stacked; a first support layer extending in a direction parallel to the substrate, which may be disposed to be in contact with the upper surface of the lower electrode and overlap with at least a portion of the lower electrode; a dielectric layer disposed on the lower electrode and the first support layer; and an upper electrode disposed on the dielectric layer. The lower electrode may include a first region having a first height that overlaps with the first support layer; and a second region having a second height that does not overlap with the first support layer and is smaller than the first height.

[0008] A semiconductor device according to exemplary embodiments may include: a substrate; lower electrodes disposed on the substrate; one or more support layers in contact with the lower electrodes and connecting adjacent lower electrodes; a dielectric layer disposed on the lower electrodes and the support layer; and an upper electrode disposed on the dielectric layer. Each of the lower electrodes may include a first electrode layer disposed on the substrate and comprising a first material, a first buffer layer disposed on the first electrode layer and comprising a second material, and a second electrode layer disposed on the first buffer layer and comprising a third material. The second material has compressive stress and may be different from the first and third materials.

[0009] A semiconductor device according to exemplary embodiments may include a lower electrode; a dielectric layer disposed on the lower electrode; and an upper electrode disposed on the dielectric layer. The lower electrode may include a plurality of electrode layers; and one or more buffer layers interposed between the plurality of electrode layers and comprising at least a metal oxide. The lower electrode may include a first region having a first height; and a second region having a second height smaller than the first height. Effects of the invention

[0011] By resolving the bending problem of a capacitor having an asymmetrical lower electrode, the reliability of the semiconductor device can be improved.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a schematic layout diagram of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 7a to 7g are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device according to exemplary embodiments. FIG. 8 is a schematic layout diagram of a semiconductor device according to exemplary embodiments. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] With reference to FIGS. 1 and FIGS. 2, a semiconductor device according to exemplary embodiments will be described.

[0018] FIG. 1 is a schematic layout of a semiconductor device (100) according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device (100) according to exemplary embodiments. FIG. 2 shows a cross-section along I-I' of FIG. 1.

[0020] Referring to FIGS. 1 and 2, a semiconductor device (100) may include a substrate (110), a lower electrode (170) on the substrate (110), a dielectric layer (180) on the lower electrode (170), and an upper electrode (190) on the dielectric layer. The lower electrode (170), the dielectric layer (180), and the upper electrode (190) may form a capacitor (CP). The semiconductor device (100) may further include a contact plug (150) and a landing pad (155) connecting the substrate (110) and the capacitor (CP).

[0022] The substrate (110) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (110) may further include impurities. The substrate (110) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0024] The substrate (110) may include a device isolation region (120) and active regions (125) defined by the device isolation region (120).

[0025] The active regions (125) may be in the form of a bar and may be arranged in an island shape extending in one direction within the substrate (110). The active regions (125) may be arranged, for example, at an angle inclined with respect to the X and Y directions and may be arranged repeatedly in multiple numbers at equal intervals. By the inclined arrangement of the active regions (125), the cell density per unit area of ​​the substrate (110) can be increased while ensuring a spacing distance between adjacent active regions (125).

[0026] The active regions (125) may have impurity regions (SD) of a predetermined depth from the upper surface of the substrate (110). The impurity regions (SD) may be spaced apart from each other. The impurity regions (SD) may be provided as source / drain regions of a transistor formed by word lines (gate electrode layer (133)). In exemplary embodiments, the depths of the impurity regions (SD) in the source region and the drain region may differ from each other.

[0028] The device isolation region (120) can be formed by a shallow trench isolation (STI) process. The device isolation region (120) can surround active regions (125) and electrically isolate them from one another. The device isolation region (120) can be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation region (120) may include multiple regions having different bottom depths depending on the width of the trench etched in the substrate (110). The device isolation region (120) can define the active regions (125).

[0030] The substrate (110) may further include a buried gate structure (130) that is embedded within the substrate (110) and extends in a first direction (Y direction).

[0031] The buried gate structure (130) may include a gate electrode layer (133), a gate dielectric film (136), and a gate capping layer (139). The gate electrode layer (133) may be provided in a line shape extending along a first direction (Y direction) to form a word line. The word line may be arranged to extend in the first direction (Y direction) across an active region (125). For example, a pair of adjacent word lines may be arranged to cross one active region (125).

[0032] The upper surface of the gate electrode layer (133) may be located at a lower level than the upper surface of the substrate (110). As used herein, the high and low of the term “level” may be defined with respect to the substantially flat upper surface of the substrate (101). The gate electrode layer (133) may constitute the gate of a buried channel array transistor (BCAT), but is not limited thereto. According to embodiments, the gate electrode layer (133) may have a form disposed on the upper surface of the substrate (110).

[0033] The gate electrode layer (133) may include a conductive material. The gate electrode layer (133) may include, for example, one or more of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). According to embodiments, the gate electrode layer (133) may have a double-layer structure formed of different materials.

[0034] The gate dielectric film (136) can conformally cover the side and bottom surfaces of the gate electrode layer (133). The gate dielectric film (136) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0035] The gate capping layer (139) may be disposed on top of the gate electrode layer (133). The gate capping layer (139) may include an insulating material, for example, silicon nitride.

[0037] The semiconductor device (100) may further include an interlayer insulating layer (140) disposed on a substrate (110). The interlayer insulating layer (140) may be formed in a plurality. The interlayer insulating layer (140) may include, for example, first to third interlayer insulating layers (143, 146, 149). The first to third interlayer insulating layers (143, 146, 149) may each include an insulating material. For example, the first to third interlayer insulating layers (143, 146, 149) may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0039] A contact plug (150) may be disposed on a substrate (110). The contact plug (150) may be formed by penetrating at least a portion of the interlayer insulating layer (140). In an exemplary embodiment, the contact plug (150) may be disposed by penetrating the first and second interlayer insulating layers (143, 146).

[0040] A contact plug (150) may be connected to one area of ​​an active region (125). A contact plug (150) may be placed between word lines (gate electrode layers (133)). The lower surface of the contact plug (150) may be located at a lower level than the upper surface of the substrate (110). The contact plug (150) may include a conductive material. The contact plug (150) may include, for example, one or more of polycrystalline silicon (Si), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), or nitrides thereof, but is not limited thereto.

[0042] The semiconductor device (100) may further include a landing pad (155) disposed between the contact plug (150) and the capacitor (CP). The landing pad (155) may electrically connect the contact plug (150) and the lower electrode (170) of the capacitor (CP). The landing pad (155) may be disposed through at least a portion of the interlayer insulating layer (140) on the contact plug (150). In an exemplary embodiment, the landing pad (155) may be disposed through the third interlayer insulating layer (149). The landing pad (155) may include a conductive material, for example, one or more of polycrystalline silicon (Si), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni) and cobalt (Co), or nitrides thereof, but is not limited thereto.

[0044] The semiconductor device (100) may further include an etch stop layer (160) disposed on an interlayer insulating layer (140). The lower electrode (170) of the capacitor (CP) may penetrate the etch stop layer (160) and come into contact with the landing pad (155). The etch stop layer (160) may include an insulating material having etch selectivity under specific etching conditions with mold layers (SL of FIG. 8a, etc.). In an exemplary embodiment, where the mold layers (SL of FIG. 8a, etc.) include silicon oxide, the etch stop layer (160) may include at least one of silicon nitride (SiN), silicon boron nitride (SiBN), or silicon carbonitride (SiCN).

[0046] The capacitor (CP) may include a lower electrode (170), a dielectric layer (180), and an upper electrode (190). The semiconductor device (100) may further include a support layer (185) that contacts the capacitor (CP), extends in a direction parallel to the substrate (110), and connects adjacent lower electrodes (170) to each other.

[0047] The lower electrode (170) can penetrate the etching stop layer (160). The lower surface of the lower electrode (170) contacts the landing pad (155), so that the lower electrode (170) can be electrically connected to the contact plug (150) and the active region (125). The upper surface of the lower electrode (170) may include a portion that contacts the uppermost support layer (185).

[0048] The lower electrode (170) may have an asymmetric structure. The lower electrode (170) may include a first region that overlaps with the upper support layer (185) in a vertical direction (Z direction) and contacts the upper support layer (185), and a second region that does not overlap with the upper support layer (185) in a vertical direction (Z direction). The second region of the lower electrode (170) may overlap in a vertical direction (Z direction) with an opening defined by the side wall (185o) of the upper support layer (185).

[0049] The first region may have a first height, and the second region may have a second height smaller than the first height. In exemplary embodiments, the upper surface of the first region may have a planar shape substantially parallel to the upper surface of the substrate (110), and the upper surface of the second region may have a recessed shape toward the upper surface of the substrate (110).

[0050] The lower electrode (170) may include a first electrode layer (171), a buffer layer (172), and a second electrode layer (173) that are sequentially stacked. The first electrode layer (171) and the second electrode layer (173) may include a conductive material. In exemplary embodiments, each of the first electrode layer (171) and the second electrode layer (173) may include one or more of a metal and a metal nitride. The first electrode layer (171) and the second electrode layer (173) may include, for example, one or more of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), and / or their nitrides. The materials included in the first electrode layer (171) and the second electrode layer (173) may be the same or different from each other.

[0051] A buffer layer (172) may be disposed between the first electrode layer (171) and the second electrode layer (173). The buffer layer (172) may include a material different from the first electrode layer (171) and the second electrode layer (173). The buffer layer (172) may be formed from a material having compressive stress. The buffer layer (172) may include one or more of metals, metal nitrides, and metal oxides having compressive stress. In exemplary embodiments, the buffer layer (172) may include a metal oxide. The buffer layer (172) may include, for example, titanium oxide (TiO), tantalum oxide (TaO), tungsten oxide (WO), etc., but is not limited thereto.

[0052] If the lower electrode has an asymmetric structure, the lower electrode may have asymmetric stress. For example, if the lower electrode (170) is formed of a conductive material having tensile stress, the tensile stress in a first region having a relatively large height may be greater than the tensile stress in a second region having a relatively small height. Due to such asymmetric tensile stress, the lower electrode may be bent in one direction.

[0053] According to exemplary embodiments of the present invention, the lower electrode (170) can relieve asymmetric stress of the lower electrode (170) having an asymmetric structure by interposing a buffer layer (172) between the first electrode layer (171) and the second electrode layer (173). For example, if the first and second electrode layers (171, 173) have tensile stress, a buffer layer (172) having compressive stress can be placed between the first and second electrode layers (171, 173). Since the tensile stress of the first and second electrode layers (171, 173) is offset by the compressive stress of the buffer layer (172), the asymmetric stress of the lower electrode (170) can be relieved.

[0054] In exemplary embodiments, the first electrode layer (171) may have a cylindrical shape having a bottom surface and a side surface. The buffer layer (172) is disposed on the first electrode layer (171) to be in contact with the first electrode layer (171) and may have a cylindrical shape having a bottom surface and a side surface. The second electrode layer (173) is disposed on the buffer layer (172) to be in contact with the buffer layer (172) and may fill the space formed by the buffer layer (172). The second electrode layer (173) may have a pillar shape, for example. In exemplary embodiments, the first electrode layer (171) and the second electrode layer (173) may be spaced apart from each other by the buffer layer (172).

[0055] The lower electrode (170) has a structure in which a buffer layer (172) is disposed between the first and second electrode layers (171, 173), thereby including a plurality of electrode layers to ensure sufficient electrical conductivity. In addition, the buffer layer (172) inserted between the plurality of electrode layers can offset the asymmetric stress of the lower electrode (170) to resolve the bending problem. Furthermore, since the materials forming the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) can be controlled differently, the stress control range of the lower electrode (170) is wide, and mass production capabilities can be improved. For example, if the buffer layer (172) is formed of a material having a strong compressive stress compared to the tensile stress of the first electrode layer (171), the second electrode layer (173) can be formed of a material having a tensile stress sufficient to offset the compressive stress of the buffer layer (172). Considering the internal stress of the lower electrode (170), the combination of materials of the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) can be varied.

[0056] The first electrode layer (171), the buffer layer (172), and the second electrode layer (173) may each include a portion in contact with the uppermost support layer (185). In exemplary embodiments, the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) in contact with the uppermost support layer (185) may be substantially coplanar.

[0058] The support layer (185) contacts the lower electrode (170) and may extend in a direction parallel to the substrate (110). The support layer (185) may include a plurality of support layers. Each support layer (185) may be spaced apart from one another in the Z direction perpendicular to the upper surface of the substrate (110). The uppermost support layer among the support layers (185) contacts the upper surface of the lower electrode (170) and may include a portion that overlaps with the lower electrode (170) in the Z direction. The remaining support layers may contact the side of the lower electrode (170).

[0059] The support layer (185) may be a structure that supports a plurality of lower electrodes (170) having a high aspect ratio. The support layer (185) may connect adjacent lower electrodes (170) to each other. The support layer (185) may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The dielectric layer (180) may be disposed to cover the lower electrode (170) and the support layer (185) on the etching stop layer (160). The dielectric layer (180) may cover the upper surface and side surface of the lower electrode (170), the upper surface of the etching stop layer (160), and the exposed surface of the support layer (185).

[0062] The dielectric layer (180) may include a high dielectric material, silicon oxide, silicon nitride, or a combination thereof. However, according to the embodiments, the dielectric layer (180) may include an oxide, nitride, silicide, oxynitride, or silicide-oxynitride comprising one of hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La).

[0063] In exemplary embodiments, the dielectric layer (180) may have compressive stress. When the dielectric layer (180) having compressive stress is placed on a lower electrode having asymmetric stress, the bending phenomenon of the lower electrode (170) may be exacerbated by the compressive stress of the dielectric layer (180). In the lower electrode (170) according to exemplary embodiments of the present invention, a buffer layer is interposed between the first and second electrode layers (171, 173) to relieve the asymmetric stress of the lower electrode (170), so that even if the dielectric layer (180) having compressive stress is placed on the lower electrode (170) having an asymmetric structure, the bending phenomenon of the lower electrode (170) can be relieved.

[0065] The upper electrode (190) may be a structure covering a plurality of lower electrodes (170), a dielectric layer (180), and a support layer (185). The upper electrode (190) may be a structure filling the space between the plurality of lower electrodes (170) and the space between the support layer (185). The upper electrode (190) may be in direct contact with the dielectric layer (180).

[0066] FIG. 2 illustrates an embodiment in which the upper electrode (190) is composed of a single electrode layer, but is not limited thereto. In other embodiments, the upper electrode (190) may include a plurality of electrode layers. The upper electrode (190) may include a conductive material. The upper electrode (190) may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0068] FIGS. 3 to 6 illustrate schematic cross-sectional views of semiconductor devices according to exemplary embodiments.

[0069] The embodiments of FIGS. 3 to 6 differ from the embodiments of FIGS. 1 and 2 in terms of capacitor (CPa, CPb, CPc, CPd) structures, etc. In the embodiments of FIGS. 3 to 6, if the same reference numerals as FIGS. 1 and 2 are used but the alphabet is different, it is intended to describe embodiments different from FIGS. 1 and 2. The features described by the same reference numerals described above may be identical or similar.

[0071] The semiconductor device (100a) of FIG. 3 differs from the embodiments of FIG. 1 and FIG. 2 in the shape of the buffer layer (172a), etc.

[0072] Referring to FIG. 3, the buffer layer (172a) can be positioned between the central axis of the lower electrode (170) and the outer surface, and close to the outer surface of the lower electrode (170). Accordingly, compared to the embodiment of FIG. 2, the thickness of the cylinder of the first electrode layer (171a) is reduced, the diameter of the cylinder of the buffer layer (172a) is increased, and the diameter of the column of the second electrode layer (173a) is increased. The shape, insertion position, etc. of the buffer layer (172a) can be changed considering the tensile stress of the first and second electrode layers (171a, 173a).

[0074] The semiconductor device (100b) of FIG. 4 differs from the embodiments of FIG. 1 and FIG. 2 in that the lower electrode layer (170b) further includes a second buffer layer (174b).

[0075] Referring to FIG. 4, the lower electrode layer (170b) may have a structure in which a first electrode layer (171b), a first buffer layer (172b), a second electrode layer (173b), a second buffer layer (174b), and a third electrode layer (175b) are sequentially stacked. In exemplary embodiments, the first electrode layer (171b) may have a cylindrical shape. The first buffer layer (172b) is positioned on the first electrode layer (171b) to contact the first electrode layer (171b) and may have a cylindrical shape. The second electrode layer (173b) is positioned on the first buffer layer (172b) to contact the first buffer layer (172b) and may have a cylindrical shape. The second buffer layer (174b) is positioned on the second electrode layer (173b) to contact the second electrode layer (173b) and may have a cylindrical shape. The third electrode layer (175b) is positioned to be in contact with the second buffer layer (174b) on the second buffer layer (174b) and may have a column shape that fills the inside of the cylinder of the second buffer layer (174b).

[0076] The lower electrode (170b) includes a plurality of buffer layers (172b, 174b) disposed between the electrode layers (171b, 173b, 175b), so that asymmetric stress can be relieved more effectively. By including a plurality of buffer layers in the lower electrode (170b), the stress control range of the lower electrode (170b) can be widened. Since the plurality of electrode layers (171b, 173b, 175b) can each be formed of different materials, the range of possible materials is widened and mass production capabilities can be improved.

[0077] The number and arrangement order of the electrode layers and buffer layers constituting the lower electrode layer (170b) are not limited thereto. For example, the lower electrode layer (170b) may include four or more electrode layers and three or more buffer layers interposed between the electrode layers. In other embodiments, the arrangement order of the buffer layers and electrode layers may be changed, or the number of electrode layers and buffer layers constituting the lower electrode layer (170b) may be the same.

[0079] The semiconductor device (100c) of FIG. 5 differs from the embodiments of FIG. 1 and FIG. 2 in the thickness of the buffer layer (172c) of the lower electrode (170c).

[0080] As illustrated in FIG. 5, by increasing the thickness of the buffer layer (172c) interposed between the first and second electrode layers (171c, 173c), the asymmetric stress of the lower electrode (170c) can be relieved more effectively. Compared to an embodiment in which the buffer layer is composed of multiple layers, the number of process steps is reduced to improve manufacturing efficiency, while sufficient compressive stress is secured to relieve asymmetric stress. In addition, since sufficient compressive stress can be secured through the thickness control of the buffer layer (172c), the range of materials that can be used for the first and second electrode layers (171c, 173c) is widened and mass production capabilities can be improved.

[0082] The semiconductor device (100d) of FIG. 6 differs from the embodiments of FIG. 1 and FIG. 2 in the structure of the lower electrode (170d).

[0083] Referring to FIG. 6, the first electrode layer (171d) may have a columnar shape. The buffer layer (172d) may be disposed on the first electrode layer (171d) and may have a layer or columnar shape. The second electrode layer (173d) may be disposed on the buffer layer (172d) and may have an asymmetrical structure. In exemplary embodiments, the second electrode layer (173d) may have a recessed cylindrical shape facing the upper surface of the substrate (110) in an area that does not overlap with the uppermost support layer (185) in the vertical direction (Z direction). However, the recessed shape of the lower electrode (170d) is not limited thereto. In other embodiments, the recessed area may extend to the buffer layer (172d) or the first electrode layer (171d).

[0084] The buffer layer (172d) of the lower electrode (170d) may be disposed between pillar-shaped electrode layers, unlike the previous embodiments in which it is disposed between cylindrical electrode layers or between a cylindrical electrode layer and a pillar-shaped electrode layer. The thickness, position, etc. of the buffer layer (172d) may vary depending on the aspect ratio of the lower electrode (170d), the type of material constituting the first and second electrode layers (171d, 173d), etc.

[0085] In the embodiment illustrated in FIG. 6, the lower electrode (170d) comprises two electrode layers (171d, 173d) and one buffer layer (172d) disposed between the electrode layers (171d, 173d), but the structure of the lower electrode (170d) is not limited thereto. In other embodiments, the lower electrode (170d) may comprise three or more electrode layers and two or more buffer layers interposed therebetween. Alternatively, the lower electrode (170d) may comprise an equal number of electrode layers and buffer layers.

[0087] FIGS. 7a to 7g are schematic cross-sectional views for illustrating the manufacturing process of a semiconductor device according to exemplary embodiments. The cross-sectional views of FIGS. 7a to 7g illustrate cross-sections corresponding to FIG. 2.

[0089] Referring to FIG. 7a, a substructure including a substrate (110) can be formed, and mold layers (SL) and support layers (185) can be alternately stacked on the substructure. Holes penetrating the mold layers (SL) and support layers (185) can be formed.

[0090] Active regions (125) and device isolation regions (120) defining the active regions (125) can be formed on the substrate (110). A portion of the substrate (110) can be removed to form trenches extending in a first direction (Y direction), and buried gate structures (130) can be formed within the trenches. Impurity regions (SD) can be formed on both sides of the buried gate structures (130), and bit line structures (not shown) can be formed along a second direction (X direction) intersecting the first direction (Y direction).

[0091] First and second interlayer insulating layers (143, 146) covering the substrate (110) may be formed. An opening may be formed through the first and second interlayer insulating layers (143, 146) to expose a portion of the active region (125). The opening may be filled with a conductive material to form contact plugs (150). In an exemplary embodiment, the contact plugs (150) may comprise one or more of polycrystalline silicon (Si), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), or may comprise nitrides thereof.

[0092] A third interlayer insulating layer (149) covering the second interlayer insulating layer (146) and the contact plugs (150) may be formed. An opening may be formed through the third interlayer insulating layer (149) to expose at least a portion of the contact plugs (150). The opening may be filled with a conductive material to form landing pads (155). In an exemplary embodiment, the landing pads (155) may comprise doped polycrystalline silicon (Si).

[0093] An etch stop layer (160) covering the third interlayer insulating layer (149) and the landing pads (155) may be formed. The etch stop layer (160) may include an insulating material having etch selectivity under specific etching conditions with the mold layers (SL). In an exemplary embodiment, where the mold layers (SL) include silicon oxide, the etch stop layer (160) may include at least one of silicon nitride (SiN) or silicon carbonitride (SiCN).

[0094] A stacked structure can be formed by alternately stacking mold layers (SL) and support layers (185) on an etching stop layer (160). In an exemplary embodiment, the mold layers (SL) may include three layers and the support layers (185) may include two layers, but the number of layers is not limited thereto. The mold layers (SL) and support layers (185) may have the same thickness or different thicknesses. In an exemplary embodiment, the bottom mold layer (SL) may have a greater thickness than the top mold layer (SL).

[0095] Afterwards, a plurality of holes penetrating the stacked structure can be formed. The plurality of holes can penetrate the etching stop layer (160) to expose the landing pad (155).

[0097] Referring to FIG. 7b, a first electrode layer (171) can be conformally formed on the interior of a plurality of holes and on the upper surface of the stacked structures.

[0098] The first electrode layer (171) may be formed by a process such as, for example, Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The first electrode layer (171) may include a conductive material. In exemplary embodiments, the first electrode layer (171) may include a metal, a metal nitride, etc. The first electrode layer (171) may include, for example, one or more of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), and / or their nitrides.

[0100] Referring to FIG. 7c, a buffer layer (172) can be formed on the first electrode layer (171).

[0101] A buffer layer (172) is formed on the first electrode layer (171) to offset stress caused by the first electrode layer (171). The buffer layer (172) may also offset stress caused by the second electrode layer (173) formed in the process of FIG. 7d described later. In exemplary embodiments, if the first electrode layer (171) is formed of a material having tensile stress, the buffer layer (172) may be formed of a material having compressive stress. In exemplary embodiments, the buffer layer (172) may include a metal, a metal nitride, a metal oxide, etc. The buffer layer (172) may be formed of, for example, a metal oxide.

[0102] The buffer layer (172) can be formed by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). If the buffer layer (172) contains a metal oxide, it may be formed by oxidation of the first buffer layer (172) by oxygen (O2), ozone (O3), or their plasma.

[0104] Referring to FIG. 7d, a second electrode layer (173) can be formed on the buffer layer (172).

[0105] The second electrode layer (173) can be formed to fill the empty space provided by the buffer layer (172) within the plurality of holes and to cover the upper surface of the buffer layer (172). The second electrode layer (173) can be formed by a process such as, for example, Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

[0106] The second electrode layer (173) may include a conductive material. In exemplary embodiments, the second electrode layer (173) may include a metal, a metal nitride, etc. The second electrode layer (173) may include, for example, one or more of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), and / or nitrides thereof. The second electrode layer (173) may be formed of the same material as the first electrode layer (171) or may be formed of a different material from the first electrode layer (171).

[0108] Referring to FIG. 7e, after removing the first electrode layer (171), buffer layer (172), and second electrode layer (173) until the upper surface of the laminated structure is exposed, an upper support layer (185) covering the upper surface of the laminated structure can be formed.

[0109] A planarization process can be performed on the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) to expose the upper surface of the top mold layer (SL). As a planarization process, for example, a Chemical Mechanical Polishing (CMP) process may be performed. By the planarization process, the upper surfaces of the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) formed inside the plurality of holes can be substantially coplanar with the upper surface of the top mold layer (SL).

[0110] The first electrode layer (171), buffer layer (172), and second electrode layer (173) formed in a plurality of holes can be separated from each other. Each of the first electrode layer (171), buffer layer (172), and second electrode layer (173) can constitute a lower electrode.

[0111] Subsequently, an upper support layer (185) covering the upper surface of the upper mold layer (SL), the first electrode layer (171), the buffer layer (172), and the second electrode layer (173) can be formed. The support layer (185) may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0113] Referring to FIG. 7f, a portion of the upper support layer (185) and a portion of the lower electrode (170) can be removed, and a portion of the support layers (185) and the mold layers (SL) can be removed.

[0114] A mask (not shown) covering a portion of the uppermost support layer (185) is formed, and the uppermost support layer (185) and the lower electrode (170) that do not overlap with the mask in a vertical direction (Z direction) can be removed by etching.

[0115] The uppermost support layer (185) may be partially removed by etching and may include an opening. The opening may be defined by the side wall (185o) of the uppermost support layer (185).

[0116] The lower electrode (170) may have an asymmetric structure by an etching process. In an exemplary embodiment, the lower electrode (170) may include a first region that contacts the upper support layer (185) and overlaps the upper support layer (185) in a vertical direction (Z direction), and a second region that overlaps the opening of the upper support layer (185) in a vertical direction (Z direction). The first region of the lower electrode (170) may have a first height. The second region of the lower electrode (170) may have a second height that is smaller than the first height. The lower electrode (170) may not be etched in the first region, and the lower electrode (170) may be etched in the second region. In the second region, the upper surface of the lower electrode (170) may have a shape that is recessed toward the upper surface of the substrate (110).

[0117] Despite the asymmetric structure caused by the first and second regions of the lower electrode (170), the asymmetric stress of the lower electrode (170) can be relieved. For example, when the first and second electrode layers (171, 173) each have tensile stress, the first and second electrode layers (171, 173) each may have tensile stress of different magnitudes in the first region and the second region. However, according to exemplary embodiments of the present invention, the lower electrode (170) includes a buffer layer (172) having compressive stress between the first electrode layer (171) and the second electrode layer (173), so that the tensile stress caused by the first and second electrode layers (171, 173) can be offset.

[0119] Referring to FIG. 7g, a dielectric layer (180) can be formed covering the lower electrode (170) and the support layers (185) in contact with the lower electrode (170).

[0120] The dielectric layer (180) can conformally cover the upper and side surfaces of the lower electrode (170), the upper surface of the etch stop layer (160), and the exposed surfaces of the support layers (185). The dielectric layer (180) may comprise a high dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0122] Referring again to FIG. 2, an upper electrode (190) can be formed on the dielectric layer (180).

[0123] The upper electrode (190) fills the empty space (TL in FIG. 7g) between the lower electrodes (170) and between the support layers (185) and can cover the lower electrodes (170) and the support layers (185). The upper electrode (190) may include a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0125] FIGS. 8 and FIGS. 9 illustrate a semiconductor device (200) according to exemplary embodiments.

[0126] FIG. 8 is a layout diagram of a semiconductor device (200) according to exemplary embodiments. FIG. 9 is a cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 9 shows a cross-section along II-II' and III-III' of FIG. 8.

[0128] Referring to FIGS. 8 and 9, the semiconductor device (200) may include a substrate (210), a plurality of first conductive lines (220), a channel layer (230), a gate electrode layer (240), a gate insulating layer (250), and a capacitor (CP). The semiconductor device (200) may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (230) extends along a vertical direction from the substrate (210).

[0129] A lower insulating layer (212) may be disposed on a substrate (210), and a plurality of first conductive lines (220) may be spaced apart from each other in the X direction and extended in the Y direction on the lower insulating layer (212). A plurality of first insulating patterns (222) may be disposed on the lower insulating layer (212) to fill the space between the plurality of first conductive lines (220). The plurality of first insulating patterns (222) may be extended in the Y direction, and the upper surface of the plurality of first insulating patterns (222) may be disposed at the same level as the upper surface of the plurality of first conductive lines (220). The plurality of first conductive lines (220) may function as bit lines of a semiconductor device (200).

[0130] In exemplary embodiments, a plurality of first conductive lines (220) may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (220) may comprise one or more of doped polycrystalline silicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), or nitrides thereof, but are not limited thereto. A plurality of first conductive lines (220) may comprise a single layer or a multilayer of the aforementioned materials. In exemplary embodiments, a plurality of first conductive lines (220) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, a carbon nanotube, or a combination thereof.

[0131] The channel layer (230) may be arranged in a matrix form spaced apart in the X and Y directions on a plurality of first conductive lines (220). The channel layer (230) may have a first width in the X direction and a first height in the Z direction, and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. The bottom portion of the channel layer (230) functions as a first source / drain region (not shown), the upper portion of the channel layer (230) functions as a second source / drain region (not shown), and a portion of the channel layer (230) between the first and second source / drain regions may function as a channel region (not shown).

[0132] In exemplary embodiments, the channel layer (230) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yIt may include O or a combination thereof. The channel layer (230) may include a single layer or a multilayer of oxide semiconductor. In some examples, the channel layer (230) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (230) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer (230) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer (230) may be polycrystalline or amorphous, but is not limited thereto. In exemplary embodiments, the channel layer (230) may include a two-dimensional semiconductor material, for example, said two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0133] The gate electrode layer (240) may extend in the X direction on both sidewalls of the channel layer (230). The gate electrode layer (240) may include a first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230) and a second sub-gate electrode (240P2) facing the second sidewall opposite the first sidewall of the channel layer (230). As one channel layer (230) is disposed between the first sub-gate electrode (240P1) and the second sub-gate electrode (240P2), the semiconductor device (200) may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (240P2) and forming only the first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230).

[0134] The gate electrode layer (240) may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode layer (240) may comprise one or more of doped polycrystalline silicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), or nitrides thereof, but is not limited thereto.

[0135] The gate insulating layer (250) surrounds the sidewalls of the channel layer (230) and may be interposed between the channel layer (230) and the gate electrode layer (240). For example, as shown in FIGS. 8 and 9, the entire sidewall of the channel layer (230) may be surrounded by the gate insulating layer (250), and a portion of the sidewall of the gate electrode layer (240) may be in contact with the gate insulating layer (250). In other embodiments, the gate insulating layer (250) may extend in the extension direction of the gate electrode layer (240) (i.e., the first direction (X direction)), and only two sidewalls of the channel layer (230) facing the gate electrode layer (240) may be in contact with the gate insulating layer (250).

[0136] In exemplary embodiments, the gate insulating layer (250) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. For example, a high dielectric film that can be used as the gate insulating layer (250) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0137] A plurality of second insulation patterns (232) may be extended along a second direction (Y direction) on a plurality of first insulation patterns (222), and a channel layer (230) may be disposed between two adjacent second insulation patterns (232) among the plurality of second insulation patterns (232). Additionally, between two adjacent second insulation patterns (232), a first filling layer (234) and a second filling layer (236) may be disposed in the space between two adjacent channel layers (230). The first filling layer (234) may be disposed at the bottom of the space between two adjacent channel layers (230), and the second filling layer (236) may be formed on the first filling layer (234) to fill the remainder of the space between two adjacent channel layers (230). The upper surface of the second buried layer (236) is positioned at the same level as the upper surface of the channel layer (230), and the second buried layer (236) can cover the upper surface of the gate electrode layer (240). Alternatively, a plurality of second insulating patterns (232) may be formed as a material layer continuous with a plurality of first insulating patterns (222), or the second buried layer (236) may be formed as a material layer continuous with the first buried layer (234).

[0138] A contact plug (260) may be disposed on the channel layer (230). The contact plug (260) may be arranged in a matrix form that is spaced apart in the X and Y directions and is positioned to overlap vertically with the channel layer (230). The contact plug (260) may include one or more of doped polycrystalline silicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), and cobalt (Co), or may include nitrides thereof, but is not limited thereto. An upper insulating layer (262) may surround the sidewalls of the contact plug (260) on a plurality of second insulating patterns (232) and a second embedded layer (236).

[0139] An etching stop layer (261) is disposed on the upper insulating layer (262), and a capacitor (CP) may be disposed on the etching stop layer (261). The capacitor (CP) may include a lower electrode (270), a dielectric layer (280), and an upper electrode (290). In an exemplary embodiment, the capacitor (CP) may have the same or similar structure as described with reference to FIGS. 1 through 6.

[0141] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0143] 100: Semiconductor device 110: Substrate 120: Device isolation area 125: Active area 130: Landfill gate structure 140: Interlayer insulation layer 150: Contact plug 155: Landing pad 160: Etching stop layer CP: Capacitor 170: Lower electrode 180: Dielectric film 185: Supporter layer 190: Upper electrode

Claims

Claim 1 A semiconductor device comprising: a substrate; a contact plug on the substrate; a lower electrode electrically connected to the contact plug and including a first electrode layer, a first buffer layer, and a second electrode layer sequentially stacked; a first support layer extending in a direction parallel to the upper surface of the substrate, which is arranged to be in contact with the upper surface of the lower electrode and overlap at least a portion of the lower electrode; a dielectric layer disposed on the lower electrode and the first support layer; and an upper electrode disposed on the dielectric layer, wherein the lower electrode comprises: a first region having a first height that overlaps with the first support layer; and a second region having a second height that does not overlap with the first support layer and is smaller than the first height. Claim 2 A semiconductor device according to claim 1, wherein the first electrode layer and the first buffer layer each have a cylinder shape, and the second electrode layer has a pillar shape that fills the interior of the first buffer layer. Claim 3 A semiconductor device according to claim 1, wherein each of the first electrode layer, the first buffer layer, and the second electrode layer includes a portion in contact with the first support layer. Claim 4 A semiconductor device according to claim 1, wherein the lower electrode further comprises: a second buffer layer disposed on the second electrode layer; and a third electrode layer disposed on the second buffer layer. Claim 5 A semiconductor device according to claim 1, wherein the first electrode layer has a pillar shape, the first buffer layer is disposed on the upper surface of the first electrode layer, and the second electrode layer is disposed on the upper surface of the first buffer layer. Claim 6 A semiconductor device comprising: a substrate; lower electrodes disposed on the substrate; a support layer in contact with the lower electrodes, connecting adjacent lower electrodes, and having an opening; a dielectric layer disposed on the lower electrodes and the support layer; and an upper electrode disposed on the dielectric layer, wherein each of the lower electrodes comprises a first electrode layer disposed on the substrate and comprising a first material, a first buffer layer disposed on the first electrode layer and comprising a second material, and a second electrode layer disposed on the first buffer layer and comprising a third material, wherein at least one of the lower electrodes comprises a first region perpendicularly overlapping with the support layer and in contact with the support layer, and a second region perpendicularly overlapping with the opening, wherein the second material is different from the first and third materials. Claim 7 A semiconductor device according to claim 6, wherein the first material and the third material each comprise at least one of a metal and a metal nitride. Claim 8 A semiconductor device according to claim 6, wherein the second material comprises at least one of a metal, a metal nitride, and a metal oxide. Claim 9 In claim 6, the lower electrodes further comprise: a second buffer layer comprising a fourth material disposed on the second electrode layer; and a third electrode layer comprising a fifth material disposed on the second buffer layer, wherein the fourth material has compressive stress and is different from the first material, the third material and the fifth material. Claim 10 A semiconductor device comprising a plurality of electrode layers and a lower electrode interposed between the plurality of electrode layers and at least one buffer layer comprising a metal oxide, wherein the lower electrode comprises a first region having a first height and a second region connected to the first region and having a second height smaller than the first height; a support layer disposed on the first region of the lower electrode; a dielectric layer disposed on the support layer and the second region of the lower electrode; and an upper electrode disposed on the dielectric layer, wherein in the first region, the one or more buffer layers are in contact with the support layer, and in the second region, the one or more buffer layers are in contact with the dielectric layer.

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