Delay control circuit and memory module including the same

Abstract

A delay control circuit comprises a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, and a delay cell that activates a predetermined number of RC circuits among the plurality of first RC circuits according to the value of a step code input from the outside, and outputs a signal input from the outside by a delay time determined according to the number of activated RC circuits; and a ZQ calibrator that comprises a plurality of pull-up circuits and a plurality of pull-down circuits, adjusts the impedance of a transmission line by adjusting the number of pull-up circuits and pull-down circuits among the plurality of pull-up circuits and the plurality of pull-down circuits that are activated, and inputs a pull-up voltage and a pull-down voltage determined based on a calibration code corresponding to the number of activated pull-up circuits and pull-down circuits to the plurality of bias inverters. The apparatus includes a first ring oscillator comprising a plurality of test delay cells having the same circuit structure as the delay cell, and a step adjustment unit that determines the component characteristics of the first and second RC circuits based on a pulse period that varies depending on whether the second RC circuits included in the first ring oscillator are activated, and activates at least some of the RC circuits among the second RC circuits based on the component characteristics and the operating frequency of the delay control circuit.

Description

Technology Field

[0001] The present invention relates to a delay control circuit and a memory module including the same. Background Technology

[0003] Dynamic Random Access Memory (DRAM), commonly employed as the main memory of electronic systems, is trending toward higher speeds and greater integration in response to user demands. Such DRAM may include multiple input / output pins. Among these multiple input / output pins, multiple command / address pins may be included.

[0004] For commands and data to be accurately transmitted to DRAM through multiple command / address pins, signals must be input to multiple command / address pins within a defined data bit time. As DRAM becomes faster, data bit times are becoming increasingly shorter. Consequently, signals must be input to multiple command / address pins almost simultaneously.

[0005] To train a DRAM so that signals can be input to multiple command / address pins almost simultaneously, a delay cell is required that can delay the command / address signals by a constant step, regardless of the DRAM's operating frequency.

[0006] delete Prior art literature

[65535] US 2004 / 0105292 A1US 2014 / 0192583 A1 The problem to be solved

[0007] The present invention aims to provide a delay control circuit capable of compensating for the PVT (Process, Voltage, Temperature) characteristics of a delay cell so that the delay cell can delay an input signal by a constant step.

[0008] The present invention aims to provide a delay control circuit capable of controlling a delay cell based on an operating frequency, so that the delay cell can delay an input signal in a constant step regardless of the operating frequency of the semiconductor device.

[0009] The present invention aims to provide a memory module comprising a memory controller capable of delaying a signal by a constant step regardless of the operating frequency of the memory device, and training the memory device using the signal delayed by the constant step. means of solving the problem

[0011] A delay control circuit according to an embodiment of the present invention comprises: a delay cell that includes a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, and activates a predetermined number of RC circuits among the plurality of first RC circuits according to the value of a step code input from the outside, and outputs a signal input from the outside by a delay time determined according to the number of activated RC circuits; and a ZQ calibrator that includes a plurality of pull-up circuits and a plurality of pull-down circuits, adjusts the impedance of a transmission line by adjusting the number of pull-up circuits and pull-down circuits among the plurality of pull-up circuits and the plurality of pull-down circuits, and inputs a pull-up voltage and a pull-down voltage determined based on a calibration code corresponding to the number of activated pull-up circuits and pull-down circuits to the plurality of bias inverters. The apparatus includes a first ring oscillator comprising a plurality of test delay cells having the same circuit structure as the delay cell, and a step adjustment unit that determines the component characteristics of the first and second RC circuits based on a pulse period that varies depending on whether the second RC circuits included in the first ring oscillator are activated, and activates at least some of the RC circuits among the second RC circuits based on the component characteristics and the operating frequency of the delay control circuit.

[0012] A delay control circuit according to an embodiment of the present invention comprises: a delay cell that includes a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, and which activates a predetermined number of RC circuits among the plurality of first RC circuits according to the value of a step code input from the outside, and outputs a signal input from the outside by a delay time determined according to the number of activated RC circuits; a ZQ calibrator that adjusts the impedance of a transmission line by adjusting the value of a ZQ calibration code and inputs a pull-up voltage and a pull-down voltage determined based on the ZQ calibration code to the plurality of bias inverters; and a step adjustment unit that determines the component characteristics of the second RC circuits based on a delay time that varies depending on whether the second RC circuits are activated, and determines the RC circuits among the second RC circuits to be activated according to the component characteristics and the operating frequency of the delay control circuit, thereby controlling the delay time of the delay cell to increase in a constant step independent of the operating frequency.

[0013] A memory module according to an embodiment of the present invention includes a memory device comprising a plurality of command / address pins; and a memory controller that inputs signals to the command / address pins, wherein the memory controller includes a delay cell that delays the input signal by a delay time determined according to the value of the input step code, and adjusts the delay cell so that the delay time increases in a constant step according to the value of the step code using a lookup table and a ZQ calibration code, and adjusts the timing of output of each of the signals so that the signals are simultaneously input to the command / address pins using the adjusted delay cell. Effects of the invention

[0015] A delay control circuit according to an embodiment of the present invention can control a delay cell to delay an input signal by compensating for the PVT characteristics of the delay cell based on a ZQ calibration code value.

[0016] A delay control circuit according to an embodiment of the present invention can determine the PVT characteristics of a delay cell using a ring oscillator including a plurality of delay cells, compensate for the PVT characteristics of the delay cell using a lookup table, and control the delay cell so that it can delay an input signal in a constant step regardless of the operating frequency of the semiconductor device.

[0017] A memory module according to an embodiment of the present invention may include a memory controller comprising a delay control circuit capable of delaying an input signal by a constant step regardless of the operating frequency of the memory device. The RCD controller can enable signals to be simultaneously input to the command / address pins of the memory device by training the memory device using the delay control circuit.

[0018] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0020] FIG. 1 is a diagram showing a delay control circuit according to an embodiment of the present invention. FIGS. 2a and 2b are drawings for explaining the circuit structure of a delay cell according to an embodiment of the present invention. FIG. 3a is a circuit diagram specifically showing an inverter according to an embodiment of the present invention. FIG. 3b is a circuit diagram specifically showing an RC circuit according to an embodiment of the present invention. FIG. 4 is a detailed drawing of a ZQ calibrator according to an embodiment of the present invention. FIGS. 5A and FIGS. 5B are drawings showing a step adjustment unit in detail according to an embodiment of the present invention. FIG. 6 is a timing diagram showing the operation timing of a step adjustment unit according to an embodiment of the present invention. FIG. 7 is a drawing showing a lookup table according to an embodiment of the present invention. FIGS. 8a to 8c are drawings for explaining the delay adjustment effect of a delay adjustment circuit according to an embodiment of the present invention. FIG. 9 is a drawing showing a memory module according to an embodiment of the present invention. Specific details for implementing the invention

[0021] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

[0022] FIG. 1 is a diagram showing a delay control circuit according to an embodiment of the present invention.

[0023] Referring to FIG. 1, the delay control circuit (10) may include a delay cell (100), a ZQ calibrator (200), and a step adjustment unit (300).

[0024] The delay cell (100) can delay an input signal (SIN) input from the outside by a delay time. The delay cell (100) can output the signal delayed by the said delay time to the outside as an output signal (SOUT).

[0025] The delay cell (100) can receive a step code (CODE[Z:0]) having a fixed number of bits from an external source so as to change the delay time. The delay cell (100) can increase the delay time as the bit value of the step code (CODE[Z:0]) increases.

[0026] Meanwhile, the delay control circuit (10) may be included in a semiconductor device having an input / output interface. The semiconductor device may perform training to adjust the data input / output timing of the interface, and the delay control circuit (10) may be used for training the interface.

[0027] In order to accurately train the above interface, it is required that the delay cell (100) be able to increase the delay time by a certain delay step as the bit value of the step code (CODE[Z:0]) increases. The size of the delay step may be independent of the operating frequency of the semiconductor device. For example, regardless of whether the operating frequency of the semiconductor device is 3200 Mbps or 6400 Mbps, it is required that the delay cell (100) be able to increase the delay time by 2.5 ps whenever the bit value of the step code (CODE[Z:0]) increases by '1'.

[0028] The delay cell (100) can be implemented using inverters and RC circuits. For example, the inverter may have a propagation delay, and the RC circuit may have an RC delay determined by a time constant. The delay cell (100) may have a delay time determined based on the propagation delay and the RC delay.

[0029] While it is difficult to reduce the propagation delay of individual inverters below a certain level, the time constant of individual RC circuits can be reduced to the required delay step level. Accordingly, the delay cell (100) can generate a reference delay using inverters, and can generate an additional delay by adjusting the number of activated RC circuits among multiple RC circuits having the same time constant based on a step code (CODE[Z:0]).

[0030] Meanwhile, even if the RC circuits included in the delay cell (100) have the same time constant, the delay time may increase non-linearly as the number of activated RC circuits increases. For example, as the number of activated RC circuits increases, the proportion of the RC delay of the RC circuits becomes greater than the full-wave delay of the inverter, so the delay time may increase rapidly as the number of activated RC circuits increases. Therefore, if the delay cell (100) is not corrected, it may be difficult to have a constant delay step.

[0031] In addition, the fact that the propagation delay and RC delay may vary when the PVT (Process, Voltage, Temperature) characteristics of the semiconductor device vary also makes it difficult for the delay cell (100) to have a constant delay step.

[0032] Additionally, if the delay control circuit (10) is controlled based on the operating frequency of the semiconductor device, it may be difficult for the delay cell (100) to have a delay step independent of the operating frequency.

[0033] According to an embodiment of the present invention, the delay control circuit (10) can control the delay cell (100) to have a delay step independent of the operating frequency and device characteristics by using a ZQ calibrator (200), a step adjustment unit (300), etc.

[0034] For example, the delay cell (100) can not only control the activation of RC circuits according to the step code (CODE[Z:0]), but also allow the delay time to increase linearly by adjusting the propagation delay of the inverter circuit.

[0035] Additionally, the delay cell (100) can compensate for the PVT characteristics of the device included in the delay cell (100) using a calibration code (ZQCAL[X:0]) output from the ZQ calibrator (200). The ZQ calibrator (200) can perform impedance adjustment so that impedance matching of the semiconductor device's transmission line is achieved despite changes in the device's PVT characteristics, and the calibration code (ZQCAL[X:0]) may be a code input for the impedance adjustment.

[0036] Additionally, the step adjustment unit (300) can output a trim code (TRIM[Y:0]) to the delay cell (100) to compensate for the PVT characteristics of the element included in the delay cell (100) and to control the delay cell (100) to have a delay step independent of the operating frequency. For example, the step adjustment unit (300) can control the delay cell (100) based on the PVT characteristics and operating frequency of the element by referring to a lookup table, thereby enabling the delay cell (100) to have a delay step independent of changes in PVT characteristics and operating frequency.

[0038] Hereinafter, a delay cell (100) according to an embodiment of the present invention is described in detail with reference to FIGS. 2a to 3b.

[0039] FIGS. 2a and 2b are drawings for explaining the circuit structure of a delay cell according to an embodiment of the present invention.

[0040] Referring to FIG. 2a, the delay cell (100) may include a plurality of sub-delay cells (101-104). Each of the sub-delay cells (101-104) may have the same circuit structure and may be connected in series with each other. That is, an input signal (SIN) may be input to the input terminal of the first sub-delay cell (101), and a delayed output signal (SOUT) may be output through the output terminal of the fourth sub-delay cell (104), and the remaining input terminals or output terminals of the sub-delay cells (101-104) may be connected to the output terminals or input terminals of adjacent sub-delay cells.

[0041] FIG. 2b is a circuit diagram showing the circuit structure of a sub-delay cell (101) in detail.

[0042] Referring to FIG. 2b, the sub-delay cell (101) may include a plurality of inverters (111, 112), a plurality of first RC circuits (121-124), and a plurality of second RC circuits (131-134).

[0043] A plurality of inverters (111, 112) can be controlled by a calibration code (ZQCAL[X:0]) described with reference to FIG. 1. The calibration code (ZQCAL[X:0]) is a signal generated by a ZQ calibrator (200) and may include a pull-up code and a pull-down code. The PVT characteristics of the plurality of inverters (111, 112) can be compensated by inputting a pull-up voltage (VPU) determined based on the pull-up code and a pull-down voltage (VPD) determined based on the pull-down code to the plurality of inverters (111, 112). An example of a more detailed circuit structure of the plurality of inverters (111, 112) will be described later with reference to FIG. 3a.

[0044] A plurality of first RC circuits (121-124) can be controlled by a step code (CODE[Z:0]) described with reference to FIG. 1. The step code (CODE[Z:0]) can control the number of first RC circuits activated in the delay cell (100). In the example of FIG. 2a and FIG. 2b, one sub-delay cell may include four first RC circuits, and the delay cell (100) including four sub-delay cells may include a total of 16 first RC circuits. In this case, the step code (CODE[Z:0]) may be composed of 4-bit data. The 4-bit data of the step code (CODE[Z:0]) can control the number of RC circuits activated among the 16 first RC circuits included in the delay cell (100). Specifically, the step code (CODE[Z:0]) can have a value from '0000' to '1111', and depending on the value of the step code (CODE[Z:0]), 0 to 16 first RC circuits can be activated.

[0045] According to an embodiment of the present invention, the delay cell (100) may further include a plurality of second RC circuits (131-134) that can be controlled by a trim code (TRIM[Y:0]) described with reference to FIG. 1. Similar to a step code (CODE[Z:0]), the trim code (TRIM[Y:0]) can control the number of second RC circuits activated in the delay cell (100). The trim code (TRIM[Y:0]) can be generated by a step adjustment unit (300) and can compensate for the PVT characteristics of the first RC circuits (121-124) and the second RC circuits (131-134), and control the delay cell (100) so that it can have a delay step of a size independent of the operating frequency.

[0046] The first RC circuits (121-124) and the second RC circuits (131-134) may have the same circuit structure and may have the same time constant. The structure of the first RC circuits (121-124) and the second RC circuits (131-134) will be described later with reference to FIG. 3b.

[0048] FIG. 3a is a circuit diagram specifically showing an inverter according to an embodiment of the present invention.

[0049] Referring to FIG. 3a, the first inverter (111) may include a plurality of transistors (TR1-TR6). The first and second transistors (TR1, TR2) may provide a basic circuit (INV) of the inverter that inverts the signal (IN) of the input terminal and outputs it to the output terminal (OUT). When the signal (IN) of the input terminal is inverted and output to the output terminal (OUT) in the basic circuit (INV), a propagation delay may occur between the signal (IN) of the input terminal and the signal (OUT) of the output terminal.

[0050] The third and fourth transistors (TR3, TR4) can adjust the magnitude of the propagation delay by controlling the amount of current flowing into the basic circuit (INV). Specifically, the amount of current flowing into the basic circuit (INV) can be controlled according to the magnitude of the positive bias voltage (VBP) applied to the gate of the third transistor (TR3) and the negative bias voltage (VBN) applied to the gate of the fourth transistor (TR4). An inverter capable of controlling the amount of current flowing into the basic circuit (INV) using bias voltages (VBP, VBN), such as the first inverter (111), may be referred to as a biased inverter.

[0051] According to an embodiment of the present invention, bias voltages (VBP, VBN) applied to the first inverter (111) can be determined according to a step code (CODE[Z:0]) input to the delay cell (100). Specifically, the bias voltages (VBP, VBN) can be determined in advance so that the delay time occurring in the delay cell (100) can increase linearly according to the step code (CODE[Z:0]).

[0052] For example, the delay control circuit (10) can increase the magnitude of the bias voltages (VBP, VBN) as the value of the step code (CODE[Z:0]) increases. Since the RC delay can increase as the value of the step code (CODE[Z:0]) increases, the proportion of the RC delay and the propagation delay can be maintained regardless of the value of the step code (CODE[Z:0]) by increasing the magnitude of the bias voltages (VBP, VBN).

[0053] According to an embodiment of the present invention, the first inverter (111) may further include fifth and sixth transistors (TR5, TR6) for compensating for the PVT characteristics of the device. The fifth transistor (TR5) may be connected in parallel with the third transistor (TR3), and the sixth transistor (TR6) may be connected in parallel with the fourth transistor (TR4). A pull-up voltage (VPU) and a pull-down voltage (VPD), determined based on a pull-up code and a pull-down code included in a calibration code (ZQCAL[X:0]), may be input to the fifth transistor (TR5) and the sixth transistor (TR6), respectively. The pull-up code and the pull-down code determined by the ZQ calibrator (200) may reflect the PVT characteristics of the device. In order for the pull-up voltage (VPU) and pull-down voltage (VPD) to compensate for the PVT characteristics of the first inverter (111), the relationship between the pull-up code and the pull-up voltage (VPU), and the relationship between the pull-down code and the pull-down voltage (VPD) can be determined in advance.

[0054] Meanwhile, other inverters included in the delay cell (100) may also have the same structure as the first inverter (111) described with reference to FIG. 3a.

[0055] FIG. 3b is a circuit diagram specifically showing an RC circuit according to an embodiment of the present invention.

[0056] Referring to FIG. 3b, the first RC circuit (121) may include a resistive component (R1) and a plurality of transistors (TR7-TR10). The first RC circuit (121) of FIG. 3b may correspond to the first RC circuit (121) of FIG. 2b, and the first RC circuit (121) of FIG. 3b shows the resistive component (R1) that is omitted in the first RC circuit (121) of FIG. 2b.

[0057] A first power supply voltage (VDD) may be applied to the active regions of the seventh transistor (TR7), and a second power supply voltage (VSS) lower than the first power supply voltage (VDD) may be applied to the active regions of the eighth transistor (TR8). That is, a voltage of the same magnitude may be applied to the active regions of the seventh and eighth transistors (TR7, TR8), respectively, and the seventh and eighth transistors (TR7, TR8) may function as MOS capacitors. The MOS capacitors and the resistive component (R1) may provide an RC delay.

[0058] The ninth and tenth transistors (TR9, TR10) can enable or disable the first RC circuit (121) by controlling the connection of the MOS capacitors and the resistive component (R1). For example, a signal (CODE[0]) based on a step code (CODE[Z:0]) can be input to the gate of the tenth transistor (TR10), and an inverted signal (CODEB[0]) of the signal (CODE[0]) can be input to the gate of the ninth transistor (TR9).

[0059] In FIG. 3b, the circuit structure of the RC circuits included in the delay cell (100) is described with the first RC circuit (121) as an example. The circuit structure shown in FIG. 3b can be applied to the first RC circuits and the second RC circuits included in the delay cell (100).

[0061] Hereinafter, with reference to FIGS. 4 to 7, a ZQ calibrator (200) and a step adjustment unit (300) that control the delay cell (100) to have a constant step delay are described in more detail.

[0062] FIG. 4 is a detailed drawing of a ZQ calibrator according to an embodiment of the present invention.

[0063] Referring to FIG. 4, the ZQ calibrator (200) may include a first pull-down unit (211), a first comparator (212), and a pull-down code engine (213) for generating a pull-down code, a second pull-down unit (221), a second comparator (222), a pull-up code engine (223), and a pull-up unit (224) for generating a pull-up code, and may include an oscillator (231) and a timer (232) for controlling the operation of generating a pull-down code and the operation of generating a pull-up code.

[0064] The oscillator (231) can generate a clock signal (ZQ_CLK) provided to the pull-down code engine (213) and the pull-up code engine (223) in response to an external start signal (ZQ_START). The timer (232) operates in response to the clock signal (ZQ_CLK) and can terminate the operation of the oscillator (231) by generating a termination signal (ZQ_END) when a set time has elapsed.

[0065] ZQ calibration refers to the process of generating an impedance code that changes as the component's PVT conditions vary. The calibration code generated as a result of ZQ calibration can be used to adjust the termination resistance value. Generally, the pad to which the external resistor serving as the calibration reference is connected is called the ZQ pad, and for this reason, the term ZQ calibration is commonly used.

[0066] In an initial state where ZQ calibration is not performed, the first pull-down unit (211), the first comparator (212), and the pull-down code engine (213) can perform a pull-down calibration operation using an external resistor (EXTR). Specifically, the first comparator (212) can receive the first divided voltage generated by the first pull-down unit (211) and the external resistor (EXTR) connected to the ZQ pad. The first comparator (212) can compare the first divided voltage with a reference voltage (Vref) and generate an up / down signal according to the comparison result. The reference voltage (Vref) may have a magnitude of VDDQ / 3 or VDDQ / 2.5, but the present invention is not limited thereto.

[0067] The pull-down code engine (213) can generate a pull-down code (PD_code) of a set number of bits in response to an up / down signal, which is the comparison result of the first comparator (212). Based on the pull-down code (PD_code), the pull-down units included in the first pull-down section (211) can be turned on or off, thereby adjusting the pull-down resistance value of the first pull-down section (211). For example, the first pull-down section (211) may include pull-down units connected in parallel with each other. The adjusted resistance value of the first pull-down section (211) can affect the first distribution voltage. Consequently, the pull-down calibration operation can be repeated until the resistance value of the first pull-down section (211) becomes equal to the resistance value of the external resistor (EXTR).

[0068] The pull-down code (PD_code) generated by the pull-down calibration operation can be input to the second pull-down unit (221). The pull-down resistance value of the second pull-down unit (221) can be determined by the pull-down code (PD_code). The second comparator (222), the pull-up code engine (223), and the pull-up unit (224) can perform a pull-up calibration operation based on the pull-down resistance value of the second pull-down unit (221). Similar to the pull-down calibration operation, the second comparator (222) can receive a second distribution voltage generated by the second pull-down unit (221) and the pull-up unit (224). The second comparator (222) can compare the second distribution voltage with a reference voltage (Vref) and output an up / down signal according to the comparison result.

[0069] The pull-up code engine (223) can generate a pull-up code (PU_code) having a set number of bits in response to an up / down signal, which is the comparison result of the second comparator (222). Based on the pull-up code (PU_code), the pull-up resistance value of the pull-up section (224) can be adjusted by turning on or off a plurality of pull-up units included in the pull-up section (224). The pull-up resistance value affects the second distribution voltage, and consequently, the pull-up calibration operation can be repeated until the magnitude of the second distribution voltage and the reference voltage (Vref) become equal.

[0070] When a ZQ calibration operation including a pull-down calibration operation and a pull-up calibration operation is performed, impedance matching of the transmission line of the semiconductor device including the delay control circuit (10) can be achieved.

[0071] The components included in the delay control circuit (10) can be manufactured in the same process and can operate under the same voltage and temperature conditions. Therefore, the PVT characteristics of the components included in the delay cell (100) can be compensated by using the pull-down code (PD_code) and pull-up code (PU_code) determined by the ZQ calibration operation. According to an embodiment of the present invention, the ZQ calibrator (200) can input the pull-down code (PD_code) and pull-up code (PU_code) to the delay cell (100). The pull-down code (PD_code) and pull-up code (PU_code) can be input to the pull-up circuit and pull-down circuit included in each of the inverters included in the delay cell (100). The PVT characteristics of the inverters can be compensated by the pull-down code (PD_code) and pull-up code (PU_code).

[0073] FIG. 5a is a drawing showing in detail a first example of a step adjustment unit according to an embodiment of the present invention.

[0074] Referring to FIG. 5a, the step adjustment unit (300) may include a ring oscillator (310), a pulse counter (320), a comparison circuit (330), and a lookup table (340).

[0075] The ring oscillator (310) may include a NAND gate and a plurality of test delay cells (311-31N). The test delay cells (311-31N) may have the same circuit structure as the delay cell (100) described with reference to FIGS. 2a and 2b. The test delay cells (311-31N) may be delay cells provided to test the delay cell (100). The area where the test delay cells (311-31N) are formed on the substrate of the semiconductor device may be a different area from the area where the delay cell (100) is formed. However, the test delay cells (311-31N) may be produced in the same process as the delay cell (100), and the test delay cells (311-31N) and the delay cell (100) may have the same PVT characteristics.

[0076] When the ring oscillator (310) includes N (N is a natural number) test delay cells (311-31N), the period of the pulse generated by the ring oscillator (310) may correspond to N times the delay time of a single delay cell. Specifically, while the start signal (TRN_START) input to the NAND gate of the ring oscillator (310) maintains a logic high state, the NAND gate may output an inverted signal of the signal input from the delay cell (31N). Since the test delay cells (311-31N) may include an even number of inverters, the signal output from the NAND gate may be input to the test delay cell (311), pass through N test delay cells (311-31N), and then be output in an uninverted state. When the uninverted signal is input to the NAND gate, the NAND gate may output an inverted signal. Accordingly, while the start signal (TRN_START) of the ring oscillator (310) maintains a logic high state, a pulse having a period corresponding to N times the delay time can be output. Meanwhile, the delay of the NAND gate can be small enough to be negligible.

[0077] Depending on the implementation, the number N of the test delay cells (311-31N) may be determined such that the period of the pulse output by the ring oscillator (310) is sufficiently larger than the operating period of the clock signal. For example, the ring oscillator (310) may include about 20 to 30 test delay cells, but the present invention is not limited thereto.

[0078] A pulse counter (320) can determine the period of a pulse output from a ring oscillator (310) using a clock signal having an operating frequency. For example, the pulse counter (320) can determine a pulse count by counting the number of rising or falling edges of the clock signal while the pulse maintains a logic high state. The pulse count can correspond to the period of the pulse.

[0079] The comparison circuit (330) can determine the PVT characteristics of the first and second RC circuits included in the test delay cells (311-31N) based on the pulse count determined by the pulse counter (320). The comparison circuit (330) can use the lookup table circuit (340) to determine the value of a trim code that allows the delay cell (100), which has the same characteristics as the PVT characteristics, to have a constant delay step regardless of the operating frequency of the delay adjustment circuit (10). The trim code can be input to the second RC circuits of the delay cell (100) to activate at least some of the RC circuits among the second RC circuits.

[0080] The lookup table circuit (340) can store information about the pulse count of the ring oscillator when the delay cell has a constant delay step, according to the PVT characteristics and according to the operating frequency of the delay adjustment circuit (10).

[0081] Meanwhile, in order for the comparison circuit (330) to determine the PVT characteristics of the first and second RC circuits, it may obtain two or more pulse counts for two or more cases in which the number of activated RC circuits among the second RC circuits included in the test delay cells (311-31N) is different. Depending on the implementation, the step adjustment unit (300) may include two or more ring oscillators and two or more counters that can operate in parallel with each other to quickly obtain the two or more pulse counts.

[0082] FIG. 5b is a drawing showing in detail a second example of a step adjustment unit according to an embodiment of the present invention.

[0083] Referring to FIG. 5b, the step adjustment unit (300a) may include a plurality of ring oscillators (310, 310a), a plurality of counters (320, 320a), a comparison circuit (330), and a lookup table circuit (340). The first ring oscillator (310), the first counter (320), the comparison circuit (330), and the lookup table circuit (340) shown in FIG. 5b may correspond to the ring oscillator (310), the counter (320), the comparison circuit (330), and the lookup table circuit (340) described with reference to FIG. 5a.

[0084] The step adjustment unit (300a) may include a second ring oscillator (310a) having the same circuit structure as the first ring oscillator (310) and a second counter (320a) having the same circuit structure as the first counter (320).

[0085] The delay control circuit (100) can activate all second RC circuits included in the first ring oscillator (310) and deactivate all second RC circuits included in the second ring oscillator (310a). The delay time of the test delay cell may vary depending on whether the second RC circuits of the test delay cell are activated. Consequently, the period of the pulse output from the first ring oscillator (310) and the period of the pulse output from the second ring oscillator (310a) may be different.

[0086] In FIG. 5b, the pulse output from the first ring oscillator (310) is shown as the maximum pulse (MAX_Pulse), and the pulse output from the second ring oscillator (310a) is shown as the minimum pulse (MIN_Pulse).

[0087] The first counter (320) can determine the maximum pulse period, which is the period of the maximum pulse (MAX_Pulse), using a clock signal, and the second counter (320a) can determine the minimum pulse period, which is the period of the minimum pulse (MIN_Pulse), using a clock signal.

[0088] The maximum pulse period from the first counter (320) and the minimum pulse period from the second counter (320a) can be input to the comparison circuit (330) as a training input signal (TRN_IN) and used to determine the PVT characteristics of the second RC circuit.

[0089] Below, the operation of the step adjustment unit (300a) described with reference to FIG. 5b is explained in detail with reference to FIG. 6.

[0091] FIG. 6 is a timing diagram showing the operation timing of a step adjustment unit according to an embodiment of the present invention.

[0092] FIG. 6 illustrates the timing of a start signal (TRN_START), a clock signal (Clock), a pulse period (MIN_Pulse, MAX_Pulse), a pulse count signal (MIN_CNT, MAX_CNT) corresponding to the pulse period, and a training input signal (TRN_IN).

[0093] When the start signal (TRN_START) changes to a logic high state, the ring oscillators (310, 310a) can oscillate and output a pulse. FIG. 6 illustrates a case where the ring oscillators (310, 310a) output a pulse from a first time point (t1).

[0094] FIG. 6 illustrates the timing of the maximum pulse (MAX_Pulse) output from the first ring oscillator (310) and the minimum pulse (MIN_Pulse) output from the second ring oscillator (310a). The maximum pulse period may correspond to N times the delay time when all of the second RC circuits of one delay cell are activated, and the minimum pulse period may correspond to N times the delay time when all of the second RC circuits of one delay cell are deactivated.

[0095] A plurality of counters (320, 320a) can determine a maximum pulse count (MAX_CNT) and a minimum pulse count (MIN_CNT) using a clock signal (Clock) having an operating frequency. Specifically, the second counter (320a) can count the number of occurrences of a rising edge of the clock signal (Clock) as the minimum pulse count (MIN_CNT) while the minimum pulse (MIN_Pulse) maintains a logic high state. The minimum pulse (MIN_Pulse) can maintain a logic high state from a first time point (t1) to a second time point (t2), and the minimum pulse count (MIN_CNT) can be determined as '13'.

[0096] Likewise, the first counter (320) can count the number of occurrences of the rising edge of the clock signal (Clock) as the maximum pulse count (MAX_CNT) while the maximum pulse (MAX_Pulse) maintains a logic high state. The maximum pulse (MAX_Pulse) can maintain a logic high state from the first time point (t1) to the third time point (t3), and the maximum pulse count (MAX_CNT) can be determined to be '19'.

[0097] Depending on the implementation, the first and second counters (320, 320a) may count the maximum pulse count (MAX_CNT) and the minimum pulse count (MIN_CNT) when the maximum pulse (MAX_Pulse) and the minimum pulse (MIN_Pulse) are in a logic low state.

[0098] The comparison circuit (330) can determine the PVT characteristics of the first and second RC circuits using the maximum pulse count (MAX_CNT) and the minimum pulse count (MIN_CNT). For example, the PVT characteristics of the first and second RC circuits can be determined as 'Fast', 'Typ', or 'Slow'.

[0099] A fast PVT characteristic of the device can be described as the device responding sensitively to external conditions. For example, the faster the PVT characteristic of the second RC circuits, the greater the pulse period can increase as the number of activated second RC circuits increases. Since the PVT characteristic of the first RC circuits may also be fast when the PVT characteristic of the second RC circuits is fast, the faster the PVT characteristic of the second RC circuits, the larger the maximum pulse count value and the minimum pulse count value may become, and the difference between the maximum pulse count value and the minimum pulse count value may also widen.

[0100] Meanwhile, the present invention is not limited to the PVT characteristics of RC circuits being determined as 'Fast', 'Typ', or 'Slow', and the PVT characteristics may be further subdivided or determined as continuous values.

[0101] Information indicating the relationship between the pulse count and the element characteristics may be stored in advance in the step adjustment unit (300). The comparison circuit (330) can determine the PVT characteristics of the second RC circuits by comparing the maximum pulse count value and the minimum pulse count value obtained from the counter with the information. Meanwhile, the information may be stored in the form of a lookup table circuit, but the present invention is not limited thereto.

[0102] When the PVT characteristics of the first and second RC circuits are determined, the comparison circuit (330) can determine the number of second RC circuits to be activated in the delay cell (100) by referring to the lookup table circuit (340).

[0104] FIG. 7 is a drawing showing a lookup table according to an embodiment of the present invention.

[0105] Referring to FIG. 7, the lookup table circuit (340) can store reference pulse count information according to the PVT characteristics and operating frequency of the RC circuit. The reference pulse count may refer to the count of pulses that can be output from the ring oscillator when the delay time between the case where all first RC circuits of the delay cell are activated and the case where all first RC circuits are deactivated is adjusted to have a predetermined difference. The predetermined difference may be determined based on the required delay step and the number of first RC circuits included in the delay cell. For example, if 16 first RC circuits are included in the delay cell (100) and the required delay step is 2.5 ps, the predetermined difference may be 40 ps (= 16 * 2.5 ps). The reference pulse count may be determined experimentally.

[0106] The comparison circuit (330) can determine a reference pulse count based on the PVT characteristics and operating frequency of the RC circuit using the lookup table circuit (340). The comparison circuit (330) can adjust the number of activated RC circuits among the second RC circuits included in the ring oscillator (310) and count the period of the pulse output from the ring oscillator (310). The comparison circuit (330) can generate a trim code (TRIM[Y:0]) based on the number of activated second RC circuits when the count of the pulse output from the ring oscillator (310) matches the reference pulse count. The trim code (TRIM[Y:0]) can be input to the delay cell (100) to control the number of second RC circuits activated in the delay cell (100), and the size of the delay step according to the step code (CODE[Z:0]) in the delay cell (100) can be determined independently of the operating frequency and the PVT characteristics of the RC circuit.

[0108] FIGS. 8a to 8c are drawings for explaining the delay adjustment effect of a delay adjustment circuit according to an embodiment of the present invention.

[0109] FIG. 8a is a graph showing the delay according to the PVT characteristics of the device when the delay of the delay cell (100) is not adjusted.

[0110] The horizontal axis of the graph in FIG. 8a represents the value of the step code, and the vertical axis represents the relative delay time according to the step code. That is, based on the delay time when the value of the step code is '0', it represents the delay time that increases as the value of the step code increases. As the value of the step code increases, the number of activated first RC circuits may increase.

[0111] Even if the first RC circuits included in the delay cell have the same time constant, the delay time may increase non-linearly as the value of the step code increases. Referring to FIG. 8a, the delay time may increase rapidly as the number of activated first RC circuits increases.

[0112] The graph in FIG. 8a illustrates the delay time for each case where the device characteristics are fast (Fast), typical (Typical), and slow (Slow). As the device characteristics become faster, the delay time can increase rapidly as the number of first RC circuits increases.

[0113] For interface training of a semiconductor device, it is required that the delay time increase linearly as the step code increases. FIG. 8a illustrates the range of relative delay times required according to the value of the step code as a PASS Zone.

[0114] If the linearity of the delay of the delay cell (100) is not corrected, the delay time increases non-linearly depending on the step code value, so the delay time goes out of the pass zone at most step code values.

[0115] FIG. 8b is a graph showing the delay according to the PVT characteristics of the device in a state where the linearity of the delay of the delay cell (100) is corrected.

[0116] The horizontal axis of the graph in FIG. 8b represents the value of the step code, and the vertical axis represents the relative delay time according to the step code. Referring to FIG. 8b, the delay time can increase linearly as the value of the step code increases.

[0117] According to an embodiment of the present invention, the inverters included in the delay cell (100) may be bias inverters, and the delay control circuit (10) can correct the linearity of the delay time by applying bias voltages determined according to a step code to the bias inverters.

[0118] For example, the delay control circuit (10) can increase the bias voltages applied to the bias inverters as the value of the step code increases. As the value of the step code increases, the RC delay can increase, and by increasing the bias voltages, the propagation delay of the inverter can be made larger, thereby maintaining a constant ratio of RC delay and propagation delay regardless of the value of the step code.

[0119] The graph in FIG. 8b illustrates the delay times for fast, typical, and slow device characteristics, respectively. Referring to FIG. 8b, when the device characteristics are typical, the relative delay time for all step code values ​​may fall within the pass zone. However, when the device characteristics are fast or slow, the delay time may fall outside the pass zone as the step code value increases. In other words, there are cases where the required delay step cannot be achieved by correcting only the linearity of the delay time.

[0120] FIG. 8c is a graph showing the delay according to the PVT characteristics of the device when the linearity of the delay time of the delay cell (100) is corrected and the device characteristics are compensated.

[0121] The horizontal axis of the graph in FIG. 8c represents the value of the step code, and the vertical axis represents the relative delay time according to the step code. Referring to FIG. 8c, the delay time according to the value of the step code can fall within the pass zone in cases where the device characteristics are fast, normal, or slow.

[0122] According to an embodiment of the present invention, the delay control circuit (10) can compensate for the component characteristics of the inverter included in the delay cell (100) using a calibration code generated by the ZQ calibrator (200). Additionally, the delay control circuit (10) can determine the number of activated RC circuits among the second RC circuits included in the delay cell (100) based on the component characteristics and operating frequency. Accordingly, the delay control circuit (10) can cause the delay cell (100) to have a predetermined delay step regardless of the component characteristics and operating frequency.

[0124] FIG. 9 is a drawing showing a memory module according to an embodiment of the present invention.

[0125] Referring to FIG. 9, the memory module (400) may include a plurality of memory devices (410), an RCD (Registering Clock Driver) controller (420), and signal pins (330). The memory devices (410), the RCD controller (420), and the signal pins (330) may be mounted on a module substrate (405).

[0126] Each memory device (410) can exchange data signals (DQ) and data strobe signals (DQS) with an external device, such as a host, through signal pins (330).

[0127] The RCD controller (420) can transmit a buffered command (CMD), address (ADDR), and clock signal (CK) received from an external device to each memory device (410). The RCD controller (420) may include an input / output interface (not shown) for receiving signals from an external device.

[0128] The RCD controller (420) can provide a command (CMD) and an address (ADDR) to each memory device (410) through a plurality of command / address pins (not shown) included in each memory device (410). For each of the plurality of command / address pins, the length of the signal path through which the command / address signals are transmitted may differ. Nevertheless, the memory device (410) can be trained so that command / address signals can be input to the plurality of command / address pins almost simultaneously.

[0129] According to an embodiment of the present invention, the RCD controller (420) may include a delay cell capable of delaying each of the command / address signals received from a host by a predetermined delay time and outputting them to a plurality of command / address pins. The delay cell may delay the input signal by a delay time determined according to the value of the input step code. The timing of the command / address signals being output to a plurality of command / address pins may be adjusted according to the value of the step code.

[0130] In order to accurately train the memory device (410), it is preferable that the delay cell be corrected so that the delay time increases by the required delay step as the value of the step code increases.

[0131] According to an embodiment of the present invention, the RCD controller (420) can adjust the delay cell so that the delay time increases by a constant delay step according to the value of the step code using a lookup table and a ZQ calibration code. The delay step may have a constant value regardless of the operating frequency of the RCD controller (420), for example, the frequency of the clock signal (CK). Accordingly, the RCD controller (420) can accurately train the memory device (410) and improve the reliability of the operation of the memory device (410) by enabling the memory device (410) to accurately receive the command / address signal output to the memory device (410).

[0132] Meanwhile, if a command (CMD) and an address (ADDR) are received from a host while the RCD controller (420) is adjusting the delay cell, the response speed to the host's command (CMD) may be delayed because the command (CMD) and address (ADDR) from the host cannot be processed until the adjustment of the delay cell is completed.

[0133] The RCD controller (420) can train the input / output interface to receive a command (CMD), an address (ADDR), and a clock signal (CK) from the host. According to an embodiment of the present invention, the RCD controller (420) can adjust the delay cell while training the input / output interface in response to the control of the host. Since the host may not provide the command (CMD) and the address (ADDR) while training the input / output interface by the host, the response speed to the command (CMD) from the host can be prevented from being delayed.

[0135] Meanwhile, the above-described contents of the present invention are merely specific embodiments for carrying out the invention. The present invention will include not only the concrete and practically usable means themselves, but also technical ideas that are abstract and conceptual ideas that can be utilized as technology in the future. Explanation of the symbols

[0137] 10: Delay adjustment circuit 100: Delay cell 200: ZQ Calibrator 300: Step control unit 400: Memory module

Claims

Claim 1 A delay control circuit comprising a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, wherein a delay cell that activates a predetermined number of RC circuits among the plurality of first RC circuits according to the value of a step code input from the outside, and outputs a signal input from the outside by a delay time determined according to the number of activated RC circuits; and a ZQ calibrator comprising a plurality of pull-up circuits and a plurality of pull-down circuits, which adjusts the impedance of a transmission line by adjusting the number of pull-up circuits and pull-down circuits among the plurality of pull-up circuits and the plurality of pull-down circuits, and inputs a pull-up voltage and a pull-down voltage determined based on a calibration code corresponding to the number of activated pull-up circuits and pull-down circuits to the plurality of bias inverters. A delay control circuit comprising a first ring oscillator including a plurality of test delay cells having the same circuit structure as the delay cell, a step adjustment unit that determines the component characteristics of the first and second RC circuits based on a pulse period that varies depending on whether the second RC circuits included in the first ring oscillator are activated, and activates at least some of the RC circuits among the second RC circuits based on the component characteristics and the operating frequency of the delay control circuit. Claim 2 In claim 1, the delay control circuit further applies bias voltages determined according to the value of the step code to the plurality of bias inverters. Claim 3 In paragraph 2, the delay control circuit wherein the bias voltages are predetermined to a value such that the delay time increases linearly as the value of the step code input to the delay cell increases. Claim 4 In paragraph 2, each of the plurality of bias inverters comprises a delay control circuit including a first transistor and a second transistor providing a basic circuit for inverting a signal at an input terminal and outputting it to an output terminal, a third transistor having a first power supply voltage applied to its source and a drain connected to the first transistor, and a first bias voltage among the bias voltages applied to its gate, and a fourth transistor having a second power supply voltage lower than the first power supply voltage applied to its source and a drain connected to the second transistor, and a second bias voltage among the bias voltages applied to its gate. Claim 5 In claim 4, each of the plurality of bias circuits further comprises a fifth transistor to which the pull-up voltage is applied, which is connected to a first power supply supplying the first power supply voltage and the first transistor, and a sixth transistor to which the pull-down voltage is applied, which is connected to a second power supply supplying the second power supply voltage and the second transistor. Claim 6 In claim 1, each of the plurality of first and second RC circuits comprises a resistor between an input terminal and an output terminal, a seventh transistor to which a first power supply voltage is applied to active regions, an eighth transistor to which a second power supply voltage lower than the first power supply voltage is applied to active regions, a ninth transistor to which a source is connected to the gate of the seventh transistor and a drain is connected to the output terminal, and a tenth transistor to which a source is connected to the gate of the eighth transistor and a drain is connected to the output terminal, and a delay control circuit to which an activation signal based on the step code is input to the gates of the ninth and tenth transistors. Claim 7 In claim 1, the step adjustment unit controls the delay time to increase by a constant delay step according to the step code input from the outside by activating at least some of the RC circuits, and the delay step is a delay control circuit independent of the operating frequency of the delay control circuit. Claim 8 In claim 1, the step adjustment unit further comprises: a counter for determining a maximum pulse count corresponding to a pulse period when all second RC circuits included in the first ring oscillator are activated, and a minimum pulse count corresponding to a pulse period when all second RC circuits are deactivated; a comparison circuit for determining the component characteristics of the second RC circuits based on the maximum pulse count and the minimum pulse count; and a lookup table for storing a reference pulse period for each component characteristic and operating frequency such that a first delay time when the value of the step code is a minimum value and a second delay time when the value of the step code is a maximum value have a predetermined difference; wherein the comparison circuit determines the reference pulse period by referring to the lookup table, determines a trim code by activating at least some of the RC circuits among the second RC circuits of the first ring oscillator so that the first ring oscillator has a reference pulse period, and activates at least some of the RC circuits among the second RC circuits of the delay cell by inputting the trim code to the second RC circuits of the delay cell. Circuit. Claim 9 A delay control circuit comprising: a delay cell that includes a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, which activates a predetermined number of RC circuits among the plurality of first RC circuits according to the value of a step code input from the outside, and outputs a signal input from the outside by a delay time determined according to the number of activated RC circuits; a ZQ calibrator that adjusts the impedance of a transmission line by adjusting the value of a ZQ calibration code and inputs a pull-up voltage and a pull-down voltage determined based on the ZQ calibration code to the plurality of bias inverters; and a step adjustment unit that determines the component characteristics of the second RC circuits based on a delay time that varies depending on whether the second RC circuits are activated, and determines the RC circuits among the second RC circuits to be activated according to the component characteristics and the operating frequency of the delay control circuit, thereby controlling the delay time of the delay cell to increase in a constant step independent of the operating frequency. Claim 10 A memory module comprises: a memory device including a plurality of command / address pins; and a memory controller that inputs signals to the command / address pins, wherein the memory controller includes a delay cell that delays the input signal by a delay time determined according to the value of the input step code, and adjusts the delay cell so that the delay time increases in a constant step according to the value of the step code using a lookup table and a ZQ calibration code, and adjusts the timing of output of each of the signals so that the signals are simultaneously input to the command / address pins using the adjusted delay cell, and wherein the lookup table stores reference pulse count information according to the operating frequency and the PVT characteristics of the RC circuit.

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