Package substrate, processing method of package substrate and package chip

Abstract

(Project) Provides a package substrate capable of relaxing the precision of the depth of cut. (Solution) The package substrate comprises a metal lead frame having a first frame portion on a grid along a planned division line and a plurality of first electrode portions extending from the first frame portion, a second frame portion on a grid along a planned division line and a plurality of second electrode portions extending from the second frame portion, and a connection frame that overlaps on the side where the device chip of the lead frame is formed and arranged, and a mold resin (12) covering the device chip and the connection frame. The tip of the second electrode portion is formed in a convex shape and is connected to the first electrode portion, and the connection frame forms an electrode when an electroplating treatment is performed on the cut surface of the first electrode portion formed by cutting the first electrode portion from the first frame portion.

Description

Technology Field

[0001] The present invention relates to a package substrate, a method for processing a package substrate, and a package chip. Background Technology

[0002] A package substrate (QFN package substrate) is used in which a semiconductor device chip is mounted on a metal frame (lead frame) and encapsulated with mold resin. On the surface of the QFN package substrate, a plurality of electrodes, generally formed of copper (Cu), are formed so as to be exposed along a planned division line (street). Each of the plurality of electrodes is connected to the device chip inside the QFN package substrate via a wire or the like.

[0003] A QFN package chip is formed by dividing a plurality of electrodes along a planned dividing line with a cutting blade and cutting the QFN package substrate (see, for example, Patent Document 1). On the side of the QFN package chip formed in this way, a copper electrode is exposed. Prior art literature

[0004] Japanese Patent Publication No. 2018-206995 The problem to be solved

[0005] Copper electrodes are prone to oxidation, and once oxidized, their solder wetting properties deteriorate. When solder wetting properties deteriorate, it becomes difficult for the electrodes of a QFN package chip to be fixed to a wiring board, such as a printed circuit board, via solder.

[0006] Therefore, to prevent the deterioration of solder wetting characteristics, a so-called wettable flank is known in which plating is performed on at least the portion of the copper electrode exposed to the side of the QFN package chip. By performing plating, the mechanical strength of the solder joint between the copper electrode and the wiring board is strengthened. In this case, the electrode is half-cut with a cutting blade to form a side on the electrode, and then, after plating is performed on the surface and side of the electrode, the center of the cutting groove is cut with a thin blade to divide it into individual package chips.

[0007] However, when the electrode is half-cut to a predetermined depth, there were many challenges, such as the difficulty in forming a groove with a high-precision cutting depth because the package substrate has thickness variations or warping, and the tendency for the cutting blade to clog or the electrode (metal) to burr to form when the metal is half-cut.

[0008] Accordingly, the objective of the present invention is to provide a package substrate capable of relaxing the precision of the depth of cut, a method for processing the package substrate, and a package chip. means of solving the problem

[0009] According to one aspect of the present invention, a package substrate is provided having a device chip mounted on a frame and coated with a mold resin, comprising: a metal lead frame having a grid-like first frame portion along a planned division line that partitions a support portion where the device chip is placed, and a plurality of first electrode portions extending to both sides from the first frame portion; a connection frame having a grid-like second frame portion along the planned division line and a plurality of second electrode portions extending to both sides from the second frame portion, and a connection frame that overlaps the side of the lead frame where the device chip is placed and formed; and the mold resin covering the device chip and the connection frame that are electrically connected to and formed with the first electrode portion of the lead frame. The tip of the second electrode portion is formed in a convex shape and is connected to the first electrode portion of the lead frame, and the connection frame forms an electrode when an electroplating treatment is performed on the cross-section of the first electrode portion formed by cutting the first electrode portion from the first frame portion.

[0010] According to another aspect of the present invention, a method for processing a package substrate in which a device chip mounted on a frame is coated with a mold resin comprises: a metal lead frame having a grid-like first frame portion along a planned division line partitioning a support portion where the device chip is placed, and a plurality of first electrode portions extending to both sides from the first frame portion; a connection frame having a grid-like second frame portion along the planned division line and a plurality of second electrode portions extending to both sides from the second frame portion, and which overlaps the side of the lead frame where the device chip is placed and formed; and a mold resin covering the device chip and the connection frame that are electrically connected to and formed with the first electrode portion of the lead frame. The method for processing the package substrate comprises cutting a first cutting blade along the planned division line on the surface side where the lead frame of the package substrate is exposed into the first frame portion of the lead frame, forming a cutting groove of a depth that does not reach the connection frame covered with the mold resin, and cutting the first frame portion to cut the first A method for processing a package substrate is provided, comprising: a cutting groove forming step in which the cutting surface of an electrode portion is exposed to the cutting groove; a plating treatment step in which, after performing the cutting groove forming step, voltage is applied to the first electrode portion cut by interposing the connection frame and the exposed surface of the first electrode portion is coated with a plating layer by electroplating; a dividing step in which, after performing the plating treatment step, the center of the cutting groove is cut with a second cutting blade thinner than the first cutting blade, and the connection frame and the mold resin are cut to divide into individual package chips; and a solder fixing step in which the surface side of the package chip is placed facing a wiring board of a mounting location and the plated first electrode portion of the package chip is connected to the electrode of the wiring board by solder.

[0011] According to another aspect of the present invention, a package chip is provided in which a device chip mounted on a support portion of a metal lead frame is coated with a mold resin, wherein the surface of the package chip where the support portion is exposed and the side of the package chip are connected by a step portion of a predetermined height and width, a first electrode portion of the lead frame electrically connected to the device chip is exposed on the surface and the side extending to the surface of the step portion, and on the side extending from the step portion to the back surface of the package chip, the cross-section of a second electrode portion of a connection frame connected to the first electrode portion is exposed, the first electrode portion is coated with a plating layer, and the second electrode portion of the connection frame is not coated with a plating layer. Effects of the invention

[0012] According to each aspect of the present invention, the effect of being able to relax the precision of the depth of cut is achieved. Brief explanation of the drawing

[0013] FIG. 1 is a plan view schematically showing a package substrate related to a first embodiment. Figure 2 is a side view of the package substrate shown in Figure 1. Figure 3 is a plan view of the back side of the package substrate shown in Figure 1. FIG. 4 is a perspective view schematically showing a package chip obtained by dividing the package substrate shown in FIG. 1. FIG. 5 is a plan view showing the main part of the lead frame constituting the frame of the package substrate shown in FIG. 1. FIG. 6 is a plan view showing the main part of the connection frame constituting the frame of the package substrate shown in FIG. 1. FIG. 7 is a plan view showing the main part of the frame of the package substrate shown in FIG. 1. FIG. 8 is a cross-sectional view along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view showing a state in which a device chip is mounted on the frame shown in FIG. 8. FIG. 10 is a cross-sectional view showing the state in which the device chip shown in FIG. 9 is coated with mold resin. FIG. 11 is a flowchart showing the flow of a processing method for a package substrate related to a first embodiment. FIG. 12 is a cross-sectional view schematically showing the cutting groove forming step of the processing method of the package substrate shown in FIG. 11. FIG. 13 is a cross-sectional view schematically showing a package substrate after the plating process step of the processing method of the package substrate shown in FIG. 11. FIG. 14 is a cross-sectional view schematically showing the divided steps of the processing method of the package substrate shown in FIG. 11. FIG. 15 is a cross-sectional view schematically showing the solder fixing step of the processing method of the package substrate shown in FIG. 11. Specific details for implementing the invention

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not limited by the contents described in the embodiments below. Furthermore, the components described below include those that can be easily conceived by those skilled in the art and are substantially identical. Additionally, the configurations described below can be appropriately combined. Furthermore, various omissions, substitutions, or changes to the configurations may be made within the scope of not departing from the gist of the present invention.

[0015] [First Embodiment]

[0016] A package substrate, a method for processing the package substrate, and a package chip related to a first embodiment of the present invention will be described based on the drawings. FIG. 1 is a schematic plan view showing a package substrate related to a first embodiment. FIG. 2 is a side view of the package substrate shown in FIG. 1. FIG. 3 is a plan view of the back side of the package substrate shown in FIG. 1. FIG. 4 is a schematic perspective view showing a package chip obtained by dividing the package substrate shown in FIG. 1. FIG. 5 is a plan view showing a main part of a lead frame constituting the frame of the package substrate shown in FIG. 1. FIG. 6 is a plan view showing a main part of a connection frame constituting the frame of the package substrate shown in FIG. 1. FIG. 7 is a plan view showing a main part of the frame of the package substrate shown in FIG. 1. FIG. 8 is a cross-sectional view along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view showing a state in which a device chip is mounted on a frame shown in FIG. 8. FIG. 10 is a cross-sectional view showing a state in which the device chip shown in FIG. 9 is coated with mold resin.

[0017] (Package substrate)

[0018] The package substrate (1) shown in FIGS. 1, 2 and 3 related to the first embodiment is divided into individual package chips (2) shown in FIG. 4 by performing cutting processes, etc. The package substrate (1) is a so-called QFN (Quad Flat Non-leaded Package) package substrate in which a device chip (8) mounted on a metal frame (3) is coated with mold resin (12).

[0019] The package substrate (1) related to the first embodiment is formed as a flat plate with a rectangular planar shape, as shown in FIG. 1. The package substrate (1) has a rectangular flat plate frame (3), and the frame (3) has a device region (4) and an outer surplus region (5) surrounding the device region (4). The frame (3) is made of a metal such as a metal containing copper (i.e., a copper alloy).

[0020] In the device area (4), a plurality of intersecting lines (6) are set. One of the intersecting lines (6) extends in a direction parallel to the long direction of the frame (3), and the other line extends in a direction orthogonal to the long direction of the frame (3) and also parallel to the width direction of the frame (3). A device chip (8) is formed and arranged in a support portion (7) partitioned by these intersecting lines (6). The lines (6) are set to penetrate the frame (3). The support portion (7) is formed by a part of the frame (3), and the device chip (8) is formed and arranged on the back side (10) (shown in FIG. 3, etc.) opposite to the surface (9). In addition, the surface (9) of the frame (3) is also the surface (9) of the package substrate (1) and the package chip (2). In each planned split line (6), an electrode (11) is formed to connect the package chip (2) to a wiring substrate, etc.

[0021] The electrode (11) is formed by a part of the frame (3), and in the first embodiment, each is formed in a straight line in a direction orthogonal to each planned division line (6), and is formed at the center of the width direction of each planned division line (6). The electrode (11) is connected to the device chip (8) by a wire (18) shown in FIG. 9, etc.

[0022] In the first embodiment, the device area (4) is formed in a plurality (three in the first embodiment) spaced apart along the long direction of the frame (3). The outer surplus area (5) is an area where the device chip (8) is not formed, and is formed by the frame (3), encircling the entire perimeter of each device area (4) and connecting adjacent device areas (4).

[0023] Additionally, the package substrate (1) is provided with a mold resin (12) that encloses (covers) the back side (10) of each device region (4), as shown in FIGS. 2 and 3. The mold resin (12) is composed of a thermoplastic resin and encloses (covers) the device chip (8) and wire (18) formed on the back side (10) of the support portion (7) of the frame (3), and is filled within the planned division line (6). On the back side (10) of the frame (3), the mold resin (12) encloses (covers) the entire device region (4). On the surface side (9) of the frame (3), the mold resin (12) encloses the support portion (7) where the device chip (8) is formed and the planned division line (6) while exposing the electrode (11).

[0024] The package substrate (1) is divided into individual package chips (2) shown in FIG. 4 by cutting the center of each planned division line (6) of each device area (4) in the width direction. In this way, the package substrate (1) related to the first embodiment is a QFN package substrate in which an electrode (11) made of metal is arranged on the planned division line (6). However, it is not limited to this, and the package substrate (1) may be a CSP (Chip Scale Packaging) substrate, etc. Also, in the first embodiment, the package chips (2) divided from the package substrate (1) are small chips with a chip size of about 1 mm × 1 mm for each side length.

[0025] In addition, in the first embodiment, the package substrate (1) has alignment marks (13) formed at both ends of the planned division line (6) on the surface (9) of the frame (3) to indicate the cutting position of the planned division line (6) during cutting process, as shown in FIG. 1. In the first embodiment, the alignment marks (13) are positioned at the center of the width direction of each planned division line (6) and at the positions of both ends along the length direction of each planned division line (6).

[0026] A package chip (2) manufactured by dividing a package substrate (1) has a device chip (8) mounted on a support (7) of a metal frame (3) coated with a mold resin (12). As shown in FIG. 4, the package chip (2) comprises a support (7) of a frame (3), a device chip (8) formed and disposed on the back surface (10) of the support (7), an electrode (11), and a mold resin (12). The mold resin (12) encapsulates the device chip (8), etc., with the surface (9) of the support (7) and the electrode (11) exposed.

[0027] Also, in the package chip (2) of the first embodiment, the surface (9) of the package chip (2) in which the support portion (7) is exposed and each side (14) of the package chip (2) are connected by a stepped portion (15) of a predetermined width and height. The stepped portion (15) is formed to connect with all sides (14) over the entire perimeter of the surface (9). The stepped portion (15) is formed on the side of the surface (9) and has a flat second side (151) that is parallel to the side (14) and also orthogonal to both the surface (9) and the back side (10), a flat surface (152) that is continuous with the second side (151) and the side (14), and a connecting portion that connects the second side (151) and the flat surface (152). The flat surface (152) is formed flat along both the surface (9) and the back surface (10). The height of the stepped portion (15) is set in advance during the design stage, etc., and is determined to a predetermined depth that is smaller than the thickness of the electrode (11).

[0028] Additionally, the package chip (2) has a plating layer (16) made of metal (shown in FIG. 13) on the surface of the electrode (11). The plating layer (16) improves the wettability of the electrode (11) of the solder (22) (shown in FIG. 15) that fixes the package chip (2) to the wiring board (20) (shown in FIG. 15). The package chip (2) is mounted on the wiring board (20) by fixing the electrode (11) to the electrode (21) of the wiring board (20) by the solder (22). Also, in FIG. 4, the plating layer (16) is omitted.

[0029] Additionally, the frame (3) of the package substrate (1) related to the first embodiment is provided with a lead frame (31) and a connection frame (32) overlapping the lead frame (31), as shown in FIG. 2. The lead frame (31) and the connection frame (32) are made of a metal such as a metal containing copper (i.e., a copper alloy), i.e., they are made of metal. Also, the same reference numerals are used for parts of the lead frame (31) and the connection frame (32) that are identical to the frame (3), and the description is omitted. The lead frame (31) is positioned on the surface (9) side of the frame (3), and the connection frame (32) is positioned on the back side (10) of the frame (3).

[0030] As shown in FIG. 5, the lead frame (31) integrally comprises a plurality of support members (7), a plurality of first frame members (33), a plurality of first electrode members (34), and an unillustrated surplus area member that constitutes an outer surplus area (5). The first frame members (33) are formed in a grid shape along a planned division line (6) that divides the support members (7) on which the device chip (8) is placed. The first frame members (33) are arranged around each support member (7). Also, in FIG. 1, the first frame members (33) are omitted. The first frame members (33) are formed in a straight line parallel to the planned division line (6). The first frame members (33) are arranged in the center of the width direction of the planned division line (6). Additionally, the first frame section (33) is connected to the support section (7) by a connecting piece (35). The first frame section (33), which is positioned at the outermost edge of the planned division line (6) of each device area (4) among the multiple planned division lines (6), is continuous with the surplus area configuration section. The width of the first frame section (33) is smaller than the width of the planned division line (6).

[0031] The first electrode portion (34) extends in a straight line from the first frame portion (33) to both sides in the width direction of the first frame portion (33). The first electrode portion (34) is positioned within the planned division line (6), and its tip is positioned spaced apart from the support portion (7). The first electrode portion (34) has a wire (18) connected to its tip and is electrically connected to the device chip (8). The first electrode portion (34) constitutes the aforementioned electrode (11). In the first embodiment, the lead frame (31) is formed with the same thickness across the support portion (7), the first frame portion (33), and the first electrode portion (34).

[0032] As shown in FIG. 6, the connection frame (32) integrally comprises a plurality of second frame portions (36), a plurality of second electrode portions (37), and an unillustrated surplus area component that constitutes an outer surplus area (5). The second frame portion (36) overlaps the side where the device chip (8) of the first frame portion (33) of the lead frame (31) is placed and is formed in a grid shape along the planned division line (6). The second frame portion (36) is formed in a straight line parallel to the planned division line (6). The second frame portion (36) is positioned at the center in the width direction of the planned division line (6). The second frame portion (36) positioned on the planned division line (6) at the outermost edge of each device area (4) among the plurality of planned division lines (6) is continuous with the surplus area component. The width of the second frame section (36) is smaller than the width of the line (6) scheduled for division.

[0033] The second electrode portion (37) extends in a straight line from the second frame portion (36) to both sides in the width direction of the second frame portion (36). The second electrode portion (37) is positioned within the planned division line (6), and its tip is positioned spaced apart from the support portion (7). The tip of the second electrode portion (37) is positioned closer to the second frame portion (36) than the tip of the first electrode portion (34). The second electrode portion (37) overlaps with the side where the device chip (8) of the first electrode portion (34) of the lead frame (31) is positioned, and is electrically connected to the first electrode portion (34).

[0034] In this way, the frame (3) is configured such that, as shown in FIGS. 7 and 8, the first frame portion (33) of the lead frame (31) placed on the surface (9) side and the second frame portion (36) of the lead frame (31) placed on the back side (10) side overlap each other, and the first electrode portion (34) and the second electrode portion overlap each other. Also, in the first embodiment, the tip of the second electrode part (37) is formed in a convex shape toward the first electrode part (34) rather than the second frame part (36), as shown in FIG. 8, and is connected to the first electrode part (34) of the lead frame (31), and the second frame part (36) is spaced apart from the first frame part (33) and overlaps, and the base of the second electrode part (37) is spaced apart from the first electrode part (34) and overlaps.

[0035] In the package substrate (1) of the above configuration, after the lead frame (31) and the connection frame (32) of the frame (3) overlap each other, a device chip (8) is placed on the back side (10) of the support member (7) as shown in FIG. 9, and the first electrode member (34) is connected to the device chip (8) by a wire (18). After the device chip (8) is placed on the support member (7), the package substrate (1) is manufactured by covering the device chip (8), the wire (18), and the connection frame (32), etc., with a mold resin (12) as shown in FIG. 10. In this way, the mold resin (12) covers the device chip (8) and the connection frame, which are formed by being electrically connected to the first electrode member (34) of the lead frame (31).

[0036] (Processing method of package substrate)

[0037] FIG. 11 is a flowchart showing the flow of a processing method for a package substrate related to a first embodiment. The processing method for a package substrate is a method of dividing a package substrate (1) into individual package chips (2) and fixing the package chips (2) to a wiring board (20). As shown in FIG. 11, the processing method for a package substrate comprises a cutting groove forming step (1001), a plating treatment step (1002), a dividing step (1003), and a solder fixing step (1004).

[0038] (Cutting groove forming step)

[0039] FIG. 12 is a cross-sectional view schematically illustrating the cutting groove forming step of the processing method of the package substrate shown in FIG. 11. The cutting groove forming step (1001) is a step of cutting a first cutting blade (41) into the first frame portion (33) of the lead frame (31) along the planned division line (6) on the side of the surface (9) where the lead frame (31) of the package substrate (1) is exposed, forming a cutting groove (19) with a depth that does not reach the second frame portion (36) of the connection frame (32) covered by the mold resin (12), and exposing the cut surface (341) of the first electrode portion (34) that is cut by cutting the first frame portion (33) to the inner surface of the cutting groove (19).

[0040] In the cutting groove forming step (1001), the cutting device (40) holds the back side (10) of the package substrate (1), i.e., the mold resin (12), by suctioning it onto the holding surface of the chuck table, which is not shown. In the cutting groove forming step (1001), the cutting device (40) captures the mark (13) on the surface (9) side of the package substrate (1) held on the chuck table using an imaging unit, and performs alignment to align the position of the first cutting blade (41) with the planned split line (6).

[0041] In the cutting groove forming step (1001), the cutting device (40) moves the chuck table and the first cutting blade (41) relative to each other along the planned division line (6), and as shown in FIG. 12, the cutting edge of the first cutting blade (41) is cut into the first frame part (33) located at the center of the width direction of the planned division line (6) to a depth that does not reach the second frame part (36) covered with mold resin (12), thereby forming a cutting groove (19) of the aforementioned depth in each planned division line (6) of the package substrate (1). Additionally, the depth is shallower than the distance from the surface (9) of the package substrate (1) to the second frame part (36). Also, the thickness of the cutting edge of the first cutting blade (41) is greater than or equal to the width of the first frame part (33).

[0042] In the cutting groove forming step (1001), the cutting device (40) cuts the first cutting blade (41) into the first frame part (33), cuts and removes the entire first frame part (33), cuts the base part of the first electrode part (34), and exposes the cut surface (341) cut by the first cutting blade (41) of the first electrode part (34) to the inner surface of the cutting groove (19). In the cutting groove forming step (1001), the cutting device (40) forms cutting grooves (19) in all planned division lines (6). In this way, in the cutting groove forming step (1001), the cutting device (40) cuts the first frame part (33) of the lead frame (31).

[0043] (Plating process step)

[0044] FIG. 13 is a cross-sectional view schematically showing a package substrate (1) after the plating treatment step of the processing method of the package substrate shown in FIG. 11. The plating treatment step (1002) is a step of applying voltage to the first electrode part (34) cut after the cutting groove forming step (1001) by interposing a connection frame (32) and covering the exposed surface of the first electrode part (34) with a plating layer (16) by electroplating.

[0045] In the plating process step (1002), the package substrate (1) after the cutting groove forming step (1001) is immersed in the first electrode portion (34) in the electrolytic solution, an electrode not shown in the electrolytic solution is set as the anode, and the first electrode portion (34) of the lead frame (31) is set as the cathode, and a voltage for a predetermined time is applied to the electrode and the connection frame (32) while supplying a material (e.g., tin) to be plated on the first electrode portion (34) in the electrolytic solution. In the plating process step (1002), as shown in FIG. 13, the exposed surface of the first electrode portion (34) is coated with a plating layer (16) by electrolytic plating. Thus, in the processing method of the package substrate related to the first embodiment, the connection frame (32) forms an electrode when the first electrode part (34) is cut from the first frame part (33) and the cutting surface (341) of the first electrode part (34) is subjected to field plating treatment.

[0046] (Split Step)

[0047] FIG. 14 is a cross-sectional view schematically illustrating a dividing step of the processing method of the package substrate shown in FIG. 11. The dividing step (1003) is a step of cutting the center in the width direction of the cutting groove (19) with a second cutting blade (51) having a thinner cutting edge than the first cutting blade (41) after performing the plating treatment step (1002), and cutting the connection frame (32) and the mold resin (12) to divide them into individual package chips (2).

[0048] In the splitting step (1003), the cutting device (50) sucks and holds the back side (10) of the package substrate (1), i.e., the mold resin (12), on the holding surface of the chuck table not shown. In the splitting step (1003), the cutting device (50) captures the mark (13) on the surface (9) side of the package substrate (1) held on the chuck table with an imaging unit and performs alignment to align the position of the second cutting blade (51) and the cutting groove (19).

[0049] In the splitting step (1003), the cutting device (50) moves the chuck table and the second cutting blade (51) relative to each other along the cutting groove (19), and as shown in FIG. 14, cuts the center of the cutting groove (19) in the width direction until it reaches the relief groove of the holding surface of the chuck table, and cuts the center of the cutting groove (19) in the width direction formed in each planned split line (6) of the package substrate (1). Also, the thickness of the cutting edge of the second cutting blade (51) is thinner than the thickness of the cutting edge of the first cutting blade (41). Therefore, the second cutting blade (51) does not come into contact with the plating layer (16) covered in the cutting groove (19) and damage the plating layer (16).

[0050] In the splitting step (1003), the cutting device (50) cuts the center in the width direction of the cutting groove (19) formed in each splitting line (6) of the package substrate (1) with the second cutting blade (51) to split the package substrate (1) into individual package chips (2). In this way, the package chip (2) is divided from the package substrate (1) by performing a cutting groove forming step (1001), a plating treatment step (1002), and a dividing step (1003) on the package substrate (1). As shown in FIG. 4, the first electrode portion (34) of the lead frame (31) electrically connected to the device chip (8) is exposed to the surface (9) and the second side (151) leading to the surface (9) of the stepped portion (15), and the cut surface (371) of the second electrode portion (37) of the connection frame (32) connected to the end of the first electrode portion (34) is exposed to the side (14) leading from the stepped portion (15) to the back surface (10) of the package chip (2). In addition, in FIG. 4, three electrode portions (34, 37) are exposed on each side (151, 14), but in the first embodiment, five are exposed.

[0051] Additionally, as shown in FIG. 14, the package chip (2) has a first electrode portion (34) covered with a plating layer (16), and the second electrode portion (37) of the connection frame (32) is not covered with a plating layer (16). In this way, the package chip (2) divided individually has the cut surface (341) of the first electrode portion (34) covered by the plating layer (16), similar to a so-called wettable flank. The package chip (2) configured as described above is a device chip (8) mounted on a support portion (7) of a metal lead frame (31) that is covered with a mold resin (12).

[0052] (Solder fixing step)

[0053] FIG. 15 is a cross-sectional view schematically illustrating the solder fixing step of the processing method of the package substrate shown in FIG. 11. The solder fixing step (1004) is a step of placing the surface (9) side of the package chip (2) facing the wiring board (20) of the mounting location, and connecting the plated first electrode part (34) of the package chip (2) and the electrode (21) of the wiring board (20) with solder (22).

[0054] In the solder fixing step (1004), as shown in FIG. 15, the surface (9) of the package chip (2) is placed on the wiring board (20), and solder (22) is supplied between the plating layer (16) covering the first electrode part (34) and the wiring board (20), thereby fixing and connecting the first electrode part (34) to the electrode (21) by the solder (22). Additionally, in the package chip (2) that is fixed and connected to the wiring board (20) in the solder fixing step (1004), the cut surface (341) of the first electrode part (34) cut in the cutting groove forming step (1001) is covered by the plating layer (16) formed by the plating process, so the wettability of the solder (22) of the first electrode part (34) is ensured.

[0055] As described above, the package substrate (1) related to the first embodiment has a frame (3) that is superimposed on a lead frame (31) and a connection frame (32), and the second electrode portion (37) of the connection frame (32) is connected to the first electrode portion (34) of the lead frame (31), and the second frame portion (36) of the connection frame (32) is superimposed with a gap between it and the first frame portion (33) of the lead frame (31). Because of this, even if the first frame portion (33) of the package substrate (1) is cut, a plating layer (16) can be formed on the cut surface (341) of the first electrode portion (34) by applying voltage through the connection frame (32).

[0056] Accordingly, in the package substrate (1), plating treatment is performed on the cut surface (341) of the first electrode part (34), that is, the exposed surface of the electrode (11), such as a so-called wettable flank, and by forming a connection frame (32) so that the first electrode part (34) can be cut (full cut) rather than half cut, the first electrode part (34) can be cut while maintaining the wettability of the side (cut surface) of the electrode (11). As a result, the package substrate (1) exhibits the effect of being able to relax the precision of the cutting depth. In addition, since the package substrate (1) can form a plating layer (16) on the cut surface (341) of the first electrode part (34) even after cutting the first electrode part (34), it exhibits the effect of being able to suppress clogging of the first cutting blade (41) and suppress the generation of burrs.

[0057] In addition, in the processing method of the package substrate related to the first embodiment, even if the first frame portion (33) of the package substrate (1) is cut in the cutting groove forming step (1001), a plating layer (16) can be formed on the cut surface (341) of the first electrode portion (34) by applying voltage through the connection frame (32) in the plating treatment step (1002). As a result, the processing method of the package substrate can cut the first electrode portion (34) while maintaining the wettability of the side (cut surface) of the electrode (11), thereby providing the effect of relaxing the precision of the cutting depth. In addition, the processing method of the package substrate allows for the formation of a plating layer (16) on the cut surface (341) of the first electrode part (34) even after the first electrode part (34) is cut, thereby suppressing clogging of the first cutting blade (41) and suppressing the generation of burrs.

[0058] Also, in the package chip (2) related to the first embodiment, the first electrode portion (34) of the lead frame electrically connected to the device chip (8) is exposed to the second side (151) of the step portion (15), and the cut surface (341) of the second electrode portion (37) of the connection frame (32) connected to the first electrode portion (34) is exposed to the side (14), and the first electrode portion (34) is covered with a plating layer (16). Because of this, in the package chip (2), even if the first frame portion (33) of the package substrate (1) is cut, a plating layer (16) can be formed on the cut surface (341) of the first electrode portion (34) by applying voltage through the connection frame (32).

[0059] As a result, the package chip (2) can cut the first electrode part (34) while maintaining the wettability of the first electrode part (34), thus providing the effect of reducing the precision of the cutting depth. In addition, even if the package chip (2) cuts the first electrode part (34), it can form a plating layer (16) on the cut surface (341) of the first electrode part (34), thereby suppressing clogging of the first cutting blade (41) and suppressing the generation of burrs.

[0060] In addition, the present invention is not limited to the first embodiment above. That is, it can be implemented with various modifications within the scope of not departing from the gist of the present invention. Explanation of the symbols

[0061] 1 : Package substrate 2 : Package chip 3 : Frame 6 : Line scheduled for division 7 : Support 8 : Device Chip 9 : Surface 10 : If it is 12: Mold resin 14: Side 15 : Step section 16: Plating layer 19: Cutting groove 20: Wiring board 21 : Electrode 22 : Solder 31 : Lead frame 32 : Connection Frame 33: 1st Frame Section 34: First electrode part 36: Second frame section 37 : Second electrode part 41: 1st cutting blade 51: Second cutting blade 151: Second side (side leading to the surface) 341 : Section (cross-section) 371 : Section (cross-section) 1001: Cutting groove forming step 1002: Plating Process Step 1003 : Split Step 1004 : Solder fixing step

Claims

Claim 1 A package substrate having a device chip mounted on a frame and coated with a mold resin, comprising: the device chip; a metal lead frame having a grid-like first frame portion along a planned division line partitioning a support portion on which the device chip is disposed, and a plurality of first electrode portions extending to both sides from the first frame portion; a connection frame having a grid-like second frame portion along the planned division line and a plurality of second electrode portions extending to both sides from the second frame portion, and a connection frame formed on the side of the lead frame where the device chip is disposed; a wire connecting the first electrode portion and the device chip; and the mold resin covering the device chip, the connection frame, and the wire, which are disposed and electrically connected to the first electrode portion of the lead frame. The tip of the second electrode portion is formed in a convex shape toward the first electrode portion more than the second frame portion and is connected to the first electrode portion of the lead frame, and the connection frame is formed such that the first electrode portion is cut from the first frame portion.

1. A package substrate forming an electrode when performing field plating treatment on the cross-section of the electrode portion. Claim 2 A method for processing a package substrate in which a device chip mounted on a frame is coated with a mold resin, wherein the package substrate comprises: a metal lead frame having a first frame portion in a grid shape along a planned division line that partitions a support portion where the device chip is placed, and a plurality of first electrode portions extending to both sides from the first frame portion; a connection frame having a second frame portion in a grid shape along the planned division line and a plurality of second electrode portions extending to both sides from the second frame portion, and a connection frame formed on the side where the device chip is placed on the lead frame; a wire connecting the first electrode portion and the device chip; and the mold resin covering the device chip, the connection frame, and the wire, which are electrically connected to and formed on the first electrode portion of the lead frame. The tip of the second electrode portion is formed in a convex shape toward the first electrode portion more than the second frame portion and is connected to the first electrode portion of the lead frame, and the connection frame is such that the first electrode portion is the first A processing method for a package substrate, wherein an electrode is formed when an electro-plating treatment is performed on the cross-section of the first electrode portion formed by cutting from the frame portion, comprises: a cutting groove forming step in which a first cutting blade is inserted into the first frame portion of the lead frame along the planned division line on the surface side where the lead frame of the package substrate is exposed, and a cutting groove is formed with a depth that does not reach the connection frame covered by the mold resin, and the cut surface of the first electrode portion, which is cut by cutting the first frame portion, is exposed in the cutting groove; a plating treatment step in which, after performing the cutting groove forming step, voltage is applied to the cut first electrode portion with the connection frame interposed therebetween, and the exposed surface of the first electrode portion is coated with a plating layer by electro-plating; and after performing the plating treatment step,A method for processing a package substrate, comprising: a dividing step of cutting the center of the cutting groove with a second cutting blade thinner than the first cutting blade and cutting the connection frame and the mold resin to divide into individual package chips; and a solder fixing step of positioning the surface side of the package chip facing a wiring board of a mounting location and connecting the plated first electrode portion of the package chip and the electrode of the wiring board with solder. Claim 3 A package chip in which a device chip mounted on a support portion of a metal lead frame is coated with mold resin, wherein the surface of the package chip exposed by the support portion and the side of the package chip are connected by a step portion of a predetermined height and width, a first electrode portion of the lead frame electrically connected to the device chip is exposed on the surface extending from the step portion to the surface of the step portion, and on the side extending from the step portion to the back surface of the package chip, the cross-section of a second electrode portion of a connection frame connected to the first electrode portion is exposed, the first electrode portion is coated with a plating layer, and the second electrode portion of the connection frame is not coated with a plating layer.

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