Microelectronic package with substrate-integrated components

Abstract

The embodiments may relate to a microelectronic package or the die thereof, comprising a die, logic, or subsystem coupled to a surface of a substrate. An inductor may be located on the substrate. Electromagnetic interference (EMI) shielding elements may be located inside the substrate and around the inductor. Other embodiments may be described or claimed.

Description

Background Technology

[0001] It may be desirable for individual dies, particularly radio frequency (RF) related dies such as power amplifiers (PAs), to be connected to each other so as to communicate or to other dies on an RF system in package (SiP). Often, such SiPs connect various dies to each other using wire bonds and two-dimensional (2D) integration methods. Brief explanation of the drawing

[0002] FIG. 1 illustrates an exemplary microelectronic package having substrate-integrated components according to various embodiments. FIG. 2 illustrates an exemplary top-down view of an exemplary microelectronic package having a substrate-integrated component according to various embodiments. FIG. 3 illustrates an exemplary top view of an exemplary microelectronic package having a substrate-integrated component according to various embodiments. FIG. 4 illustrates an exemplary top view of an exemplary microelectronic package having a substrate-integrated component according to various embodiments. FIG. 5 illustrates an exemplary top view of an exemplary microelectronic package having a substrate-integrated component according to various embodiments. FIG. 6 illustrates an exemplary view of an in-package inductor according to various embodiments. FIG. 7 illustrates an alternative exemplary microelectronic package having substrate-integrated components according to various embodiments. FIG. 8 illustrates an exemplary technique for manufacturing a microelectronic package having a substrate-integrated component according to various embodiments. FIG. 9 is a side cross-sectional view of an integrated circuit (IC) device assembly that may include a microelectronic package having a substrate-integrated component according to various embodiments. FIG. 10 is a block diagram of an exemplary electrical device that may include a microelectronic package having a substrate-integrated component according to various embodiments. Specific details for implementing the invention

[0003] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, wherein the same numbers denote the same parts throughout and are illustrated as exemplary embodiments in which the subject matter of this disclosure may be practiced. It should be understood that other embodiments may be used and that structural or logical changes may be made without departing from the scope of this disclosure. Accordingly, the following detailed description should not be construed in a limiting sense.

[0004] For the purposes of this disclosure, the phrase “A or B” means (A), (B) or (A and B). For the purposes of this disclosure, the phrase “A, B or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0005] Descriptions may use perspective-based descriptions such as top / bottom, inside / outside, up / down, etc. Such descriptions are used merely to facilitate discussion and are not intended to limit the application of the embodiments described herein in any particular way.

[0006] The description may use the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Additionally, terms such as "comprising," "including," and "having" used in relation to the embodiments of the present disclosure are synonyms.

[0007] The term “combined with” may be used in this specification together with its derivatives. “Combined” may mean two or more of the following: “Combined” may mean that two or more elements are in direct physical or electrical contact. However, “Combined” may also mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and that one or more other elements are combined or connected between elements referred to as being combined with each other. The term “directly combined” may mean that two or more elements are in direct contact.

[0008] In various embodiments, the phrase “first feature [[formed / deposited / placed / etc.]] on the second feature” may mean that the first feature is formed / deposited / placed / etc. on the feature layer, and at least a portion of the first feature may be in direct contact (e.g., direct physical or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature).

[0009] Various actions may be described sequentially as multiple individual actions in a manner that is most helpful for understanding the claimed object. However, the order of description should not be interpreted as implying that these operations must necessarily depend on the order.

[0010] As used herein, the term “module” may refer to, be part of, or include one or more software or firmware programs, combinational logic circuits, or other suitable components that provide the described functions, such as an application-specific integrated circuit (ASIC), electronic circuit, processor (shared, dedicated, or group), or memory (shared, dedicated, or group).

[0011] The embodiments of this specification may be described in connection with various drawings. Unless expressly stated otherwise, the dimensions in the drawings are intended to represent the illustrative examples rather than express proportional dimensions. For example, various lengths, widths, and heights of elements in the drawings may not be drawn to scale unless otherwise indicated. Additionally, while some schematic diagrams of exemplary structures of the various devices and assemblies described herein may be drawn with precise right angles and straight lines, it should be understood that such diagrams may not reflect realistic process limitations that would cause features not to appear so "ideally" when any of the structures described herein are inspected using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In these images of the actual structure, possible process defects (e.g., edges of the material that are not perfectly straight, tapered vias or other openings, careless rounding of corners or variations in thickness of different material layers, temporary helical sections, complex dislocations within edges or crystal regions, and / or temporary dislocations of single atoms or atomic clusters) may also be visible. Other defects not listed herein may exist, but these are common in the field of device manufacturing.

[0012] As previously mentioned, it may be desirable for dies such as power amplifiers (PAs), switches, control logic, and low-noise amplifiers (LNAs) to be connected to each other or to other dies within or on a microelectronic package, such as an RF SiP. In legacy microelectronic packages, wire bonds may have been used to first connect the dies to the package substrate and then to other passive or active components or dies of the microelectronic package through the package substrate (particularly the interconnects of the package substrate).

[0013] In addition, conventional microelectronic packages can generally utilize a planar 2D integration method in which all components of the microelectronic package are located on a single layer and adjacent to each other. This method may vary depending on how semiconductor packaging materials (e.g., low-temperature co-fired ceramic (LTCC), organic, or other types of semiconductor packaging materials) are used to interconnect different components of the SiP. In these legacy microelectronic packages, architectures with up to 10 metal layers may have been used with secondary level interconnects (SLI) of the ball grid array (BGA) or land grid array (LGA) types. Several (e.g., more than 40) passive devices, such as resistors, inductors, or capacitors, may be mounted as surface mount devices (SMDs) in the package or implemented as integrated elements of the package substrate using the metal layers of the package substrate. Additionally, if a high-Q inductor is required, it can be placed within or on the outermost metal layer of the package substrate, whereas a low-Q inductor can use up to four metal layers of the package substrate. The microelectronic package can then be overmolded to protect the device from the environment.

[0014] In addition, electromagnetic interference (EMI) solutions can be implemented in legacy packages as a conductive thin film of a material (e.g., copper (Cu) or some other similar metallic or non-metallic material) that covers the outer surface of the microelectronic package and connects to the ground layer of the microelectronic package, creating a structure similar to a "Faraday cage."

[0015] In addition, wire bonds can be used in legacy packages to protect specific devices from interference, and via walls inside the package can further help reduce crosstalk. Thermal solutions (for dies or other components in microelectronic packages) can be implemented using a thermal via array inside the packaging substrate, as current solutions can use a face-up approach (i.e., using the active side of the die or SMD facing away from the package substrate) to assemble the die in the system. Wire bonds can be used to interconnect the die or SMD to the package substrate.

[0016] Generally, the filters in legacy packages may include interconnects of several (e.g., 10-20) acoustic resonator dies, such as surface acoustic wave (SAW) resonators, bulk acoustic wave (BAW) resonators, and thin-film bulk acoustic resonators (FBARs), or may include some other types of resonators along with appropriate matching circuits, such as inductors. Typically, three or four layers of the package substrate may be occupied by matching inductors under the die shadow. Other dies, such as integrated passive devices (IPDs), switches, and digital logic dies, may also be placed in the package and likewise need to be interconnected using wire bonds.

[0017] However, for thermal solutions in legacy packages, particularly for face-up mounted dies, heat can only be extracted from the die to the substrate on which the die is mounted, for example, via a via array. Such solutions can make the layer beneath the die shadow undesirable for signal routing. However, as requirements for die performance, particularly PA performance, become more stringent, these heat extraction paths may be insufficient to meet design criteria. Furthermore, since the face-up die interconnect to the package substrate is a wire bond in legacy packages, there may not be a practical solution for extracting heat from the top of the die (for example, the portion of the die facing away from the package substrate). Such heat extraction from the top of the die may be desirable because any such mechanism would necessarily be close to the active surface of the die, making heat extraction potentially more efficient than existing techniques.

[0018] Furthermore, wire bonds in conventional microelectronic packages can increase package area due to design rules regarding how wires are guided from die pads to substrate pads. In particular, when wire bonds are used for RF shielding, they can significantly increase the z-height of the microelectronic package.

[0019] Finally, in a 2D planar approach, the trace length may be increased to interconnect various dies and components of a microelectronic package, which reduces the space available for additional components and may increase the number of layers on the package substrate or increase the cost of the microelectronic package.

[0020] Unlike the legacy microelectronic packages described above, the embodiments of this specification relate to the use of wafer reconfiguration and increased functional integration on a single die to achieve a small form factor and a reduction in packaging layers. Additionally, vias such as through-mold vias (TMVs) or through-substrate vias (TSVs) may be used to further reduce the z-height and improve crosstalk parameters. Thick and thin rewiring layers may be used for high-Q inductor integration or signal routing, respectively.

[0021] The embodiments can provide many advantages. For example, the embodiments can result in a reduction of the XY dimensions of the microelectronic package. Furthermore, the use of flip-chip dies can reduce the overall z-height of the microelectronic package. Additionally, increased functional integration on a single die can reduce the number of packaging layers, thereby reducing both the z-height and the XY area. High-Q inductors (e.g., inductors with a Q factor greater than about 50) can be integrated using a combination of a thick redistribution layer and lithographically defined vias. Routing and low-Q inductors and capacitors can be integrated into a thin redistribution layer at the bottom of the interconnect stack. TMVs and molded interconnects can create EMI shielding for the dies of the microelectronic package. Thus, the z-height can be kept low because EMI measurements can utilize molded metal layers instead of wire bonds. The embodiments can also improve thermal parameters through added thermal paths via the mold.

[0022] FIG. 1 illustrates an exemplary microelectronic package (100) having a substrate-integrated component according to various embodiments. In some embodiments, the microelectronic package (100) may be referred to as an RF front-end module (FEM), whereas in other embodiments, the microelectronic package (100) may be part of an RF FEM or include components thereof.

[0023] Generally, the package (100) may include one or more dies (105) coupled to the package substrate (110). The die (105) may be, for example, a processor such as a CPU (central processing unit), a GPU (general processing unit), a core of a distributed processor, or some other type of processor, or may include such. Alternatively, the die (105) may include memory such as double data rate (DDR) memory, non-volatile memory (NVM), volatile memory, read-only memory (ROM), or some other type of memory or die. In some embodiments, the die (105) may be or may include an RF chip or RF circuit configured to generate, process, transmit, or receive a wireless signal such as a third generation (3G), fourth generation (4G), fifth generation (5G), Wi-Fi, or some other type of wireless signal. For example, the die may be an IPD, a switch, digital logic, a power amplifier, a low-noise amplifier, or some other type of RF-related die. In some embodiments, the die (105) may include one or more passive components, such as capacitors, resistors, etc. Various active or passive components may be located inside, partially inside, or on the surface of the die (105).

[0024] The package substrate (110) may be considered, for example, as a core or coreless substrate. The package substrate (110) may include one or more layers of dielectric material that may be organic or inorganic. The package substrate (110) may further include one or more conductive elements such as vias, pads, traces, microstrips, striplines, etc. The conductive elements may be located inside or on the surface of the package substrate. Generally, the conductive elements may allow the routing of signals through the package substrate (110) or between elements coupled to the package substrate (110). In some embodiments, the package substrate (110) may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or some other type of substrate.

[0025] Generally, the die (105) may be coupled to the package substrate (110) by one or more interconnects (125). The interconnects (125) may be solder bumps formed from materials such as, for example, tin, silver, copper, etc. If solder bumps are used for the interconnects (125), the solder bumps may be elements of a BGA as shown in FIG. 1. In other embodiments, the interconnects (125) may be some other type of interconnect. Generally, the interconnects (125) may physically or communically couple the die (105) to the package substrate (110). For example, one or more interconnects (125) may be physically coupled to the pads of the die (105) and the pads of the package substrate (110) (not shown in FIG. 1 to avoid confusion) and allow electrical signals to pass between them. In another embodiment, the interconnect (125) may physically connect the die (105) and the package substrate (110), but the interconnect (125) may not communicably connect the die (105) and the package substrate (110).

[0026] The package substrate (110) may further include a plurality of interconnects (120) which may be referred to as SLI. The interconnects (120) may be formed of a material similar to the material of the aforementioned interconnects (125). For example, the interconnects (125) may be formed of a solder material including tin, silver, copper, etc. While the interconnects (125) may be solder bumps of a BGA, in other embodiments, the interconnects (125) may be elements such as a solder grid array (SGA), LGA, pin grid array (PGA), etc. Generally, the interconnects (120) may enable the microelectronic package (100) to communicate, physically combine, or communicate physically combine with other elements of an electronic device such as a motherboard, interposer, PCB, etc.

[0027] The microelectronic package (100) may further include an overmolding material (135) capable of at least partially surrounding the die (105). The overmolding material (135) may be or may include a dielectric material such as epoxy or some other overmolding material. One or more TMVs (130) may be located within the overmolding material. The TMVs may be formed from a material such as copper or some other type of electrically conductive material. As is generally known, the TMVs (130) may be moved to an EMI shielding layer (140) located on the overmolding material (135) on the package substrate (110). Similar to the TMVs (130), the EMI shielding layer (140) may be formed from an electrically conductive material such as copper or some other material. Although not explicitly shown in FIG. 1, the EMI shielding layer (140) may be communicably coupled to the ground plane of the microelectronic package (100) or the electronic device to which the microelectronic package forms part. The EMI shielding layer (140) and the TMV (130) may at least partially surround the die (105) and serve as an EMI shield for the die (105). For example, the TMV (130) located between two dies (105) may reduce or eliminate EMI interference (i.e., crosstalk) between the two dies (105), or between one of the dies (105) and another element of the electronic device to which the microelectronic package (100) forms part.

[0028] As described above, the package substrate (110) may include one or more conductive elements such as vias, pads, traces, microstrips, striplines, etc. These elements may be formed from a conductive material such as copper, gold, or some other material. In some embodiments, transverse elements such as traces, striplines, microstrips, etc. may be referred to as a redistribution layer. As can be seen, the package substrate (110) may include, for example, a redistribution layer (115a) having a trace (150) having a first thickness, and, for example, a redistribution layer (115b) having a trace (155) having a second thickness.

[0029] The first thickness, i.e., the thickness of the trace (150), may be greater than about 30 micrometers ("microns") when measured in the direction from the top of FIG. 1 to the bottom of FIG. 1. The second thickness, i.e., the thickness of the trace (155), may be less than about 30 microns. Generally, the redistribution layer (115a) may be used as a matching inductor for the die (105). The inductor from the redistribution layer (115a) may be, for example, a high-Q inductor having a Q-factor greater than approximately 50. The redistribution layer (115b) may be used as a low-Q inductor (for example, an inductor having a Q-factor less than 50) or for routing signals (for example, digital, baseband, or RF signals) through the package substrate (110). Additionally, as can be seen, various traces (155 and 150) of the redistribution layer may be joined by one or more TSVs (145). The TSV (145) may be defined lithographically and may be a single via that communicably joins two elements, or, for example, a trench via extending laterally through the package substrate (110). The trench via may be used to form an inductor, for example, which will be described in more detail in relation to FIG. 6.

[0030] FIGS. 2 through 5 illustrate exemplary top views of an exemplary microelectronic package having substrate-integrated components according to various embodiments. Specifically, FIGS. 2 through 5 illustrate exemplary views of a microelectronic package (200) at different levels. Specifically, FIGS. 2 through 5 illustrate views (201, 201a, 201b, 201c, 201d, 201e, 201f, and 201g). The progressively listed views may be descending levels of the microelectronic package (starting from FIG. 1). Specifically, view (201) is a drawing obtained through an overmolded material and die, such as the overmolded material (135) and die (105) of FIG. 1. Views (201a-201d) are descending cross-sectional views of a redistribution layer of a microelectronic package (200) having a thickness greater than that of the redistribution layer (which may have a thickness of less than about 30 microns) of views (201e-201g) (e.g., a thickness of about 30 microns or more). Specifically, views (201a-201d) are views of a redistribution layer in a region similar to the redistribution layer (115a), and views (201e-201g) are views of a redistribution layer in a region similar to the redistribution layer (115b). View (201a) may be of a redistribution layer adjacent to the cross-sectional view of view (201); and view (201b) may be of a redistribution layer adjacent to the redistribution layer of view (201a); View (201c) may be a rewiring layer adjacent to the rewiring layer of view (201b), etc. Each and all elements of each drawing may not be explicitly enumerated or called, but elements that share the characteristics of an enumerated element within a drawing or between drawings may generally share the characteristics described in relation to that enumerated element.

[0031] Starting from view (201), the microelectronic package (200) may include a number of dies (205a, 205b, and 205c) (collectively referred to as dies (205)). Each die of the dies (205) may have a different function. For example, die (205c) may be a filter, such as an Acoustic Wave Resonator (AWR) filter. Die (205b) may be, for example, a switch, an IPD, a digital logic, or some other type of die. Die (205a) may be, for example, a PA or some other type of die. The dies (205) may be located within an overmolding material (235) that is similar to the overmolding material (135) and may share one or more characteristics. As can be seen in view (201), the overmolding material (235) may generally surround the dies (205).

[0032] Various dies (205) may be surrounded by TMV (230) which is similar to TMV (130) and may share one or more characteristics. Specifically, TMV (230) may be formed of a conductive material such as copper or some other material and may serve to electromagnetically shield the dies (205) from each other. Additionally, when TMV (230) is combined with an EMI shielding layer such as an EMI shielding layer (140), TMV (230) and the EMI shielding layer may electromagnetically shield the dies (205) from EMI caused by components outside the microelectronic package (200).

[0033] It will be understood that while the TMV (230) is generally depicted as a single element in the shape of a square or rectangle, in other embodiments the TMV (230) may have different shapes (e.g., elliptical, circular, etc.). In some embodiments, one or more dies (205) may not be surrounded by the TMV. In some embodiments, one or more TMVs (230) may consist of a series of individual TMVs spaced closely apart from each other to provide EMI shielding for one of the dies (205). In some embodiments, the TMV (230) may be conductively connected to the ground plane of each TMV and view (201a-201g).

[0034] View (201a) illustrates a view of a rewiring layer of a microelectronic package (200) adjacent to an element of view (201). Specifically, the microelectronic package (200) may include a package substrate (210) that is similar to the package substrate (110) and shares one or more characteristics. The package substrate (210) may include a plurality of cavities, such as cavities (202, 203, 207, etc.). As can be seen, the cavities can generally be aligned with the dies (205). Specifically, cavity (202) can be aligned with die (205c), cavity (203) can be aligned with die (205b), and cavity (207) can be aligned with die (205a). However, it will be understood that this alignment may vary in other embodiments, and that the cavity may not be fully aligned with one or more dies, or that a single cavity may be defined in the die shadow of two dies. As used herein, the term “die shadow” may refer to a space of the package substrate (210) located beneath one of the dies, such as dies (205a / 205b / 205c). Similarly, the term “cavity” as used herein may refer to a region surrounded by a conductive element that electromagnetically separates that region from other electrically or electromagnetically active regions.

[0035] Cavities (202, 203, 207) may be defined by traces (211), which may be similar to traces (115). Within cavities (202, 203, 207), additional traces may define one or more elements, such as inductors. Various inductors may have different loop numbers or different sizes. For example, an inductor (213) within cavity (207) may be relatively large and generally circular, whereas an inductor (209) within a cavity such as cavity (202) may generally be square-shaped. A specific inductor may be, for example, an inductor used in an AWR-based filter, a PA and LNA matching network, or some other type of inductor.

[0036] View (201b) is a cross-sectional view of a redistribution layer adjacent to the redistribution layer of View (201a). As can be seen, the redistribution layer of View (201b) may share several elements similar or identical to the redistribution layer of View (201a). Some of the elements of the redistribution layer of View (201b) may be communicably coupled to the elements of the redistribution layer of View (201a) by one or more TSVs, such as TSVs (145) (not shown in the drawing based on the location where the view was obtained). For example, a TSV may communicably couple an inductor (209) of the redistribution layer of View (201b) to an inductor (209) of the redistribution layer of View (201a). In this way, a multi-loop inductor may be formed on multiple layers of the microelectronic package (200). Similarly, the inductor (213) of the view (201b) can be communicateably coupled to the inductor (213) of the redistribution layer (201a) of the view (201a) by one or more TSVs.

[0037] In some embodiments, the TSV may be one or more distinct vias, wherein each of the plurality of vias is coupled to, for example, the inductor (209) at different locations along the inductor. In other embodiments, the TSV may be a “trench via” extending laterally along the length, width, or both of the microelectronic package (200). These trench vias coupled with the traces forming the inductor may together form a relatively large inductor element, and the relatively large inductor element has a total thickness equal to the thickness of the traces forming the inductor (209) at two levels of the redistribution layer and the thickness of the TSV. Further details regarding the inductor will be described below in relation to FIG. 6.

[0038] Similar to the inductor (209), the traces (211) can be coupled to each other by one or more TSVs. By coupling the traces (211) together with one or more TSVs, the traces (211) and the TSVs can form EMI shielding for elements within the cavity (203, 202, 207, etc.), more specifically, such as the inductor (209 / 213). Additionally, the TSVs can communicately couple the traces (211) of the rewiring layer of the view (201a) to the TMV (230) of the view (201) of the microelectronic package. In this way, the die (205) and the inductor located in the die shadow of the die (e.g., inductor (209 or 213)) can be shielded together in the cavity within the microelectronic package.

[0039] As previously described with respect to the TMV (230), the trace (211) and the TSV may be described or discussed as a single element, but in some embodiments, the trace (211) or the TSV connecting the trace (211) may be separate elements spaced sufficiently close to each other to provide EMI shielding to the cavity. For example, in some embodiments, one or more of the cavities (202 / 203 / 207) may not be surrounded by the trace, but instead may be surrounded by a plurality of individual single pads that are communically connected together by the TSV or trench via. In other embodiments, other variations may exist.

[0040] View (201c) illustrates a view of a redistribution layer adjacent to the redistribution layer of View (201b). As can be seen, the redistribution layer of View (201c) may include elements similar to the elements of the redistribution layer of Views (201a, 201b). However, as can be seen, the redistribution layer of View (201c) may include one or more EMI shields (217) located in a cavity, such as, for example, cavity (202), cavity (203), or cavity (207). The EMI shield (217) may be coupled with the ground plane of the microelectronic package (200) (for example, the ground plane (218) of the view (201e or 201g) of the redistribution layer located further down than the interconnect stack). The EMI shield (217) may be communicably coupled by one or more individual TSVs, trench vias, or some other type of TSV having a trace (211) that defines a cavity to which the EMI shield (217) is aligned. In this way, the aforementioned EMI shielding layer in relation to the EMI shield (217), TSVs, TMVs, traces, and, for example, elements (140), may jointly encase one or more dies (205) and one or more inductors (209 or 211). Such encasement reduces or neutralizes crosstalk between elements of the microelectronic package (200), or otherwise protects the elements of the microelectronic package (200) from EMI.

[0041] View (201d) illustrates a view of a rewiring layer adjacent to the rewiring layer of View (201c). As can be seen, the rewiring layer of View (201d) may include some elements similar to those described above in relation to the previous view. Additionally, the rewiring layer illustrated in View (201d) may include one or more routing traces (219). The routing traces (219) may be used to communicably combine elements of the previous layer (e.g., elements of a cavity such as cavity (205a) communicably combine with elements of a cavity such as cavity (205b), another cavity (205a), cavity (202), etc.).

[0042] View (201e) illustrates a view of a redistribution layer adjacent to the redistribution layer of view (201d). As previously described, 201e may be a view of a redistribution layer in an area similar to the area of ​​the redistribution layer (115b). More specifically, 201e may be a drawing of a redistribution layer having a thickness of about 30 microns or less. The redistribution layer may include a ground plane (218) of the microelectronic package (200). The ground plane (218) may be formed of a conductive material such as copper or other material and may be coupled to the ground of the microelectronic package (200) (the microelectronic package (200) is part of an electronic device) or to some other type of ground plane. The ground plane (218) may be communicably coupled to the aforementioned trace (211), EMI shield (217), or EMI shielding layer (140) by, for example, one or more TSVs, trench vias, routing traces (219), etc. In this way, various elements providing EMI protection to the die of the microelectronic package may be communicably coupled to the ground.

[0043] Views (201f and 201g) illustrate additional redistribution layers of a microelectronic package. Specifically, the redistribution layer of view (201f) may be adjacent to the redistribution layer of view (201e), and the redistribution layer of view (201g) may be adjacent to the redistribution layer of view (201f). The redistribution layers of views (201f and 201g) may be redistribution layers having a thickness of approximately less than 30 microns, similar to the redistribution layer of view (201e). The redistribution layer of view (201g) may include a ground plane (218) similar to the ground plane of the redistribution layer of view (201e). The redistribution layer of view (201f) may include one or more routing traces (219) similar to the routing trace (219) of the redistribution layer of view (201f).

[0044] It will be understood that the embodiments illustrated in FIGS. 1 through 5 are intended to be simplified exemplary embodiments related to the concepts of this specification. Specifically, in some embodiments, one or more of the various cavities (202, 203, 207, etc.) may include elements in addition to the illustrated elements, such as additional inductors, capacitors, resistors, or other circuits. Additionally, while the various cavities are illustrated and discussed as being completely sealed by traces (211) and TSVs or TMVs, in some embodiments, routing between the various elements may be required, so one or more breaks may exist in the EMI shielding of the elements of the microelectronic package (200). Furthermore, while the various cavities are generally illustrated as having a square or rectangular shape or a specific configuration, in other embodiments, the cavities may span more or fewer layers than discussed and may have different cross-sectional shapes, etc. Similarly, the microelectronic package (200) may have different shapes, more or fewer layers, etc. Additionally, it will be understood that the drawings are not intended to depict each and every layer of the microelectronic package, and that additional layers may exist, including additional interconnects that allow, for example, connection of additional dies, additional EMI shielding, etc. Other embodiments may have other variations.

[0045] It should be noted that the inductor (209) shown in views (201a and 201b) may be generally identical, and the inductor (209) shown in views (201c and 201d) may be generally identical. This may be because the inductor (209) occupies a total of four redistribution layers (e.g., the redistribution layers of views (201a-201d)) and includes two sections each spanning two redistribution layers. Alternatively, the inductor (209) may include a first section spanning the redistribution layers of views (201a, 201b) and a second section spanning the redistribution layers of views (201c, 201d). Each section may include trench vias connecting the different layers of the section together. Alternatively, the microelectronic package (200) may include a first trench via connected along the length of an inductor (209) in the redistribution layer of views (201a and 201b). Similarly, the microelectronic package (200) may include a second trench via connected along the length of an inductor (209) in the redistribution layer of views (201c and 201d). As used herein, the term “trench via” may also refer to a conductive element spanning between two layers (e.g., vias) having a width or length. Such vias may be formed, for example, lithographically on a package substrate.

[0046] FIG. 6 illustrates a perspective view of an exemplary inductor (309) that is similar to the inductor (209) and may share one or more characteristics. The inductor (309) may comprise two sections (350a and 350b). The first section (350a) may comprise two layers (351a and 351b), which may be traces such as those shown in views (201a and 201b). The layers (351a and 351b) may be joined together by a trench via (345) extending along the length between the layers (351a and 351b). The second section (350b) may likewise comprise two layers separated by a trench via. The first section (350a) and the second section (350b) can be joined together by vias (352) that can physically and electrically join the two sections together.

[0047] The use of an inductor, such as inductor (309), can provide significant advantages when placed on a package substrate of a microelectronic package. Specifically, by forming an inductor from different redistribution layers of the microelectronic package (e.g., layers (351a and 351b)) and joining the layers together by trench vias such as trench vias (345), each section of the inductor can have a thickness equal to the thickness of each redistribution layer and trench via. This increased thickness can provide a relatively high Q-value (e.g., a Q-value of approximately 50 or higher) for the inductor (309).

[0048] Generally, the embodiments of this specification can provide many advantages as described above. In some embodiments, using flip-chip type dies such as dies (105, 205a-c) can reduce the total z-height compared to legacy microelectronic packages because the overall mold thickness can be reduced due to the absence of wire bonds. A total z-height of less than about 800 microns can be achieved for microelectronic packages. Additionally, the EMI solution can be further enhanced by using continuous TMV or TSV around the die, which may allow for a smaller footprint for die placement. Furthermore, although die (205c) is described as a single AWR filter, it can be understood that the AWR die may be a composite die including a shielding hermetic lid with or without a passive structure (e.g., capacitor or inductor) integrated.

[0049] Although the embodiments have been described for microelectronic packages, it will be understood that in some embodiments, elements within the substrate may be integrated, for example, onto a single die to form a die that incorporates multiple functions. Integrating multiple functions onto a single die can enable the optimization of interfaces between the different subsystems required for each function. For example, if two functions are on a single die, off-chip matching networks may be reduced or eliminated.

[0050] Each of the multiple functions may be, for example, a function related to RF FEM and is implemented as digital logic on the die. For example, the die may include a first subsystem related to PA and other subsystems related to IPD, switches, digital logic, etc. In some embodiments, the die may include multiple subsystems each related to an AWR filter. Various subsystems or their associated components, such as matching networks, inductors, etc., may be interconnected on the die itself without passing through a package substrate to which the die is attached, which can lead to a reduction in the total number of package metal layers and a reduction in the total XY area of ​​the microelectronic package. For example, if a subsystem related to digital logic and a subsystem related to RF switches are integrated on the same die, package interconnects at the package substrate level may not be required to interconnect the two subsystems, which can lead to a reduction of at least one or two package metal layers. Similarly, introducing an inductor into the AWR die (or composite die if a shielding cover is included) can further reduce the medal layer required on the package substrate because the interconnect between the AWR die and the inductor can occur on the die. Increasing the available die area for the PA die can provide additional advantages regarding heat dissipation.

[0051] As a specific example, elements (100 and 200) are described as microelectronic packages, but in some embodiments, elements (100 and 200) may be multifunctional dies rather than microelectronic packages. Specifically, elements (105, 205a, 205b, 205c, etc.) may be digital logic or other components related to the function of an RF FEM, such as switches, IPDs, PAs, LNAs, AWRs, or some other elements. Elements (110 and 210) may be die substrates rather than package substrates. Other aspects of elements (100 and 200) may be similarly modified to change scale from package level to die level while still including substrate-integrated elements such as inductors, trench vias, or other elements.

[0052] FIG. 7 illustrates an exemplary microelectronic package having substrate-integrated components according to various embodiments. It will be understood that the embodiment of FIG. 7 is intended as an exemplary embodiment, and other variations may include more or fewer elements, elements in different arrangements, etc.

[0053] Specifically, FIG. 7 may be a top view of a microelectronic package (400) that may include elements similar to elements of a microelectronic package (200). The microelectronic package (400) may include an overmolding material (435) that may be similar to an overmolding material (135 or 235). The microelectronic package (400) may further include a plurality of TMVs (430) that may be similar to TMVs (130 or 230).

[0054] The microelectronic package (400) may further include a plurality of dies (405a and 405b). The dies (405a and 405b) may be multifunctional dies as described above. For example, die (405a) may integrate digital logic or other components related to the functions of an RF FEM, such as a PA, digital logic, IPD, switch, etc. Similarly, die (405b) may be a multifunctional die implementing a plurality of AWR filters, with or without integrated passive components. For example, each AWR filter may be associated with a different bandwidth. It will be understood that these multiple functions are described herein by way of example, and that other dies may include more or fewer or different functions, or may be single-function dies.

[0055] The microelectronic package (400) may further include a plurality of SMDs (407) that are coupled to the package substrate of the microelectronic package by a plurality of pads (460). The SMDs (407) may be, for example, inductors, capacitors, resistors, etc.

[0056] FIG. 8 is an exemplary technique for manufacturing a microelectronic package having substrate-integrated components according to various embodiments. Generally, the embodiments may be described in relation to the microelectronic package (100) of FIG. 1, but it will be understood that the described technique may be applicable to other embodiments of this specification, wholly or partially, with or without modification.

[0057] This technique may include lithographically defining a trace on a substrate to form an inductor in 805. The trace may be similar to, for example, the trace (150) defined on the substrate (110). As discussed in relation to the microelectronic package (200) or the inductor (309), the trace may define an inductor such as the inductor (309) together with traces on other rewiring layers of the substrate.

[0058] This technique may further include lithographically defining vias on a substrate to form an electromagnetic shield surrounding an inductor in 810. The vias may be similar to, for example, vias (145) or TSVs (211). As described with respect to the microelectronic package (200), the vias may form an electromagnetic shield (typically surrounding an inductor, die, or both) together with an EMI shield, such as an EMI shield (217) and an EMI shield layer (140).

[0059] The technique may further include combining the die with a package substrate such that the inductor is in the die shadow of the die in 815. The die may be similar to, for example, the die (105) or some other die discussed or described herein.

[0060] It will be understood that the embodiment described above with respect to FIG. 8 is intended to be a highly simplified exemplary technique, and that other embodiments may differ from the embodiments described herein. For example, certain elements may be performed in a different order than illustrated, elements may be performed simultaneously, elements may be added or subtracted, etc.

[0061] FIG. 9 is a side cross-sectional view of an IC device assembly (1700) that may include one or more IC packages or other electronic components (e.g., dies) including one or more microelectronic packages having substrate-integrated components according to any of the embodiments disclosed herein. The IC device assembly (1700) includes a plurality of components disposed on a circuit board (1702) (e.g., may be a motherboard). The IC device assembly (1700) includes components disposed on a first side (1740) of the circuit board (1702) and a second side (1742) opposite the circuit board (1702), wherein, generally, the components may be disposed on one side or both sides (1740 and 1742).

[0062] In some embodiments, the circuit board (1702) may be a PCB comprising a plurality of metal layers separated from one another by dielectric material layers and interconnected by electrically conductive vias. Any one or more metal layers may be formed into a desired circuit pattern (optional together with other metal layers) to route electrical signals between components coupled to the circuit board (1702). In other embodiments, the circuit board (1702) may be a non-PCB substrate.

[0063] The IC device assembly (1700) illustrated in FIG. 9 includes a package-on-interposer structure (1736) coupled to a first side (1740) of a circuit board (1702) by a coupling component (1716). The coupling component (1716) can electrically and mechanically couple the package-on-interposer structure (1736) to the circuit board (1702) and may include a solder ball (illustrated in FIG. 9), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0064] The package-on-interposer structure (1736) may include an IC package (1720) coupled to the package interposer (1704) by a coupling component (1718). The coupling component (1718) may take any suitable form for the application, as in the form described above in relation to the coupling component (1716). Although a single IC package (1720) is shown in FIG. 9, multiple IC packages may be coupled to the package interposer (1704), and in practice, additional package interposers may be coupled to the package interposer (1704). The package interposer (1704) may provide an intervening substrate used to bridge the circuit board (1702) and the IC package (1720). The IC package (1720) may be, for example, a die, an IC device, or any other suitable component, or may include these. Generally, the package interposer (1704) can spread connections with a wider pitch or reroute connections to other connections. For example, the package interposer (1704) can be coupled to a set of BGA conductive contacts of a coupling component (1716) to couple an IC package (1720) (e.g., a die) to a circuit board (1702). In the embodiment illustrated in FIG. 9, the IC package (1720) and the circuit board (1702) are attached to both sides of the package interposer (1704), but in other embodiments, the IC package (1720) and the circuit board (1702) may be attached to the same side of the package interposer (1704). In some embodiments, three or more components may be interconnected through the package interposer (1704).

[0065] In some embodiments, the package interposer (1704) may be formed as a PCB comprising a plurality of metal layers separated from one another by a dielectric material layer and interconnected by electrically conductive vias. In some embodiments, the package interposer (1704) may be formed from a polymer material such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin having an inorganic filler, ceramic material, or polyimide. In some embodiments, the package interposer (1704) may be formed from an alternative rigid or flexible material that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer (1704) may include metal lines (1710) and vias (1708), including TSVs (1706), though it is not limited to them. The package interposer (1704) may further include an embedded device (1714) comprising both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, PAs, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the package interposer (1704). The package-on-interposer structure (1736) may take any form of package-on-interposer structure known in the art. In some embodiments, the package interposer (1704) may include one or more substrate-integrated components.

[0066] The IC device assembly (1700) may include an IC package (1724) coupled to a first side (1740) of a circuit board (1702) by a coupling component (1722). The coupling component (1722) may take the form of any one of the embodiments described above with respect to the coupling component (1716), and the IC package (1724) may take the form of any one of the embodiments described above with respect to the IC package (1720).

[0067] The IC device assembly (1700) illustrated in FIG. 9 includes a package-on-package structure (1734) coupled to a second side (1742) of a circuit board (1702) by a coupling component (1728). The package-on-package structure (1734) may include an IC package (1726) and an IC package (1732) coupled together by a coupling component (1730) such that the IC package (1726) is positioned between the circuit board (1702) and the IC package (1732). The coupling component (1728, 1730) may take the form of any one of the embodiments of the coupling component (1716) discussed above, and the IC package (1726, 1732) may take the form of any one of the embodiments of the IC package (1720) described above. The package-on-package structure (1734) can be configured according to any package-on-package structure known in the industry.

[0068] FIG. 10 is a block diagram of an exemplary electronic device (1800) that may include one or more microelectronic packages having one or more substrate-integrated components according to any embodiment disclosed herein. For example, any suitable component among the components of the electronic device (1800) may include one or more of an IC device assembly (1700), an IC package, an IC device, or a die disclosed or discussed herein. Although a number of components included in the electronic device (1800) are illustrated in FIG. 10, one or more of these components may be omitted or repeated to suit the application. In some embodiments, some or all of the components included in the electronic device (1800) may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0069] Additionally, in various embodiments, the electric device (1800) may not include one or more of the components illustrated in FIG. 10, but the electric device (1800) may include an interface circuit for coupling to one or more of these components. For example, the electric device (1800) may not include a display device (1806), but may include a display device interface circuit (e.g., a connector and a driver circuit) to which the display device (1806) can be connected. In another set of examples, the electric device (1800) may not include an audio input device (1824) or an audio output device (1808), but may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which the audio input device (1824) or the audio output device (1808) can be connected.

[0070] The electrical device (1800) may include a processing device (1802) (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. The memory processing device (1802) may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms within hardware), server processors, or other suitable processing devices. The electrical device (1800) may include a memory (1804) that may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., ROM), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory (1804) may include a memory that shares a die with the processing device (1802). These memories may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0071] In some embodiments, the electric device (1800) may include a communication chip (1812) (e.g., one or more communication chips). For example, the communication chip (1812) may be configured to manage wireless communication for data transmission with the electric device (1800). The term “wireless” and its derivatives may be used to denote circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data over a non-solid medium using modulated electromagnetic radiation. These terms do not imply that the devices in question do not include any wires, although this may be the case in some embodiments.

[0072] The communication chip (1812) can implement any of a number of wireless standards or protocols, including but not limited to IEEE (Institute for Electrical and Electronic Engineers) standards, such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16 - 2005 revision), LTE (Long-Term Evolution) projects and any modifications, updates and / or revisions (e.g., Advanced LTE projects, UMB (Ultra Mobile Broadband) projects (also called "3GPP2"), etc.). An IEEE 802.16 compatible Broadband Wireless Access (BWA) network is generally referred to as a WiMAX network, which is an abbreviation for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformity and interoperability tests for the IEEE 802.16 standard. The communication chip (1812) can operate according to GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), HSPA (High Speed ​​Packet Access), E-HSPA (Evolved HSPA), or LTE networks. The communication chip (1812) can operate according to EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network), or E-UTRAN (Evolved UTRAN).The communication chip (1812) may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as other wireless protocols designated as 3G, 4G, 5G, and the next generation. In other embodiments, the communication chip (1812) may operate according to other wireless protocols. The electrical device (1800) may include an antenna (1822) for facilitating wireless communication and / or receiving other wireless communication (e.g., AM or FM radio transmission).

[0073] In some embodiments, the communication chip (1812) may manage wired communication such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As mentioned above, the communication chip (1812) may include a number of communication chips. For example, the first communication chip (1812) may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and the second communication chip (1812) may be dedicated to long-range wireless communication such as GPS (Global Positioning System), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip (1812) may be dedicated to wireless communication, and the second communication chip (1812) may be dedicated to wired communication.

[0074] The electric device (1800) may include a battery / power circuit (1814). The battery / power circuit (1814) may include one or more energy storage devices (e.g., a battery or a capacitor) and / or a circuit for connecting a component of the electric device (1800) from the electric device (1800) to a separate energy source (e.g., AC line power).

[0075] The electrical device (1800) may include a display device (1806) (or a corresponding interface circuit as described above). The display device (1806) may include any visual indicator such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0076] The electrical device (1800) may include an audio output device (1808) (or a corresponding interface circuit as described above). The audio output device (1808) may include any device that produces an audible indicator, such as a speaker, a headset, or earbuds.

[0077] The electrical device (1800) may include an audio input device (1824) (or a corresponding interface circuit as described above). The audio input device (1824) may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument having a MIDI (musical instrument digital interface) output).

[0078] The electric device (1800) may include a GPS device (1818) (or a corresponding interface circuit as described above). The GPS device (1818) may communicate with a satellite-based system and receive the location of the electric device (1800) as is known in the industry.

[0079] The electrical device (1800) may include another output device (1810) (or a corresponding interface circuit as described above). Examples of the other output device (1810) may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to another device, or an additional storage device.

[0080] The electrical device (1800) may include another input device (1820) (or a corresponding interface circuit as described above). Examples of the other input device (1820) may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a QR (Quick Response) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0081] The electric device (1800) may have any desired form factor, such as a handheld or portable electric device (e.g., mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, PDA (Personal Digital Assistant), ultra-mobile personal computer, etc.), a desktop electric device, a server device or other network computing component, a printer, a scanner, a monitor, a set-top box entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electric device. In some embodiments, the electric device (1800) may be any other electronic device that processes data.

[0082] Examples of various embodiments

[0083] Example 1 includes a substrate having multiple layers, a die coupled to a face of the substrate, an inductor disposed within the substrate and within the die shadow of the die, and an electromagnetic interference (EMI) shielding element disposed within the substrate and surrounding the inductor.

[0084] Example 2 includes the microelectronic package of Example 1, and the inductor includes metal elements located on two layers of the substrate.

[0085] Example 3 includes the microelectronic package of Example 1, and the inductor includes a conductive element in a first layer of the package substrate, a conductive element in a second layer of the package substrate, and a conductive element in a third layer of the package substrate, and the conductive elements of the first and second layers are electronically coupled by trench vias.

[0086] Example 4 includes the microelectronic package of Example 1, and the EMI shielding element includes a through-substrate via (TSV) within the substrate.

[0087] Example 5 includes a microelectronic package of any one of Examples 1-4, and an EMI shielding element further surrounds the die.

[0088] Example 6 includes a microelectronic package of any one of Examples 1-4, and the die is a power amplifier (PA) or an acoustic resonator (AWR).

[0089] Example 7 includes a microelectronic package of any one of Examples 1-4, wherein a plurality of layers comprises a first subset layer, each layer of the first subset layer has a first z-height, and a plurality of layers comprises a second subset layer, each layer of the second subset layer has a second z-height.

[0090] Example 8 includes a microelectronic package of any one of Examples 1-4, and the microelectronic package has a z-height of less than 300 micrometers ("microns").

[0091] Example 9 includes a die for use in a radio frequency (RF) front-end module (FEM), the die includes a substrate, a first subsystem associated with a first function of the RF FEM—the first subsystem is coupled to the substrate—and a second subsystem associated with a second function of the RF FEM—the second subsystem is coupled to the substrate—and a trench via located on the substrate and coupled to the first subsystem and the second subsystem in a communicable manner.

[0092] Example 10 includes the die of Example 9, and the first function is related to a power amplifier (PA) and the second function is related to an integrated passive device (IPD), logic, or switch.

[0093] Example 11 includes the die of Example 9 or 10, the first function is related to a resonator, and the second function is related to a filter.

[0094] Example 12 includes the die of Example 9 or 10, and the substrate includes an inductor within the substrate, and the inductor is coupled to communicate with the first logic or the second logic.

[0095] Example 13 includes the die of Example 12, and the inductor is electromagnetically shielded by vias in the substrate.

[0096] Example 14 includes a method for forming a microelectronic package for use in a radio frequency (RF) front-end module (FEM), the method including the steps of lithographically defining traces on a substrate to form an inductor, lithographically defining vias on a substrate to form an electromagnetic shield surrounding the inductor, and joining the die to the substrate such that the inductor is in the die shadow of the die.

[0097] Example 15 includes the method of Example 14, and the die includes a subsystem related to the first function of the RF FEM and a subsystem related to the second function of the RF FEM.

[0098] Example 16 includes the method of Example 14, and the die is an acoustic resonator (AWR).

[0099] Example 17 includes the method of Example 14 and further includes the step of combining the second die with the substrate.

[0100] Example 18 includes any one of the methods of Examples 14-17, and the step of defining a trace by a lithographic method to form an inductor includes the step of defining a first trace by a lithographic method within a first layer of a substrate and defining a second trace by a lithographic method within a second layer of a substrate, and the step of combining the first trace and the second trace so as to be communicable.

[0101] Example 19 includes the method of Example 18, and the step of lithographically defining a trace to form an inductor further includes the step of lithographically defining a third trace within a third layer of the substrate.

[0102] Example 20 includes the method of Example 19 and further includes the step of lithographically defining a trench via to communicably connect the third trace and the second trace.

[0103] Various embodiments may include any suitable combination of the foregoing embodiments (e.g., “and” may be “and / or”), including alternative (or) embodiments of the embodiments described above in a linked form (and). Furthermore, some embodiments may include one or more manufactured articles (e.g., non-transient computer-readable media) storing instructions that, when executed, perform the operation of any foregoing embodiment. Additionally, some embodiments may include a device or system having any suitable means for performing the various operations of the foregoing embodiments.

[0104] The foregoing description of the exemplified embodiments, including those described in the summary, is not intended to be exclusive or limiting of the exact form disclosed. While specific implementations and examples of various embodiments or concepts are described herein for illustrative purposes, various equivalent modifications may be possible as recognized by those skilled in the art. Such modifications may be made in light of the above detailed description, summary, drawings, or claims.

Claims

Claim 1 A microelectronic package comprises a package substrate, a die coupled to a face of the package substrate, an overmold material that at least partially surrounds the die—the overmold material includes conductive through-mold vias (TMVs) adjacent to the die—a first inductor and a second inductor disposed within the package substrate and within the die shadow of the die, and an electromagnetic interference (EMI) shielding element located within the package substrate and surrounding the first inductor and the second inductor, wherein the package substrate comprises a first redistribution layer having a first thickness and a second redistribution layer having a second thickness, the second thickness being smaller than the first thickness, the first inductor being within the first redistribution layer, the second inductor being within the second redistribution layer, and the second inductor having a Q-factor smaller than that of the first inductor Microelectronic package having Claim 2 In claim 1, at least one of the first inductor and the second inductor comprises a metal element located on two layers of the package substrate, in a microelectronic package. Claim 3 A microelectronic package according to claim 1, wherein at least one of the first inductor and the second inductor comprises a conductive element in a first layer of the package substrate, a conductive element in a second layer of the package substrate, and a conductive element in a third layer of the package substrate, wherein the conductive element of the first layer and the conductive element of the second layer are electronically coupled by trench vias. Claim 4 In claim 1, the EMI shielding element is a microelectronic package comprising a through-substrate via (TSV) within the package substrate. Claim 5 In claim 1, the EMI shielding element is a microelectronic package further surrounding the die. Claim 6 In claim 1, the die is a microelectronic package that is a power amplifier (PA) or an acoustic resonator (AWR). Claim 7 A microelectronic package according to claim 1, wherein the package substrate comprises a plurality of layers, the plurality of layers comprises a first subset layer including a first redistribution layer, each layer of the first subset layer having a first z-height, the plurality of layers comprises a second subset layer including a second redistribution layer, and each layer of the second subset layer having a second z-height. Claim 8 In claim 1, the microelectronic package is a microelectronic package having a height of less than 300 micrometers. Claim 9 In claim 1, the inductor is a multi-loop inductor in a microelectronic package. Claim 10 In claim 1, the microelectronic package is a microelectronic package that is an RF front-end module (FEM). Claim 11 A microelectronic package according to claim 1, further comprising an EMI shielding layer on the overmolded material above at least a portion of the die. Claim 12 An electronic device comprising a processing device and a communication chip, wherein at least one of the processing device and the communication chip comprises a microelectronic package, and the microelectronic package comprises a package substrate comprising a first redistribution layer and a second redistribution layer thinner than the first redistribution layer, a die coupled to a face of the package substrate, an overmolding material comprising a conductive TMV at least partially surrounding the die and adjacent to the die, a first inductor and a second inductor located in each of the first redistribution layer and the second redistribution layer of the package substrate and within the die shadow of the die, and an electromagnetic interference (EMI) shielding element located within the package substrate and surrounding the inductor. Claim 13 An electronic device according to claim 12, wherein at least one of the first inductor and the second inductor comprises a metal element located on two layers of the package substrate. Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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