Temperature-locked loop for optical elements with temperature-dependent response

Abstract

The example described herein generally relates to a temperature-locked loop for optical elements. In the example, the device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a sheer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. The input node of the sheer circuit is coupled to the output node of the DCTS. The processor has an input node coupled to the output node of the sheer circuit. The DAC has an input node coupled to the output node of the processor and is configured to be coupled to a heater. Based on the signal output by the sheer circuit, the processor is configured to control both the DCTS and the output voltage on the output node of the DAC to reduce the DC component of the signal on the output node of the DCTS.

Description

Technology Field

[0001] Examples of the present disclosure generally relate to temperature-locked loops for optical elements having a temperature-dependent response. Background Technology

[0002] Optical devices have been used for communication such as through optical fiber channels. Optical communication can enable low-loss physical channels and high speeds. As with electrical devices, some optical devices can be used to process or filter signals, even if they are optical signals. However, some optical devices may possess features that are absent or insignificant in electrical devices. The further growth and implementation of optical devices in future technologies may require these features to be addressed.

[0003] The examples described herein relate to devices and methods for temperature locking loops for optical elements having a temperature-dependent response. In some examples, setting tracking and temperature locking may be implemented for optical devices operating at high speeds.

[0004] An example described herein is a device. The device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage, a slicer circuit, and a processor. The DC-controllable transimpedance stage has an input node and an output node. The input node of the DC-controllable transimpedance stage is configured to be electrically coupled to a photodiode. The slicer circuit has an input node and an output node. The input node of the slicer circuit is electrically coupled to the output node of the DC-controllable transimpedance stage. The processor has an input node that is electrically coupled to the output node of the slicer circuit. The processor is configured to control the DC-controllable transimpedance stage to reduce the DC component of the signal on the output node of the DC-controllable transimpedance stage based on the signal on the output node of the slicer circuit. The DAC has an input node electrically coupled to the output node of the processor and an output node configured to be electrically coupled to the heater. The processor is configured to control the output voltage on the output node of the DAC based on a signal on the output node of the slicer circuit.

[0005] Another example described herein is a method for controlling the temperature of a device. A DC setting is generated by a processor, wherein the DC setting is output from the processor to a DC-controllable transimpedance stage. The DC-controllable transimpedance stage has an input node electrically coupled to a photodiode. The photodiode is configured to receive an optical signal passed from an optical element. The optical element has a temperature-dependent optical response. The processor generates a DC setting based on a signal on the output node of the DC-controllable transimpedance stage. After generating the DC setting, a temperature setting is generated by the processor. A code output from the processor to a DAC is based on the voltage setting. The DAC has an output node electrically coupled to a heater positioned in close proximity to the optical element. The processor generates a temperature setting based on a signal on the output node of the DC-controllable transimpedance stage.

[0006] Another example described herein is a device. The device includes an optical element, a photodiode, a heater, a transimpedance stage, a slicer circuit, and a processor. The optical element is configured to pass an optical signal and has a temperature-dependent optical response. The photodiode is positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode. The heater is positioned in close proximity to the optical element and is configured to convert electrical energy into thermal energy. The input node of the transimpedance stage is electrically coupled to the photodiode. The transimpedance stage includes a controllable current source electrically connected between the input node of the transimpedance stage and a power node. The input node of the slicer circuit is electrically coupled to the output node of the transimpedance stage. The input node of the processor is electrically coupled to the output node of the slicer circuit. The processor is configured to control the current of a controllable current source based on an output signal on the output node of the slicer circuit, and is configured to control the amount of electrical energy supplied to the heater based on an output signal on the output node of the slicer circuit.

[0007] These and other embodiments can be understood by referring to the detailed description below. Brief explanation of the drawing

[0008] In order to enable a detailed understanding of the features cited above, more specific descriptions of the briefly summarized above may be obtained by referring to exemplary embodiments, some of which are illustrated in the attached drawings. However, it should be noted that the attached drawings merely illustrate typical exemplary embodiments and should not be construed as limiting their scope. Figure 1 is a package of a device according to some examples. FIG. 2 is a simplified schematic diagram of at least a part of the device of FIG. 1 according to some examples. Figures 3a and 3b are charts illustrating the effects when the center wavelength of an optical signal according to some examples is on the right (right-hand side, RHS) and left (left-hand side, LHS), respectively, of the peak of the magnitude of the optical response. FIG. 4 is a more detailed illustration of a simplified schematic diagram of FIG. 2 according to some examples. Figure 5 is a flowchart of a method for a temperature-fixed loop according to some examples. FIG. 6 illustrates a schematic diagram of a digital signal processor (DSP) of FIG. 4 according to some examples. FIG. 7 is a timing diagram of various signals of a DSP according to some examples, a voltage output from a digital-to-analog converter (DAC) of FIG. 4, and the temperature of a heater of FIG. 4. FIG. 8 is a schematic circuit diagram of a controllable current source according to some examples. FIG. 9 is a timing diagram of the thermal code output by the DSP, the voltage output from the DAC of FIG. 4, and the temperature of the heater of FIG. 4, according to some examples. FIG. 10 is a schematic diagram of a pulse width modulation (PWM) circuit of a DSP according to some examples. FIGS. 11a and FIGS. 11b are timing diagrams illustrating signals generated in PWM circuits in different modes according to some examples. Figures 12a and 12b are flowcharts of the operation of a tracking circuit of a DSP according to some examples. FIG. 13 is a simplified schematic diagram of a device according to some examples. FIG. 14 is a flowchart of the sequential operation of the device of FIG. 13 according to some examples. For the sake of understanding, the same reference numbers have been used to designate identical elements common to the drawings whenever possible. It is considered that elements of one example may be beneficially merged in other examples. Detailed explanation The examples described herein relate to devices and methods for a temperature-locked loop for optical elements having a temperature-dependent response. Generally, devices according to some examples include an electrical integrated circuit (IC) die (containing an electrical IC) and an optical die (containing an optoelectronic circuit). The optical die and the optoelectronic circuit include an optical element, a photodiode, and a heater. The optical element is configured to pass an optical signal, and the optical element has a temperature-dependent optical response. Exemplary optical elements include a ring modulator, a dual-ring filter, a Mech-Zehnder interferometer (MZI), etc. The photodiode is positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode. A heater is positioned in close proximity to the optical element. The electrical IC die and the electrical IC include a controller and a first digital-to-analog converter (DAC). The photodiode is electrically coupled to the input node of the controller. The output node of the controller is electrically coupled to the input node of the first DAC, and the output node of the first DAC is electrically coupled to the heater. Generally, the controller is configured to control the temperature of the heater and thereby control the optical element so that the optical element can have a target optical response at the target wavelength of the optical signal. The controller can cause the first DAC to output a voltage having a dithering duty cycle. Additionally, the controller of the electrical IC may include a transimpedance stage, a slicer circuit, and a processor (e.g., a digital signal processor (DSP)). The transimpedance stage may include a controllable current source having a second DAC and a transimpedance amplifier. The processor is configured to repeatedly track DC settings and temperature settings. The DC settings may include a code output to the second DAC that causes the second DAC to output a bias voltage to the controllable current source and / or one or more selection signals that cause a biased transistor in the controllable current source to operably engage or disengage. The controllable current source is configured to reduce and / or eliminate the DC component of the signal output by the transimpedance stage. The temperature settings may include a level selection value and a duty code, and in some examples, a thermal code having a dither duty cycle is generated based on the level selection value and the duty code and output to the first DAC. The voltage output from the first DAC can control a heater to achieve a temperature in the optical die such that the optical element has an optical response having a peak or trough aligned with, for example, a target wavelength. DC settings and temperature settings can be tracked based on signals sampled from the slicer circuit and based on each signal output from the transimpedance stage. In some examples, tracking and locking can be implemented for optical devices operating at high speeds, such as 53 Gb / s or higher. Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are indicated by similar reference numbers throughout the drawings. It should be noted that the drawings are intended merely to facilitate the description of features. They are not intended as an all-encompassing description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the examples illustrated are not required to have all the embodiments or advantages shown. The embodiments or advantages described in relation to a particular example are not necessarily limited to that example and may be practiced in any other examples even if they are not so illustrated or so explicitly described. Additionally, while the methods described herein may be described in a specific order of operations, other methods according to other examples may be implemented in various other orders having more or fewer operations (e.g., including different serial or parallel performance of various operations). In the following description, various signals, data, or codes are described in relation to the operation of various circuits. The described signal, data, or code indicates a corresponding node to which the signal, data, or code is applied or propagated, and also indicates nodes that are communicably coupled or electrically connected. For example, the description of a signal, data, or code output from a first circuit and an input to a second circuit indicates that the output node of the first circuit (where the signal, data, or code is output from the first circuit) is communicably coupled or electrically connected to the input node of the second circuit. Explicit description of such nodes may be omitted in the following description, but those skilled in the art will readily understand the existence of the nodes. Additionally, a given node may have multi-bit positions, such as those for multi-bit data or multi-bit codes. FIG. 1 illustrates a package (100) of a device according to some examples. The package (100) includes an electrical integrated circuit (IC) die (102), an optical die (104), and a package substrate (106). The electrical IC die (102) includes various circuits configured to generate an electrical signal transmitted to the optical die (104) and includes a control circuit configured to control the optical response of the optical die (104). The optical die (104) is configured to generate an optical signal based on the received electrical signal and, for example, to transmit the optical signal through an optical fiber. The optical die (104) is mechanically attached and electrically coupled to the electric IC die (102) (e.g., the rear side of the electric IC die (102)) by external electrical connectors (112). In some examples, the external electrical connectors (112) are minibumps. The electric IC die (102) (e.g., the front side of the electric IC die (102)) is mechanically attached and electrically coupled to the first side of the package substrate (106) by external electrical connectors (114). In some examples, the external electrical connectors (114) are C4 (controlled collapse chip connection). The external electrical connectors (116) are located on the second side of the package substrate (106) (e.g., opposite the first side of the package substrate (106)) and are mechanically attached and electrically coupled to the package substrate (106). FIG. 2 is a simplified schematic diagram of at least a portion of the device of FIG. 1 according to some examples. In the illustrated example, the electric IC die (102) includes an electric IC (202), and the optical die (104) includes an optoelectronic circuit (204). The electric IC (202) includes a controller (210) and a DAC (212). Although not illustrated, the electric IC (202) further includes a circuit for generating an electric signal to be transmitted as an optical signal through an optical channel. The optoelectronic circuit (204) includes an optical source (220), an optical element (222), an optical output channel (224), a photodiode (226), and a heater (228). The optical element (222) may be any optical element configured to transmit an optical signal and having a temperature-dependent optical response, such as a ring modulator, a dual-ring filter, a Mech-Zehnder interferometer (MZI), etc. In some examples, the heater (228) is a resistor, but; Any heater can be implemented. Generally, the circuit of the electrical IC (202) generates an electrical signal that is transmitted to the optoelectronic circuit (204). The optical source (220) generates an optical signal based on the received electrical signal and transmits the optical signal to the optical element (222). The optical signal output from the optical element (222) is transmitted through the optical output channel (224). A photodiode (226) is placed in the optical die (104) so ​​that a portion of the optical signal output from the optical element (222) is incident on the photodiode (226). The photodiode (226) is configured to generate a current in response to the optical signal incident on the photodiode (226) (including being electrically coupled to a power node, such as a VDD node, for example). The photodiode (226) is electrically coupled to a controller (210), and the controller (210) is configured to detect the current generated by the photodiode (226). The controller (210) outputs a digital value to the DAC (212) in response to the detected current. The DAC (212) is configured to convert the digital value into an analog voltage and / or current. A heater (228) is electrically coupled to the DAC (212) and placed on the optical die (104) in proximity to the optical element (222). The DAC (212) is configured to output an analog voltage and / or current to the heater (228). In response to the received analog voltage and / or current, the heater (228) can control the temperature of the optical element (222). In some examples, the optical element (222) has an optical response that may vary based on the temperature of the optical element (222). FIGS. 3a and 3b are charts illustrating the effects of temperature on the optical response of the optical element (222) according to some examples. The charts in FIGS. 3a and 3b have wavelength (λ) along the x-axis and the magnitude of the optical response (|H|) of the optical element (222) (e.g., as a function of wavelength) along the y-axis. FIGS. 3a and 3b illustrate the center wavelength (λc) (302) of the optical signal output by the optical element (222). FIGS. 3a illustrates the effects when the center wavelength (λc) (302) is at the right (RHS) of the peak of the optical response magnitude, and FIGS. 3b illustrates the effects when the center wavelength (λc) (302) is at the left (LHS) of the peak of the optical response magnitude. FIG. 3a illustrates a first response (304) when the optical element (222) is at a first temperature and a second response (306) when the optical element (222) is at a second temperature. The first temperature is lower than the second temperature. In this RHS scenario, the first response (304) has a magnitude (314) at the center wavelength (λc) (302) that is smaller than the magnitude (316) of the second response (306) at the center wavelength (λc) (302). Increasing the temperature of the optical element (222) from the first temperature to the second temperature increases the magnitude at the center wavelength (λc) (302), which brings the center wavelength (λc) (302) closer to the peak for the second response (306). Conversely, reducing the temperature of the optical element (222) from the second temperature to the first temperature can reduce the magnitude at the center wavelength (λc) (302), which moves the center wavelength (λc) (302) further away from the peak for the first response (304). FIG. 3b illustrates a first response (324) when the optical element (222) is at a first temperature and a second response (326) when the optical element (222) is at a second temperature. The first temperature is lower than the second temperature. In this LHS scenario, the first response (324) has a magnitude (334) at the center wavelength (λc) (302) that is larger than the magnitude (336) of the second response (326) at the center wavelength (λc) (302). Increasing the temperature of the optical element (222) from the first temperature to the second temperature reduces the magnitude at the center wavelength (λc) (302), which moves the center wavelength (λc) (302) further away from the peak for the second response (326). Conversely, decreasing the temperature of the optical element (222) from the second temperature to the first temperature can increase the size at the center wavelength (λc) (302), which brings the center wavelength (λc) (302) closer to the peak for the first response (324). Generally, the examples described herein may control the temperature of the optical element (222) by means of a temperature locking loop to control the optical response of the optical element (222). A heater (228) is configured to generate mostly localized thermal energy in close proximity to the optical element (222), and the heater (228) is controlled by a controller (210). The controller (210) may control the heater (228) to provide thermal energy to increase and / or decrease the temperature of the optical element (222) in response to an optical signal detected by a photodiode (226), for example, to bring the peak or trough of the magnitude of the optical response of the optical element (222) closer to the center wavelength of the optical signal. In some examples, the heater (228) may not actively reduce the temperature of the optical element (222). Rather, thermal energy may be dissipated from the package (100) by employing, for example, a heat spreader, which, when combined with the amount of reduced thermal energy provided by the heater (228), can result in a reduction in the temperature of the optical element (222) (e.g., a total reduction in thermal energy). In these situations, the temperature may be increased by the heater (228) providing thermal energy at a greater rate than the thermal energy is dissipated, and the temperature may be reduced by the heater providing thermal energy at a lesser rate than the thermal energy is dissipated (if any). FIG. 4 is a more detailed illustration of a simplified schematic diagram of FIG. 2 according to some examples. The controller (210) includes a DC-controllable transimpedance stage, a slicer circuit (402), a DAC (404), and a DSP (406). The DC-controllable transimpedance stage includes a current source (410), a resistor (412), a transimpedance amplifier (TIA) (414), a controllable current source (416), and a DAC (418). The cathode of the photodiode (226) is electrically connected to a first power node (e.g., VDD node), and the anode of the photodiode (226) is electrically coupled to an input node (420) of a DC-controllable transimpedance stage—which may also be an input node of a controller (210). A current source (410) is electrically connected between the first power node (e.g., VDD node) and the input node (420). The current source (410) may be or include a current mirror biased by a static current so that the current source (410) is configured to provide a static or constant current. A controllable current source (416) is electrically connected between the input node (420) and a second power node (e.g., ground node). The first terminal of the resistor (412) is electrically connected to the input node (420), and the second terminal of the resistor (412) (opposite to the first terminal) is electrically connected to the output node (422) of the DC-controllable transimpedance stage. The input node of the TIA (414) is electrically connected to the input node (420), and the output node of the TIA (414) is electrically connected to the output node (422). The signal input node of the slicer circuit (402) is electrically connected to the output node (422) of the DC-controllable transimpedance stage. The reference voltage input node of the slicer circuit (402) is electrically connected to the output node of the DAC (404). The output node of the slicer circuit (402) is electrically connected to the input node of the DSP (406). In some examples, the slicer circuit (402) may be a comparator or may include a comparator. The input node of the DAC (404) may be electrically coupled to a memory element, for example, which stores a digital value corresponding to the reference voltage (Vref) (such as electrical fuses (e-fuses)). In some examples, the reference voltage (Vref) may be VDD / 2. The DSP (406) includes a controllable current source (416) and a DAC (418) and has one or more control output nodes electrically connected to each of one or more control input nodes of a DC-controllable transimpedance stage. The DSP (406) has a control output node electrically connected to the control input node of the controllable current source (416). The DSP (406) has another control output node electrically connected to the input node of the DAC (418). The output node of the DAC (418) is electrically connected to the bias voltage node of the controllable current source (416). In the illustrated example, the controllable current source (416) has two mechanisms by which the controllable current source (416) can be controlled, which will be described in detail later. In other examples, one and / or different mechanisms may be implemented to control the controllable current source (416). The DSP (406) has another output node electrically connected to the input node of the DAC (212). The DSP (406) may include combinational logic, sequential logic, state machine, and any other circuit, or any combination thereof. The DSP (406) is generally configured to implement the functions described herein and may also implement each of the functions by hardware alone, by hardware executing machine-executable instructions, or by a combination thereof (e.g., some of the functions are implemented by hardware alone, while other parts of the functions are implemented by hardware executing machine-readable instructions). The output node of the DAC (212) is electrically coupled to the input node of the heater (228). In the illustrated example, the heater (228) is or includes a resistor (430). In the illustrated example, the resistor (430) is electrically connected between the input node of the heater (228) and a power node (e.g., a ground node). When in operation, the photodiode (226) generates a current in response to an optical signal incident on the photodiode (226). The current generated by the photodiode (226) is received by the controller (210) at the input node (420) as an input current (Iin). The DC-controllable transimpedance stage generates a voltage signal at the output node (422) of the DC-controllable transimpedance stage based on the input current (Iin) at the input node (420). The slicer circuit (402) generates a logic "1" or a logic "0" based on whether the voltage signal at the output node (422) is greater than the reference voltage output by the DAC (404). The DAC (404) generates the reference voltage based on, for example, a digital value stored in a memory element that is communically coupled to the input node of the DAC (404). The reference voltage may be a static voltage, and as a result, in some examples, the digital value stored in the memory element may be static. The DSP (406) samples the logic "1" and logic "0" generated by the slicer circuit (402). As illustrated in FIG. 5, the DSP (406) repeatedly tracks DC settings in block (502) and tracks temperature settings in block (504). When tracking DC settings in block (502), the DSP (406) sets DC settings for the controllable current source (416) and DAC (418) to provide a current IDC that switches the DC component of the input current (Iin) at the input node (420) to a second power node (e.g., a ground node). This can cause the DC component of the voltage signal at the output node (422) to be reduced and / or removed. Reducing and / or removing this DC component of the voltage signal can allow the slicer circuit (402) and the DSP (406) to more accurately capture logic "1" and logic "0" for the optical signal incident on the photodiode (226). Generally, and as will be described in more detail later, the DSP (406) responsively increases or decreases the current IDC of the controllable current source (416) based on the number of logic "1s" and logic "0s" captured from the slicer circuit (402). The voltage output from the DAC (212) to the heater (228) is diluted between different duty cycles during the time period in which samples from the slicer circuit (402) are captured for DC setting tracking in the block (502). Generally, for a statistically significant sample size, it is assumed that the optical signal incident on the photodiode (226) has an equal number of logic "1s" and logic "0s". Thus, as the voltage output from the DAC (212) is dided between different duty cycles, if the number of captured logic "1s" is significantly greater than, for example, the number of captured logic "0s", a DC component may be present in the voltage signal at the output node (422), and the DSP (406) responsively adjusts the current IDC of the controllable current source (416) to reduce and / or eliminate the DC component of the voltage signal from the output node (422). Conversely, if the number of captured logic "0"s is significantly greater than, for example, the number of captured logic "1"s, the current IDC of the controllable current source (416) may incorrectly switch a portion of the AC component of the input current (Iin) at the input node (420), and the DSP (406) responsively adjusts the current IC of the controllable current source (416) to restore the switched AC component of the voltage signal at the output node (422). When tracking temperature settings in block (504), the DSP (406) sets a code provided to the DAC (212), which in turn provides voltage and / or current to the heater (228) (e.g., resistor (430)). Depending on the rate at which thermal energy is dissipated from the package (100) and the voltage and / or current, the temperature of the optical element (222) may be maintained, increased, or decreased, which may adjust the optical response of the optical element (222). The code has a dithering duty cycle. For example, the code may have one duty cycle in which the clock signal is logic low and another duty cycle in which the clock signal is logic high. As will be described in more detail later, the DSP (406) responsively increases or decreases the level of code and / or the duty cycle of the code provided to the DAC (212) based on the number of logic "1s" and logic "0s" sampled at a given time in each cycle of the clock signal. Generally, the number of captured logic "1s" and logic "0s" indicates whether the center wavelength of the optical signal is on the RHS or LHS of the optical response of the optical element (222), partly due to the DC settings. The DSP (406) causes the level of code and / or the duty cycle provided to the DAC (212) to be adjusted based on the number of captured logic "1s" and logic "0s" so that the temperature of the optical element (222) is responsively adjusted. For example, since the package (100) may be placed in an environment where the ambient temperature may vary, the DSP (406) may repeatedly track DC settings and temperature settings to adjust the amount of electrical energy supplied to the heater (228) that converts the heater into thermal energy. In each iteration, the DC settings may be reset to a predetermined initial amount so that the amount of current IDC of the controllable current source (416) can be newly determined for each iteration. The temperature settings may be adjusted for each iteration. In some examples, the temperature settings are not reset for each iteration. The following drawings and descriptions provide more detailed examples that are programmable in some embodiments. Other examples may not be programmable, or may be programmable in fewer, more, or different embodiments. Those skilled in the art will readily understand variations for modifying the following examples to omit or include various programmability. FIG. 6 illustrates a schematic diagram of a DSP (406) according to some examples. The DSP (406) includes a clock frequency division circuit (602), a clock generation circuit (604), multiplexers (606, 614), a maximum / minimum calculation circuit (608), a synchronization circuit (610), a tracking circuit (612), and a pulse width modulation (PWM) circuit (616). FIG. 6 also illustrates DACs (212, 418), a heater (228), a slicer circuit (402), and a controllable current source (416) to facilitate the description of various signals. Before describing FIG. 6 in detail, the various signals identified in FIG. 6 are generally described in relation to the timing chart of FIG. 7. This general description will help relate the operations and functions to be described in detail later. The DSP clock signal (dsp_clk) is generally the clock signal on which the operation of the DSP (406) is based. The track clock signal (track_clk) is a frequency-divided clock signal based on dsp_clk. In the examples described herein, track_clk has a frequency that is half the frequency of dsp_clk, but the frequency of track_clk may be other divided amounts of the frequency of dsp_clk. In the example, the frequency of dsp_clk is 875 MHz, and the frequency of track_clk is 437.5 MHz. The sampling clock signal (sampling_clk) and the peak lock signal (slicer_clk_peaklock) have the same frequency and are phase-aligned. sampling_clk partially controls when the DSP (406) is in the DC setting tracking phase of block (502) and when it is in the temperature setting tracking phase of block (504). sampling_clk may be programmable. Generally, sampling_clk has a frequency that is a smaller number of orders of magnitude than the frequency of dsp_clk. For example, the frequency of sampling_clk may be from approximately tens of kilohertz to approximately tens of megahertz. slicer_clk_peaklock is generally at a logic "1" level except for a short time in each cycle when a decision by the DSP (406) is made to increase or decrease the temperature settings, which resets the slicer circuit (402). The PWM mode clock signal (pwm_mode_clk) is illustrated in FIG. 7 and may not be apparent in the DSP (406). pwm_mode_clk represents the frequency at which signals are output from the PWM circuit (616). pwm_mode_clk is a frequency-divided clock signal based on dsp_clk. In the examples described below, pwm_mode_clk has a programmable frequency. The frequency of pwm_mode_clk can be any divided amount of the frequency of dsp_clk, whether programmable or not. In an example, pwm_mode_clk is programmable between two modes, one of which controls pwm_mode_clk to have a frequency that is 1 / 16 of the frequency of dsp_clk, and the other controls pwm_mode_clk to have a frequency that is 1 / 4 of the frequency of dsp_clk. The analog output voltage (Vout_thermal_dac) is output from the DAC (212) to the heater (228). Vout_thermal_dac is based on signals output from the DSP (406) and has the same frequency as pwm_mode_clk. Vout_thermal_dac oscillates between a k-level voltage (v[k]) and a (k+1)-level voltage (v[k+1]). The duty cycle of Vout_thermal_dac is dithered based on sampling_clk. When sampling_clk is logic low, Vout_thermal_dac has a duty cycle DC0, and when sampling_clk is logic high, Vout_thermal_dac has a duty cycle DC1. Duty cycle DC1 is greater than duty cycle DC0. Vout_thermal_dac with duty cycle DC0 causes the temperature in the heater (228) to become temperature Temp0. Vout_thermal_dac with duty cycle DC1 causes the temperature in the heater (228) to become temperature Temp0+deltaTemp. The delay (702) in the change from duty cycle DC0 to duty cycle DC1 may occur before the change in response to the temperature. The temperature in the heater (228) may be a composite function of the rate at which electrical energy is converted into thermal energy by the heater (228) and the rate at which thermal energy is dissipated from the package (100). When Vout_thermal_dac is larger (e.g., for voltage v[k+1] versus voltage v[k]), greater thermal energy is converted in the heater (228). Consequently, a larger duty cycle of Vout_thermal_dac causes more thermal energy to be converted in the heater (228) compared to a Vout_thermal_dac of a smaller duty cycle (assuming Vout_thermal_dac dithers between the same voltages for the duty cycles). This can cause more thermal energy to accumulate in the heater (228), which can increase the temperature. The increase in temperature may be a logarithmic response, but FIG. 7 illustrates a step increase or decrease for the sake of example. In some examples, the delay (702) between the time the duty cycle of Vout_thermal_dac increases and the time the temperature in the heater (228) reaches temperature Temp0+deltaTemp is about 6 μs. Multiple cycles of diding Vout_thermal_dac may occur between the time the duty cycle increases and the time the temperature in the heater (228) reaches temperature Temp0+deltaTemp. The temperature in the heater (228) can be controlled by selecting which k-level voltage v[k] and (k+1)-level voltage v[k+1] will be dithered, and by selecting the duty cycle for dithering Vout_thermal_dac. Selecting a value for k determines the voltage levels that Vout_thermal_dac dithers. Selecting these voltage levels can determine the possible temperature range that can be achieved in the heater (228) (e.g., from temperature Temp[k] to temperature Temp[k+1]). Selecting the duty cycle of Vout_thermal_dac for the dither can achieve a temperature in the range from temperature Temp[k] to temperature Temp[k+1] in the heater (228). The duty cycle can achieve interpolation of the temperature in the heater (228) within the range from temperature Temp[k] to temperature Temp[k+1] due to the accumulation (e.g., integration) of thermal energy converted by the heater (228). Lower duty cycles can cause the temperature in the heater (228) to approach temperature Temp[k], whereas higher duty cycles can cause the temperature in the heater (228) to approach temperature Temp[k+1]. Referring again to FIG. 6, the clock frequency divider circuit (602) is configured to divide the frequency of an input clock signal into two portions, for example. The clock frequency divider circuit (602) may include a clocked D flip-flop configured to divide the frequency into two. dsp_clk is an input on the input node of the clock frequency divider circuit (602), and track_clk is an output on the output node of the clock frequency divider circuit (602). The clock generation circuit (604) is configured to generate sampling_clk and slicer_clk_peaklock based on track_clk, a programmable sampling frequency value (prog_sampling_freq), and a programmable sampling offset value (prog_sampling_offset). The clock generation circuit (604) may include any suitable logic or other circuit for generating sampling_clk and slicer_clk_peaklock. prog_sampling_freq may select a primary frequency for sampling_clk, and the available primary frequencies may be determined by the architecture and circuit implemented by the clock generation circuit (604). prog_sampling_offset may select a number of additional cycles of track_clk to be included within one cycle for sampling_clk, and the available number of additional cycles may be determined by the architecture and circuit implemented by the clock generation circuit (604). For example, assuming that 32,768 cycles of track_clk occur for each cycle of the selected primary frequency represented by prog_sampling_freq, and that the number of additional cycles represented by prog_sampling_offset is 128, then sampling_clk will accordingly have a frequency that achieves 32,896 (e.g., 32,768 + 128) cycles of track_clk per cycle of sampling_clk. The frequency of sampling_clk can be written mathematically as presented below: Here, fsampling_clk and ftrack_clk are the respective frequencies of sampling_clk, f(prog_sampling_freq) is the first frequency represented by prog_sampling_freq, and C(prog_sampling_freq) is the number of additional cycles represented by prog_sampling_offset. Table 1 below lists exemplary values ​​for ftrack_clk, prog_sampling_freq, f(prog_sampling_freq), prog_sampling_offset, C(prog_sampling_freq), and fsampling_clk in the example. [Table 1] The clock generation circuit (604) also generates slicer_clk_peaklock based on sampling_clk. Slicer_clk_peaklock is generally at a logic level that enables the slicer circuit (402) except for a relatively short amount of time during each cycle of sampling_clk, as described above, where slicer_clk_peaklock is at a logic level that resets the slicer circuit (402). The time during which Slicer_clk_peaklock is at a logic level that resets the slicer circuit (402) allows the DSP (406) to determine, and possibly adjust, the code output to the DAC (212) during the temperature setting tracking step in block (504). The multiplexer (606) is configured to receive track_clk at the "1" selected input node and slicer_clk_peaklock at the "0" selected input node. The multiplexer (606) is configured to selectively output track_clk and the slicer_clk_peaklock as slicer clock signals (slicer_clk) based on control signals input from the multiplexer (614), which will be described later. Generally, when DC setting tracking is enabled, slicer_clk is track_clk during the DC setting tracking phase of block (502), and slicer_clk is slicer_clk_peaklock during the temperature setting tracking phase of block (504). When DC setting tracking is disabled, slicer_clk is track_clk. The maximum / minimum calculation circuit (608) is configured to calculate the maximum and / or minimum number of logic "1" and / or "0" that are targeted for capture during the cycle of sampling_clk. Since the signal captured from the slicer circuit (402) is a complementary signal, determining the maximum number of logic "1" can also represent the minimum number of logic "0", and vice versa. Accordingly, various logic can be implemented using any one or a combination of the maximum and / or minimum number of logic "1" and / or "0". In the example described herein, the maximum / minimum calculation circuit (608) is configured to calculate the maximum and minimum number of logic "1". The maximum / minimum calculation circuit (608) may include any suitable logic or other circuit for calculating the maximum and / or minimum. The maximum / minimum calculation circuit (608) is configured to calculate the maximum number of logic "1"s (MAX1) and the minimum number of logic "1"s (MIN1) based on the programmable TIA DC error rate value (prog_tia_dc_ratio), prog_sampling_freq, prog_sampling_offset, and track_clk in the illustrated example. Prog_tia_dc_ratio represents the percentage of error samples that can be included in the number of samples captured from the slicer circuit (402) within one cycle of sampling_clk. For example, 1% of the number of samples captured may be errors, and if the number of samples is 32,896 (e.g., the number of cycles of track_clk per cycle of sampling_clk in the above example), the number of error samples may be 329 out of 32,896. For DC setting tracking, multiple samples are captured from the slicer circuit (402) based on track_clk during individual cycles of sampling_clk. During the cycles of sampling_clk, Vout_thermal_dac has different duty cycles for different parts of sampling_clk, as described above in relation to FIG. 7. Accordingly, after a delay (702), during one cycle of sampling_clk, the temperature in the heater (228) will be dimmed so that the response of the optical element (222) is likewise dimmed. Under these conditions, if the DC component of the input current (Iin) is present and is not substantially removed, the samples captured from the slicer circuit (402) based on track_clk may have a significantly larger number of logic "1s" compared to the number of logic "0s," or vice versa. Ideally (though not practical), the DC component of the input current (Iin) is removed, and the number of logic "1s" is equal to the number of logic "0s." For a statistically significant sample size, it is assumed that the number of logic "1s" of the optical signal incident on the photodiode (226) is equal to the number of logic "0s," so that the number of logic "1s" in the samples captured by the slicer circuit (402) is equal to the number of logic "0s." Accordingly, any deviation of the number of captured logic "1s" equal to the number of captured logic "0s" is assumed to be an error. As a result, MAX1 is calculated as the sum of half the number of cycles of track_clk per cycle of sampling_clk and 1.5 times the percentage represented by prog_tia_dc_ratio, and MIN1 is calculated as the sum of half the number of cycles of track_clk per cycle of sampling_clk and -0.5 times the percentage represented by prog_tia_dc_ratio.As shown above, the number of cycles of track_clk per cycle of Sampling_clk can be calculated as the sum of the number of additional cycles of track_clk and prog_sampling_offset per cycle of the primary frequency represented by prog_sampling_frequency. MAX1 can be written mathematically as presented below: Here, ftrack_clk, f(prog_sampling_freq), and C(prog_sampling_offset) are as mentioned above, and E(prog_tia_dc_ratio) is the percentage (divided by 100) represented by prog_tia_dc_ratio. If MAX1 is not an integer, MAX1 is rounded down to the nearest integer. MIN1 can be written mathematically as presented below: If MIN1 is not an integer, MIN1 is rounded to the nearest integer. Table 2 below lists exemplary values ​​for prog_tia_dc_ratio, E(prog_tia_dc_ratio), and the resulting MIN1 and MAX1, assuming prog_sampling_freq[1:0] = 00 and prog_sampling_offset[3:0] = 0000 as shown in Table 1. [Table 2] In particular, before going to the tracking circuit (612), signals output from the tracking circuit (612) to the DAC (418) and the controllable current source (416) are described. The transimpedance stage DAC digital code (tia_dac_code) is a multi-bit value (e.g., an 8-bit value) output from the tracking circuit (612) to the DAC (418). The DAC (418) converts the multi-bit value of the tia_dac_code into an analog bias voltage (v_tia_dac) output to the controllable current source (416). The transimpedance stage current selection digital code (tia_ictrl) is a multi-bit code (e.g., an 8-bit code) output from the tracking circuit (612) to the controllable current source (416). Generally, the controllable current source (416) comprises a number of series-connected pairs of transistors electrically connected in parallel (e.g., channels of electrically series-connected transistors). For each pair, one of the transistors has a gate node electrically connected to v_tia_dac to bias the resistor to have a resistance, and the other of the transistors has a gate node electrically connected to each bit position of tia_ictrl to selectively and operablely electrically connect each pair of transistors in a parallel configuration. Referring briefly to FIG. 8 to explain V_tia_dac and tia_ictrl, an exemplary controllable current source (416) is illustrated. The controllable current source (416) comprises i pairs connected in series of n-type transistors (802-0, 804-0, 802-1, 804-1, . . . 802-(i-1), 804-(i-1)) (e.g., n-type field-effect transistors (FETs)). For each pair of series-connected n-type transistors (802, 804), the source node of the n-type transistor (802) is electrically connected to a power node (e.g., a ground node); the drain node of the n-type transistor (802) is electrically connected to the source node of the n-type transistor (804); and the drain node of the n-type transistor (804) is electrically connected to node (810). As a result, i series-connected pairs of n-type transistors (802, 804) are electrically connected in parallel. Each gate node of the n-type transistors (802) is electrically connected to the node to which v_tia_dac is applied. Each gate node of the n-type transistors (804) is electrically connected to the node to which each bit value of tia_ictrl is applied. For example, the gate node of the n-type transistor (804-0) is electrically connected to the node to which tia_ictrl[0] is applied; The gate node of the n-type transistor (804-1) is electrically connected to the node to which tia_ictrl[1] is applied, etc. V_tia_dac can bias the n-type transistors (802) to have a desired resistance. The bit positions of Tia_ictrl can selectively cause the n-type transistors (804) to be individually open (e.g., non-conducting) or closed (e.g., conducting) to selectively and operablely connect the parallel n-type transistors (802) to achieve effective resistance. Operablely electrically connecting the parallel biased n-type transistors (802) can control the current IDC flowing through the node (810). Referring again to FIG. 6, the synchronization circuit (610) is configured to synchronize the input signal (tia_in) from the slicer circuit (402) with track_clk. The synchronization circuit (610) may be, for example, a clock-triggered flip-flop or include such a. The synchronization circuit (610) outputs the synchronized tia_in to the tracking circuit (612). The tracking circuit (612) is configured responsively to track tia_in and output various codes for controlling the controllable current source (416) (e.g., for DC setting tracking). The tracking circuit (612) is configured to receive track_clk from the clock frequency splitter circuit (602), sampling_clk from the clock generation circuit (604), the synchronized tia_in from the synchronization circuit (610), MIN1 and MAX1 from the max / min calculation circuit (608), and a programmable DC tracking confidence vote value (prog_tia_dc_vote). The tracking circuit (612) is also configured to generate and output tia_dac_code, tia_ictrl, and a tracking DC setting step completion signal (tia_dc_track_done). Prog_tia_dc_vote indicates the number of sampling cycles within a predefined number of cycles in sampling_clk when the number of logic "1"s captured from tia_in (based on track_clk) is between MIN1 and MAX1 to determine whether the DC setup tracing step is complete. Tia_dc_track_done indicates whether the DC setup tracing phase is complete. In this example, tia_dc_track_done is logical "0" while the DC setup tracing phase is in progress and logical "1" when the DC setup tracing phase is complete. If the number of logic "1"s captured based on track_clk for each cycle of sampling_clk for a number of cycles of prog_tia_dc_vote before a predetermined number of cycles of sampling_clk occur is greater than MIN1 and less than MAX1, then tia_dc_track_done is set to logic "1" to indicate that the DC setting tracking step is completed; otherwise, after a predetermined number of cycles of sampling_clk occur, tia_dac_code and / or tia_ictrl are adjusted to adjust the current IDC of the controllable current source (416), and another repetition of a predetermined number of cycles is performed to continue the DC setting tracking step. Further details of this DC setting tracking step are described later. The tracking circuit (612) outputs tia_dc_track_done, which is set to logic "0" during the DC setting tracking phase as shown above, and is set to logic "1" when the DC setting tracking phase is completed. Tia_dc_track_done is inverted and input to the "1" selection input node of the multiplexer (614). Logic "1" is input to the "0" selection input node of the multiplexer (614). The selection control input node of the multiplexer (614) receives a transimpedance stage DC tracking enable signal (tia_dc_track_en), which may be a user-configurable enable signal. The output node of the multiplexer (614) is communicably coupled to the selection control input node of the multiplexer (606). When DC setting tracking is disabled (therefore tia_dc_track_en is set to logic "0"), the multiplexer (614) outputs logic "1" to the selection control input node of the multiplexer (606), which causes the multiplexer (606) to output slicer_clk_peaklock as slicer_clk to the slicer circuit (402). When DC setting tracking is enabled (therefore tia_dc_track_en is set to logic "1"), the multiplexer (614) outputs the inverted tia_dc_track_done to the selection control input node of the multiplexer (606), which causes the multiplexer (606) to output slicer_clk_peaklock as slicer_clk to the slicer circuit (402) when the DC setting tracking step is completed (e.g., when tia_dc_track_done is logic "1"), and to output track_clk as slicer_clk to the slicer circuit (402) during the DC setting tracking step (e.g., when tia_dc_track_done is logic "0"). Before continuing with the tracking circuit (612) and the PWM circuit (616), the signals output from the PWM circuit (616) to the DAC (212) are described. The output DAC thermal code (Dout_thermal_code[63:0]) is a multi-bit value (e.g., a 64-bit thermal code in the illustrated example) output from the PWM circuit (616) to the DAC (212). In this example, the DAC (212) converts the thermal code of Dout_thermal_code[63:0] into Vout_thermal_dac, which is output to the heater (228). Fig. 9 illustrates aspects of these signals. In any case, Dout_thermal_code[63:0] may have selected k-bit positions (Dout_thermal_code[k]) with the frequency of pwm_mode_clk, and Dout_thermal_code[k] (and in some scenarios, Dout_thermal_code[k+1] or Dout_thermal_code[k-1]) may be dithered by a selected duty cycle. One cycle of Pwm_mode_clk is, for example, between time t0 and time t1. Additionally, three cycles of pwm_mode_clk are between time t0 and time t2 for exemplary purposes. Dout_thermal_code[k] has a duty cycle DC0 between time t0 and time t2. For illustrative purposes, the duty cycle DC0 is 50%. Between time t0 and time t2, bit position(s) from bit position (k-1) (Dout_thermal_code[k-1]) to bit position 0 (Dout_thermal_code[0]) are logical "1". Bit position(s) from bit position (k+1) (Dout_thermal_code[k+1]) to bit position 63 (Dout_thermal_code

[63] ) are logical "0". The bit positions of Dout_thermal_code[63:0] having these values ​​between time t0 and time t2 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] with a duty cycle corresponding to duty cycle DC0, which makes the temperature in the heater (228) become temperature Temp0, as described above in relation to FIG. 7. At time t2, the duty cycle of Dout_thermal_code[k] is increased to duty cycle DC1. Dout_thermal_code[k] has a duty cycle DC1 between time t2 and time t4. For illustrative purposes, the duty cycle DC0 is 70%. Between time t2 and time t4, Dout_thermal_code[(k-1):0] is logic "1" and Dout_thermal_code[63:(k+1)] is logic "0". Bit positions of Dout_thermal_code[63:0] with these values ​​between time t2 and time t4 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] with a duty cycle corresponding to duty cycle DC1. Vout_thermal_dac between time t2 and time t4 causes the temperature in the heater (228) to increase to temperature Temp0+deltaTemp, as described above in relation to FIG. 7. As illustrated, the temperature in the heater (228) increases from temperature Temp0 to temperature Temp0+deltaTemp at time t3 following the increase in the duty cycle at time t2. In some examples, the delay between the time when the duty cycle of Dout_thermal_code[k] increases (e.g., at time t2) and the time when the temperature in the heater (228) reaches temperature Temp0+deltaTemp (e.g., at time t3) is about 6 μs. Additionally, in some examples, the cycle of pwm_mode_clk may be on the order of tens of nanoseconds, and thus, multiple cycles of Dout_thermal_code[k] may occur between the time the duty cycle increases and the time the temperature in the heater (228) reaches the temperature Temp0+deltaTemp. At time t4, the duty cycle of Dout_thermal_code[k] is reduced to duty cycle DC0. Dout_thermal_code[k] has duty cycle DC0 following time t4 in FIG. 9. At time t4 and subsequently, Dout_thermal_code[(k-1):0] is logic "1" and Dout_thermal_code[63:(k+1)] is logic "0". Bit positions of Dout_thermal_code[63:0] having these values ​​following time t4 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] with a duty cycle corresponding to duty cycle DC0. Following time t4, Vout_thermal_dac causes the temperature in the heater (228) to be reduced to temperature Temp0. As described, the temperature in the heater (228) decreases from the temperature Temp0+deltaTemp to the temperature Temp0 at time t5 following the decrease in the duty cycle at time t4. The temperature in the heater (228) can be controlled by selecting which k-bit position of Dout_thermal_code[63:0] will oscillate and by selecting duty cycles for diadding Dout_thermal_code[k]. Selecting a value for K determines the voltage levels at which Vout_thermal_dac oscillates. In the illustrated example, since Dout_thermal_code[63:0] is a 64-bit code, Vout_thermal_dac can be one of 65 possible voltages (v[0], v[1], ... v

[64] ). The available voltages are v[0] <v[1]<v[2]< . . . <v

[64] 가 되도록 순차적으로 증가한다. 이로 인해, k의 더 큰 값을 선택하는 것은 전압들(v[k], v[k+1])이 더 큰 레벨들로 되게 할 수 있고, 반대로, k의 더 작은 값을 선택하는 것은 전압들(v[k], v[k+1])이 더 낮은 레벨들로 되게 할 수 있다. 이들 전압 레벨들을 선택하는 것은 히터(228)에서 달성될 수 있는 가능한 온도 범위(예를 들어, 온도 Temp[k]로부터 온도 Temp[k+1]까지)를 결정할 수 있다. Selecting a duty cycle for adding Dout_thermal_code[k] can achieve a temperature in the range from temperature Temp[k] to temperature Temp[k+1] in the heater (228). The duty cycle can achieve interpolation of the temperature in the heater (228) within the range from temperature Temp[k] to temperature Temp[k+1] due to the accumulation (e.g., integration) of thermal energy converted by the heater (228). Lower duty cycles can cause the temperature in the heater (228) to approach temperature Temp[k], whereas higher duty cycles can cause the temperature in the heater (228) to approach temperature Temp[k+1]. The illustration in FIG. 9 shows Dout_thermal_code[63:0] where k is not 0 and not 63 (e.g., some bit positions are each logical "1" and other bit positions are each logical "0"), but k can be 0 and 63. Also, the duty cycle of Dout_thermal_code[k] can be 0% and 100%. In some examples, when k is 0 and the duty cycle is 0%, Dout_thermal_code[63:0] is at the saturation minimum, and in some examples, when k is 63 and the duty cycle is 100%, Dout_thermal_code[63:0] is at the saturation maximum. In addition, as illustrated by some exemplary scenarios below, dithering between different duty cycles can cause multiple bit positions of Dout_thermal_code[63:0] to oscillate in the duty cycle. For example, if the dithering step increase is 20% duty cycle and the duty cycle of k bit positions is 90%, the duty cycle can be dithered between Dout_thermal_code[k] oscillating in the 90% duty cycle (where Dout_thermal_code[(k-1):0] is logical "1" and Dout_thermal_code[63:(k+1)] is logical "0") and Dout_thermal_code[k+1] oscillating in the 10% duty cycle (where Dout_thermal_code[k:0] is logical "1" and Dout_thermal_code[63:(k+2)] is logical "0"). Referring again to FIG. 6, the tracking circuit (612) is configured to track tia_in and output a duty code (duty_code) and a k-level select signal (k_sel) to the PWM circuit (616) to control the heater (228) (e.g., for tracking a temperature setting). The tracking circuit (612) is configured to receive a programmable PWM resolution value (prog_pwm_res) and a programmable PWM step value (prog_pwm_step). Prog_pwm_res is a value representing the frequency at which one or more bit positions of Dout_thermal_code[63:0] oscillate (e.g., the frequency of pwm_mode_clk described above). Prog_pwm_step is a value representing the step for increasing the duty_code. Together, prog_pwm_res and prog_pwm_step can be used to explicitly or implicitly determine the available values ​​for the duty_code. As will be described later, k_sel indicates which k-bit position of Dout_thermal_code[63:0] will oscillate with the duty cycle represented by duty_code when sampling_clk is logical low. In some examples, prog_pwm_res is a value representing the number of dsp_clk cycles per cycle of pwm_mode_clk, and prog_pwm_step is a value representing the number of dsp_lk cycles per increment or decrement of duty_code. In the example, dsp_clk has a frequency of 875 MHz; prog_pwm_res represents 16 or 64 cycles of dsp_clk per cycle of pwm_mode_clk; and prog_pwm_step represents 1, 2, 4, or 8 cycles of dsp_clk per increment or decrement of duty_code. Table 3 details this example with the available resulting values ​​for duty_code. [Table 3] The tracking circuit (612) is configured to capture a predetermined number of samples of tia_in at each falling edge of sampling_clk and, based on the captured samples, to increase or decrease k_sel and / or duty_code during temperature setting tracking. In the first iteration for temperature setting tracking, k_sel and duty_code may be initialized to some values. During temperature setting tracking, the tracking circuit (612) captures a predetermined n samples of tia_in. The tracking circuit (612) determines whether the number of logic "1"s is greater than or equal to half of the predetermined n. If so, the tracking circuit (612) increases duty_code to the next available value, provided that duty_code is not at the highest available value. When duty_code is at the highest available value, the tracking circuit (612) increments k_sel by 1 (unless k_sel is at the highest available value) and resets duty_code to the lowest available value. If K_sel and duty_code are at their respective highest available values, the output signals from the PWM circuit (616) are saturated, and the values ​​of k_sel and duty_code are maintained. In this scenario, an error flag may be set. The following pseudocode shows how k_sel and duty_code can be incremented based on the example in Table 3 above. This pseudocode determines the next available duty_code mathematically and implicitly, and increments k_sel and resets duty_code under appropriate conditions by associating k_sel with duty_code. Temp_incr = (k_sel x 26) + duty_code + 2[(2 x prog_pwm_res) + prog_pwm_step] / / Associate k_sel and duty_code; add incremental step size if(temp_incr < 4096) { k_sel = temp_incr[11:6]; duty_code = temp_incr[5:0]} / / When k_sel and duty_code are not saturated and can be incremented, extract the incremented k_sel and duty_code from temp_incr If the number of captured logic "1"s is less than or equal to half of a predetermined n, the tracking circuit (612) decreases the duty_code to the next available value if the duty_code is not at the lowest available value. When the duty_code is at the lowest available value, the tracking circuit (612) decreases k_sel by 1 (unless k_sel is at the lowest available value) and resets the duty_code to the highest available value. If k_sel and duty_code are at the lowest available values, the output signals from the PWM circuit (616) are saturated, and the values ​​of k_sel and duty_code are maintained. In this scenario, an error flag may be set. The following pseudocode shows how k_sel and duty_code can be decremented based on the example in Table 3 above. This pseudocode determines the next available duty_code mathematically and implicitly, and decrementes k_sel and resets duty_code under appropriate conditions by associating k_sel with duty_code. Temp_incr = (k_sel x 26) + duty_code - 2[(2 x prog_pwm_res) + prog_pwm_step] / / Combine k_sel and duty_code; subtract the incremental step size if(temp_incr > -1) { k_sel = temp_incr[11:6]; duty_code = temp_incr[5:0]} / / When k_sel and duty_code are not saturated and can be decreased, extract incremented k_sel and duty_code from temp_incr If either k_sel and / or duty_code is modified (e.g., increased, decreased, or reset) by the tracking circuit (612), the tracking circuit (612) resets tia_dc_track_done to logic "0" and resets tia_dac_code and tia_ictrl to 0. After maintaining the values ​​of k_sel and duty_code or resetting tia_dc_track_done, tia_dac_code, and tia_ictrl, the temperature setting tracking is completed and the tracking circuit (612) loops back to the DC setting tracking. The tracking circuit (612) may implement any logic, state machine (e.g., finite state machine), and / or other circuit capable of executing machine-executable instructions to implement DC setting tracking and temperature setting tracking. With reference to FIG. 6, FIG. 10 is a schematic diagram of a PWM circuit (616) according to some examples. The PWM circuit (616) is configured to receive dsp_clk, track_clk, prog_pwm_res, programmable duty cycle dither step value (prog_pwm_dither_step), sampling_clk, k_sel, and duty_code, and is configured to generate and output Dout_thermal_code[63:0]. The PWM circuit (616) is configured to generate a dither k-level selection value (k_sel_dither) and a dither duty code value (duty_code_dither) based on k_sel, duty_code, and prog_pwm_dither_step, and is configured to generate and output Dout_thermal_code[63:0] based on k_sel and duty_code when sampling_clk is logic low and based on k_sel_dither and duty_code_dither when sampling_clk is logic high. The PWM circuit (616) generally includes an arithmetic / logic unit (ALU) (1002) configured to generate k_sel_dither and duty_code_dither by adding the duty cycle step size represented by prog_pwm_dither_step to k_sel and duty_code. The ALU (1002) of the PWM circuit (616) associates k_sel and duty_code (where duty_code is the least significant bit position and k_sel is the next most significant bit position) and adds the duty cycle step size represented by prog_pwm_dither_step to the associated k_sel and duty_code. After addition, if the next most significant bit position after the number of bit positions of the associated k_sel and duty_code is "1", the remaining less significant bit positions of the result can be cleared. After addition, if the next most significant bit position after the number of bit positions of the associated k_sel and duty_code is "0", then the bit position of the result corresponding to k_sel (from the association) in the batch and the remaining lesser bit positions are k_sel_dither, and the least significant bit positions corresponding to duty_code (from the association) in the batch are duty_code_dither. Additionally, the ALU (1002) may include logic to perform a check operation for the prog_pwm_dither_step based on prog_pwm_res. As will be understood later, the available duty cycles, and the resulting available duty_code_dither, may be limited based on the mode indicated by prog_pwm_res. In the example in Table 3, when prog_pwm_res is "0", no check for prog_pwm_dither_step is performed, but when prog_pwm_dither_step is not a multiple of 4 and prog_pwm_res is "1", a check to cut prog_pwm_dither_step to the next multiple of 4 is performed.The following pseudocode illustrates an example of this operation of the ALU (1002) by various values ​​having predetermined bit lengths. If(prog_pwm_res == 1) { prog_pwm_dither_step = integer(prog_pwm_dither_step / 4) x 4} / / In the mode indicated by prog_pwm_res = 1, if prog_pwm_dither_step is not a multiple of 4, truncate prog_pwm_dither_step to the nearest multiple of 4 temp_concat = (k_sel x 26) + duty_code / / temp_concat is 13 bits ([12:0]) and k_sel and duty_code are each 6 bits ([5:0]); concatenate k_sel and duty_code to "0" in temp_concat

[12] temp_accum_dither = temp_concat + prog_pwm_dither_step if(temp_accum_dither

[12] == 1) { temp_accum_dither = 4096} / / If temp_accum_dither >= 4096, set temp_accum_dither = 4096 (temp_accum_dither

[12] = 1 and temp_accum_dither[11:0] = 0) k_sel_dither = temp_accum_dither[12:6] / / Extract k_sel_dither from temp_accum_dither duty_code_dither = temp_accum_dither[5:0] / / Extract duty_code_dither from temp_accum_dither Table 4 below illustrates some exemplary values ​​generated by the pseudocode above. [Table 4] The PWM circuit (616) includes a state machine and / or counter (1004) configured to generate and output intermediate signals (PWM_int[m]) having different duty cycles (wherein PWM_int[m] is based on dsp_clk and prog_pwm_res). For example, for a given m, PWM_int[m] may be generated by asserting a logic "1" as PWM_int[m] for the number of cycles of dsp_clk based on m position and prog_pwm_res, and then asserting a logic "0" as PWM_int[m] for the remaining number of cycles of dsp_clk based on prog_pwm_res. FIGS. 11a and FIGS. 11b are timing diagrams of various PWM_int[m] based on different prog_pwm_res according to some examples. FIG. 11a illustrates the signals when prog_pwm_res = 0 as presented in Table 3 (e.g., a frequency of 13.67 MHz for pwm_mode_clk or 64 cycles of dsp_clk per cycle of pwm_mode_clk). In FIG. 10, pwm_mode_clk is not explicitly generated but is illustrated as a reference in FIG. 11a. FIG. 11a illustrates a period (1102) of 64 cycles of dsp_clk, which corresponds to one cycle of each PWM_int[m] and pwm_mode_clk in this mode. In this mode, the state machine and / or counter (1004) sets PWM_int[m] to a logic "1" at the beginning of each cycle of each PWM_int[m]. The state machine and / or counter (1004) maintains PWM_int[m] as logical "1" for m cycles of dsp_clk (e.g., by counting the number of rising edges of dsp_clk). In the (m+1) cycles of dsp_clk, the state machine and / or counter (1004) sets PWM_int[m] to logical "0" and maintains PWM_int[m] at that value for the remaining number of cycles of dsp_clk in the cycle of PWM_int[m]. For example, PWM_int[0] is not logical "1" for any cycle of dsp_clk, but is logical "0" for each cycle of dsp_clk. PWM_int[1] is logical "1" for one initial cycle of dsp_clk in the cycle of PWM_int[1] and logical "0" for 63 subsequent cycles of dsp_clk in the cycle of PWM_int[1]. PWM_int[2] is logical "1" for two initial cycles of dsp_clk in the cycle of PWM_int[2] and logical "0" for 62 subsequent cycles of dsp_clk in the cycle of PWM_int[2].PWM_int

[63] is logical "1" for the first 63 cycles of dsp_clk in the cycle of PWM_int

[63] , and logical "0" for the last cycle of dsp_clk in the cycle of PWM_int

[63] . FIG. 11b illustrates the signals when prog_pwm_res = 1 as presented in Table 3 (e.g., a frequency of pwm_mode_clk of 54.69 MHz or 16 cycles of dsp_clk per cycle of pwm_mode_clk). As in FIG. 11a, pwm_mode_clk is illustrated as a reference in FIG. 11b. FIG. 11b also illustrates a period (1104) of 16 cycles of dsp_clk, which corresponds to one cycle of each PWM_int[m] and pwm_mode_clk in this mode. In this mode, the state machine and / or counter (1004) sets PWM_int[m] to a logic "1" at the beginning of each cycle of each PWM_int[m]. The state machine and / or counter (1004) maintains PWM_int[m] as logical "1" for (m / 4) cycles of dsp_clk (e.g., by counting the number of rising edges of dsp_clk). In ((m / 4) + 1) cycles of dsp_clk, the state machine and / or counter (1004) sets PWM_int[m] to logical "0" and maintains PWM_int[m] at that value for the remaining number of cycles of dsp_clk in the cycle of PWM_int[m]. For example, PWM_int[0] is not logical "1" for any cycle of dsp_clk, but logical "0" for each cycle of dsp_clk. PWM_int[4] is logical "1" for one initial cycle of dsp_clk in the cycle of PWM_int[4] and logical "0" for 15 subsequent cycles of dsp_clk in the cycle of PWM_int[4]. PWM_int[8] is logical "1" for two initial cycles of dsp_clk in the cycle of PWM_int[8] and logical "0" for 14 subsequent cycles of dsp_clk in the cycle of PWM_int[8].PWM_int

[60] is logical "1" for the first 15 cycles of dsp_clk in the cycle of PWM_int

[60] and logical "0" for the last cycle of dsp_clk in the cycle of PWM_int

[60] . In this mode, the state machine and / or counter (1004) can disable any PWM_int[m] where m is not a multiple of 4. As is evident from FIGS. 11a and 11b, the duty cycle of PWM_int[m] increases with increasing value of m. Additionally, the duty cycles may be distributed differently between the different modes illustrated in FIGS. 11a and 11b. For example, taking PWM_int[4] as an example, in FIG. 11a, PWM_int[4] is logical "1" for the first four cycles of dsp_clk in period (1102) and logical "0" for the remaining 60 cycles of dsp_clk in period (1102), whereas in FIG. 11b, PWM_int[4] is logical "1" for four instances of one cycle of dsp_clk distributed over the entire period (1102) and logical "0" for the remaining 6 cycles of dsp_clk in period (1102). Referring again to FIG. 10, the PWM circuit (616) further includes multiplexers (1010, 1020, 1030, 1032) and flip-flops (1012, 1014, 1022, 1024, 1034). The multiplexer (1010) has a “0” select input node configured to receive a duty_code and communicateably coupled to an ALU (1002), and a “1” select input node configured to receive a duty_code_dither and communicateably coupled to an ALU (1012). The multiplexer (1010) has a select control input node configured to receive a sampling_clk. The multiplexer (1010) has an output node communicateably coupled to an input node of the flip-flop (1012). The flip-flop (1012) has an output node that is communically coupled to the input node of the flip-flop (1014). The flip-flop (1014) has an output node that is communically coupled to the select control input node of the multiplexer (1030). The flip-flop (1012) has a clock input node configured to receive track_clk, and the flip-flop (1014) has clock input nodes configured to receive dsp_clk. As is apparent, each input node and output node of the multiplexer (1010) and the flip-flops (1012, 1014) may be a multi-bit node. Thus, although the flip-flop (1012) or the flip-flop (1014) is schematically illustrated in singular, multiple single-bit flip-flops may be implemented for the illustrated flip-flop, each corresponding to each bit position. The multiplexer (1020) has a “0” selection input node configured to receive k_sel and communicateably coupled to the ALU (1002), and a “1” selection input node configured to receive k_sel_dither and communicateably coupled to the ALU (1002). The multiplexer (1020) has a selection control input node configured to receive sampling_clk. The multiplexer (1020) has an output node communicateably coupled to the input node of the flip-flop (1022). The flip-flop (1022) has an output node communicateably coupled to the input node of the flip-flop (1024). The flip-flop (1024) has an output node communicateably coupled to the selection control input node of the multiplexer (1032). The flip-flop (1022) has a clock input node configured to receive track_clk, and the flip-flop (1024) has clock input nodes configured to receive dsp_clk. As is apparent, each input node and output node of the multiplexer (1020) and the flip-flops (1022, 1024) may be a multi-bit node. Because of this, although the flip-flop (1022) or the flip-flop (1024) is schematically illustrated in singular, multiple single-bit flip-flops may be implemented for the illustrated flip-flop, each corresponding to each bit position. In the illustrated example, the multiplexer (1030) has 64 "m" selection input nodes (where m is from 0 to 63), is communicably coupled to the ALU (1002), and is configured to receive each PWM_int[m]. The multiplexer (1030) has an output node configured to output a PWM duty code signal (pwm_duty_code). In the illustrated example, the multiplexer (1032) has 65 "q" select input nodes (where q is 0 to 64). Each of the 65 "q" select input nodes is a 64-bit input node and is configured to receive each column code (therm[q]). For each therm[q], the pwm_duty_code output from the multiplexer (1030) is mapped to the q-bit position of each therm[q]; each bit position of each therm[q] smaller than q is set to logic "1"; and each bit position of each therm[q] larger than q is set to logic "0". Generally, for each therm[q], a 64-bit column code is generated, where the q-bit position is oscillated as pwm_duty_code. Each bit position of therm

[64] is set to a logic "1" (e.g., each bit position of therm

[64] is less than q = 64). therm

[64] may be in a saturation condition. The multiplexer (1032) has an output node that is communically coupled to the input node of the flip-flop (1034). The flip-flop (1034) has an output node that is the output node of the PWM circuit (616) to which Dout_thermal_code[63:0] is provided. The flip-flop (1034) has a clock input node configured to receive dsp_clk. As is apparent, each input node and output node of the multiplexer (1032) and the flip-flop (1034) are 64-bit nodes in the illustrated example. As a result, although the flip-flop (1034) is schematically illustrated in a singular manner, 64 single-bit flip-flops can be implemented for the illustrated flip-flop (1034), each corresponding to each bit position. In describing the additional operation of FIG. 10, the operation of the flip-flops (1012, 1014, 1022, 1024, 1034) is omitted. These flip-flops generally synchronize signals to each clock, such as track_clk or dsp_clk. Since this operation is obvious to those skilled in the art, it is omitted for brevity. When operating, the ALU (1002) generates and outputs k_sel_dither and duty_code_dither as described above, and the state machine and / or counter (1004) generates and outputs PWM_int[m] (where m is 0 to 63) as described above. When sampling_clk is logical low (e.g., corresponding to a "0" selection for multiplexers (1010, 1020)), the multiplexer (1010) outputs duty_code to the selection control input node of the multiplexer (1030), which causes the multiplexer (1030) to output PWM_int[duty_code] as pwm_duty_code. As a result, the multiplexer (1030) outputs a signal having a desired duty cycle. Additionally, when sampling_clk is logical low, the multiplexer (1020) outputs k_sel to the selection control input node of the multiplexer (1032), which causes the multiplexer (1032) to output therm[k_sel] as Dout_thermal_code[63:0]. As a result, the multiplexer (1032) outputs a thermal code having a signal with a desired duty cycle at a desired bit position. When sampling_clk is logically high (corresponding, for example, to a "1" selection for multiplexers (1010, 1020), the multiplexer (1010) outputs duty_code_dither to the selection control input node of the multiplexer (1030), which causes the multiplexer (1030) to output PWM_int[duty_code_dither] as pwm_duty_code. As a result, the multiplexer (1030) outputs a signal having the desired duty cycle. Also, when sampling_clk is logically high, the multiplexer (1020) outputs k_sel_dither to the selection control input node of the multiplexer (1032), which causes the multiplexer (1032) to output therm[k_sel_dither] as Dout_thermal_code[63:0]. As a result, the multiplexer (1032) outputs a column code having a signal with a desired duty cycle at a desired bit position, which may differ from the column code output when sampling_clk is logically low. Generally, when sampling_clk is a logical row: Dout_thermal_code[63:0] = therm[k_sel] = {(63-k_sel)'d0, pwm_duty_code = PWM_int[duty_code], (k_sel)'b1} When sampling_clk is logically high: Dout_thermal_code[63:0] = therm[k_sel_dither] = {(63-k_sel_dither)'d0, pwm_duty_code = PWM_int[duty_code_dither], (k_sel_dither)'b1} FIGS. 12a and 12b are flowcharts of the operation (1200A, 1200B) of the tracking circuit (612) of the DSP (406) according to some examples. For context, the entire operation of the DSP (406) will be described by the flowcharts of FIGS. 12a and 12b. Generally, FIG. 12a illustrates DC setting tracking, and FIG. 12b illustrates temperature setting tracking. Initially, the user programs values ​​for various programmable values. The user can write values ​​for the programmable values ​​to memory, registers, etc., that the DSP (406) can access. The user writes values ​​for prog_pwm_res, prog_pwm_step, prog_pwm_dither_step, prog_sampling_freq, prog_sampling_offset, prog_tia_dc_ratio, prog_tia_dc_vote, and tia_dc_track_en. Additionally, the clock frequency splitting circuit (602) generates track_clk from dsp_clk as described above. The clock generation circuit (604) generates sampling_clk_peaklock based on prog_sampling_freq, prog_sampling_offset, and track_clk as described above. The maximum / minimum calculation circuit (608) calculates MAX1 and MIN1 based on prog_tia_dc_ratio, prog_sampling_freq, and prog_sampling_offset as described above. Referring to the operation (1200A) of FIG. 12a, in block (1202), tia_dac_code, tia_ictrl, k_sel, tia_dc_track_done, the majority vote counter (count_majority_vote), and the round track counter (round_dc_track) are set to 0, and duty_code is set to the middle value of the range of available values ​​for duty_code. By setting tia_dac_code and tia_ictrl to 0, the current generated by the controllable current source (416) is reduced to a minimum amount and / or turned off, which reduces the removal of the DC component from the current Iin to a minimum amount and / or does not remove the DC component from the current Iin. If duty_code is set to an intermediate value (e.g., 32 in the example of FIG. 10), the multiplexer (1030) of the PWM circuit (616) outputs PWM_int[duty_code] when sampling_clk is low, so that the output PWM_int[duty_code] has a duty cycle of 50 percent or near thereto. If k_sel is set to 0, the multiplexer (1032) of the PWM circuit (616) outputs therm[k_sel = 0] = {63'd0,pwm_duty_code = PWM_int[duty_code]} as Dout_thermal_code[63:0] when sampling_clk is low. Additionally, the ALU (1002) generates k_sel_dither and duty_code_dither based on k_sel, duty_code, and prog_pwm_dither_step set in block (1202).The multiplexer (1032) of the PWM circuit (616) outputs the therm[k_sel_dither] = {(63-k_sel_dither)'d0, pwm_duty_code = PWM_int[duty_code_dither], (k_sel_dither)'b1} as Dout_thermal_code[63:0] when sampling_clk is high. Accordingly, Dout_thermal_code[63:0] is set to dither between different duty codes based on sampling_clk, which causes the temperature in the heater (228) and Vout_thermal_dac to dither in response. In block (1204), a determination is made as to whether tia_dc_track_done is equal to 0. If tia_dc_track_done is not equal to 0, the operation proceeds to the temperature setting tracking of FIG. 12b, which is described later. If tia_dc_track_done is equal to 0, in block (1206), samples of tia_in are captured at each rising edge of track_clk during one cycle of sampling_clk, and a number of logical "1"s is counted. As indicated above, during one cycle of sampling_clk, the duty cycle of Dout_thermal_code[63:0] is dithered, which causes the temperature in the heater (228) to be dithered. Capturing samples of tia_in through one cycle of sampling_clk may allow samples to be captured that are responses to different optical responses of the optical element (222) due to different temperatures of the heater (228). In block (1208), a determination is made as to whether the number of captured logical "1"s is greater than or equal to MIN1 and less than or equal to MAX1. Generally, the determination in block (1208) indicates whether the number of captured logical "1"s is within the error range indicated by prog_tia_dc_ratio. If the number of captured logical "1"s is within MIN1 and MAX1, in block (1210), count_majority_vote is incremented by 1. After block (1210), or if the number of captured logical "1"s is not within MIN1 and MAX1, in block (1212), a determination is made as to whether count_majority_vote is equal to prog_tia_dc_vote. If count_majority_vote is equal to prog_tia_dc_vote, in block (1214), tia_dc_track_done is set to 1, and count_majority_vote and round_dc_track are set to 0. After block (1214), the operation loops back to block (1204). If count_majority_vote is not equal to prog_tia_dc_vote, in block (1216), a determination is made as to whether round_dc_track is equal to a predetermined number x. The predetermined number x can be a programmable value or coded as an algorithm. If round_dc_track is not equal to the predetermined number x, in block (1218), round_dc_track is incremented by 1. After block (1218), the operation loops back to block (1204). If round_dc_track is equal to a predetermined number x, then in block (1220), tia_dac_code and / or tia_ictrl are incremented. Increasing tia_dac_code and / or tia_ictrl increases the current IDC through the controllable current source (416). An increment in either tia_dac_code or tia_ictrl may be accompanied by a decrease in the other in some situations. The way tia_dac_code and tia_ictrl are modified may be based on considerations such as the target step increase for each iteration of block (1220) and the structure of the controllable current source (416). For example, tia_dac_code may be set to a decreased value, and may be independently increased in multiple subsequent iterations of block (1220) without increasing tia_ictrl until tia_dac_code saturates in another iteration of block (1220) where tia_ictrl is increased. Even with a decreased tia_dac_code (and a corresponding decreased v_tia_dac), increasing tia_ictrl may cause another series-connected pair of n-type transistors (802, 804) to be operably electrically coupled between node (810) and a power node (e.g., a ground node) so as to increase the accumulated current (and resulting current IDC) flowing through the channels of the n-type transistors (804). After block (1220), in block (1222), count_majority_vote and round_dc_track are set to 0, and the operation loops back to block (1204). Generally, looping of the operation by blocks (1204-1222) forms a DC setup trace. Before round_dc_track becomes equal to x, the number of times samples are captured in block (1206) is counted, and tia_dac_code and / or tia_ictrl are incremented. count_majority_vote counts the number of times samples captured in block (1206) are within the error range represented by MAX1 and MIN1 while round_dc_track is less than x. When count_majority_vote becomes equal to prog_tia_dc_vote, tia_dac_code and tia_ictrl are at values ​​sufficient for the captured samples to be within the error range represented by MAX1 and MIN1 with a certain confidence level. If count_majority_vote is equal to prog_tia_dc_vote, the DC setup tracing is terminated and tia_dc_track_done is set to 1. Generally, after x iterations (e.g., capturing samples for x cycles of sampling_clk), if the number of iterations in which the captured samples were within the error range indicated by MIN1 and MAX1 is less than prog_tia_dc_vote, the current IDC is increased by incrementing tia_dac_code and / or tia_ictrl, and subsequent iterations for DC setting tracking are continued by resetting count_majority_vote and round_dc_track. Before x iterations are completed, if the number of iterations in which the captured samples were within the error range indicated by MIN1 and MAX1 is equal to prog_tia_dc_vote, the DC setting tracking is terminated by setting tia_dc_track_done to 1 (causing block (1204) to proceed to temperature setting tracking), and the current IDC is set for temperature setting tracking. count_majority_vote and round_dc_track are reset for the subsequent iteration of the DC setting trace following the temperature setting trace. Referring again to the operation (1200A) of FIG. 12a, if the decision in block (1204) is that tia_dc_track_done is not equal to 0 (e.g., that DC setup tracking is terminated), then in step (1252), samples of tia_in are captured at each time of the cycles of sampling_clk for y cycles of sampling_clk, and the number of captured logic "1"s and logic "0"s are counted. In some examples, each sample is captured at a time in each cycle while sampling_clk is logic low and before and near the rising edge of sampling_clk. For example, each sample may be captured for 10 cycles of dsp_clk before each rising edge of sampling_clk. A dedicated signal having a rising or falling edge corresponding to this sample time may be implemented. In block (1254), a determination is made as to whether the total count of logical "1" and logical "0" is equal to the number y. If not, an error has occurred, and the temperature setting trace is terminated so that the operation loops loop back to block (1204) for DC setting trace. If the total count of logical "1" and logical "0" is equal to the number y, in block (1256), a determination is made as to whether the count of logical "1" is greater than half the number y. Generally, block (1256) determines whether more logical "1" or more logical "0" have been counted. If the counted number of logical "1"s is greater than or equal to half the number of y, in block (1258), a determination is made as to whether k_sel and duty_code are at each maximum value. If both k_sel and duty_code are at each maximum value (e.g., Dout_thermal_code[63:0] indicates that it is at the maximum duty code), in block (1260), k_sel and duty_code are maintained at their respective values, and an error flag may be set. After block (1260), the temperature setting trace is terminated so that the operation loops loop back to block (1204) for DC setting trace. If either or both of k_sel and duty_code are not at each maximum value, in block (1262), k_sel and / or duty_code are incremented as described above. After block (1262), in block (1264), tia_dc_track_done, tia_dac_code, and tia_ictrl are set to 0, which terminates the temperature setting track and resets the variables for the subsequent DC setting track. After block (1264), the operation loops back to block (1204) for the DC setting track. If the counted number of logical "1"s is less than or equal to half the number of y, in block (1266), a determination is made as to whether k_sel and duty_code are at each minimum value. If both k_sel and duty_code are at each minimum value (e.g., indicating that Dout_thermal_code[63:0] is at the minimum duty code), in block (1260), k_sel and duty_code are maintained at their respective values, and an error flag may be set. After block (1260), the temperature setting trace is terminated so that the operation loops loopback to block (1204) for DC setting trace. If either or both of k_sel and duty_code are not at each minimum value, in block (1268), k_sel and / or duty_code are reduced as described above. After block (1268), in block (1270), tia_dc_track_done, tia_dac_code, and tia_ictrl are set to 0, which terminates the temperature setting track and resets the variables for the subsequent DC setting track. After block (1270), the operation loops back to block (1204) for the DC setting track. Changing k_sel and duty_code causes the PWM circuit (616) to responsively change k_sel_dither and duty_code_dither. Changing k_sel, duty_code, k_sel_dither, and duty_code_dither causes Dout_thermal_code[63:0] to dither between different duty codes, which in turn causes Vout_thermal_dac to dither between different duty cycles and possibly between different voltage levels. Changing Vout_thermal_dac causes the temperature in the heater (228) to increase or decrease. DC settings are determined based on samples captured in block (1206) across the dither, based on sampling_clk between a first temperature and a second temperature (arising from the dither duty cycles of Dout_thermal_code[63:0]). In the example described, when sampling_clk is logic high, the first temperature occurs in the optical element (222), and when sampling_clk is logic low, a second temperature higher than the first temperature occurs in the optical element (222). Generally, the optical response of the optical element (222) at the first and second temperatures may be as shown in FIG. 3a or FIG. 3b. In the RHS scenario of FIG. 3a, samples captured when the optical element (222) is at a second temperature and has a second response (306) with a magnitude (316) at a center wavelength (λc) (302) have lower loss compared to samples captured when the optical element (222) is at a first temperature and has a second response (304) with a magnitude (314) at a center wavelength (λc) (302). In the example described, samples are captured when sampling_clk is logical low and near the end of the cycle when sampling_clk is low, which causes the optical element (222) to reach or nearly reach the second temperature. When samples are captured multiple times when the optical element (222) is at the second temperature, the lower loss of the response (306) at a magnitude (316) compared to DC settings causes the captured samples to be more logical "1". As a result, the counted number of logic "1"s being more than half of the total number of samples generally indicates that the center wavelength (λc) (302) of the optical signal is on the RHS of the optical response, as in FIG. 3a. Temperature settings (e.g., k_sel and / or duty_code) are generally increased responsively to cause the peak of the optical response of the optical element (222) to shift toward the center wavelength (λc) (302) of the optical signal. In the LHS scenario of FIG. 3b, when the optical element (222) is at a second temperature and has a second response (326) with magnitude (336) at the center wavelength (λc) (302), the captured samples have greater loss compared to the samples captured when the optical element (222) is at a first temperature and has a second response (324) with magnitude (334) at the center wavelength (λc) (302). When samples are captured multiple times when the optical element (222) is at the second temperature, the greater loss of the response (326) at magnitude (336) compared to the DC settings causes the captured samples to have fewer logic "1s." Consequently, the counted number of logic "1s" being more than half of the total number of samples generally indicates that the center wavelength (λc) (302) of the optical signal is on the LHS of the optical response, as in FIG. 3b. Temperature settings (e.g., k_sel and / or duty_code) are generally reduced responsively so that the peak of the optical response of the optical element (222) moves toward the center wavelength (λc) (302) of the optical signal. A person skilled in the art can easily understand variations of such temperature setting tracking (e.g., variations of implemented logic). For example, in block (1252), if samples are captured when sampling_clk is high, k_sel and / or duty_code may be decreased when the counted number of logic "1" is greater than half of the number y, and k_sel and / or duty_code may be increased when the counted number of logic "1" is less than half of the number y. As indicated by FIGS. 12a and 12b, DC setting tracking and temperature setting tracking are performed iteratively as illustrated in FIG. 5. Before performing DC setting tracking for each iteration, tia_dac_code and tia_ictrl are set or reset so that tia_dac_code and tia_ictrl are determined independently of any previous values ​​of tia_dac_code and tia_ictrl. Additionally, iterations of temperature setting tracking may be augmented with respect to the values ​​of k_sel and duty_code generated by the previous iteration of temperature setting tracking. Through repeated iterations of DC setting tracking and temperature setting tracking, the device can be continuously recalibrated, for example, if the ambient temperature of the environment in which the device is placed changes. FIG. 13 is a simplified schematic diagram of a device according to some examples. The device (which may be in a package such as that in FIG. 1) includes an electric IC (1302) on an electric IC die (102) and an optoelectronic circuit (1304) on an optical die (104). The electric IC includes controllers (210-1, 210-2, 210-3), DACs (212-1, 212-2, 212-3), and a controller (1303). Each controller (210-1, 210-2, 210-3) and the corresponding DAC (212-1, 212-2, 212-3) is configured and generally operates as the controller (210) and DAC (212) described above. The controller (1303) is communicably coupled to the controllers (210-1, 210-2, 210-3) and is configured to control operations between the controllers (210-1, 210-2, 210-3). Although not illustrated, the electrical IC (1302) further includes a circuit for generating an electrical signal to be transmitted as an optical signal through an optical channel. The optoelectronic circuit (1304) includes an optical source (not specifically shown), a common channel path (1310), an odd channel path (1312), an even channel path (1314), a Mech-Zehnder interferometer (MZI) wavelength splitter (1320), MZI filters (1322, 1324), a photodiode (226), and heaters (228-1, 228-2, 228-3). A heater (228-1) is positioned in proximity to the MZI wavelength splitter (1320) on the optical die (104). A heater (228-2) is positioned in proximity to the MZI filter (1322) on the optical die (104). A heater (228-3) is positioned in proximity to the MZI filter (1324) on the optical die (104). A common channel path (1310) is configured to transmit odd channel optical signals (1340) and even channel optical signals (1342). An MZI wavelength splitter (1320) receives odd channel optical signals (1340) and even channel optical signals (1342) from the common channel path (1310) and is configured to split the odd channel optical signals (1340) to the odd channel path (1312) and the even channel optical signals (1342) to the even channel path (1314). An MZI filter (1322) receives the odd channel optical signals (1340) from the odd channel path (1312), suppresses spurious even channel optical signals, and is configured to transmit the odd channel optical signals (1340) over the optical channel. The MZI filter (1324) is configured to receive even channel optical signals (1342) from an even channel path (1314), suppress spurious odd channel optical signals, and transmit even channel optical signals (1342) on an optical channel. A photodiode (226) is placed in the optical die (104) such that a portion of the optical signal output from the MZI filters (1322, 1324) is incident on the photodiode (226). The photodiode (226) is configured to generate current in response to the optical signal being incident on the photodiode (226). The output node (1330) of the photodiode (226) is electrically coupled to each input node (420-1, 420-2, 420-3) of the DC-controllable transimpedance stages of the controllers (210-1, 210-2, 210-3). The heater (228-1) is electrically coupled to the DAC (212-1); the heater (228-2) is electrically coupled to the DAC (212-2); and the heater (228-3) is electrically coupled to the DAC (212-3). When in operation, the photodiode (226) generates current in response to optical signals from the MZI filters (1322, 1324) being incident on the photodiode (226). The current generated by the photodiode (226) is divided between the controllers (210-1, 210-2, 210-3) at the input nodes (420-1, 420-2, 420-3) as each input current (Iin1, Iin2, Iin3) and received by them. Each controller (210-1, 210-2, 210-3) operates for each input current (Iin1, Iin2, Iin3) as described above. The controller (1303) controls the controllers (210-1, 210-2, 210-3) to sequentially perform DC setting tracking and temperature setting tracking among the controllers (210-1, 210-2, 210-3). FIG. 14 is a flowchart of these sequential operations according to some examples. In block (1402), DC setting tracking is performed by controller (210-1), and in block (1404), temperature setting tracking is performed by controller (210-1). In block (1406), DC setting tracking is performed by controller (210-2), and in block (1408), temperature setting tracking is performed by controller (210-2). In block (1410), DC setting tracking is performed by controller (210-3), and in block (1412), temperature setting tracking is performed by controller (210-3). Controller (1303) can adjust and control which controller starts the DC setting tracking based on which controller has finished the temperature setting tracking. Each DC setting trace for each controller (210-1, 210-2, 210-3) can be performed individually as described above, and each temperature setting trace for each controller (210-1, 210-2, 210-3) can be performed individually as described above. Accordingly, the examples in FIGS. 13 and 14 illustrate how a single photodiode can be implemented to control a plurality of, for example, optical filters. This example illustrates that the sequential operation of a plurality of controllers using the same photodiode can operate to control the temperature of a plurality of, for example, optical filters within an optical die. Some non-limiting examples can be expressed as follows. As an example 1 device, As the first controller: A first DC-controllable transimpedance stage having an input node and an output node — the input node of the first DC-controllable transimpedance stage is configured to be electrically coupled to a photodiode —; A first slicer circuit having an input node and an output node — the input node of the first slicer circuit is electrically coupled to the output node of a first DC-controllable transimpedance stage —; and A first controller comprising: a first processor having an input node electrically coupled to an output node of a first slicer circuit—the first processor is configured to control a first DC-controllable transimpedance stage to reduce a DC component of a signal on an output node of a first DC-controllable transimpedance stage based on a signal on an output node of the first slicer circuit—and A device comprising: a first digital-to-analog converter (DAC) having an input node electrically coupled to an output node of a first processor and an output node configured to be electrically coupled to a heater— wherein the first processor is configured to control an output voltage on the output node of the first DAC based on a signal on the output node of a first slicer circuit. Example 2. In Example 1, A photodiode electrically coupled to the input node of a first DC-controllable transimpedance stage; An optical element configured to pass an optical signal and having a temperature-dependent optical response — positioned relative to a photodiode such that at least a portion of the optical signal is incident on the photodiode —; and A device further comprising a heater electrically coupled to the output node of the first DAC — the heater is positioned in close proximity to an optical element —. Example 3. In Example 1, the first DC-controllable transimpedance stage is: A transimpedance amplifier electrically connected between the input node of the first DC-controllable transimpedance stage and the output node of the first DC-controllable transimpedance stage; and A device further comprising a controllable current source electrically connected between an input node and a power node of a first DC-controllable transimpedance stage. Example 4. A device in Example 1, wherein the first processor is configured to control the output voltage on the output node of the first DAC to dither between different duty cycles. Example 5. In Example 1, the first processor is: Repeatedly: To determine a DC setting for controlling the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage — the first processor is configured to control the first DC-controllable transimpedance stage using the DC setting to reduce the DC component of a signal on the first DC-controllable transimpedance stage —; and A device configured such that, after determining a DC setting, a temperature setting is determined to control the output voltage on the output node of the first DAC — the first processor is configured to control the output voltage on the output node of the first DAC using the temperature setting. Example 6. In Example 1, the first processor is: A tracking circuit configured to capture samples of a signal on the output node of a first slicer circuit, to generate a current control setting of a first DC-controllable transimpedance stage based on first samples captured from the signal on the output node of the first slicer circuit, and to generate a duty code and a level selection code based on second samples captured from the signal on the output node of the first slicer circuit and subsequent to the first samples captured; and A device further comprising a pulse width modulation circuit configured to generate a dither duty code and a dither level selection code based on a duty code and a level selection code, and to generate a thermal code having a dither duty cycle output to an input node of a first DAC. Example 7. In Example 1, As a second controller: A second DC-controllable transimpedance stage having an input node and an output node — the input node of the second DC-controllable transimpedance stage is electrically connected to the input node of the first DC-controllable transimpedance stage, and the input node of the second DC-controllable transimpedance stage is configured to be electrically coupled to a photodiode —; A second slicer circuit having an input node and an output node — the input node of the second slicer circuit is electrically coupled to the output node of the second DC-controllable transimpedance stage —; and A second controller comprising: a second processor having an input node electrically coupled to an output node of a second slicer circuit—the second processor is configured to control a second DC-controllable transimpedance stage to reduce a DC component of a signal on an output node of a second DC-controllable transimpedance stage based on a signal on an output node of the second slicer circuit—and A device further comprising: a second DAC having an input node electrically coupled to an output node of a first processor and an output node configured to be electrically coupled to a heater— wherein the second processor is configured to control an output voltage on the output node of the second DAC based on a signal on the output node of a second slicer circuit. Example 8. As a method for controlling the temperature of a device, A step of generating a first DC setting output from the processor to a first DC-controllable transimpedance stage by a processor ― the first DC-controllable transimpedance stage has an input node electrically coupled to a photodiode, the photodiode is configured to incident an optical signal passed from a first optical element thereon, the first optical element has a temperature-dependent optical response, and the processor generates the first DC setting based on a signal on the output node of the first DC-controllable transimpedance stage ―; and A method comprising the step of, after generating a first DC setting, generating a first temperature setting by a processor— wherein a first code output from the processor to a first digital-to-analog converter (DAC) is based on a first voltage setting, and the first DAC has an output node electrically coupled to a first heater positioned in proximity to a first optical element, and the processor generates the first temperature setting based on a signal on the output node of a first DC-controllable transimpedance stage. Example 9. A method in which, in Example 8, the step of generating a first DC setting and the step of generating a first temperature setting are performed repeatedly. Example 10. A method of Example 8, further comprising the step of diluting the duty cycle of the voltage on the output node of the first DAC based on the first temperature setting. Example 11. In Example 8, the step for creating the DC settings is: Repeat until the boat counter is equal to the first predetermined amount: A step of capturing a plurality of samples based on a signal on the output node of a first DC-controllable transimpedance stage; A step of incrementing the boat counter when the captured samples of each iteration are within the error range; A step of incrementing the round counter when the round counter is less than a second predetermined amount; and When the round counter is greater than the second predetermined amount: Step of adjusting the first DC setting; and A method comprising the step of resetting a boat counter and a round counter. Example 12. In Example 8, the step for creating the temperature setting is: A step of capturing a plurality of samples based on a signal on the output node of a first DC-controllable transimpedance stage; and A method comprising the step of adjusting a first temperature setting based on whether the captured samples have a majority logic "1". Example 13. In Example 8, the first DC-controllable transimpedance stage is: A transimpedance amplifier electrically connected between the input node of the first DC-controllable transimpedance stage and the output node of the first DC-controllable transimpedance stage; and A method comprising a controllable current source electrically connected between an input node and a power node of a first DC-controllable transimpedance stage — wherein the first DC setting controls the current of the controllable current source. Example 14. Method in Example 8, wherein the first code is a column code having a dithering duty cycle. Example 15. In Example 8, After generating a first temperature setting, a step of generating a second DC setting output to a second DC-controllable transimpedance stage ― the second DC-controllable transimpedance stage has an input node electrically coupled to a photodiode, the photodiode is also configured to incident an optical signal passed from a second optical element thereon, the second optical element has a temperature-dependent optical response, and the second DC setting is generated based on a signal on the output node of the second DC-controllable transimpedance stage ―; and A method further comprising the step of generating a second temperature setting after generating a second DC setting — wherein a second code output to a second DAC is based on the second temperature setting, and the second DAC has an output node electrically coupled to a second heater positioned in proximity to a second optical element, wherein the second temperature setting is generated based on a signal on the output node of a second DC-controllable transimpedance stage. Example 16. As a device, An optical element configured to pass an optical signal and having a temperature-dependent optical response; A photodiode positioned relative to an optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode; A heater positioned in close proximity to an optical element and configured to convert electrical energy into thermal energy; Transimpedance stage ― The input node of the transimpedance stage is electrically coupled to a photodiode, and the transimpedance stage includes a controllable current source electrically connected between the input node of the transimpedance stage and a power node ―; Slicer circuit ― the input node of the slicer circuit is electrically coupled to the output node of the transimpedance stage ―; and A device comprising a processor — the input node of the processor is electrically coupled to the output node of the slicer circuit, the processor is configured to control the current of a controllable current source based on an output signal on the output node of the slicer circuit, and is configured to control the amount of electrical energy supplied to a heater based on an output signal on the output node of the slicer circuit. Example 17. The device of Example 16, further comprising a digital-to-analog converter (DAC), wherein the input node of the DAC is electrically coupled to the output node of a processor, and the output node of the DAC is electrically coupled to a heater; and wherein the processor is configured to control the amount of electrical energy supplied to the heater by controlling the output voltage on the output node of the DAC. Example 18 In Example 17, the device is configured such that the processor outputs a thermal code on an output node of the processor electrically coupled to an input node of the DAC, and the thermal code has a dither duty cycle. Example 19. In Example 16, the processor is configured to generate a first setting for controlling the current of a controllable current source, and the processor repeatedly until the boat counter is equal to a first predetermined amount: Capturing a plurality of first samples of the output signal on the output node of the slicer circuit; Increment the boat counter when the first captured samples of each iteration are within the error range; When the round counter is less than a second predetermined amount, the round counter is incremented; and When the round counter is equal to the second predetermined amount: Adjusting the first setting; and A device configured to generate a first setting by resetting the boat counter and the round counter. Example 20. In Example 19, the processor is configured to generate a thermal code to control the amount of electrical energy supplied to the heater, the thermal code is output on the output node of the processor, and the process is: Capturing a plurality of second samples of the output signal on the output node of the slicer circuit; Adjusting the selection settings based on whether the captured second samples have a majority logic "1"; and A device configured to generate a heat code by generating a heat code based on a selection setting. The foregoing relates to specific examples, but other examples and additional examples may be devised without departing from the basic scope, and the scope is determined by the following examples.

Claims

Claim 1 As a device, as a first controller: a first DC-controllable transimpedance stage having an input node and an output node — the input node of the first DC-controllable transimpedance stage is configured to be electrically coupled to a photodiode —; a first slicer circuit having an input node and an output node — the input node of the first slicer circuit is electrically coupled to the output node of the first DC-controllable transimpedance stage —; and a first processor having an input node electrically coupled to the output node of the first slicer circuit — the first processor is configured to control the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage based on a signal on the output node of the first slicer circuit — the first controller comprising; A first digital-to-analog converter (DAC) having an input node electrically coupled to an output node of the first processor and an output node configured to be electrically coupled to a heater — the first processor is configured to control an output voltage on the output node of the first DAC based on a signal on the output node of the first slicer circuit —; the photodiode electrically coupled to an input node of the first DC-controllable transimpedance stage; an optical element configured to pass an optical signal and having a temperature-dependent optical response — the optical element is positioned relative to the photodiode such that at least a portion of the optical signal is incident on the photodiode —; and the heater electrically coupled to an output node of the first DAC, wherein the heater is positioned in close proximity to the optical element. Claim 2 delete Claim 3 A device according to claim 1, wherein the first DC-controllable transimpedance stage comprises: a transimpedance amplifier electrically connected between an input node of the first DC-controllable transimpedance stage and an output node of the first DC-controllable transimpedance stage; and a controllable current source electrically connected between an input node of the first DC-controllable transimpedance stage and a power node. Claim 4 A device according to claim 1, wherein the first processor is configured to control the output voltage on the output node of the first DAC to dither between different duty cycles. Claim 5 A device according to claim 1, wherein the first processor is configured to: repeatedly: determine a DC setting for controlling the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage — the first processor is configured to control the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage using the DC setting —; and after determining the DC setting, determine a temperature setting for controlling the output voltage on the output node of the first DAC — the first processor is configured to control the output voltage on the output node of the first DAC using the temperature setting — Claim 6 The device according to claim 1, wherein the first processor comprises: a tracking circuit configured to capture samples of a signal on the output node of the first slicer circuit, to generate a current control setting of the first DC-controllable transimpedance stage based on first samples captured from the signal on the output node of the first slicer circuit, and to generate a duty code and a level selection code based on second samples captured from the signal on the output node of the first slicer circuit and subsequent to the captured first samples; and a pulse width modulation circuit configured to generate a dither duty code and a dither level selection code based on the duty code and the level selection code, and to generate a thermal code having a dither duty cycle output to the input node of the first DAC. Claim 7 In claim 1, as a second controller: a second DC-controllable transimpedance stage having an input node and an output node — the input node of the second DC-controllable transimpedance stage is electrically connected to the input node of the first DC-controllable transimpedance stage, and the input node of the second DC-controllable transimpedance stage is configured to be electrically coupled to the photodiode —; a second slicer circuit having an input node and an output node — the input node of the second slicer circuit is electrically coupled to the output node of the second DC-controllable transimpedance stage —; A device comprising: a second controller having an input node electrically coupled to an output node of the second slicer circuit—the second processor being configured to control the second DC-controllable transimpedance stage to reduce the DC component of a signal on an output node of the second DC-controllable transimpedance stage based on a signal on an output node of the second slicer circuit; and a second DAC having an input node electrically coupled to a first output node of the second processor and an output node configured to be electrically coupled to a second heater—the second processor being configured to control an output voltage on an output node of the second DAC based on a signal on an output node of the second slicer circuit. Claim 8 As a device, an optical element configured to pass an optical signal and having a temperature-dependent optical response; a photodiode — said photodiode is positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode —; a heater positioned in proximity to the optical element and configured to convert electrical energy into thermal energy; a transimpedance stage — the input node of the transimpedance stage is electrically coupled to the photodiode, and the transimpedance stage includes a controllable current source electrically connected between the input node of the transimpedance stage and a power node —; a slicer circuit — the input node of the slicer circuit is electrically coupled to the output node of the transimpedance stage —; A device comprising: a processor — the input node of the processor is electrically coupled to the output node of the slicer circuit, the processor is configured to control the current of the controllable current source based on an output signal on the output node of the slicer circuit, and is configured to control the amount of electrical energy provided to the heater based on an output signal on the output node of the slicer circuit. Claim 9 A device according to claim 8, further comprising a digital-to-analog converter (DAC), wherein the input node of the DAC is electrically coupled to the output node of the processor, and the output node of the DAC is electrically coupled to the heater; and wherein the processor is configured to control the amount of electrical energy provided to the heater by controlling the output voltage on the output node of the DAC. Claim 10 A device according to claim 9, wherein the processor is configured to output a thermal code on an output node of the processor electrically coupled to an input node of the DAC, and the thermal code has a dither duty cycle. Claim 11 A device according to claim 8, wherein the processor is configured to generate a first setting for controlling the current of the controllable current source, and the processor is configured to generate the first setting by repeatedly: capturing a plurality of first samples of an output signal on an output node of the slicer circuit until a vote counter equals a first predetermined amount; incrementing the vote counter when the captured first samples of each iteration are within an error range; incrementing the round counter when the round counter is less than a second predetermined amount; and adjusting the first setting when the round counter equals the second predetermined amount; and resetting the vote counter and the round counter. Claim 12 A device according to claim 11, wherein the processor is configured to generate a thermal code for controlling the amount of electrical energy supplied to the heater, the thermal code is output on an output node of the processor, and the processor is configured to: capture a plurality of second samples of an output signal on an output node of the slicer circuit; adjust a selection setting based on whether the captured second samples have a majority of logic "1"; and generate the thermal code based on the selection setting. Claim 13 A method for controlling the temperature of a device, wherein a processor generates a first DC setting output from the processor to a first DC-controllable transimpedance stage — the first DC-controllable transimpedance stage has an input node electrically coupled to a photodiode, the photodiode is configured to incident an optical signal passed from a first optical element upon it, the first optical element has a temperature-dependent optical response, and the processor generates the first DC setting based on a signal on the output node of the first DC-controllable transimpedance stage —; A method comprising the step of, after generating the first DC setting, generating a first temperature setting by the processor— wherein a first code output from the processor to a first digital-to-analog converter (DAC) is based on the first temperature setting, and the first DAC has an output node electrically coupled to a first heater positioned in proximity to the first optical element, wherein the processor generates the first temperature setting based on a signal on the output node of the first DC-controllable transimpedance stage. Claim 14 A method according to claim 13, wherein the step of generating the first DC setting comprises: repeatedly capturing a plurality of samples based on a signal on the output node of the first DC-controllable transimpedance stage until the boat counter is equal to a first predetermined amount; incrementing the boat counter when the captured samples of each iteration are within an error range; incrementing the round counter when the round counter is less than a second predetermined amount; and adjusting the first DC setting when the round counter is greater than or equal to the second predetermined amount; and resetting the boat counter and the round counter. Claim 15 A method according to claim 13, further comprising the step of generating a second DC setting output to a second DC-controllable transimpedance stage after generating the first temperature setting — wherein the second DC-controllable transimpedance stage has an input node electrically coupled to the photodiode, and the photodiode is also configured to incident an optical signal passed from a second optical element upon it, and the second optical element has a temperature-dependent optical response, and the second DC setting is generated based on a signal on the output node of the second DC-controllable transimpedance stage — and the step of generating a second temperature setting after generating the second DC setting — wherein a second code output to a second DAC is based on the second temperature setting, and the second DAC has an output node electrically coupled to a second heater disposed in close proximity to the second optical element, and the second temperature setting is generated based on a signal on the output node of the second DC-controllable transimpedance stage.

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