Semiconductor device, display device provided with said semiconductor device and electronic device provided with said semiconductor device

Abstract

In a transistor having an oxide semiconductor, fluctuations in electrical characteristics are suppressed, and reliability is improved. A semiconductor device having a transistor. The transistor has a first conductive film functioning as a first gate electrode, a first gate insulating film, a first oxide semiconductor film having a channel region, a second gate insulating film, a second oxide semiconductor film functioning as a second gate electrode, and a second conductive film. The second oxide semiconductor film has a region with a higher carrier density than the first oxide semiconductor film. The second conductive film has a region in contact with the first conductive film.

Description

Technology Field

[0001] One embodiment of the present invention relates to a semiconductor device having an oxide semiconductor film and a display device having said semiconductor device.

[0002] Furthermore, one embodiment of the present invention is not limited to the technical fields described above. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, or a method of manufacturing. Alternatively, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. More specifically, it relates to a semiconductor device, a display device, a light-emitting device, a lighting device, a capacitor device, a memory device, an imaging device, a method of driving the same, or a method of manufacturing the same.

[0003] In addition, the term "semiconductor device" in this specification and others refers to any device capable of functioning by utilizing semiconductor characteristics. Semiconductor devices such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are forms of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may have semiconductor devices. Background Technology

[0004] Technology for constructing transistors (also known as field-effect transistors (FETs) or thin-film transistors (TFTs)) using semiconductor thin films formed on a substrate having an insulating surface is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices. While semiconductor materials, represented by silicon, are widely known for semiconductor thin films applicable to transistors, oxide semiconductors are also drawing attention as alternative materials.

[0005] For example, a technology for fabricating a transistor using an In-Ga-Zn-based oxide as an oxide semiconductor is disclosed (see Patent Document 1). In addition, a technology for fabricating a transistor of an oxide thin film having a self-aligned top gate structure is disclosed (see Patent Document 2).

[0006] In addition, a semiconductor device is disclosed that reduces oxygen deficiency in an oxide semiconductor layer by using an insulating layer that releases oxygen upon heating on an insulating layer on the lower insulating layer of an oxide semiconductor layer forming a channel (see Patent Document 3). Prior art literature

[0007] Japanese Patent Publication No. JP 2007-96055, Japanese Patent Publication No. JP 2009-278115, Japanese Patent Publication No. JP 2012-009836 The problem to be solved

[0008] Examples of transistors having oxide semiconductor films include reverse staggered (also known as bottom-gate structure) and staggered (also known as top-gate structure) types. When applying transistors with oxide semiconductor films to display devices, reverse staggered transistors are frequently used over staggered transistors because their fabrication process is relatively simpler and manufacturing costs can be suppressed. However, as display screens become larger or image quality becomes higher, reverse staggered transistors face the problem of degraded image quality due to increased signal delay caused by parasitic capacitance between the gate electrode, source electrode, and drain electrode. Therefore, there is a demand for the development of structures for staggered transistors with oxide semiconductor films that possess stable electrical characteristics and high reliability.

[0009] Furthermore, when fabricating a transistor using an oxide semiconductor film in the channel region, oxygen vacancies formed within the channel region of the oxide semiconductor film become a problem because they affect the transistor characteristics. For example, if oxygen vacancies are formed within the channel region of the oxide semiconductor film, carriers are generated due to these oxygen vacancies. When carriers are generated within the channel region of the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film in the channel region occur, such as a shift in the threshold voltage. Additionally, a problem arises where variations in electrical characteristics occur from transistor to transistor. Therefore, it is desirable to have minimal oxygen vacancies in the channel region of the oxide semiconductor film. Meanwhile, in a transistor using an oxide semiconductor film in the channel region, it is desirable for the oxide semiconductor film in contact with the source and drain electrodes to have high oxygen vacancies and low resistance in order to reduce contact resistance with the source and drain electrodes.

[0010] In light of the above problems, one embodiment of the present invention has as its objective to suppress variations in electrical characteristics in a transistor having an oxide semiconductor. Alternatively, one embodiment of the present invention has as its objective to improve reliability in a transistor having an oxide semiconductor. Alternatively, one embodiment of the present invention has as its objective to provide a transistor having a large on-current having an oxide semiconductor. Alternatively, one embodiment of the present invention has as its objective to provide a transistor having a small off-current having an oxide semiconductor. Alternatively, one embodiment of the present invention has as its objective to provide a semiconductor device with reduced power consumption. Alternatively, one embodiment of the present invention has as its objective to provide a novel semiconductor device. Alternatively, one embodiment of the present invention has as its objective to provide a method for manufacturing a novel semiconductor device.

[0011] Furthermore, the description of the aforementioned problem does not prevent the existence of other problems. Moreover, one embodiment of the present invention is not necessarily required to solve all of these problems. Problems other than those described above become naturally apparent from the description in the specification, etc., and problems other than those described above can be derived from the description in the specification, etc. means of solving the problem

[0012] One embodiment of the present invention is a semiconductor device having a transistor, wherein the transistor has a first conductive film, a first insulating film on the first conductive film, a first oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film in between, a second insulating film on the first oxide semiconductor film, a second oxide semiconductor film having a region overlapping with the first oxide semiconductor film with the second insulating film in between, a second conductive film on the second oxide semiconductor film, and a third insulating film on the first oxide semiconductor film, on the second oxide semiconductor film, and on the second conductive film, wherein the first oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, the second oxide semiconductor film has a region having a carrier density higher than that of the channel region, and the second conductive film has a region in contact with the first conductive film.

[0013] In addition, another embodiment of the present invention is a semiconductor device having a transistor, wherein the transistor comprises a first conductive film, a first insulating film on the first conductive film, a first oxide semiconductor film having a region overlapping with the first conductive film with the first insulating film in between, a second insulating film on the first oxide semiconductor film, a second oxide semiconductor film having a region overlapping with the first oxide semiconductor film with the second insulating film in between, a second conductive film on the second oxide semiconductor film, and a third insulating film on the first oxide semiconductor film, on the second oxide semiconductor film, and on the second conductive film, wherein the first oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, and the second oxide semiconductor film has a region having a carrier density higher than that of the channel region, and the first insulating film, the second insulating film, and the second oxide semiconductor film have a first opening, and a second The conductive film is a semiconductor device having a region in contact with the first conductive film at the first opening.

[0014] In each of the above configurations, it is preferable that the second conductive film has light-blocking properties. In addition, it is preferable that the sheet resistance of the second conductive film is 10Ω / square (Ω / sq.) or less.

[0015] In addition, in each of the above configurations, the transistor further comprises a third conductive film and a fourth conductive film, wherein the third conductive film has a region electrically connected to a first oxide semiconductor film in a source region through a second opening provided in the third insulating film, and the fourth conductive film has a region electrically connected to a first oxide semiconductor film in a drain region through a third opening provided in the third insulating film.

[0016] In addition, in each of the above configurations, it is preferable that at least one of the first oxide semiconductor film and the second oxide semiconductor film has In, Zn, and M (M is Al, Ga, Y, or Sn).

[0017] In addition, in each of the above configurations, when the second oxide semiconductor film has In, Zn, and M, it is preferable to have a region where the content of In is greater than or equal to the content of M. In addition, when the first oxide semiconductor film has In, Zn, and M, it is preferable to have a region where the content of In is greater than or equal to the content of M.

[0018] In addition, in each of the above configurations, it is preferable that the third insulating film has at least one of nitrogen and hydrogen.

[0019] In addition, in each of the above configurations, it is preferable that the first oxide semiconductor film has a crystalline portion, and that the crystalline portion has c-axis orientation.

[0020] Furthermore, another embodiment of the present invention is a display device having a semiconductor device and a display element of each of the above forms. Additionally, another embodiment of the present invention is an electronic device having a semiconductor device and a sensor of the above forms. In this specification, the term "display device" refers to an image display device. Furthermore, a module equipped with a connector, such as a Flexible Printed Circuit (FPC) or Tape Carrier Package (TCP), a module having a printed circuit board provided at the end of the TCP, or a module in which an Integrated Circuit (IC) is directly mounted on the display device by the Chip On Glass (COG) method are all included in an embodiment of the present invention. Effects of the invention

[0021] According to one embodiment of the present invention, fluctuations in electrical characteristics can be suppressed in a transistor having an oxide semiconductor. Alternatively, according to one embodiment of the present invention, reliability can be improved in a transistor having an oxide semiconductor. Alternatively, according to one embodiment of the present invention, a transistor having a large on-current having an oxide semiconductor can be provided. Alternatively, according to one embodiment of the present invention, a transistor having a small off-current having an oxide semiconductor can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0022] Furthermore, the description of these effects does not interfere with the existence of other effects. Also, one embodiment of the present invention is not necessarily required to possess all of these effects. Additionally, effects other than these become naturally apparent from the description in the specification, drawings, claims, etc., and other effects can be derived from the description in the specification, drawings, claims, etc. Brief explanation of the drawing

[0023] FIG. 1 is a drawing illustrating the top surface and cross-section of a semiconductor device. FIG. 2 is a drawing illustrating the top surface and cross-section of a semiconductor device. FIG. 3 is a diagram illustrating a cross-section of a semiconductor device. FIG. 4 is a drawing illustrating a cross-section of a semiconductor device. FIG. 5 is a diagram illustrating a cross-section of a semiconductor device. FIG. 6 is a diagram illustrating a cross-section of a semiconductor device. FIG. 7 is a drawing illustrating a cross-section of a semiconductor device. FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 14 is a diagram illustrating the range of atomic number ratios of an oxide semiconductor, which is one embodiment of the present invention. Figure 15 is a diagram illustrating the crystallization of InMZnO4. Figure 16 is a band diagram in a stacked structure of an oxide semiconductor. Figure 17 is a diagram illustrating the structural analysis by XRD of CAAC-OS and a single-crystal oxide semiconductor, and a diagram showing the limited field electron diffraction pattern of CAAC-OS. FIG. 18 shows a cross-sectional TEM image of CAAC-OS, a planar TEM image, and image analysis images thereof. Figure 19 shows the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. Figure 20 is a cross-sectional TEM image of an a-like OS. FIG. 21 is a diagram illustrating the change in the crystal portion of In-Ga-Zn oxide due to electron irradiation. FIG. 22 is a top view illustrating one form of a display device. FIG. 23 is a cross-sectional view illustrating one form of a display device. FIG. 24 is a cross-sectional view illustrating one form of a display device. FIG. 25 is a cross-sectional view illustrating one form of a display device. FIG. 26 is a cross-sectional view illustrating one form of a display device. FIG. 27 is a cross-sectional view illustrating one form of a display device. FIG. 28 is a block diagram and circuit diagram illustrating a display device. FIG. 29 is a circuit diagram and timing chart for illustrating one embodiment of the present invention. FIG. 30 is a graph and circuit diagram for illustrating one embodiment of the present invention. FIG. 31 is a circuit diagram and timing chart for illustrating one embodiment of the present invention. FIG. 32 is a circuit diagram and timing chart for illustrating one embodiment of the present invention. FIG. 33 is a block diagram, circuit diagram, and waveform diagram for illustrating one embodiment of the present invention. FIG. 34 is a circuit diagram and timing chart for illustrating one embodiment of the present invention. FIG. 35 is a circuit diagram for illustrating one embodiment of the present invention. FIG. 36 is a circuit diagram for illustrating one embodiment of the present invention. FIG. 37 is a drawing illustrating a display module. FIG. 38 is a drawing illustrating an electronic device. FIG. 39 is a drawing illustrating an electronic device. FIG. 40 is a perspective view illustrating a display device. FIG. 41 is a drawing illustrating the measurement results of sheet resistance according to an embodiment. FIG. 42 is a drawing illustrating the measurement results of contact chain resistance according to an embodiment. FIG. 43 is a drawing illustrating a cross-section of a transistor according to an embodiment. FIG. 44 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 45 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 46 is a diagram illustrating the reliability test results of a transistor according to an embodiment. FIG. 47 is a diagram illustrating the Id-Vg characteristics of a transistor during light irradiation according to an embodiment. FIG. 48 is a diagram illustrating the Id-Vg characteristics of a transistor during light irradiation according to an embodiment. FIG. 49 is a drawing illustrating a TEM image of a transistor according to an embodiment. FIG. 50 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 51 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 52 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 53 is a drawing illustrating the ESR measurement results according to an embodiment. FIG. 54 is a diagram illustrating the measurement results of a signal spin density having three peaks according to an embodiment. FIG. 55 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 56 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 57 is a drawing illustrating the TDS analysis results according to an embodiment. FIG. 58 is a drawing illustrating a cross-section of a transistor according to an embodiment. FIG. 59 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 60 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 61 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 62 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 63 is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 64 is a diagram illustrating the reliability test results of a transistor according to an embodiment. FIG. 65 is a diagram illustrating the Id-Vg characteristics of a transistor during light irradiation according to an embodiment. FIG. 66 is a diagram illustrating the Id-Vg characteristics of a transistor during light irradiation according to an embodiment. FIG. 67 is a diagram illustrating the Id-Vg characteristics of a transistor during light irradiation according to an embodiment. Specific details for implementing the invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description below, and its form and details may be varied without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the description of the embodiments shown below.

[0025] In addition, the location, size, range, etc. of each component depicted in drawings, etc., may not show the actual location, size, or range to facilitate understanding. Therefore, the disclosed invention is not necessarily limited to the location, size, or range, etc. disclosed in the drawings, etc.

[0026] In addition, ordinal numbers such as "first," "second," etc. assigned in this specification are used for convenience and may not indicate the process order or stacking order. Therefore, for example, it is possible to explain by appropriately rephrasing "first" as "second" or "third." Furthermore, the ordinal numbers described in this specification and the ordinal numbers used to specify an embodiment of the present invention may not coincide.

[0027] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships of the components with reference to the drawings. Additionally, the positional relationships of the components vary appropriately depending on the direction in which each component is depicted. Therefore, the terms described in this specification are not limited to those used hereto and may be appropriately rephrased depending on the situation.

[0028] In addition, in describing the composition of the invention using drawings in this specification and others, reference numerals indicating the same thing are used commonly across different drawings.

[0029] Furthermore, even when referred to as a "semiconductor" in the present specification, etc., it may possess characteristics of an "insulator," for example, if its conductivity is sufficiently low. Additionally, the boundary between a "semiconductor" and an "insulator" is ambiguous, so there are cases where they cannot be strictly distinguished. Therefore, the term "semiconductor" as used in the present specification, etc., may be rephrased as "insulator." Likewise, the term "insulator" as used in the present specification, etc., may be rephrased as "semiconductor." Alternatively, the term "insulator" as used in the present specification, etc., may be rephrased as "semi-insulator."

[0030] Furthermore, even when the term "semiconductor" is used in this specification, etc., it may possess characteristics of a "conductor," for example, if its conductivity is sufficiently high. Additionally, the boundary between a "semiconductor" and a "conductor" is ambiguous, so there are cases where they cannot be strictly distinguished. Therefore, the term "semiconductor" as used in this specification, etc., may be rephrased as "conductor." Likewise, the term "conductor" as used in this specification, etc., may be rephrased as "semiconductor."

[0031] In addition, as defined in this specification, etc., a transistor is a device having at least three terminals including a gate, a drain, and a source. Furthermore, it has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and can flow current through the drain, the channel region, and the source. In addition, as defined in this specification, etc., the channel region refers to a region through which current mainly flows.

[0032] In addition, the functions of the source and drain may be interchanged when transistors with different polarities are used or when the direction of the current changes during circuit operation. Therefore, the terms source and drain may be used interchangeably in this specification.

[0033] Furthermore, channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part within the semiconductor through which current flows when the transistor is in the ON state) and the gate electrode overlap, or in the region where the channel is formed, for example, in a top view of a transistor. Additionally, it cannot be said that the channel length of a single transistor takes the same value in all regions. That is, the channel length of a single transistor may not be determined as a single value. Therefore, in this specification and others, the channel length is defined as any one value, maximum value, minimum value, or average value in the region where the channel is formed.

[0034] Channel width refers to the length of the region where the semiconductor (or the part within the semiconductor where current flows when the transistor is in the ON state) and the gate electrode overlap, for example, or the region where the source and drain face each other in the region where the channel is formed. Furthermore, it cannot be said that the channel width of a single transistor takes the same value in all regions. That is, the channel width of a single transistor may not be determined as a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the region where the channel is formed.

[0035] Furthermore, in this specification and others, the expression "electrically connected" includes cases where the connection is made through "something having an electrical function." Here, "something having an electrical function" is not particularly limited as long as it is capable of transmitting and receiving electrical signals between the connected objects. For example, "something having an electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistors, inductors, capacitors, and other various functional elements.

[0036] Furthermore, voltage often refers to the potential difference between an arbitrary potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be rephrased as potential.

[0037] Additionally, the terms "film" and "layer" may be interchanged in this specification and others. For example, the term "conductive layer" may be replaced with the term "conductive film." Or, for example, the term "insulating film" may be replaced with the term "insulating layer."

[0038] Furthermore, unless specifically mentioned in this specification or the like, off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or cut-off state). Unless specifically mentioned, the off state refers to a state in which the voltage between the gate and source (Vgs) is lower than the threshold voltage (Vth) for an n-channel transistor, and a state in which the voltage between the gate and source (Vgs) is higher than the threshold voltage (Vth) for a p-channel transistor. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage between the gate and source (Vgs) is lower than the threshold voltage (Vth).

[0039] The off-current of a transistor may depend on Vgs. Therefore, the statement that the off-current of a transistor is less than or equal to I may mean that there exists a value of Vgs at which the off-current of the transistor becomes less than or equal to I. The off-current of a transistor may refer to the off-current in an off-state at a predetermined Vgs, an off-state at a Vgs within a predetermined range, or an off-state at a Vgs where a sufficiently reduced off-current is obtained.

[0040] As an example, when the threshold voltage (Vth) is 0.5V and Vgs is 0.5V, the drain current is 1×10 -9 When A and Vgs is 0.1V, the drain current is 1×10 -13When A is and Vgs is -0.5V, the drain current is 1×10 -19 When A is and Vgs is -0.8V, the drain current is 1×10 -22 Assume an n-channel transistor A. The drain current of the transistor is 1×10 when Vgs is -0.5V, or when Vgs is in the range of -0.5V to -0.8V. -19 Since it is less than or equal to A, the off-current of the above transistor is 1×10 -19 There are cases where it is stated that it is less than or equal to A. The drain current of the above transistor is 1×10 -22 Since there exists a Vgs that is less than or equal to A, the off-current of the transistor is 1×10 -22 There are cases where it is said that it is less than or equal to A.

[0041] In addition, in the present specification and others, the off-current of a transistor having a channel width (W) may be expressed as a current value flowing per channel width (W). In addition, it may be expressed as a current value flowing per a predetermined channel width (e.g., 1 μm). In the latter case, the unit of the off-current may be expressed as a unit having the dimension of current / length (e.g., A / μm).

[0042] The off-current of a transistor may depend on temperature. Unless otherwise specified, the term "off-current" in this specification may refer to the off-current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, it may refer to the off-current at a temperature where the reliability of a semiconductor device, etc., including the transistor is guaranteed, or at a temperature where the semiconductor device, etc., including the transistor is used (e.g., any one of a temperature between 5°C and 35°C). The phrase "the off-current of the transistor is I or less" may refer to the existence of a value of Vgs such that the off-current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature where the reliability of a semiconductor device, including the transistor is guaranteed, or at a temperature where the semiconductor device, including the transistor, is used (e.g., any one of a temperature between 5°C and 35°C).

[0043] The off-current of a transistor may depend on the voltage (Vds) between the drain and the source. Unless otherwise specified, the off-current in this specification may refer to the off-current when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, it may refer to the off-current at a Vds where the reliability of a semiconductor device, etc., including the transistor is guaranteed, or at a Vds used in a semiconductor device, etc., including the transistor. The statement that the off-current of the transistor is less than or equal to I may refer to the existence of a value of Vgs such that the off-current of the transistor is less than or equal to I at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or Vds used in the semiconductor device including the transistor.

[0044] In the above explanation of off-current, the drain may be read as the source. That is, off-current may also refer to the current flowing through the source when the transistor is in the off state.

[0045] In addition, the term "leakage current" may be used interchangeably with "off current" in this specification and others. Furthermore, in this specification and others, "off current" may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state.

[0046] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or greater and 10° or less. Accordingly, cases of -5° or greater and 5° or less are included. In addition, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or greater and 30° or less. In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or greater and 100° or less. Accordingly, cases of 85° or greater and 95° or less are included. In addition, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or greater and 120° or less.

[0047] In addition, in this specification, if the crystal is a trigonal or rhombohedral crystal system, it is indicated as a hexagonal crystal system.

[0048] (Embodiment 1)

[0049] In this embodiment, an example of a semiconductor device of one form of the present invention and a method for manufacturing a semiconductor device is described below using FIGS. 1 to 16.

[0050] <Example of Semiconductor Device Configuration 1>

[0051] FIG. 1 (A) is a top view of a transistor (100) having a semiconductor device of one form of the present invention. FIG. 1 (B) is a cross-sectional view of the cross-section between the dotted line X1-X2 shown in FIG. 1 (A), and FIG. 1 (C) is a cross-sectional view of the cross-section between the dotted line Y1-Y2 shown in FIG. 1 (A). Additionally, in FIG. 1 (A), some of the components of the transistor (100), such as the substrate (102) and insulating film, are omitted for clarity.

[0052] In addition, the dotted line X1-X2 direction in (A) of Fig. 1 is sometimes referred to as the channel length (L) direction of the transistor (100), and the dotted line Y1-Y2 direction as the channel width (W) direction of the transistor (100).

[0053] A transistor (100) has a conductive film (106) that functions as a first gate electrode (also called a bottom gate electrode) on a substrate (102), an insulating film (104) on the substrate (102) and the conductive film (106), an oxide semiconductor film (108) on the insulating film (104), an insulating film (110) on the oxide semiconductor film (108), an oxide semiconductor film (112) and a conductive film (114) that function as a second gate electrode (also called a top gate electrode) on the insulating film (110), and an insulating film (116) on the insulating film (104), the oxide semiconductor film (108), the oxide semiconductor film (112), and the conductive film (114). Additionally, the oxide semiconductor film (108) has a channel region (108i) that overlaps with the oxide semiconductor film (112) and the conductive film (114) and is in contact with the insulating film (110), a source region (108s) that is in contact with the insulating film (116), and a drain region (108d) that is in contact with the insulating film (116).

[0054] Additionally, the transistor (100) has an insulating film (118) on an insulating film (116), a conductive film (120s) electrically connected to an oxide semiconductor film (108) in a source region (108s) through an opening (141s) provided in the insulating film (116) and the insulating film (118), and a conductive film (120d) electrically connected to an oxide semiconductor film (108) in a drain region (108d) through an opening (141d) provided in the insulating film (116) and the insulating film (118).

[0055] Additionally, in the present specification, etc., the insulating film (104) may be referred to as the first insulating film, the insulating film (110) as the second insulating film, the insulating film (116) as the third insulating film, and the insulating film (118) as the fourth insulating film. Also, in the transistor (100), the insulating film (104) has the function of a first gate insulating film, and the insulating film (110) has the function of a second gate insulating film. Therefore, in the present specification, etc., the insulating film (104) may be referred to as the first gate insulating film, and the insulating film (110) as the second gate insulating film. Additionally, the conductive film (120s) has the function of a source electrode, and the conductive film (120d) has the function of a drain electrode. Therefore, in the present specification, etc., the conductive film (120s) may be referred to as the source electrode, and the conductive film (120d) as the drain electrode.

[0056] The oxide semiconductor film (112) has the function of supplying oxygen to the insulating film (110). Since the oxide semiconductor film (112) has the function of supplying oxygen to the insulating film (110), excess oxygen can be contained within the insulating film (110). Since the insulating film (110) has an excess oxygen region, the excess oxygen can be supplied to the oxide semiconductor film (108), more specifically within the channel region (108i). Thus, a highly reliable semiconductor device can be provided.

[0057] Additionally, to supply excess oxygen within the oxide semiconductor film (108), excess oxygen may be supplied to the insulating film (104) formed below the oxide semiconductor film (108). However, in this case, the oxygen contained within the insulating film (104) may also be supplied to the source region (108s) and drain region (108d) of the oxide semiconductor film (108). When excess oxygen is supplied to the source region (108s) and drain region (108d), the resistance of the source region (108s) and drain region (108d) may increase.

[0058] Meanwhile, by configuring the insulating film (110) formed on the upper side of the oxide semiconductor film (108) to have excess oxygen, excess oxygen can be selectively supplied only to the channel region (108i). Alternatively, after supplying excess oxygen to the channel region (108i), source region (108s), and drain region (108d), the carrier density of the source region (108s) and drain region (108d) can be selectively increased.

[0059] The insulating film (116) has at least one of nitrogen and hydrogen. By configuring the insulating film (116) to have at least one of nitrogen and hydrogen, at least one of nitrogen and hydrogen can be supplied to the oxide semiconductor film (108) and the oxide semiconductor film (112). As a result, a source region (108s) and a drain region (108d) can be formed in the oxide semiconductor film (108).

[0060] Additionally, the oxide semiconductor film (112) supplies oxygen to the insulating film (110), and then supplies at least one of nitrogen and hydrogen from the insulating film (116) or the conductive film (114), thereby forming a donor level near the conduction band and increasing the carrier density. In other words, the oxide semiconductor film (112) also functions as an oxide conductor (OC). Therefore, the oxide semiconductor film (112) has a higher carrier density than at least the channel region (108i) of the oxide semiconductor film (108).

[0061] Generally, oxide semiconductors have transparency to visible light because they have a large energy gap. Meanwhile, oxide conductors are oxide semiconductors that have donor levels near the conduction band. Therefore, oxide conductors have a small effect of absorption due to donor levels and have transparency to visible light to the same degree as oxide semiconductors. Therefore, in order to prevent light from being incident on the oxide semiconductor film (112), it is desirable to have a conductive film (114) on the oxide semiconductor film (112).

[0062] The conductive film (114) is preferably made of a material that has light-blocking properties. In addition, a material with high conductivity is preferred, that is, a material with low sheet resistance is preferred. Specifically, the sheet resistance of the conductive film (114) is preferably 100Ω / sq. or less, more preferably 10Ω / sq. or less. Therefore, the conductive film (114) is preferably made of metal.

[0063] Additionally, if the conductive film (114) has the function of supplying at least one of nitrogen and hydrogen in excess, there may be cases where at least one of nitrogen and hydrogen is supplied to the channel region (108i) of the oxide semiconductor film (108). Therefore, it is desirable for the conductive film (114) to have a low function of supplying at least one of nitrogen and hydrogen. Additionally, it is desirable for the conductive film (114) to have a low function of permeating at least one of nitrogen and hydrogen.

[0064] Additionally, the source region (108s) and drain region (108d) of the oxide semiconductor film (108) and the oxide semiconductor film (112) may each have an element that forms an oxygen vacancy. Representative examples of the elements that form the oxygen vacancy include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and noble gases. In addition, representative examples of noble gas elements include helium, neon, argon, krypton, and xenon.

[0065] When impurity elements are added to an oxide semiconductor film, the bonds between metal elements and oxygen within the film are broken, forming oxygen vacancies. Alternatively, when impurity elements are added, oxygen bonded to metal elements within the film bonds with the impurity elements, causing oxygen to detach from the metal elements and form oxygen vacancies. As a result, the carrier density in the oxide semiconductor film increases, leading to higher conductivity.

[0066] Additionally, in the transistor (100), it is preferable to have a region where the side portion of the insulating film (110), the side portion of the oxide semiconductor film (112), and the side portion of the conductive film (114) are aligned. In other words, in the transistor (100), the upper portion of the insulating film (110) and the lower portion of the oxide semiconductor film (112) are substantially aligned, and the upper portion of the oxide semiconductor film (112) and the lower portion of the conductive film (114) are substantially aligned. For example, the above-described structure can be achieved by processing the insulating film (110) using the conductive film (114) as a mask.

[0067] Additionally, the transistor (100) has a region where the conductive film (106) and the conductive film (114) are in contact through an opening (143) provided in the insulating film (104), the insulating film (110), and the oxide semiconductor film (112), and they are electrically connected. Therefore, the same potential is supplied to the conductive film (106) and the conductive film (114).

[0068] In order to reduce the power consumption of the transistor (100) or to stabilize the electrical characteristics of the transistor (100), it is desirable that the contact resistance (contact resistance) or contact chain resistance of the conductive film (106) and the conductive film (114) be low.

[0069] In this way, the transistor (100) is configured to have a conductive film that functions as a gate electrode above and below an oxide semiconductor film (108).

[0070] ≪S-channel structure≫

[0071] As illustrated in (C) of FIG. 1, the oxide semiconductor film (108) is sandwiched between the first gate insulating film and the second gate insulating film, and between the conductive film (106) functioning as the first gate electrode, the oxide semiconductor film (112) functioning as the second gate electrode, and the conductive film (114). The length of the conductive film (106) in the channel width direction is longer than the length of the oxide semiconductor film (108) in the channel width direction. Additionally, the length of the oxide semiconductor film (112) in the channel width direction is longer than the length of the oxide semiconductor film (108) in the channel width direction. Additionally, the length of the conductive film (114) in the channel width direction is longer than the length of the oxide semiconductor film (108) in the channel width direction. Additionally, the conductive film (106) and the conductive film (114) have a contact area at an opening (143) provided in the insulating film (104), the insulating film (110), and the oxide semiconductor film (112), and since they are electrically connected, at least one side of the side of the oxide semiconductor film (108) in the channel width direction is facing the conductive film (114) with the insulating film (110) interposed therebetween. That is, the entire channel width direction of the oxide semiconductor film (108) is covered by the conductive film (106) and the conductive film (114) with the first gate insulating film and the second gate insulating film interposed therebetween.

[0072] In other words, in the channel width direction of the transistor (100), the conductive film (106) and the conductive film (114) are configured to surround the oxide semiconductor film (108) with the first gate insulating film and the second gate insulating film interposed.

[0073] By having this configuration, the oxide semiconductor film (108) of the transistor (100) can be electrically surrounded by the electric field of the conductive film (106) functioning as the first gate electrode and the conductive film (114) functioning as the second gate electrode. A device structure of a transistor that electrically surrounds the oxide semiconductor film, in which a channel region is formed by the electric field of the first gate electrode and the second gate electrode, such as the transistor (100), can be called a Surrounded channel (abbreviated as S-channel) structure.

[0074] Since the transistor (100) has an S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film (108) by means of the conductive film (106) and the conductive film (114). Therefore, the current driving capability of the transistor (100) is improved, making it possible to obtain high on-current characteristics. In addition, since the on-current can be increased, it is possible to miniaturize the transistor (100). Furthermore, since the transistor (100) has a structure surrounded by the conductive film (106) and the conductive film (114), the mechanical strength of the transistor (100) can be increased.

[0075] In addition, by making the above configuration, the region where carriers flow in the oxide semiconductor film (108) becomes the insulating film (104) side of the oxide semiconductor film (108), the insulating film (110) side of the oxide semiconductor film (108), and a wide area within the oxide semiconductor film (108), so the carrier mobility of the transistor (100) increases. As a result, as the on-current of the transistor (100) increases, the field-effect mobility increases, and specifically, the field-effect mobility is 10 cm 2It becomes greater than / V·s. Furthermore, the field-effect mobility mentioned here is not an approximation of mobility as a physical property of the oxide semiconductor film, but rather an indicator of the current driving force in the transistor's saturation region, and is the apparent field-effect mobility.

[0076] Additionally, in the channel width direction of the transistor (100), an opening different from the opening (143) may be formed on the opposite side of the oxide semiconductor film (108) from the part where the opening (143) is formed.

[0077] Components of a semiconductor device

[0078] Below, the components included in the semiconductor device of the present embodiment will be described in detail.

[0079] Oxide Semiconductor Film

[0080] In the oxide semiconductor film (108) of the transistor (100) which is one form of the present invention, an oxide semiconductor may be used. The oxide semiconductor will be described below.

[0081] It is preferable that the oxide semiconductor contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, or tin, etc. In addition, it may contain one or more types selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0082] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Additionally, element M is aluminum, gallium, yttrium, or tin, etc. Other elements that can be applied as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, multiple combinations of the aforementioned elements may be used as element M.

[0083] First, (A) of Fig. 14, (B) of Fig. 14, Using (C) of FIG. 14, a preferred range of atomic ratios of indium, element M, and zinc in an oxide semiconductor, which is one embodiment of the present invention, is described. Also, FIG. 14 does not describe the atomic ratio of oxygen. Additionally, each term for the atomic ratios of indium, element M, and zinc in the oxide semiconductor is denoted as [In], [M], and [Zn].

[0084] In FIG. 14 (A), FIG. 14 (B), and FIG. 14 (C), the dashed lines represent the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):1 (-1≤α≤1, α is -1 or greater and 1 or less), the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):2, the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):3, the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):4, and the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):5.

[0085] Also, the dotted line represents the line where the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≥0, β is 0 or greater), the line where the atomic ratio of [In]:[M]:[Zn]=1:2:β, the line where the atomic ratio of [In]:[M]:[Zn]=1:3:β, the line where the atomic ratio of [In]:[M]:[Zn]=1:4:β, the line where the atomic ratio of [In]:[M]:[Zn]=2:1:β, and the line where [In]:[M]:[Zn]=5:1:β.

[0086] In addition, oxide semiconductors with an atomic ratio of [In]:[M]:[Zn]=0:2:1 or values ​​near this, as shown in Fig. 14, are prone to having a spinel-type crystal structure.

[0087] Figures 14 (A) and 14 (B) illustrate an example of a preferred range of atomic ratios of indium, element M, and zinc in an oxide semiconductor, which is one form of the present invention.

[0088] As an example, FIG. 15 illustrates the crystal structure of InMZnO4 with [In]:[M]:[Zn]=1:1:1. FIG. 15 also shows the crystal structure of InMZnO4 when observed from a direction parallel to the b-axis. Furthermore, the metallic element in the layer having element M, zinc, and oxygen (hereinafter referred to as the (M, Zn) layer) shown in FIG. 15 represents element M or zinc. In this case, the ratio of element M to zinc is assumed to be the same. Elements M and zinc are interchangeable, and their arrangement is irregular.

[0089] InMZnO4 has a layered crystal structure (also called a layered structure), and as shown in FIG. 15, for every one layer having indium and oxygen (hereinafter referred to as the In layer), there are two layers of (M, Zn).

[0090] In addition, indium and element M can substitute for each other. Therefore, element M in the (M, Zn) layer can be substituted for indium to be represented as the (In, M, Zn) layer. In this case, it has a layered structure in which there are two (In, M, Zn) layers for every one In layer.

[0091] In addition, oxide semiconductors with an atomic ratio of [In]:[M]:[Zn]=1:1:2 have a layered structure having three (M, Zn) layers for every one In layer. That is, when [Zn] increases relative to [In] and [M], the ratio of the (M, Zn) layers to the In layer increases when the oxide semiconductor is crystallized.

[0092] However, in oxide semiconductors, when the total number of (M, Zn) layers for one In layer is non-integer, there are cases where there are multiple types of layered structures in which the total number of (M, Zn) layers for one In layer is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, there are cases where a layered structure in which there are two (M, Zn) layers for one In layer and a layered structure in which there are three (M, Zn) layers are mixed.

[0093] For example, when depositing an oxide semiconductor using a sputtering device, a film is formed having an atomic ratio that deviates from that of the target. In particular, depending on the substrate temperature during deposition, the [Zn] of the film may be smaller than that of the target.

[0094] In addition, there are cases where multiple phases coexist within an oxide semiconductor (two-phase coexistence, three-phase coexistence, etc.). For example, at atomic ratios near [In]:[M]:[Zn]=0:2:1, two phases—a spinel-type crystal structure and a layered crystal structure—are likely to coexist. Also, at atomic ratios near [In]:[M]:[Zn]=1:0:0, two phases—a bixbyite-type crystal structure and a layered crystal structure—are likely to coexist. When multiple phases coexist within an oxide semiconductor, grain boundaries (also called grain boundaries) may be formed between different crystal structures.

[0095] In addition, the carrier mobility (electron mobility) of oxide semiconductors can be increased by increasing the indium content. This is because, in oxide semiconductors containing indium, element M, and zinc, the s-orbitals of heavy metals mainly contribute to carrier conduction, and increasing the indium content increases the region where s-orbitals overlap; therefore, oxide semiconductors with a high indium content have higher carrier mobility compared to oxide semiconductors with a low indium content.

[0096] Meanwhile, as the content of indium and zinc in the oxide semiconductor decreases, the carrier mobility decreases. Therefore, at the atomic ratio [In]:[M]:[Zn]=0:1:0 and atomic ratios near this atomic ratio (e.g., region C shown in (C) of FIG. 14), the insulation is increased.

[0097] Accordingly, an oxide semiconductor, which is one embodiment of the present invention, preferably has an atomic ratio shown as region A in (A) of FIG. 14, which is prone to forming a layered structure with high carrier mobility and few grain boundaries.

[0098] Additionally, region B shown in (B) of FIG. 14 represents [In]:[M]:[Zn]=4:2:3 to 4.1 and values ​​near this. Near values ​​include, for example, an atomic ratio of [In]:[M]:[Zn]=5:3:4. The oxide semiconductor having the atomic ratio shown in region B is an excellent oxide semiconductor with particularly high crystallinity and high carrier mobility.

[0099] Furthermore, the conditions under which oxide semiconductors form a layered structure are not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. On the other hand, even if the atomic ratio is the same, a layered structure may or may not be formed depending on the formation conditions. Therefore, the illustrated region represents the atomic ratio in which the oxide semiconductor has a layered structure, and the boundary between region A to region C is not strictly defined.

[0100] Next, the configuration of using oxide semiconductors in transistors will be explained.

[0101] Furthermore, by using oxide semiconductors in transistors, carrier scattering at grain boundaries can be reduced, thereby enabling the realization of transistors with high field-effect mobility. Additionally, highly reliable transistors can be realized.

[0102] In addition, it is desirable to use an oxide semiconductor with a low carrier density in the channel region of the transistor. For example, the carrier density of an oxide semiconductor is 8×10 11 / cm 3 Less than, preferably 1×10 11 / cm 3 Less than, more preferably 1×10 10 / cm 3 Less than and 1×10 -9 / cm 3 It is good to do it this way.

[0103] Furthermore, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors can lower carrier density because they have fewer carrier sources. Additionally, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors may also have a lower trap level density because they have a low defect level density.

[0104] Furthermore, charges trapped in the trap levels of oxide semiconductors take a long time to dissipate, sometimes acting like fixed charges. Therefore, transistors in which the channel region is formed in oxide semiconductors with a high trap level density may experience unstable electrical characteristics.

[0105] Therefore, to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration within the oxide semiconductor in the channel region. Furthermore, to reduce the impurity concentration within the oxide semiconductor, it is desirable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0106] Here, the influence of each impurity in oxide semiconductors is explained.

[0107] When silicon or carbon, which are Group 14 elements, are present in an oxide semiconductor, defect levels are formed. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentrations obtained by Secondary Ion Mass Spectrometry (SIMS)) are 2×10⁻⁶ 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 The following applies.

[0108] Furthermore, if alkali metals or alkaline earth metals are included in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, transistors using an oxide semiconductor containing alkali metals or alkaline earth metals in the channel region are prone to normally-on characteristics. Consequently, it is desirable to reduce the concentration of alkali metals or alkaline earth metals within the oxide semiconductor in the channel region. Specifically, the concentration of alkali metals or alkaline earth metals within the oxide semiconductor obtained by SIMS is 1×10⁻⁶ 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 The following applies.

[0109] Furthermore, when nitrogen is included in an oxide semiconductor, the generation of electron carriers increases carrier density, making it prone to n-type transformation. As a result, transistors having a channel region containing an oxide semiconductor containing nitrogen are prone to normaly-on characteristics. Therefore, it is desirable to reduce the nitrogen content in the oxide semiconductor of the channel region as much as possible. For example, the nitrogen concentration in the oxide semiconductor is 5×10⁻⁶ in SIMS. 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 The following applies.

[0110] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, which can lead to the formation of oxygen vacancies. When hydrogen enters these oxygen vacancies, electron carriers may be generated. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electron carriers. Therefore, transistors having an oxide semiconductor containing hydrogen in the channel region are prone to exhibiting normaly-on characteristics. Consequently, it is desirable to reduce the hydrogen content in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration obtained by SIMS in the oxide semiconductor of the channel region is 1×10⁻⁶ 20 atoms / cm 3 Less than, preferably 1×10 19 atoms / cm 3 Less than, more preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 Make it less than.

[0111] By using an oxide semiconductor with sufficiently reduced impurities in the channel region of a transistor, stable electrical characteristics can be imparted.

[0112] In addition, it is desirable for the oxide semiconductor film to have an energy gap of 2 eV or more, 2.5 eV or more, or 3 eV or more.

[0113] In addition, the thickness of the oxide semiconductor film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 60 nm or less.

[0114] In addition, when the oxide semiconductor film is an In-M-Zn oxide, the atomic ratio of metal elements in the sputtering target used to deposit the In-M-Zn oxide is preferably In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7, etc.

[0115] In addition, the atomic ratio of metal elements in the deposited oxide semiconductor film may vary by approximately ±40% of the atomic ratio of metal elements included in the sputtering target. For example, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1, the atomic ratio of the deposited oxide semiconductor film may be approximately In:Ga:Zn = 4:2:3. Furthermore, when using a sputtering target with an atomic ratio of In:Ga:Zn = 5:1:7, the atomic ratio of the formed oxide semiconductor film may be approximately In:Ga:Zn = 5:1:6.

[0116] Meanwhile, the source region (108s) and the drain region (108d) are in contact with the insulating film (116). As the source region (108s) and the drain region (108d) are in contact with the insulating film (116), at least one of hydrogen and nitrogen is added from the insulating film (116) to the source region (108s) and the drain region (108d), thereby increasing the carrier density.

[0117] In addition, the oxide semiconductor film (108) is not limited to the structure described above, and it is preferable to use a material of an appropriate composition according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, in order to obtain the required semiconductor characteristics of the transistor, it is desirable to appropriately adjust the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the oxide semiconductor film.

[0118] Additionally, the oxide semiconductor film (108) may have a non-single crystal structure. A non-single crystal structure includes, for example, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In a non-single crystal structure, the amorphous structure has the highest defect level density, and the CAAC-OS has the lowest defect level density.

[0119] In addition, the oxide semiconductor film (108) may be a single layer having two or more of the amorphous structure region, microcrystalline structure region, polycrystalline structure region, CAAC-OS region, and single crystal structure region, or a stacked structure of the film.

[0120] Additionally, in the oxide semiconductor film (108), the crystallinity of the channel region (108i) and the source region (108s) and drain region (108d) may differ. Specifically, in the oxide semiconductor film (108), the source region (108s) and drain region (108d) may have lower crystallinity than the channel region (108i). This is because if impurity elements are added to the source region (108s) and drain region (108d), damage occurs to the source region (108s) and drain region (108d), causing a decrease in crystallinity.

[0121] Additionally, the oxide semiconductor film (112) can be formed using the same material and manufacturing method as the oxide semiconductor film (108) described above. For example, as the oxide semiconductor film (112), In oxide, In-Sn oxide, In-Zn oxide, In-Ga oxide, Zn oxide, Al-Zn oxide, or In-Ga-Zn oxide can be used. In particular, it is preferable to use In-Sn oxide or In-Ga-Zn oxide. Additionally, as the oxide semiconductor film (112), materials such as indium tin oxide (abbreviated: ITO) or silicon-containing indium tin oxide (abbreviated: ITSO) can be used. Furthermore, manufacturing costs can be reduced by configuring the oxide semiconductor film (112) and the oxide semiconductor film (108) to have the same metal element.

[0122] For example, when using In-M-Zn oxide as the oxide semiconductor film (112), it is preferable that the atomic ratio of the metal elements in the sputtering target used to deposit the In-M-Zn oxide has a region where In is greater than or equal to M. Examples of such atomic ratios of the metal elements in the sputtering target include In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7, and the vicinity thereof. Furthermore, the oxide semiconductor film (112) is not limited to the composition of the sputtering target. Additionally, the structure of the oxide semiconductor film (112) can be a single-layer structure or a stacked structure of two or more layers.

[0123] Additionally, as the oxide semiconductor film (112), an oxide semiconductor represented by In-Ga-Zn oxide can be used. The carrier density of this oxide semiconductor is increased by supplying at least one of nitrogen and hydrogen from the insulating film (116). In other words, the oxide semiconductor of the oxide semiconductor film (112) functions as an oxide conductor (OC). Therefore, this oxide semiconductor can be used as a gate electrode.

[0124] For example, in the case where the second gate electrode has a structure having an oxide semiconductor film (112) and a conductive film (114), a stacked structure is preferred in which the oxide conductor (OC) described above is used in the oxide semiconductor film (112) and a metal film is used in the conductive film (114).

[0125] When using a stacked structure of an oxide semiconductor and a light-shielding metal film as the second gate electrode, it is suitable because the channel region (108i) formed below the oxide semiconductor film (112) can be shielded. Additionally, when using a stacked structure of an oxide semiconductor or oxide conductor (OC) and a light-shielding metal film as the oxide semiconductor film (112), the metal film (e.g., titanium film, tungsten film, etc.) is formed on the oxide semiconductor or oxide conductor (OC) so that the constituent elements within the metal film diffuse toward the oxide semiconductor or oxide conductor (OC) side to reduce resistance, or the resistance is reduced due to damage during the formation of the metal film (e.g., sputtering damage), or oxygen within the oxide semiconductor or oxide conductor (OC) diffuses into the metal film to form oxygen vacancies, thereby reducing resistance.

[0126] ≪Insulating film functioning as the first gate insulating film≫

[0127] The insulating film (104) can be formed by appropriately using methods such as sputtering, CVD, deposition, pulsed laser deposition (PLD), printing, or coating. Additionally, the insulating film (104) can be formed by, for example, by forming a single layer or stacking an oxide insulating film and a nitride insulating film. Furthermore, in order to improve the interface characteristics with the oxide semiconductor film (108), it is preferable that at least the region of the insulating film (104) that contacts the oxide semiconductor film (108) be formed as an oxide insulating film. Additionally, by using an oxide insulating film that releases oxygen upon heating as the insulating film (104), oxygen contained in the insulating film (104) can be transferred to the oxide semiconductor film (108) through heat treatment.

[0128] The thickness of the insulating film (104) can be 50 nm or more, or 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By making the insulating film (104) thicker, the amount of oxygen released from the insulating film (104) can be increased, and the oxygen deficiency included in the interface level at the interface between the insulating film (104) and the oxide semiconductor film (108), and in the channel region (108i) of the oxide semiconductor film (108) can be reduced.

[0129] As an insulating film (104), for example, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide, etc., may be used, and can be provided as a single layer or a stack. In this embodiment, a stacked structure of a silicon nitride film and a silicon nitride oxide film is used as the insulating film (104). In this way, by making the insulating film (104) into a stacked structure, using a silicon nitride film on the lower side and a silicon nitride oxide film on the upper side, oxygen can be efficiently introduced into the oxide semiconductor film (108).

[0130] In addition, in the present specification, etc., silicon nitride oxide refers to a composition in which the oxygen content is higher than the nitrogen content, and preferably, it refers to a composition in which oxygen is 55 atomic% or more and 65 atomic% or less, nitrogen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. Silicon nitride oxide refers to a composition in which the nitrogen content is higher than the oxygen content, and preferably, it refers to a composition in which nitrogen is 55 atomic% or more and 65 atomic% or less, oxygen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less.

[0131] In addition, the region in the insulating film (104) that is in contact with at least the oxide semiconductor film (108) is preferably an oxide insulating film, and it is more preferable to have a region (oxygen excess region) containing oxygen in excess of the stoichiometric composition. In other words, the insulating film (104) is an insulating film capable of releasing oxygen. Furthermore, to provide an excess oxygen region in the insulating film (104), it is preferable to form the insulating film (104) under an oxygen atmosphere, for example. Alternatively, oxygen may be added to the insulating film (104) after deposition. A method for adding oxygen to the insulating film (104) after deposition will be described later.

[0132] In addition, as an insulating film (104), hafnium silicate (HfSiO₂) x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-added hafnium aluminate (HfAl x O y N zHigh-k materials such as hafnium oxide and yttrium oxide can be suitably used. Materials containing hafnium or yttrium have a higher dielectric constant compared to silicon oxide or silicon nitride oxide. Therefore, by using the high-k material in the insulating film (104), the film thickness can be increased compared to when a silicon oxide film is used, so the leakage current caused by tunnel current can be reduced. In other words, a transistor with a small off-current can be realized. In addition, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to make a transistor with a small off-current, it is desirable to use hafnium oxide having a crystal structure. Examples of crystal structures include monoclinic and cubic systems. However, one embodiment of the present invention is not limited to these.

[0133] In addition, in this embodiment, as an insulating film (104), a silicon nitride film is formed on the conductive film (106) side and a silicon oxide film is formed on the oxide semiconductor film (108) side by stacking. The silicon nitride film has a higher dielectric constant than the silicon oxide film, and the film thickness required to obtain a capacitance of the same degree as that of the silicon oxide film is large. Therefore, by including a silicon nitride film as the first gate insulating film of the transistor (100), the first gate insulating film can be physically made thicker. Accordingly, by suppressing the decrease in the dielectric breakdown voltage of the transistor (100) and further improving the dielectric breakdown voltage, electrostatic breakdown of the transistor (100) can be suppressed.

[0134] ≪Insulating film functioning as a second gate insulating film≫

[0135] The insulating film (110) functions as a gate insulating film of the transistor (100). Additionally, the insulating film (110) has the function of supplying oxygen to the oxide semiconductor film (108), particularly the channel region (108i). For example, the insulating film (110) can be formed by forming a single layer or a stack of an oxide insulating film or a nitride insulating film. Furthermore, in order to improve the interface characteristics with the oxide semiconductor film (108), it is preferable that the region of the insulating film (110) in contact with the oxide semiconductor film (108) be formed using at least an oxide insulating film. For example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, etc., can be used as the insulating film (110).

[0136] In addition, the thickness of the insulating film (110) can be 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less, or 10 nm or more and 250 nm or less.

[0137] In addition, it is desirable for the insulating film (110) to have few defects, and typically, it is desirable for the signal observed by Electron Spin Resonance (ESR) to be small. For example, the E' center observed when the g value is 2.001 can be cited as the signal described above. In addition, the E' center is attributed to the dangling bonds of silicon. As for the insulating film (110), the spin density attributed to the E' center is 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3 It is preferable to use a silicon oxide film or a silicon nitride film of the following quality.

[0138] In addition, in addition to the signal described above, a signal attributable to nitrogen dioxide (NO2) may be observed in the insulating film (110). The signal is divided into three signals by the nuclear spin of N, and each is observed with a g value of 2.037 or higher and 2.039 or lower (first signal), a g value of 2.001 or higher and 2.003 or lower (second signal), and a g value of 1.964 or higher and 1.966 or lower (third signal).

[0139] For example, as an insulating film (110), the spin density attributable to nitrogen dioxide (NO2) is 1×10 17 spins / cm 3 1×10 18 spins / cm 3 It is suitable to use an insulating film of less than [amount].

[0140] In addition, nitrogen oxides (NO₂) including nitrogen dioxide (NO₂) x ) forms a level within the insulating film (110). This level is located within the energy gap of the oxide semiconductor film (108). Therefore, nitrogen oxide (NO x When the level diffuses to the interface between the insulating film (110) and the oxide semiconductor film (108), the level may trap electrons on the insulating film (110) side. As a result, the trapped electrons remain near the interface between the insulating film (110) and the oxide semiconductor film (108), thereby shifting the threshold voltage of the transistor in the positive direction. Therefore, if a film with a low nitrogen oxide content is used as the insulating film (110), the shift of the threshold voltage of the transistor can be reduced.

[0141] Nitrogen oxides (NO₂) x For example, a silicon nitride film can be used as an insulating film with a low emission of ). The silicon nitride film is subjected to thermal desorption spectroscopy (TDS) with nitrogen oxide (NO₂). xIt is a membrane where the release of ammonia is greater than the release of ), and typically, the ammonia release is 1×10 18 cm -3 At least 5×10 19 cm -3 The above amount of ammonia release is the total amount in the range of a temperature of heat treatment in TDS of 50°C or higher and 650°C or lower, or 50°C or higher and 550°C or lower.

[0142] Nitrogen oxides (NO₂) x Since ) reacts with ammonia and oxygen during heat treatment, using an insulating film with a high ammonia emission rate results in nitrogen oxides (NO x ) is reduced.

[0143] In addition, when the insulating film (110) is analyzed by SIMS, the nitrogen concentration in the film is 6×10 20 atoms / cm 3 It is desirable that it be less than or equal to this.

[0144] In addition, hafnium silicate (HfSiO₂) is used as an insulating film (110). x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-added hafnium aluminate (HfAl x O y N z High-k materials such as hafnium oxide may also be used. By using the above high-k materials, gate leakage of the transistor can be reduced.

[0145] In addition, the insulating film (110) may be formed using a CVD method with an organic silane gas. As the organic silane gas, silicon-containing compounds such as ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), and trisdimethylaminosilane (SiH(N(CH3)2)3) may be used. By using a CVD method with an organic silane gas, an insulating film (110) with high coverage can be formed.

[0146] ≪The Third Insulating Layer≫

[0147] The insulating film (116) has at least one of nitrogen and hydrogen. As the insulating film (116), a nitride insulating film may be used as an example. As the nitride insulating film, for example, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc., can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The hydrogen concentration contained in the insulating film (116) is 1×10⁻⁶ 22 atoms / cm 3 Ideally, the above is desirable. Additionally, the insulating film (116) is in contact with the source region (108s) and drain region (108d) of the oxide semiconductor film (108). Additionally, the insulating film (116) has a region in contact with the oxide semiconductor film (112). Thus, the hydrogen concentration in the source region (108s), drain region (108d), and oxide semiconductor film (112) in contact with the insulating film (116) is increased, thereby increasing the carrier density of the source region (108s), drain region (108d), and oxide semiconductor film (112). Furthermore, the source region (108s), drain region (108d), and oxide semiconductor film (112) may each have a region in which the hydrogen concentration within the film is the same due to contact with the insulating film (116).

[0148] ≪Fourth Insulating Layer≫

[0149] As an insulating film (118), an oxide insulating film or a nitride insulating film can be formed as a single layer or a stack. For example, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide can be used as the insulating film (118), and it can be provided as a single layer or a stack.

[0150] In addition, it is preferable that the insulating film (118) be a film that functions as a barrier film for hydrogen, water, etc. from the outside.

[0151] The thickness of the insulating film (118) can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0152] ≪First gate electrode and conductive film functioning as a pair of electrodes≫

[0153] The conductive film (106) and the conductive film (120s, 120d) can be formed using a sputtering method, a vacuum deposition method, a pulsed laser deposition (PLD) method, a thermal CVD method, etc. Additionally, the conductive film (106) and the conductive film (120s, 120d) can be formed using, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy having the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal element. Additionally, a metal element selected from either manganese and zirconium or a plurality thereof may be used. Furthermore, the conductive film (106) and the conductive film (120s, 120d) may be formed as a single-layer structure or as a stacked structure of two or more layers. For example, there are a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon, and a three-layer structure in which a copper film is laminated on a copper film containing manganese and a copper film containing manganese is further formed thereon. In addition, an alloy film or nitride film may be used in combination with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium on aluminum.

[0154] In particular, it is suitable to use a material containing copper as the conductive film (106) and the conductive film (120s, 120d). Using a material containing copper for the conductive film (106, 120s, 120d) can lower the resistance. For example, even when a large-area substrate is used as the substrate (102), signal delay, etc., can be suppressed.

[0155] Additionally, the conductive film (106) and the conductive film (120s, 120d) may be made of a transparent conductive material such as an oxide containing indium and tin (abbreviated as ITO), an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing indium, gallium, and zinc, or an oxide containing silicon, indium, and tin (abbreviated as ITSO). Additionally, the conductive material having transparency may be made into a stacked structure of the metal element.

[0156] The thickness of the conductive film (106) and the conductive film (120s, 120d) can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0157] ≪Conducting film (114) functioning as a second gate electrode≫

[0158] The conductive film (114) functioning as the second gate electrode can be formed using the same material and manufacturing method as the conductive film (106) functioning as the first gate electrode described above and the conductive films (120s, 120d) functioning as a pair of electrodes. Alternatively, it may be a stacked structure thereof.

[0159] Additionally, it is desirable that the conductive film (114) has a low function of supplying at least one of nitrogen and hydrogen. Additionally, it is desirable that the conductive film (114) has a low function of permeating at least one of nitrogen and hydrogen. Specifically, for example, copper, molybdenum, tungsten, titanium, and tantalum, or their nitrides are preferred. Nitrides having nitrogen and metal, such as molybdenum nitride, tantalum nitride, and titanium nitride, are preferred because they have high conductivity, high barrier properties against copper or hydrogen, and are stable.

[0160] ≪Circuit Board≫

[0161] As for the substrate (102), various substrates can be used and are not particularly limited. Examples of substrates include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, ceramic substrates, sapphire substrates, plastic substrates, metal substrates, stainless steel substrates, substrates having stainless steel foil, tungsten substrates, substrates having tungsten foil, flexible substrates, bonding films, paper containing fibrous materials, or base material films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, bonding films, and base films include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or, as an example, there are synthetic resins such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Alternatively, examples include polyamide, polyimide, aramid, epoxy, inorganic deposited film, or paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, it is possible to manufacture transistors with low variation in characteristics, size, or shape, high current capability, and small size. By constructing circuits using such transistors, it is possible to achieve low power consumption or high integration of the circuit.

[0162] In addition, when a glass substrate is used as the substrate (102), a large-area substrate such as the 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm), 9th generation (2400mm × 2800mm), and 10th generation (2950mm × 3400mm) can be used to produce a large-sized display device.

[0163] In addition, a flexible substrate may be used as the substrate (102), and a transistor may be formed directly on the flexible substrate. Alternatively, a stripping layer may be provided between the substrate (102) and the transistor. The stripping layer can be used to transfer the semiconductor device to another substrate after it has been partially or entirely completed on the substrate (102) and separated from the substrate (102). At this time, the transistor may be transferred to a substrate with poor heat resistance or a flexible substrate. In addition, the stripping layer described above may be configured with, for example, a stacked structure of an inorganic film such as a tungsten film and a silicon oxide film, or a structure in which a resin film such as polyimide is formed on the substrate.

[0164] Examples of substrates on which a transistor is formed include, in addition to the substrate capable of forming the aforementioned transistor, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, fabric substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupro, rayon, recycled polyester), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are resistant to breakage, impart heat resistance, reduce weight, or make them thin.

[0165] <Configuration Examples 2 to 6 of Semiconductor Devices>

[0166] Next, configurations different from the semiconductor devices shown in (A), (B), and (C) of FIG. 1 will be described with reference to FIG. 2 to 7.

[0167] ≪Example of Semiconductor Device Configuration 2≫

[0168] Figure 2 (A) is a top view of a transistor (100A), Figure 2 (B) is a cross-sectional view between X1 and X2 of Figure 2 (A), and Figure 2 (C) is a cross-sectional view between Y1 and Y2 of Figure 2 (A).

[0169] The transistor (100A) shown in (A), (B), and (C) of FIG. 2 has a different shape of oxide semiconductor film (112) and conductive film (114) from the transistor (100) described above. Specifically, the lower end of the oxide semiconductor film (112) of the transistor (100A) is formed inwardly compared to the upper end of the insulating film (110). In other words, the side end of the insulating film (110) is located outwardly compared to the side end of the oxide semiconductor film (112).

[0170] For example, the oxide semiconductor film (112), the conductive film (114), and the insulating film (110) can be processed with the same mask, and the oxide semiconductor film (112) and the conductive film (114) can be processed by a wet etching method, and the insulating film (110) can be processed by a dry etching method, respectively, to obtain the structure described above.

[0171] Additionally, there are cases where a region (108f) is formed within the oxide semiconductor film (108) by making the oxide semiconductor film (112) and the conductive film (114) have the structure described above. The region (108f) is formed between the channel region (108i) and the source region (108s), and between the channel region (108i) and the drain region (108d).

[0172] The region (108f) functions as either a high-resistance region or a low-resistance region. A high-resistance region is a region that has the same resistance as the channel region (108i) and where the oxide semiconductor film (112) and the conductive film (114) functioning as the gate electrode do not overlap. When the region (108f) is a high-resistance region, the region (108f) functions as a so-called offset region. When the region (108f) functions as an offset region, in order to suppress the reduction of the on-current of the transistor (100A), it is preferable to make the region (108f) 1 μm or less in the channel length (L) direction.

[0173] Additionally, the low-resistance region is a region that has lower resistance than the channel region (108i) and higher resistance than the source region (108s) and the drain region (108d). When the region (108f) is a low-resistance region, the region (108f) functions as a so-called LDD (Lightly Doped Drain) region. When the region (108f) functions as an LDD region, the electric field in the drain region can be relaxed, thereby reducing fluctuations in the threshold voltage of the transistor caused by the electric field in the drain region.

[0174] Additionally, when the region (108f) is a low-resistance region, for example, at least one of hydrogen and nitrogen is supplied to the region (108f) from the insulating film (116), or the insulating film (110), the oxide semiconductor film (112), and the conductive film (114) are used as a mask, and an impurity element is added from the top of the conductive film (114), thereby forming the impurity through the insulating film (110) to the oxide semiconductor film (108).

[0175] ≪Example of Semiconductor Device Configuration 3≫

[0176] Next, variations of the semiconductor device shown in (A), (B), and (C) of FIG. 2 will be described with reference to (A) and (B) of FIG. 3.

[0177] Figures 3 (A) and (B) are cross-sectional views of a transistor (100B). Since the top view of the transistor (100B) is the same as the transistor (100A) shown in Figure 2 (A), the explanation will be based on Figure 2 (A). Figure 3 (A) is a cross-sectional view between the dotted line X1-X2 of Figure 2 (A), and Figure 3 (B) is a cross-sectional view between the dotted line Y1-Y2 of Figure 2 (A).

[0178] The transistor (100B) differs from the transistor (100A) described above in that it is provided with an insulating film (122) that functions as a flattening insulating film. The rest of the configuration is the same as that of the transistor (100A) described above and exhibits the same effect.

[0179] The insulating film (122) has the function of flattening irregularities caused by transistors, etc. As the insulating film (122), it is preferable that it be insulating and is formed using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, etc. Examples of the organic material include a photosensitive resin material such as acrylic resin or polyimide resin.

[0180] In addition, in (A) and (B) of FIG. 3, the shape of the opening of the insulating film (122) is made smaller than the opening (141s, 141d), but is not limited thereto and may be made, for example, a shape similar to the opening (141s, 141d) or a shape larger than the opening (141s, 141d).

[0181] In addition, although (A) and (B) of FIG. 3 illustrate a configuration in which a conductive film (120s, 120d) is provided on an insulating film (122), it is not limited thereto, and for example, a configuration in which a conductive film (120s, 120d) is provided on an insulating film (118) and an insulating film (122) is provided on the conductive film (120s, 120d) may be provided.

[0182] ≪Example of Semiconductor Device Configuration 4≫

[0183] Next, variations of the semiconductor device illustrated in (A), (B), and (C) of FIG. 1 will be described with reference to FIG. 4 and FIG. 5.

[0184] Figures 4 (A) and (B) are cross-sectional views of a transistor (100C). Since the top view of the transistor (100C) is the same as the transistor (100) shown in Figure 1 (A), the explanation will be based on Figure 1 (A). Figure 4 (A) is a cross-sectional view between the dotted line X1-X2 in Figure 1 (A), and Figure 4 (B) is a cross-sectional view between the dotted line Y1-Y2 in Figure 1 (A).

[0185] The transistor (100C) has a different shape of the insulating film (110) compared to the transistor (100) described above. The rest of the configuration is the same as that of the transistor (100) described above and exhibits the same effect.

[0186] The insulating film (110) of the transistor (100C) is located inward from the oxide semiconductor film (112). In other words, the side of the insulating film (110) is located inward from the bottom of the oxide semiconductor film (112). For example, after processing the oxide semiconductor film (112) and the conductive film (114), the insulating film (110) can be side-etched by wet etching using an etchant, etc., to achieve the configuration shown in (A) and (B) of FIG. 4. In addition, by making the insulating film (110) into the structure described above, a hollow region (147) is formed on the underside of the oxide semiconductor film (112).

[0187] The hollow region (147) contains air and functions as part of the gate insulating film. Additionally, the relative permittivity of the hollow region (147) is equal to that of air and is approximately 1. Therefore, when voltage is applied to the oxide semiconductor film (112) that functions as the gate electrode by structuring the transistor (100C), the voltage supplied to the channel region (108i) below the hollow region (147) becomes lower than the voltage supplied to the channel region (108i) below the insulating film (110). Thus, the channel region (108i) below the hollow region (147) effectively functions as an overlap region (also called the Lov region). Additionally, the Lov region is a region that overlaps with the oxide semiconductor film (112) that functions as the gate electrode and has lower resistance than the channel region (108i).

[0188] Figures 5 (A) and (B) are cross-sectional views of a transistor (100D). Since the top view of the transistor (100D) is the same as the transistor (100) shown in Figure 1 (A), the explanation will be based on Figure 1 (A). Figure 5 (A) is a cross-sectional view between the dotted line X1-X2 in Figure 1 (A), and Figure 5 (B) is a cross-sectional view between the dotted line Y1-Y2 in Figure 1 (A).

[0189] The transistor (100D) differs from the transistor (100) described above in the shape of the insulating film (110) and the insulating film (116). The rest of the configuration is the same as that of the transistor (100) described above and exhibits the same effect.

[0190] The insulating film (110) of the transistor (100D) is located inward from the oxide semiconductor film (112) and the conductive film (114). In other words, the side of the insulating film (110) is located inward from the bottom of the oxide semiconductor film (112). For example, after processing the oxide semiconductor film (112) and the conductive film (114), the insulating film (110) can be side-etched by wet etching using an etchant, etc., to achieve the configuration shown in (A) and (B) of FIG. 5. In addition, after the insulating film (110) is made into the structure described above, the insulating film (116) is formed so that the insulating film (116) extends below the oxide semiconductor film (112) and comes into contact with the oxide semiconductor film (108) located below the oxide semiconductor film (112).

[0191] With the above configuration, the source region (108s) and the drain region (108d) are located inward from the bottom portion of the oxide semiconductor film (112). Accordingly, the transistor (100D) has an Lov region.

[0192] By having a structure that has an Lov region, such as transistors (100C) and (100D), a high resistance region is not formed between the channel region (108i), the source region (108s), and the drain region (108d), so the on-current of the transistor can be increased.

[0193] ≪Example of Semiconductor Device Configuration 5≫

[0194] Next, variations of the semiconductor device illustrated in (A), (B), and (C) of FIG. 1 will be described with reference to FIG. 6 and FIG. 7.

[0195] Figures 6 (A) and (B) are cross-sectional views of a transistor (100E). Since the top view of the transistor (100E) is the same as the transistor (100) shown in Figure 1 (A), the explanation will be based on Figure 1 (A). Figure 6 (A) is a cross-sectional view between the dotted line X1-X2 in Figure 1 (A), and Figure 6 (B) is a cross-sectional view between the dotted line Y1-Y2 in Figure 1 (A).

[0196] The transistor (100E) has a different structure of oxide semiconductor film (108) from the transistor (100) described above. Other than this, the configuration is the same as that of the transistor (100) described above and exhibits the same effect.

[0197] The oxide semiconductor film (108) of the transistor (100E) has an oxide semiconductor film (108_1) on an insulating film (116), an oxide semiconductor film (108_2) on an oxide semiconductor film (108_1), and an oxide semiconductor film (108_3) on an oxide semiconductor film (108_2).

[0198] In addition, the channel region (108i), source region (108s), and drain region (108d) are each three-layer stacked structures of oxide semiconductor film (108_1), oxide semiconductor film (108_2), and oxide semiconductor film (108_3).

[0199] Figures 7 (A) and (B) are cross-sectional views of a transistor (100F). Since the top view of the transistor (100F) is the same as the transistor (100) shown in Figure 1 (A), the explanation will be based on Figure 1 (A). Figure 7 (A) is a cross-sectional view between the dotted line X1-X2 in Figure 1 (A), and Figure 7 (B) is a cross-sectional view between the dotted line Y1-Y2 in Figure 1 (A).

[0200] The transistor (100F) has a different structure of oxide semiconductor film (108) from the transistor (100) described above. The rest of the configuration is the same as that of the transistor (100) described above and exhibits the same effect.

[0201] The oxide semiconductor film (108) of the transistor (100F) has an oxide semiconductor film (108_2) on the insulating film (116) and an oxide semiconductor film (108_3) on the oxide semiconductor film (108_2).

[0202] Additionally, the channel region (108i), source region (108s), and drain region (108d) are each two-layer stacked structures of oxide semiconductor film (108_2) and oxide semiconductor film (108_3).

[0203] Additionally, the transistor (100F) has a stacked structure of oxide semiconductor film (108_2) and oxide semiconductor film (108_3) in the channel region (108i).

[0204] ≪Band Structure≫

[0205] Here, the case in which the oxide semiconductor has a two-layer or three-layer structure is described. The band diagram of the insulator in contact with the stacked structure of oxide semiconductor S1, oxide semiconductor S2, and oxide semiconductor S3, and the band diagram of the insulator in contact with the stacked structure of oxide semiconductor S2 and oxide semiconductor S3 are described with reference to FIG. 16. In addition, in FIG. 16, the oxide semiconductors having oxide semiconductor films (108_1), oxide semiconductor films (108_2), and oxide semiconductor films (108_3) are represented as oxide semiconductor (S1), oxide semiconductor (S2), and oxide semiconductor (S3), and the insulators having insulating films (104) and insulating films (110) are represented as insulators (I1) and insulators (I2).

[0206] FIG. 16 (A) is an example of a band diagram in the film thickness direction of a stacked structure having an insulator (I1), an oxide semiconductor (S1), an oxide semiconductor (S2), an oxide semiconductor (S3), and an insulator (I2). FIG. 16 (B) is also an example of a band diagram in the film thickness direction of a stacked structure having an insulator (I1), an oxide semiconductor (S2), an oxide semiconductor (S3), and an insulator (I2). Additionally, for ease of understanding, the band diagram shows the energy level (Ec) at the bottom of the conduction band of the insulator (I1), the oxide semiconductor (S1), the oxide semiconductor (S2), the oxide semiconductor (S3), and the insulator (I2).

[0207] It is preferable that the oxide semiconductor (S1) and the oxide semiconductor (S3) have energy levels at the bottom of the conduction band that are closer to the vacuum level than that of the oxide semiconductor (S2), and, for example, that the difference between the energy level at the bottom of the conduction band of the oxide semiconductor (S2) and the energy level at the bottom of the conduction band of the oxide semiconductor (S1) and the oxide semiconductor (S3) is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less. That is, it is preferable that the difference between the electron affinity of the oxide semiconductor (S1) and the oxide semiconductor (S3) and the electron affinity of the oxide semiconductor (S2) is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less.

[0208] As shown in FIG. 16 (A) and FIG. 16 (B), the energy levels at the bottom of the conduction band in the oxide semiconductor (S1), oxide semiconductor (S2), and oxide semiconductor (S3) change gradually. In other words, it can be said that they change continuously or are continuously connected. To obtain such a band diagram, it is desirable to lower the defect level density of the mixed layer formed at the interface between the oxide semiconductor (S1) and the oxide semiconductor (S2), or at the interface between the oxide semiconductor (S2) and the oxide semiconductor (S3).

[0209] Specifically, by having an oxide semiconductor (S1) and an oxide semiconductor (S2), and an oxide semiconductor (S2) and an oxide semiconductor (S3) have a common element other than oxygen (by making it the main component), a mixed layer with a low defect level density can be formed. For example, if the oxide semiconductor (S2) is an In-Ga-Zn oxide semiconductor, it is preferable to use an In-Ga-Zn oxide semiconductor, a Ga-Zn oxide semiconductor, gallium oxide, etc., as the oxide semiconductor (S1) and the oxide semiconductor (S3).

[0210] At this time, the main path of the carrier becomes the oxide semiconductor (S2). Since the defect level density at the interface between the oxide semiconductor (S1) and the oxide semiconductor (S2) and at the interface between the oxide semiconductor (S2) and the oxide semiconductor (S3) can be lowered, the influence of carrier conduction due to interface scattering is reduced, and a high on-current can be obtained.

[0211] When an electron is captured at a trap level, the captured electron acts like a fixed charge, causing the threshold voltage of the transistor to shift in the positive direction. By providing an oxide semiconductor (S1) and an oxide semiconductor (S3), the trap level can be moved away from the oxide semiconductor (S2). With this configuration, the threshold voltage of the transistor can be prevented from shifting in the positive direction.

[0212] The oxide semiconductor (S1) and oxide semiconductor (S3) use materials with sufficiently low conductivity compared to the oxide semiconductor (S2). At this time, the oxide semiconductor (S2), the interface between the oxide semiconductor (S2) and the oxide semiconductor (S1), and the interface between the oxide semiconductor (S2) and the oxide semiconductor (S3) mainly function as channel regions. For example, for the oxide semiconductor (S1) and the oxide semiconductor (S3), it is preferable to use an oxide semiconductor with an atomic ratio represented by region C, where the insulation is high, in (C) of FIG. 14. Additionally, region (C) shown in (C) of FIG. 14 represents an atomic ratio of [In]:[M]:[Zn]=0:1:0 or a value near it.

[0213] In particular, when using an oxide semiconductor with an atomic ratio represented by region A in the oxide semiconductor (S2), it is preferable to use an oxide semiconductor in which [M] / [In] is 1 or more, preferably 2 or more, for the oxide semiconductor (S1) and oxide semiconductor (S3). Additionally, it is suitable to use an oxide semiconductor in which [M] / ([Zn]+[In]) is 1 or more, which can obtain sufficiently high insulation as the oxide semiconductor (S3).

[0214] <Method for Manufacturing a Semiconductor Device 1>

[0215] Next, an example of a method for manufacturing a transistor (100) illustrated in FIG. 1 will be described with reference to FIG. 8 to FIG. 11. FIG. 8 to FIG. 11 are cross-sectional views in the channel length (L) direction and channel width (W) direction illustrating a method for manufacturing a transistor (100).

[0216] First, a conductive film (106) is formed on a substrate (102), and then, the conductive film (106) is formed by processing the conductive film into an island shape (see (A) in FIG. 8).

[0217] As for the conductive film (106), it can be formed by appropriately using a sputtering method, CVD method, deposition method, pulsed laser deposition (PLD) method, printing method, coating method, etc. In this embodiment, a tungsten film with a thickness of 100 nm is formed as the conductive film (106) by a sputtering method. Alternatively, a tantalum nitride film with a thickness of 10 nm and a copper film with a thickness of 100 nm are formed by a sputtering method. Next, an insulating film (104) is formed on the substrate (102) and the conductive film (106), and an oxide semiconductor film is formed on the insulating film (104). After that, an oxide semiconductor film (107) is formed by processing the oxide conductive film into an island shape (see (B) in FIG. 8).

[0218] As an insulating film (104), it can be formed by appropriately using a sputtering method, CVD method, deposition method, pulsed laser deposition (PLD) method, printing method, coating method, etc. In this embodiment, as an insulating film (104), a silicon nitride film with a thickness of 400 nm and a silicon nitride film with a thickness of 50 nm are formed using a PECVD device.

[0219] Additionally, after forming the insulating film (104), oxygen may be added to the insulating film (104). Oxygen added to the insulating film (104) may include oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. Additionally, methods for adding oxygen may include ion doping, ion implantation, plasma treatment, etc. Furthermore, after forming a film that inhibits the escape of oxygen on the insulating film, oxygen may be added to the insulating film (104) through this film.

[0220] As a film that inhibits the escape of oxygen as described above, it can be formed using a conductive material such as a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, an alloy having the metal element described above as a component, an alloy combining the metal element described above, a metal nitride having the metal element described above, a metal oxide having the metal element described above, or a metal nitride oxide having the metal element described above.

[0221] In addition, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film (104) can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

[0222] The oxide semiconductor film (107) can be formed by sputtering, coating, pulsed laser deposition, laser ablation, thermal CVD, etc. Additionally, the oxide semiconductor film (107) can be formed by forming a mask on the oxide semiconductor film by a lithography process and then using this mask to etch a portion of the oxide semiconductor film. Alternatively, the oxide semiconductor film (107) may be formed directly by using a printing method to isolate the device.

[0223] When forming an oxide semiconductor film by the sputtering method, an RF power supply, an AC power supply, a DC power supply, etc., can be appropriately utilized as a power supply device for generating plasma. Furthermore, as the sputtering gas for forming the oxide semiconductor film, a noble gas (typically argon), oxygen, or a mixture of a noble gas and oxygen is appropriately used. Additionally, when using a mixture of a noble gas and oxygen, it is desirable to increase the ratio of oxygen to the noble gas.

[0224] In addition, when forming an oxide semiconductor film, for example, when using a sputtering method, crystallinity can be increased by forming the oxide semiconductor film at a substrate temperature of 150°C or higher and 750°C or lower, or 150°C or higher and 450°C or lower, or 200°C or higher and 350°C or lower.

[0225] In addition, in this embodiment, an oxide semiconductor film with a thickness of 40 nm is formed by using a sputtering device as the oxide semiconductor film (107) and using an In-Ga-Zn metal oxide (In:Ga:Zn=4:2:4.1[atomic ratio]) as the sputtering target.

[0226] In addition, after forming the oxide semiconductor film (107), heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film (107). The temperature of the heat treatment is typically 150°C or higher and below the deformation point of the substrate, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0227] The heat treatment may be performed in an inert gas atmosphere containing noble gases such as helium, neon, argon, xenon, or krypton, or nitrogen. Alternatively, the material may be heated in an oxygen atmosphere after being heated in an inert gas atmosphere. Furthermore, it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, etc. The treatment time should be between 3 minutes and 24 hours.

[0228] For this heat treatment, electric furnaces, RTA devices, etc., can be used. By using an RTA device, heat treatment can be performed at a temperature above the deformation point of the substrate for a short period of time. Therefore, the heat treatment time can be shortened.

[0229] The hydrogen concentration obtained by secondary ion mass spectrometry within the oxide semiconductor film by forming the film while heating the oxide semiconductor film, or by performing a heat treatment after forming the oxide semiconductor film, is 5×10 19 atoms / cm3 Less than or equal to, or 1×10 19 atoms / cm 3 Below, 5×10 18 atoms / cm 3 Less than or equal to, or 1×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Less than or equal to, or 1×10 16 atoms / cm 3 It can be done as follows.

[0230] Next, an insulating film (110_0) is formed on the insulating film (104) and the oxide semiconductor film (107) (see (C) in FIG. 8).

[0231] As an insulating film (110_0), a silicon oxide film or a silicon nitride film can be formed using the PECVD method. In this case, as the source gas, it is preferable to use a silicon-containing depositional gas and an oxidizing gas. Representative examples of silicon-containing depositional gases include silane, disilane, trisilane, and silane fluoride. Examples of oxidizing gases include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

[0232] In addition, as an insulating film (110_0), a silicon nitride film with a small amount of defects can be formed by using a PECVD method in which the flow rate of the oxidizing gas is greater than 20 times and less than 100 times, or between 40 times and 80 times, and the pressure inside the processing chamber is less than 100 Pa or 50 Pa or less.

[0233] In addition, a dense silicon oxide film or silicon oxide nitride film can be formed as an insulating film (110_0) by maintaining a substrate placed in a vacuum-evacuated processing chamber of a PECVD device at a temperature of 280°C or higher and 400°C or lower, introducing raw material gas into the processing chamber to set the pressure in the processing chamber to 20 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 250 Pa or lower, and supplying high-frequency power to an electrode provided in the processing chamber.

[0234] In addition, the insulating film (110_0) may be formed using a plasma CVD method using microwaves. Microwaves refer to a frequency range of 300 MHz to 300 GHz. Microwaves have a low electron temperature and low electron energy. Furthermore, regarding the supplied power, the proportion used for electron acceleration is small, and it can be used for the dissociation and ionization of more molecules, and a high-density plasma (high-density plasma) can be excited. Therefore, it is possible to form an insulating film (110_0) with less plasma damage to the film surface and deposits and fewer defects.

[0235] In addition, an insulating film (110_0) can be formed using a CVD method with an organic silane gas. As the organic silane gas, silicon-containing compounds such as ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), and trisdimethylaminosilane (SiH(N(CH3)2)3) can be used. By using a CVD method with an organic silane gas, an insulating film (110_0) with high coverage can be formed.

[0236] In this embodiment, a silicon nitride film with a thickness of 150 nm is formed using a PECVD device as an insulating film (110_0).

[0237] Next, an oxide semiconductor film (112_0) is formed on the insulating film (110_0). Additionally, when forming the oxide semiconductor film (112_0), oxygen is added from the oxide semiconductor film (112_0) into the insulating film (110_0) (see (D) in FIG. 8).

[0238] As a method for forming the oxide semiconductor film (112_0), it is preferable to use a sputtering method and to form it in an atmosphere containing oxygen gas during formation. By forming the oxide semiconductor film (112_0) in an atmosphere containing oxygen gas during formation, oxygen can be suitably added to the insulating film (110_0).

[0239] In addition, in (D) of FIG. 8, oxygen added to the insulating film (110_0) is schematically illustrated by an arrow. Also, as the oxide semiconductor film (112_0), a material such as the oxide semiconductor film (107) described above can be used.

[0240] In this embodiment, an oxide semiconductor film with a thickness of 20 nm is formed by using a sputtering device as the oxide semiconductor film (112_0) and using an In-Ga-Zn metal oxide (In:Ga:Zn=5:1:7[atomic ratio]) as the sputtering target.

[0241] Next, a mask is formed by lithography at a desired location on the oxide semiconductor film (112_0), and then an opening (143) leading to the conductive film (106) is formed by etching a portion of the oxide semiconductor film (112_0), the insulating film (110_0), and the insulating film (104) (see (A) in FIG. 9).

[0242] As a method for forming the opening (143), a wet etching method and / or a dry etching method may be appropriately used. In this embodiment, the opening (143) is formed using a dry etching method.

[0243] Next, a conductive film (114_0) is formed on the oxide semiconductor film (112_0) to cover the opening (143). By forming the conductive film (114_0) to cover the opening (143), the conductive film (106) and the conductive film (114_0) are electrically connected (see (B) in FIG. 9).

[0244] Next, a mask (140) is formed at a desired location on the conductive film (114_0) by a lithography process (see (C) in FIG. 9).

[0245] Next, the conductive film (114_0), the oxide semiconductor film (112_0), and the insulating film (110_0) are processed by etching on the mask (140), and then the mask (140) is removed to form the island-shaped conductive film (114), the island-shaped oxide semiconductor film (112), and the island-shaped insulating film (110) (see (D) in FIG. 9).

[0246] In this embodiment, the processing of the conductive film (114_0), oxide semiconductor film (112_0), and insulating film (110_0) is performed using a dry etching method.

[0247] Additionally, when processing the conductive film (114), the oxide semiconductor film (112), and the insulating film (110), there are cases where the thickness of the oxide semiconductor film (107) in the region where the conductive film (114) does not overlap is thinned. Or, when processing the conductive film (114), the oxide semiconductor film (112), and the insulating film (110), there are cases where the thickness of the insulating film (104) in the region where the oxide semiconductor film (107) does not overlap is thinned.

[0248] Next, an impurity element (145) is added on the insulating film (104), oxide semiconductor film (107), oxide semiconductor film (112), and conductive film (114) (see (A) of FIG. 10).

[0249] Methods for adding impurity elements (145) include ion doping, ion implantation, and plasma treatment. In the case of plasma treatment, impurity elements can be added by generating plasma in a gas atmosphere containing the impurity elements to be added and performing plasma treatment. As devices for generating the plasma, dry etching devices, ashing devices, plasma CVD devices, high-density plasma CVD devices, etc., can be used.

[0250] Additionally, as a source gas for the impurity element (145), one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, and noble gases may be used. Alternatively, one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with noble gases may be used. By adding the impurity element (145) to the oxide semiconductor film (107) and the oxide semiconductor film (112) using one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with noble gases, one or more of noble gases, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine may be added to the oxide semiconductor film (107) and the oxide semiconductor film (112).

[0251] Alternatively, after adding a noble gas, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2 may be added to the oxide semiconductor film (107) and the oxide semiconductor film (112).

[0252] Alternatively, after adding one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2, a noble gas may be added to the oxide semiconductor film (107) and the oxide semiconductor film (112).

[0253] The addition of impurity elements (145) can be controlled by appropriately setting injection conditions such as acceleration voltage and dose amount. For example, when adding argon by ion implantation, the acceleration voltage is 10 kV or more and 100 kV or less, and the dose amount is 1 × 10⁻⁶ 13 ions / cm 2 1×10 16 ions / cm 2 It is good to keep it below, for example, 1×10 14 ions / cm 2 It is best to do so. In addition, when adding phosphorus ions by ion implantation, the acceleration voltage is 30 kV and the dose is 1 × 10⁻⁶. 13 ions / cm 2 At least 5×10 16 ions / cm 2 It is good to keep it below, for example, 1×10 15 ions / cm 2 It is good to do it this way.

[0254] In addition, although the present embodiment is exemplified by a configuration in which the impurity element (145) is added after removing the mask (140), it is not limited thereto, and, for example, the addition of the impurity element (145) may be performed while leaving the mask (140) intact.

[0255] In addition, in this embodiment, an impurity argon is added to the oxide semiconductor film (107) and the oxide semiconductor film (112) using a doping device as an element (145). In addition, although this embodiment exemplifies a configuration in which argon is added as the impurity element (145), it is not limited thereto, and, for example, a configuration in which nitrogen is added may also be used. Furthermore, for example, a process of adding the impurity element (145) may not be performed.

[0256] Next, an insulating film (116) is formed on the insulating film (104), oxide semiconductor film (107), oxide semiconductor film (112), and conductive film (114). Additionally, by forming the insulating film (116), the oxide semiconductor film (107) in contact with the insulating film (116) becomes a source region (108s) and a drain region (108d). Furthermore, the oxide semiconductor film (107) not in contact with the insulating film (116), in other words, the oxide semiconductor film (107) in contact with the insulating film (110), becomes a channel region (108i). Thus, an oxide semiconductor film (108) having a channel region (108i), a source region (108s), and a drain region (108d) is formed (see (B) of FIG. 10).

[0257] As an insulating film (116), it can be formed by selecting a material that can be used for the insulating film (116). In this embodiment, a silicon nitride film with a thickness of 100 nm is formed as an insulating film (116) using a PECVD device.

[0258] By using a silicon nitride film as the insulating film (116), hydrogen within the silicon nitride film enters the oxide semiconductor film (112), source region (108s), and drain region (108d) in contact with the insulating film (116), thereby increasing the carrier density of the oxide semiconductor film (112), source region (108s), and drain region (108d).

[0259] Next, an insulating film (118) is formed on the insulating film (116) (see (C) in FIG. 10).

[0260] As an insulating film (118), it can be formed by selecting a material that can be used for the insulating film (118). In this embodiment, as an insulating film (118), a silicon nitride film with a thickness of 300 nm is formed using a PECVD device.

[0261] Next, a mask is formed by lithography at a desired location on the insulating film (118), and then a portion of the insulating film (118) and the insulating film (116) is etched to form an opening (141s) extending to a source region (108s) and an opening (141d) extending to a drain region (108d) (see (A) in FIG. 11).

[0262] As a method for etching the insulating film (118) and the insulating film (116), a wet etching method and / or a dry etching method may be appropriately used. In this embodiment, the insulating film (118) and the insulating film (116) are processed using a dry etching method.

[0263] Next, a conductive film (120) is formed on the insulating film (118) to cover the openings (141s, 141d) (see (B) in FIG. 11).

[0264] As for the conductive film (120), it can be formed by selecting a material that can be used for the conductive film (120s, 120d). In this embodiment, as the conductive film (120), a stacked film of a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm is formed using a sputtering device.

[0265] Next, a mask is formed at a desired location on the conductive film (120) by a lithography process, and then a conductive film (120s) and a conductive film (120d) are formed by etching a portion of the conductive film (120) (see (C) in FIG. 11).

[0266] As a processing method for the conductive film (120), a wet etching method and / or a dry etching method may be appropriately used. In this embodiment, the conductive film (120) is processed using a dry etching method to form a conductive film (120s, 120d).

[0267] A transistor (100) illustrated in FIG. 1 can be manufactured by the above process.

[0268] In addition, the film (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor (100) can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), or atomic layer deposition (ALD). Alternatively, it can be formed by coating or printing. As for the film deposition method, sputtering and plasma chemical vapor deposition (PECVD) are representative, but thermal CVD may also be used. An example of thermal CVD is organometallic chemical vapor deposition (MOCVD).

[0269] The thermal CVD method performs film deposition by maintaining the chamber at atmospheric or reduced pressure, simultaneously introducing source gases and an oxidizing agent into the chamber, and reacting them near or on the substrate to deposit the film onto the substrate. As such, since the thermal CVD method is a film deposition method that does not generate plasma, it has the advantage of preventing the formation of defects caused by plasma damage.

[0270] In addition, the ALD method performs film deposition by maintaining the chamber at atmospheric pressure or reduced pressure, introducing a source gas for the reaction into the chamber and reacting it, and repeating this process. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas along with the source gas. For example, two or more types of source gases may be supplied to the chamber sequentially. In this case, to prevent the mixing of the various types of source gases, the inert gas is introduced after the first source gas has reacted, and then the second source gas is introduced. Alternatively, instead of introducing the inert gas, the first source gas may be discharged by vacuum evacuation, and then the second source gas may be introduced. A first layer is deposited by the first source gas adsorbing and reacting on the substrate surface, and a second layer is deposited on the first layer by the adsorption and reaction of the second source gas introduced later, thereby forming a thin film. By controlling this gas introduction sequence and repeating this process multiple times until a desired thickness is achieved, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be controlled by the number of gas introduction cycles, precise film thickness control is possible, making it suitable for fabricating fine FETs.

[0271] Thermal CVD methods, such as the MOCVD method, can form films such as the aforementioned conductive film, insulating film, oxide semiconductor film, and metal oxide film. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. The method is not limited to this combination, and triethylgallium (Ga(C2H5)3) may be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) may be used instead of dimethylzinc.

[0272] For example, when forming a hafnium oxide film using a film deposition apparatus utilizing the ALD method, two types of gases are used: a raw gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH3)2]4) or tetrakis(ethylmethylamide) hafnium, etc.) and ozone (O3) as an oxidizing agent.

[0273] For example, when forming an aluminum oxide film using a film deposition apparatus utilizing the ALD method, two types of gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0274] For example, when forming a silicon oxide film using a film formation apparatus utilizing the ALD method, hexachlorodisilane is adsorbed onto the film surface and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbate.

[0275] For example, when forming a tungsten film using a film deposition apparatus utilizing the ALD method, WF6 gas and B2H6 gas are introduced sequentially to form an initial tungsten film, and then WF6 gas and H2 gas are used to form a tungsten film. Additionally, SiH4 gas may be used instead of B2H6 gas.

[0276] For example, when depositing an oxide semiconductor film, such as an In-Ga-Zn-O film, using a deposition apparatus utilizing the ALD method, an In-O layer is formed using In(CH3)3 gas and O3 gas, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and then a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. Furthermore, the order of these layers is not limited to this example. Additionally, mixed compound layers such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Furthermore, H2O gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, but it is more preferable to use O3 gas that does not contain H.

[0277] <Method for Manufacturing Semiconductor Devices 2>

[0278] Next, an example of a method for manufacturing a transistor (100B) illustrated in FIG. 3 will be described with reference to FIG. 12 and FIG. 13. FIG. 12 and FIG. 13 are cross-sectional views in the channel length (L) direction and channel width (W) direction illustrating a method for manufacturing a transistor (100B).

[0279] First, similar to the method of manufacturing the transistor (100) described above, a conductive film (106), an insulating film (104), an oxide semiconductor film (107), an oxide semiconductor film (112_0), and a conductive film (114_0) are formed on a substrate (102) (see (A) and (B) of FIGS. 8 and 9).

[0280] Next, a mask (140) is formed at a desired location on the conductive film (114_0) by a lithography process (see (C) in FIG. 9).

[0281] Next, the conductive film (114_0) and the oxide semiconductor film (112_0) are processed by etching over the mask (140) to form an island-shaped conductive film (114) and an island-shaped oxide semiconductor film (112) (see (A) in FIG. 12).

[0282] In this embodiment, the conductive film (114_0) and the oxide semiconductor film (112_0) are processed using a wet etching method.

[0283] Next, an insulating film (110_0) is processed by etching over the mask (140) to form an island-shaped insulating film (110) (see (B) in FIG. 12).

[0284] In this embodiment, the insulating film (110_0) is processed using a dry etching method.

[0285] Next, after removing the mask (140), an impurity element (145) is added over the insulating film (104), oxide semiconductor film (107), oxide semiconductor film (112), and conductive film (114) (see (C) in FIG. 12).

[0286] Additionally, when adding impurity elements (145), a large amount of impurity is added to the exposed surface area of ​​the oxide semiconductor film (107) (which later becomes the source area (108s) and drain area (108d)). Meanwhile, in the area where the oxide semiconductor film (112) of the oxide semiconductor film (107) does not overlap and the insulating film (110) overlaps (which later becomes the area (108f)), the impurity elements (145) are added through the insulating film (110), so the amount of impurity elements (145) added is less than in the source area (108s) and drain area (108d).

[0287] In addition, in this embodiment, an impurity argon is added to the oxide semiconductor film (107) and the oxide semiconductor film (112) using a doping device as an element (145).

[0288] In addition, although the present embodiment exemplifies a configuration in which argon is added as the impurity element (145), it is not limited thereto, and, for example, a configuration in which nitrogen is added may also be used. Furthermore, for example, the process of adding the impurity element (145) may not be performed. If the process of adding the impurity element (145) is not performed, the region (108f) has an impurity concentration equivalent to that of the channel region (108i).

[0289] Next, an insulating film (116) is formed on an insulating film (104), an oxide semiconductor film (107), an insulating film (110), an oxide semiconductor film (112), and a conductive film (114). Additionally, by forming the insulating film (116), the oxide semiconductor film (107) in contact with the insulating film (116) becomes a source region (108s) and a drain region (108d). Furthermore, the oxide semiconductor film (107) not in contact with the insulating film (116), in other words, the oxide semiconductor film (107) in contact with the insulating film (110), becomes a channel region (108i). Thus, an oxide semiconductor film (108) having a channel region (108i), a source region (108s), and a drain region (108d) is formed (see (D) in FIG. 12).

[0290] Additionally, a region (108f) is formed between the channel region (108i) and the source region (108s), and between the channel region (108i) and the drain region (108d).

[0291] Next, an insulating film (118) is formed on the insulating film (116) (see (A) in FIG. 13).

[0292] Next, a mask is formed by lithography at a desired location on the insulating film (118), and then a portion of the insulating film (118) and the insulating film (116) is etched to form an opening (141s) extending to a source region (108s) and an opening (141d) extending to a drain region (108d) (see (B) in FIG. 13).

[0293] Next, an insulating film (122) is formed on the insulating film (118) (see (C) in FIG. 13).

[0294] Additionally, the insulating film (122) functions as a flattening insulating film. Additionally, the insulating film (122) has an opening at a position that overlaps with the openings (141s, 141d).

[0295] In this embodiment, a photosensitive acrylic resin is applied using a spin coater device as an insulating film (122), and then an insulating film (122) having an opening is formed by photosensitive a desired area of ​​the acrylic resin.

[0296] Next, a conductive film (120) is formed on the insulating film (122) to cover the openings (141s, 141d) (see (D) in FIG. 13).

[0297] Next, a mask is formed by a lithography process at a desired location on the conductive film (120), and then a conductive film (120s, 120d) is formed by etching a portion of the conductive film (120).

[0298] In this embodiment, a dry etching method is used for processing the conductive film (120). Additionally, when processing the conductive film (120), a portion of the upper part of the insulating film (122) may be removed.

[0299] A transistor (100B) shown in Fig. 3 can be manufactured by the above process.

[0300] In addition, when manufacturing the above transistor (100B), the insulating film (104), oxide semiconductor film (107), oxide semiconductor film (110_0), oxide semiconductor film (112_0), conductive film (114), impurity element (145), insulating film (116), insulating film (118), openings (141s, 141d), and conductive film (120) can be formed by utilizing the contents described in <1-4. Method of manufacturing semiconductor device 1>.

[0301] In addition, although an example has been shown in this embodiment where the transistor has an oxide semiconductor film, the present invention is not limited thereto. In one embodiment of the present invention, the transistor does not have to have an oxide semiconductor film. As an example, the channel region, the vicinity of the channel region, the source region, or the drain region of the transistor may be formed from a material having Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc.

[0302] The configurations and methods described in the above embodiments may be used in appropriate combination with the configurations and methods described in other embodiments.

[0303] (Embodiment 2)

[0304] In this embodiment, the structure of the oxide semiconductor, etc., will be explained with reference to FIGS. 17 to 21.

[0305] Structure of Oxide Semiconductors

[0306] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0307] In addition, from another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0308] Regarding amorphous structures, there are generally views that they are isotropic, do not possess heterogeneous structures, are in a metastable state, have non-fixed atomic arrangements, have flexibility in bond angles, and possess short-range order but not long-range order.

[0309] In other words, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that is not isotropic (e.g., having a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, an a-like OS is an unstable structure that is not isotropic but has cavities (also called voids). In terms of instability, an a-like OS is physically similar to an amorphous oxide semiconductor.

[0310] <caac-os>

[0311] First, I will explain CAAC-OS.

[0312] CAAC-OS is a type of oxide semiconductor having multiple c-axis oriented crystal regions (also called pellets).

[0313] The case of analyzing CAAC-OS by X-ray diffraction (XRD) is described. For example, when the structure of CAAC-OS having a crystal of InGaZnO4 classified as space group R-3m is analyzed by the out-of-plane method, a peak appears when the diffraction angle (2θ) is around 31°, as shown in (A) of FIG. 17. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal in CAAC-OS has c-axis orientation and that the c-axis is oriented in a direction substantially perpendicular to the plane where the film of CAAC-OS is formed (also called the surface to be formed) or the upper plane. In addition, in addition to the peak when 2θ is around 31°, a peak may also appear when 2θ is around 36°. The peak when 2θ is around 36° is attributed to a crystal structure classified as space group Fd-3m. Therefore, it is desirable for CAAC-OS not to exhibit this peak.

[0314] Meanwhile, when analyzing the structure of CAAC-OS by the in-plane method, in which X-rays are incident from a direction parallel to the surface to be formed, a peak appears when 2θ is around 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Furthermore, even when 2θ is fixed around 56° and the sample is analyzed (φ-scan) while rotating the sample with the normal vector of the sample plane as the axis (φ-axis), no clear peak appears, as shown in (B) of FIG. 17. On the other hand, when φ-scanning is performed on a single crystal InGaZnO4 with 2θ fixed around 56°, six peaks originating from a crystal plane equivalent to the (110) plane are observed, as shown in (C) of FIG. 17. Therefore, based on structural analysis using XRD, it can be confirmed that the orientation of CAAC-OS along the a-axis and b-axis is irregular.

[0315] Next, the CAAC-OS analyzed by electron diffraction will be described. For example, regarding a CAAC-OS having an InGaZnO4 crystal, if an electron beam with a probe diameter of 300 nm is incident parallel to the surface to be formed of the CAAC-OS, a diffraction pattern (also called a limited-field electron diffraction pattern) as shown in Fig. 17 (D) may appear. This diffraction pattern includes spots originating from the (009) plane of the InGaZnO4 crystal. Therefore, it can be seen through electron diffraction that the pellet contained in the CAAC-OS has c-axis orientation, and that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. Meanwhile, for the same sample, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the sample surface is shown in Fig. 17 (E). In Fig. 17 (E), a ring-shaped diffraction pattern can be observed. Therefore, it can be seen that the a-axis and b-axis of the pellet included in the CAAC-OS do not have orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. In addition, the first ring in (E) of FIG. 17 is thought to be due to the (010) plane and (100) plane, etc. of the crystal of InGaZnO4. In addition, the second ring in (E) of FIG. 17 is thought to be derived from the (110) plane, etc.

[0316] In addition, when observing the combined image of the bright-field image and diffraction pattern of CAAC-OS (also called a high-resolution TEM image) using a transmission electron microscope (TEM), multiple pellets can be identified. On the other hand, there are cases where the boundaries between pellets, i.e., grain boundaries (also called grain boundaries), cannot be clearly identified even in high-resolution TEM images. Therefore, it can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur in CAAC-OS.

[0317] Figure 18 (A) is a high-resolution TEM image of a cross-section of the CAAC-OS observed from a direction substantially parallel to the sample plane. A spherical aberration corrector function was used for observing the high-resolution TEM image. A high-resolution TEM image using the spherical aberration corrector function is specifically referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, by an atomic resolution analysis electron microscope (JEM-ARM200F manufactured by JEOL Ltd.).

[0318] In Fig. 18 (A), a pellet, which is a region where metal atoms are arranged in a layered shape, can be observed. It can be seen that the size of a single pellet is 1 nm or larger, or 3 nm or larger. Therefore, the pellet may be referred to as a nanocrystal (nc). Additionally, CAAC-OS may be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects the irregularities of the surface to be formed or the top surface of CAAC-OS and becomes parallel to the surface to be formed or the top surface of CAAC-OS.

[0319] In addition, Figs. 18 (B) and Figs. 18 (C) show Cs-corrected high-resolution TEM images of the CAAC-OS plane observed from a direction substantially perpendicular to the sample plane. Figs. 18 (D) and Figs. 18 (E) are image-processed images of Figs. 18 (B) and Figs. 18 (C), respectively. The image processing method is described below. First, an FFT image is acquired by performing a Fast Fourier Transform (FFT) on Fig. 18 (B). Next, 2.8 nm from the origin in the acquired FFT image -1 at 5.0nm -1 Mask processing is performed while leaving the range between them intact. Next, an image processed is obtained by performing an Inverse Fast Fourier Transform (IFFT) on the masked FFT image. The image obtained in this way is called the FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from a Cs-corrected high-resolution TEM image and represents a grid array.

[0320] In (D) of Fig. 18, the parts where the grid arrangement is disrupted are shown as dashed lines. The area enclosed by the dashed lines is a single pellet. Also, the parts shown by the dashed lines are the connections between pellets. Since the dashed lines are hexagonal, it can be seen that the pellets are hexagonal. Furthermore, the shape of the pellets is not limited to a regular hexagon, and they are often non-regular hexagonal.

[0321] In Figure 18 (E), a dotted line is shown between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned. Even near the dotted line, no clear grain boundaries can be observed. When the surrounding lattice points are connected with the center of the lattice point near the dotted line, distorted hexagons, pentagons, and / or heptagons are formed. In other words, it can be seen that the formation of grain boundaries is suppressed by deforming the lattice arrangement. This is thought to be because the CAAC-OS allows for deformation due to factors such as the atomic arrangement not being dense in the ab plane direction or the change in bond distance between atoms caused by the substitution of metal elements.

[0322] As described above, CAAC-OS has c-axis orientation and also has a crystal structure in which multiple pellets (nano-crystals) are connected and deformed in the ab-plane direction. Therefore, CAAC-OS can also be called an oxide semiconductor having a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

[0323] CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of oxide semiconductors can be degraded by the incorporation of impurities or the generation of defects, CAAC-OS can also be described as an oxide semiconductor with low levels of impurities or defects (such as oxygen vacancies).

[0324] Furthermore, impurities are elements other than the main components of oxide semiconductors, and include hydrogen, carbon, silicon, and transition metal elements. For example, elements (such as silicon) that have a stronger bonding affinity with oxygen than the metal elements constituting the oxide semiconductor deplete oxygen from the semiconductor, thereby disrupting the atomic arrangement and becoming a factor that lowers crystallinity. Additionally, heavy metals such as iron and nickel, as well as argon and carbon dioxide, have large atomic radii (or molecular radii), which disrupts the atomic arrangement of oxide semiconductors and thus lowers crystallinity.

[0325] <nc-os>

[0326] Next, nc-OS will be explained.

[0327] The case of analyzing nc-OS by XRD is described. For example, when the structure of nc-OS is analyzed by the out-of-plane method, no peaks indicating orientation appear. In other words, the crystals of nc-OS do not have orientation.

[0328] In addition, for example, when an nc-OS having an InGaZnO4 crystal is thinned and an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed in a region with a thickness of 34 nm, a ring-shaped diffraction pattern (nano-beam electron diffraction pattern) is observed as shown in FIG. 19 (A). Also, the diffraction pattern (nano-beam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in FIG. 19 (B). In FIG. 19 (B), multiple spots are observed within the ring-shaped region. Therefore, although orderliness is not confirmed in the nc-OS when an electron beam with a probe diameter of 50 nm is incident, orderliness is confirmed when an electron beam with a probe diameter of 1 nm is incident.

[0329] In addition, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed, as shown in (C) of FIG. 19. Therefore, it can be seen that in the range with a thickness of less than 10 nm, the nc-OS has a highly ordered region, that is, a crystal. In addition, there are regions where a regular electron diffraction pattern is not observed because the crystals are oriented in various directions.

[0330] Figure 19 (D) shows a Cs-corrected high-resolution TEM image of a cross-section of an nc-OS observed from a direction substantially parallel to the surface to be formed. The nc-OS has regions where crystallization can be identified and regions where clear crystallization cannot be identified, such as the parts indicated by auxiliary lines in the high-resolution TEM image. The size of the crystallization included in the nc-OS is 1 nm or larger and 10 nm or smaller, and is particularly often 1 nm or larger and 3 nm or smaller. Additionally, oxide semiconductors with crystallization sizes greater than 10 nm and less than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. In the case of nc-OS, for example, grain boundaries may not be clearly identified in high-resolution TEM images. Furthermore, nanocrystals may share the same origin as the pellets in CAAC-OS. Therefore, the crystallization of the nc-OS may be referred to as pellets below.

[0331] As such, nc-OS exhibits periodicity in the atomic arrangement in minute regions (e.g., regions from 1 nm to 10 nm, particularly from 1 nm to 3 nm). Additionally, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Consequently, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductors.

[0332] In addition, since the crystal orientation among the pellets (nanocrystals) does not have regularity, nc-OS may also be called an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

[0333] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS or amorphous oxide semiconductors. However, nc-OS does not exhibit regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density compared to CAAC-OS.

[0334] <a-like OS>

[0335] a-like OS is an oxide semiconductor that has a structure intermediate between nc-OS and amorphous oxide semiconductors.

[0336] Figure 20 shows high-resolution cross-sectional TEM images of an a-like OS. Here, Figure 20 (A) is a high-resolution cross-sectional TEM image of an a-like OS when electron irradiation was started. Figure 20 (B) is 4.3×10 8 e - / nm 2 electrons (e - This is a high-resolution cross-sectional TEM image of an a-like OS after electron irradiation. From Figure 20 (A) and Figure 20 (B), it can be seen that a striped bright region extending in the longitudinal direction from the start of electron irradiation is observed in the a-like OS. Additionally, it can be seen that the shape of the bright region changes after electron irradiation. Furthermore, the bright region is presumed to be a cavity or a low-density region.

[0337] Because it has a cavity, the a-like OS is an unstable structure. Below, to show that the a-like OS is an unstable structure compared to CAAC-OS and nc-OS, changes in the structure caused by electron irradiation are shown.

[0338] a-like OS, nc-OS, and CAAC-OS are prepared as samples. These samples are all In-Ga-Zn oxides.

[0339] First, high-resolution cross-sectional TEM images of each sample are acquired. Based on the high-resolution cross-sectional TEM images, each sample has a crystalline region.

[0340] In addition, it is known that the unit cell of the InGaZnO4 crystal has a structure in which a total of 9 layers are layered and superimposed in the c-axis direction, consisting of 3 In-O layers and 6 Ga-Zn-O layers. The spacing between these adjacent layers is approximately equal to the lattice plane spacing (also called the d value) of the (009) plane, and this value is calculated to be 0.29 nm from the analysis of the crystal structure. Therefore, the region where the spacing of the lattice fringes is 0.28 nm or more and 0.30 nm or less was considered as the crystal region of InGaZnO4 below. Furthermore, the lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0341] Figure 21 is an example of investigating the average crystal size of crystal regions (22 to 30 locations) of each sample. In addition, the length of the aforementioned lattice stripes was defined as the size of the crystal region. In Figure 21, it can be seen that in the a-like OS, the crystal region grows larger depending on the cumulative electron dose resulting from TEM image acquisition, etc. In Figure 21, the crystal region (also called the initial nucleus), which was approximately 1.2 nm in size at the beginning of TEM observation, [is] electrons (e - The cumulative irradiation amount of ) is 4.2×10 8 e - / nm 2 It can be seen that it grew to a size of approximately 1.9 nm when it reached this point. Meanwhile, for nc-OS and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10⁻⁶ 8 e - / nm 2 It can be seen that the size of the crystal region did not change within the range up to [value]. In Fig. 21, it can be seen that regardless of the cumulative electron irradiation dose, the crystal region sizes of nc-OS and CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively. Furthermore, a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and observation by TEM. The electron beam irradiation conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), the diameter of the irradiation area was set to 230 nm.

[0342] As such, in a-like OS, growth of crystal regions due to electron irradiation is sometimes observed. On the other hand, in nc-OS and CAAC-OS, growth of crystal regions due to electron irradiation is rarely observed. In other words, it can be seen that a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0343] Furthermore, because it contains cavities, a-like OS is a structure with lower density compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single-crystal oxide semiconductor with the same composition. Additionally, the densities of nc-OS and CAAC-OS are 92.3% or more and less than 100% of the density of a single-crystal oxide semiconductor with the same composition. It is difficult to deposit oxide semiconductors with a density of less than 78% of a single-crystal oxide semiconductor.

[0344] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single-crystal InGaZnO4 having a rhombohedral structure is 6.357 g / cm³ 3 Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm³ 3 Above 5.9 g / cm² 3 It is less than. Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm³ 3 Above 6.3g / cm² 3 It is less than.

[0345] In addition, if a single crystal with the same composition does not exist, a density equivalent to that of a single-crystal oxide semiconductor with a desired composition can be estimated by combining single-crystal oxide semiconductors with different compositions in arbitrary proportions. The density equivalent to that of a single-crystal oxide semiconductor with a desired composition is preferably estimated by using a weighted average of the ratios in which single-crystal oxide semiconductors with different compositions are combined. However, it is desirable to estimate the density by combining as few types of single crystals as possible.

[0346] As described above, oxide semiconductors have various structures, and each has various characteristics. In addition, the oxide semiconductor may be a stacked film having two or more types among, for example, amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0347] Carrier Density of Oxide Semiconductors

[0348] Next, the carrier density of oxide semiconductors is explained below.

[0349] Factors affecting the carrier density of an oxide semiconductor include oxygen vacancies (Vo) within the oxide semiconductor or impurities within the oxide semiconductor.

[0350] If the oxygen vacancy in the oxide semiconductor increases, the defect level density increases when this oxygen vacancy combines with hydrogen (this state is also called VoH). Alternatively, if the impurity in the oxide semiconductor increases, the defect level density increases due to the impurities. Therefore, by controlling the defect level density in the oxide semiconductor, the carrier density of the oxide semiconductor can be controlled.

[0351] Here, we consider a transistor that uses an oxide semiconductor in the channel region.

[0352] For the purpose of suppressing a negative shift in the threshold voltage of a transistor or reducing the off-current of a transistor, it is desirable to lower the carrier density of the oxide semiconductor. When lowering the carrier density of the oxide semiconductor, it is preferable to lower the defect level density by lowering the impurity concentration within the oxide semiconductor. In this specification and other documents, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of a high-purity intrinsic oxide semiconductor is 8×10⁻⁶ 15 cm -3 Less than, preferably 1×10 11 cm -3 Less than, more preferably 1×10 10 cm -3 Less than and 1×10 -9 cm -3 It is good to do it this way.

[0353] On the other hand, if the objective is to improve the on-current of a transistor or to enhance its field-effect mobility, it is desirable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of the oxide semiconductor, it is preferable to slightly increase the impurity concentration or the defect level density. Alternatively, it is preferable to make the band gap of the oxide semiconductor smaller. For example, within the range where the on / off ratio of the transistor's Id-Vg characteristic is obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher defect level density can be considered substantially intrinsic. Furthermore, an oxide semiconductor with high electron affinity, which consequently results in a smaller band gap and, consequently, an increased density of thermally excited electrons (carriers), can be considered substantially intrinsic. Additionally, when using an oxide semiconductor with higher electron affinity, the threshold voltage of the transistor becomes lower.

[0354] The aforementioned oxide semiconductor with increased carrier density is slightly n-type. Therefore, the oxide semiconductor with increased carrier density may be called 'Slightly-n'.

[0355] The carrier density of a practically intrinsic oxide semiconductor is 1×10⁻⁶ 5 cm -3 1×10 18 cm -3 Less than 1×10 is preferable. 7 cm -3 1×10 17 cm -3 The following is more preferable, and 1×10 9 cm -3 At least 5×10 16 cm -3 The following is more preferable, and 1×10 10 cm -3 1×10 16 cm -3 The following is more preferable, and 1×10 11 cm -3 1×10 15 cm -3 The following is more desirable.

[0356] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0357] (Embodiment 3)

[0358] In this embodiment, an example of a display device having a transistor as exemplified in the above-described embodiment is described below using FIGS. 22 to 32.

[0359] FIG. 22 is a top view illustrating an example of a display device. The display device (700) illustrated in FIG. 22 has a pixel portion (702) provided on a first substrate (701), a source driver circuit portion (704) and a gate driver circuit portion (706) provided on the first substrate (701), a sealing material (712) arranged to surround the pixel portion (702), the source driver circuit portion (704), and the gate driver circuit portion (706), and a second substrate (705) provided facing the first substrate (701). Additionally, the first substrate (701) and the second substrate (705) are sealed by the sealing material (712). That is, the pixel portion (702), the source driver circuit portion (704), and the gate driver circuit portion (706) are sealed by the first substrate (701), the sealing material (712), and the second substrate (705). Additionally, although not shown in FIG. 22, a display element is provided between the first substrate (701) and the second substrate (705).

[0360] Additionally, the display device (700) is provided with an FPC terminal (708) (FPC: Flexible printed circuit) that is electrically connected to the pixel section (702), source driver circuit section (704), gate driver circuit section (706), and gate driver circuit section (706), respectively, in an area different from the area enclosed by the sealing material (712) on the first substrate (701). Additionally, an FPC (716) is connected to the FPC terminal (708), and various signals are supplied to the pixel section (702), source driver circuit section (704), and gate driver circuit section (706) via the FPC (716). Additionally, a signal line (710) is connected to the pixel section (702), source driver circuit section (704), gate driver circuit section (706), and FPC terminal (708), respectively. Various signals supplied by the FPC (716) are supplied to the pixel section (702), source driver circuit section (704), gate driver circuit section (706), and FPC terminal section (708) through the signal line (710).

[0361] Additionally, a plurality of gate driver circuit sections (706) may be provided in the display device (700). Furthermore, as for the display device (700), an example has been shown in which the source driver circuit section (704) and the gate driver circuit section (706) are formed on the same first substrate (701) as the pixel section (702), but this configuration is not limited thereto. For example, only the gate driver circuit section (706) may be formed on the first substrate (701), or only the source driver circuit section (704) may be formed on the first substrate (701). In this case, the configuration may be such that a source driver circuit or a gate driver circuit, etc., is formed on a substrate (e.g., a driving circuit board formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) is formed on the first substrate (701). Additionally, the method of connecting the separately formed driving circuit board is not particularly limited, and methods such as the COG (Chip On Glass) method or wire bonding method may be used.

[0362] In addition, the pixel portion (702), source driver circuit portion (704), and gate driver circuit portion (706) of the display device (700) have a plurality of transistors, and a transistor, which is a semiconductor device of one form of the present invention, can be applied.

[0363] Additionally, the display device (700) may have various elements. Examples of the elements include, for instance, an electroluminescence (EL) element (an EL element including organic and inorganic materials, an organic EL element, an inorganic EL element, an LED, etc.), a light-emitting transistor element (a transistor that emits light according to current), an electron emission element, a liquid crystal element, an electronic ink element, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a MEMS (micro electro mechanical systems) display (for example, a grating light valve (GLV), a digital micro mirror device (DMD), a digital micro shutter (DMS) element, an interference modulation (IMOD) element, etc.), a piezoelectric ceramic display, etc.

[0364] In addition, an example of a display device using an EL element is an EL display. An example of a display device using an electron emission element is a field emission display (FED) or a surface-conduction electron-emitter display (SED). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. Furthermore, when realizing a transmissive liquid crystal display or a reflective liquid crystal display, it is preferable that some or all of the pixel electrodes function as reflective electrodes. For example, it is preferable that some or all of the pixel electrodes be made of aluminum, silver, etc. In addition, in that case, a memory circuit such as SRAM may be provided below the reflective electrodes. This allows for further reduction of power consumption.

[0365] Additionally, the display method in the display device (700) may use a progressive method or an interlaced method. Furthermore, when displaying in color, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, it may be composed of one color element using two of the RGB colors, such as in a pentile array, and configured by selecting two different colors according to the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. Additionally, the size of the display area may differ for each dot of the color element. However, the disclosed invention is not limited to a color display device and may be applied to a black and white display device.

[0366] In addition, a coloring layer (also called a color filter) may be used to display a full-color display device using white light emission (W) from a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.). The coloring layer may be used by appropriately combining, for example, red (R), green (G), blue (B), yellow (Y), etc. By using a coloring layer, color reproduction can be improved compared to the case where a coloring layer is not used. At this time, by arranging an area having a coloring layer and an area not having a coloring layer, white light from the area not having a coloring layer may be used directly for display. By arranging an area not having a coloring layer in some parts, the reduction in brightness caused by the coloring layer can be minimized when performing a bright display, and power consumption may be reduced by about 20% to 30%. However, when using a self-emissive element such as an organic EL element or an inorganic EL element for a full-color display, R, G, B, Y, and W may be emitted from elements having their respective light emission colors. By using self-emissive elements, power consumption can be reduced more than when using a colored layer.

[0367] In addition, as a colorization method, in addition to the method of converting a portion of the light from the aforementioned white light into red, green, and blue by passing it through a color filter (color filter method), a method of using red, green, and blue light respectively (three-color method), or a method of converting a portion of the light from the blue light into red or green (color conversion method, quantum dot method) may be applied.

[0368] In this embodiment, a configuration using a liquid crystal element and an EL element as a display element is described with reference to FIGS. 23 and 24. Additionally, FIG. 23 is a cross-sectional view of the dotted line QR shown in FIG. 22, and is a configuration using a liquid crystal element as a display element. Additionally, FIG. 24 is a cross-sectional view of the dotted line QR shown in FIG. 22, and is a configuration using an EL element as a display element.

[0369] First, the common parts shown in FIGS. 23 and 24 will be described, and then the different parts will be described below.

[0370] <Description of the common parts of the display device>

[0371] The display device (700) illustrated in FIGS. 23 and 24 has a lead wiring section (711), a pixel section (702), a source driver circuit section (704), and an FPC terminal section (708). Additionally, the lead wiring section (711) has a signal line (710). Additionally, the pixel section (702) has a transistor (750) and a capacitance element (790). Additionally, the source driver circuit section (704) has a transistor (752).

[0372] The transistor (750) and transistor (752) have the same configuration as the transistor (100) described above. Additionally, regarding the configuration of the transistor (750) and transistor (752), other transistors shown in the above-described embodiment may be used.

[0373] The transistor used in this embodiment has an oxide semiconductor film that is purified and suppresses the formation of oxygen vacancies. The transistor can reduce the off-current. Therefore, the retention time of electrical signals, such as image signals, can be extended, and the recording interval can also be set to be long when the power is on. As a result, the frequency of refresh operations can be reduced, thereby exhibiting the effect of suppressing power consumption.

[0374] Furthermore, the transistor used in this embodiment can be driven at high speeds because it can achieve a relatively high field-effect mobility. For example, by using such a high-speed driven transistor in a liquid crystal display device, the switching transistor of the pixel section and the driver transistor used in the driving circuit section can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed by a silicon wafer or the like as a separate driving circuit, the number of semiconductor device components can be reduced. In addition, by using a high-speed driven transistor in the pixel section as well, high-quality images can be provided.

[0375] The capacitance element (790) has an oxide semiconductor film having the transistor (750), a lower electrode formed through a process of processing the same oxide semiconductor film, a conductive film functioning as the source electrode and drain electrode having the transistor (750), and an upper electrode formed through a process of processing the same conductive film. Additionally, between the lower electrode and the upper electrode, an insulating film is provided that is formed through a process of forming an insulating film identical to the third insulating film and the fourth insulating film having the transistor (750). That is, the capacitance element (790) has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

[0376] Additionally, in FIGS. 23 and 24, a flattened insulating film (770) is provided over the transistor (750), transistor (752), and capacitive element (790).

[0377] As for the flattening insulating film (770), heat-resistant organic materials such as polyimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, polyamide resin, and epoxy resin may be used. Additionally, the flattening insulating film (770) may be formed by stacking multiple insulating films formed from these materials. Furthermore, the configuration may be configured without providing the flattening insulating film (770).

[0378] Additionally, FIGS. 23 and 24 illustrate a configuration in which transistors of the same structure are used for the transistor (750) of the pixel unit (702) and the transistor (752) of the source driver circuit unit (704), but are not limited thereto. For example, the pixel unit (702) and the source driver circuit unit (704) may use different transistors.

[0379] In addition, when different transistors are used for the pixel section (702) and the source driver circuit section (704), a combination of the staggered transistor and the reverse staggered transistor shown in Embodiment 1 may be used. Specifically, examples include a configuration in which a staggered transistor is used for the pixel section (702) and a reverse staggered transistor is used for the source driver circuit section (704), or a configuration in which a reverse staggered transistor is used for the pixel section (702) and a staggered transistor is used for the source driver circuit section (704). Additionally, the source driver circuit section (704) may be read as a gate driver circuit section. Furthermore, the reverse staggered transistor may have a channel-etch type structure or a channel-protect type structure. Also, for the reverse staggered transistor, a structure having the S-channel structure described above is preferred. Furthermore, the structures of these transistors may be freely combined.

[0380] The signal line (710) is formed through the same process as the conductive film that functions as the source electrode and drain electrode of the transistor (750) and transistor (752). Additionally, the signal line (710) may use a conductive film formed through a different process than the source electrode and drain electrode of the transistor (750) and transistor (752), for example, an oxide semiconductor film formed through the same process as the oxide semiconductor film that functions as the gate electrode. For example, if a material containing copper elements is used as the signal line (710), signal delay caused by wiring resistance is reduced, and it can be displayed on a large screen.

[0381] Additionally, the FPC terminal portion (708) has a connection electrode (760), an anisotropic conductive film (780), and an FPC (716). Additionally, the connection electrode (760) is formed through the same process as the conductive film that functions as the source electrode and drain electrode of the transistor (750) and transistor (752). Additionally, the connection electrode (760) is electrically connected to the terminal of the FPC (716) through the anisotropic conductive film (780).

[0382] Additionally, for the first substrate (701) and the second substrate (705), for example, a glass substrate may be used. Also, for the first substrate (701) and the second substrate (705), a flexible substrate may be used. Examples of flexible substrates include plastic substrates.

[0383] Additionally, a structure (778) is provided between the first substrate (701) and the second substrate (705). The structure (778) is a pillar-shaped spacer obtained by selectively etching an insulating film and is provided to control the distance (cell gap) between the first substrate (701) and the second substrate (705). Additionally, a spherical spacer may be used as the structure (778).

[0384] Additionally, on the side of the second substrate (705), a light-blocking film (738) that functions as a black matrix, a coloring film (736) that functions as a color filter, and an insulating film (734) that is in contact with the light-blocking film (738) and the coloring film (736) are provided.

[0385] <Example of configuration of a display device using a liquid crystal element>

[0386] The display device (700) illustrated in FIG. 23 has a liquid crystal element (775). The liquid crystal element (775) has a conductive film (772), a conductive film (774), and a liquid crystal layer (776). The conductive film (774) is provided on the side of the second substrate (705) and functions as a counter electrode. The display device (700) illustrated in FIG. 23 can display an image by controlling the transmission and non-transmission of light through the change in the orientation state of the liquid crystal layer (776) by the voltage applied to the conductive film (772) and the conductive film (774).

[0387] Additionally, the conductive film (772) is connected to the conductive film that functions as the source electrode and drain electrode of the transistor (750). The conductive film (772) is formed on the planarizing insulating film (770) and functions as a pixel electrode, that is, an electrode on one side of the display element. Additionally, the conductive film (772) functions as a reflective electrode. The display device (700) shown in FIG. 23 is a so-called reflective color liquid crystal display device that uses external light to reflect light to the conductive film (772) and displays it through the colored film (736).

[0388] As the conductive film (772), a conductive film that is transparent to visible light or a conductive film that is reflective to visible light may be used. For the conductive film that is transparent to visible light, it is preferable to use a material containing, for example, one type selected from indium (In), zinc (Zn), and tin (Sn). For the conductive film that is reflective to visible light, it is preferable to use a material containing, for example, aluminum or silver. In this embodiment, a conductive film that is reflective to visible light is used as the conductive film (772).

[0389] Additionally, in the display device (700) illustrated in FIG. 23, irregularities are provided on a portion of the flattening insulating film (770) of the pixel portion (702). These irregularities can be formed, for example, by forming the flattening insulating film (770) as a resin film and providing irregularities on the surface of the resin film. Additionally, a conductive film (772) that functions as a reflective electrode is formed along the irregularities. Thus, when external light is incident on the conductive film (772), it is possible to diffusely reflect the light from the surface of the conductive film (772), thereby improving visibility.

[0390] Additionally, although the display device (700) illustrated in FIG. 23 is exemplified as a reflective color liquid crystal display device, it is not limited thereto. For example, the conductive film (772) may be a transparent color liquid crystal display device by using a conductive film that is transparent to visible light. In the case of a transparent color liquid crystal display device, the unevenness provided on the planarizing insulating film (770) may be configured not to be provided.

[0391] Here, an example of a transmissive color liquid crystal display device is illustrated in FIG. 25. FIG. 25 is a cross-sectional view of the dotted line QR shown in FIG. 22, and is a configuration using a liquid crystal element as a display element. In addition, the display device (700) shown in FIG. 25 is an example of a configuration using a transverse electric field method (e.g., FFS mode) as a driving method for the liquid crystal element. In the configuration shown in FIG. 25, an insulating film (773) is provided on a conductive film (772) that functions as a pixel electrode, and a conductive film (774) is provided on the insulating film (773). In this case, the conductive film (774) functions as a common electrode (also called a common electrode), and can control the orientation state of the liquid crystal layer (776) by the electric field generated between the conductive film (772) and the conductive film (774) through the insulating film (773).

[0392] Additionally, although not illustrated in FIG. 23 and FIG. 25, the configuration may be such that an alignment layer is provided on either or both of the conductive film (772) or the conductive film (774), on the side in contact with the liquid crystal layer (776). Additionally, although not illustrated in FIG. 23 and FIG. 25, optical members (optical substrates), such as a polarizing member, a phase difference member, and an anti-reflection member, may be appropriately provided. For example, circular polarization by a polarizing substrate and a phase difference substrate may be used. Additionally, a backlight, a side light, etc., may be used as a light source.

[0393] When using liquid crystal elements as display devices, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc., may be used. Depending on the conditions, these liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, isotropic phases, etc.

[0394] In addition, when adopting the transverse electric field method, a liquid crystal exhibiting a blue phase without using an alignment layer may be used. The blue phase is one of the liquid crystal phases and is a phase that appears just before transitioning from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition mixed with a chiral agent in a weight percent or more is used in the liquid crystal layer to improve the temperature range. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response speed and is optically isotropic, so alignment treatment is unnecessary. Furthermore, since an alignment layer is not required, rubbing treatment is also unnecessary; thus, electrostatic breakdown caused by rubbing treatment can be prevented, thereby reducing defects or damage to the liquid crystal display device during the manufacturing process. In addition, the liquid crystal material exhibiting the blue phase has low dependence on the viewing angle.

[0395] In addition, when using a liquid crystal element as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used.

[0396] In addition, a normally black liquid crystal display may be used, for example, a transmissive liquid crystal display employing a vertical alignment (VA) mode. Several types of vertical alignment modes may be used, such as MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV mode.

[0397] <Display device using light-emitting elements>

[0398] The display device (700) illustrated in FIG. 24 has a light-emitting element (782). The light-emitting element (782) has a conductive film (784), an EL layer (786), and a conductive film (788). The display device (700) illustrated in FIG. 24 can display an image by the EL layer (786) of the light-emitting element (782) emitting light. Additionally, the EL layer (786) has an organic compound or an inorganic compound such as a quantum dot.

[0399] Examples of materials that can be used for organic compounds include fluorescent materials or phosphorescent materials. In addition, examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials. In addition, materials containing element groups 12 and 16, 13 and 15, or 14 and 16 may be used. Alternatively, quantum dot materials having elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) may be used.

[0400] Additionally, the conductive film (784) is connected to the conductive film that functions as the source electrode and drain electrode of the transistor (750). The conductive film (784) is formed on the planarizing insulating film (770) and functions as a pixel electrode, that is, an electrode on one side of the display element. As for the conductive film (784), a conductive film that is transparent to visible light or a conductive film that is reflective to visible light may be used. For a conductive film that is transparent to visible light, it is preferable to use a material containing, for example, one type selected from indium (In), zinc (Zn), and tin (Sn). For a conductive film that is reflective to visible light, it is preferable to use a material containing, for example, aluminum or silver.

[0401] Additionally, in the display device (700) illustrated in FIG. 24, an insulating film (730) is provided over a flattened insulating film (770) and a conductive film (784). The insulating film (730) covers a portion of the conductive film (784). Additionally, the light-emitting element (782) is a top emission structure. Thus, the conductive film (788) is transparent and transmits light emitted by the EL layer (786). Additionally, while the present embodiment exemplifies a top emission structure, it is not limited thereto. For example, it can be applied to a bottom emission structure that emits light toward the conductive film (784) side, or a dual emission structure that emits light toward both the conductive film (784) side and the conductive film (788) side.

[0402] Additionally, a colored film (736) is provided at a position overlapping with the light-emitting element (782), and a light-blocking film (738) is provided at a position overlapping with the insulating film (730), the lead wiring portion (711), and the source driver circuit portion (704). Additionally, the colored film (736) and the light-blocking film (738) are covered with an insulating film (734). Additionally, the space between the light-emitting element (782) and the insulating film (734) is filled with a sealing film (732). Furthermore, in the display device (700) illustrated in FIG. 24, a configuration providing a colored film (736) has been exemplified, but it is not limited thereto. For example, if the EL layer (786) is formed independently for each pixel, a configuration that does not provide a colored film (736) may be used.

[0403] <Example of a configuration providing input / output devices to a display device>

[0404] In addition, an input / output device may be provided to the display device (700) shown in FIGS. 24 and 25. Examples of the input / output device may include a touch panel.

[0405] A configuration providing a touch panel (791) to the display device (700) shown in FIGS. 24 and 25 is illustrated in FIGS. 26 and 27.

[0406] FIG. 26 is a cross-sectional view of a configuration in which a touch panel (791) is provided on a display device (700) shown in FIG. 24, and FIG. 27 is a cross-sectional view of a configuration in which a touch panel (791) is provided on a display device (700) shown in FIG. 25.

[0407] First, the touch panel (791) shown in FIGS. 26 and FIGS. 27 will be described below.

[0408] The touch panel (791) illustrated in FIGS. 26 and 27 is a so-called in-cell type touch panel provided between a substrate (705) and a coloring film (736). The touch panel (791) is preferably formed on the substrate (705) side before forming the light-blocking film (738) and the coloring film (736).

[0409] Additionally, the touch panel (791) has a light-blocking film (738), an insulating film (792), an electrode (793), an electrode (794), an insulating film (795), an electrode (796), and an insulating film (797). For example, when a test object such as a finger or a stylus comes into close contact, a change in the mutual capacitance of the electrode (793) and the electrode (794) can be detected.

[0410] Additionally, the intersection of electrodes (793) and (794) is indicated on the upper side of the transistor (750) illustrated in FIGS. 26 and 27. The electrode (796) is electrically connected to two electrodes (793) that accommodate the electrode (794) through an opening provided in the insulating film (795). Also, FIGS. 26 and 27 illustrate a configuration in which the region where the electrode (796) is provided is provided in the pixel section (702), but is not limited thereto and may be formed, for example, in the source driver circuit section (704).

[0411] The electrode (793) and the electrode (794) are provided in an area that overlaps with the light-blocking film (738). Additionally, as shown in FIG. 26, it is preferable that the electrode (793) is provided so as not to overlap with the light-emitting element (782). As shown in FIG. 27, it is preferable that the electrode (793) is provided so as not to overlap with the liquid crystal element (775). In other words, the electrode (793) has an opening in an area that overlaps with the light-emitting element (782) and the liquid crystal element (775). That is, the electrode (793) has a mesh shape. By making this configuration, the electrode (793) can be configured so as not to block the light emitted by the light-emitting element (782). Alternatively, the electrode (793) can be configured so as not to block the light transmitted through the liquid crystal element (775). Therefore, since the reduction in brightness caused by the placement of the touch panel (791) is very small, a display device with high visibility and reduced power consumption can be realized. Additionally, the electrode (794) may also be configured in the same way.

[0412] Additionally, since the electrode (793) and the electrode (794) do not overlap with the light-emitting element (782), a metal material with low transmittance of visible light can be used for the electrode (793) and the electrode (794). Alternatively, since the electrode (793) and the electrode (794) do not overlap with the liquid crystal element (775), a metal material with low transmittance of visible light can be used for the electrode (793) and the electrode (794).

[0413] Therefore, compared to an electrode using an oxide material with high transmittance of visible light, the resistance of the electrode (793) and the electrode (794) can be lowered, thereby improving the sensor sensitivity of the touch panel.

[0414] For example, conductive nanowires may be used for electrodes (793), (794), and (796). The nanowires may have an average diameter of 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. Additionally, as the nanowires, metal wires such as Ag nanowires, Cu nanowires, or Al nanowires, or carbon nanotubes may be used. For example, when Ag nanowires are used for any one or all of electrodes (664), (665), and (667), the light transmittance for visible light may be 89% or more, and the sheet resistance may be 40 Ω / sq. or more and 100 Ω / sq. or less.

[0415] Additionally, while FIGS. 26 and 27 illustrate the configuration of an in-cell type touch panel, it is not limited thereto. For example, it may be a so-called on-cell type touch panel formed on a display device (700), or a so-called out-cell type touch panel attached to the display device (700).

[0416] In this way, a display device of one form of the present invention can be used in combination with various types of touch panels.

[0417] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0418] (Embodiment 4)

[0419] In this embodiment, a display device having a semiconductor device of one form of the present invention is described with reference to FIG. 28.

[0420] <Circuit configuration of the display device>

[0421] The display device illustrated in (A) of FIG. 28 has a region having a pixel of a display element (hereinafter referred to as a pixel portion (502)), a circuit portion disposed outside the pixel portion (502) and having a circuit for driving the pixel (hereinafter referred to as a driving circuit portion (504)), a circuit having a protection function for the element (hereinafter referred to as a protection circuit (506)), and a terminal portion (507). Additionally, the device may be configured without providing a protection circuit (506).

[0422] It is preferable that part or all of the driving circuit part (504) be formed on the same substrate as the pixel part (502). This allows for a reduction in the number of components or terminals. If part or all of the driving circuit part (504) is not formed on the same substrate as the pixel part (502), part or all of the driving circuit part (504) can be mounted by COG or TAB (Tape Automated Bonding).

[0423] The pixel section (502) has a circuit (hereinafter referred to as the pixel circuit (501)) for driving a plurality of display elements arranged in X rows (X is a natural number greater than or equal to 2) and Y columns (Y is a natural number greater than or equal to 2), and the driving circuit section (504) has driving circuits such as a circuit that outputs a signal (scan signal) for selecting a pixel (hereinafter referred to as the gate driver (504a)) and a circuit that supplies a signal (data signal) for driving the display elements of the pixel (hereinafter referred to as the source driver (504b)).

[0424] The gate driver (504a) has a shift register, etc. The gate driver (504a) receives a signal to drive the shift register through the terminal portion (507) and outputs a signal. For example, the gate driver (504a) receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver (504a) has the function of controlling the potential of the wiring to which the scanning signal is supplied (hereinafter referred to as scanning line (GL_1) to scanning line (GL_X)). In addition, a plurality of gate drivers (504a) may be provided, and the scanning line (GL_1) to scanning line (GL_X) may be divided and controlled by the plurality of gate drivers (504a). Alternatively, the gate driver (504a) has the function of supplying an initialization signal. However, it is not limited thereto, and the gate driver (504a) may supply other signals.

[0425] The source driver (504b) has a shift register, etc. Through the terminal portion (507), the source driver (504b) receives a signal (image signal) that serves as the basis for the data signal, in addition to a signal for driving the shift register. The source driver (504b) has the function of generating a data signal to be recorded in the pixel circuit (501) based on the image signal. Additionally, the source driver (504b) has the function of controlling the output of the data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. Additionally, the source driver (504b) has the function of controlling the potential of the wiring to which the data signal is supplied (hereinafter referred to as data line (DL_1) to data line (DL_Y)). Alternatively, the source driver (504b) has the function of supplying an initialization signal. However, not limited thereto, the source driver (504b) may supply other signals.

[0426] The source driver (504b) is configured, for example, using a plurality of analog switches. The source driver (504b) can output a signal obtained by time-dividing an image signal as a data signal by sequentially turning on a plurality of analog switches. Additionally, the source driver (504b) may be configured using a shift register or the like.

[0427] In each of the plurality of pixel circuits (501), a pulse signal is input through one of the plurality of scan lines (GL) to which a scan signal is supplied, and a data signal is input through one of the plurality of data lines (DL) to which a data signal is supplied. Additionally, the recording and maintenance of data signals in each of the plurality of pixel circuits (501) is controlled by a gate driver (504a). For example, in the pixel circuit (501) of the m-th row and n-th column, a pulse signal is input from the gate driver (504a) through a scan line (GL_m) (m is a natural number less than or equal to X), and a data signal is input from the source driver (504b) through a data line (DL_n) (n is a natural number less than or equal to Y) according to the potential of the scan line (GL_m).

[0428] The protection circuit (506) illustrated in (A) of FIG. 28 is connected, for example, to a scan line (GL) which is wiring between a gate driver (504a) and a pixel circuit (501). Alternatively, the protection circuit (506) is connected to a data line (DL) which is wiring between a source driver (504b) and a pixel circuit (501). Alternatively, the protection circuit (506) may be connected to wiring between a gate driver (504a) and a terminal section (507). Alternatively, the protection circuit (506) may be connected to wiring between a source driver (504b) and a terminal section (507). Additionally, the terminal section (507) refers to a part provided with a terminal for inputting power and control signals and image signals from an external circuit to the display device.

[0429] The protection circuit (506) is a circuit that makes the wiring and other wiring conductive when a potential outside a certain range is supplied to the wiring to which it is connected.

[0430] As illustrated in (A) of FIG. 28, by providing a protection circuit (506) to each of the pixel portion (502) and the driving circuit portion (504), the resistance of the display device to overcurrent caused by ESD (Electro Static Discharge), etc., can be increased. However, the configuration of the protection circuit (506) is not limited thereto, and, for example, it may be configured such that the protection circuit (506) is connected to the gate driver (504a) or the source driver (504b). Alternatively, it may be configured such that the protection circuit (506) is connected to the terminal portion (507).

[0431] In addition, although the case in (A) of FIG. 28 illustrates a case where the driving circuit portion (504) is formed by a gate driver (504a) and a source driver (504b), this configuration is not limited to this. For example, it may be configured such that only the gate driver (504a) is formed, and a separate source driver circuit is formed on a substrate (e.g., a driving circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film).

[0432] In addition, the plurality of pixel circuits (501) shown in (A) of FIG. 28 can be configured, for example, as shown in (B) of FIG. 28.

[0433] The pixel circuit (501) illustrated in (B) of FIG. 28 has a liquid crystal element (570), a transistor (550), and a capacitance element (560). The transistor (550) may be a transistor as described in the above-described embodiment.

[0434] The potential of one of the pair of electrodes of the liquid crystal element (570) is appropriately set according to the specifications of the pixel circuit (501). The orientation state of the liquid crystal element (570) is set according to the recorded data. In addition, a common potential may be supplied to one of the pair of electrodes of the liquid crystal element (570) of each of the plurality of pixel circuits (501). In addition, a different potential may be supplied to one of the pair of electrodes of the liquid crystal element (570) of each row of pixel circuits (501).

[0435] For example, as a driving method for a display device equipped with a liquid crystal element (570), TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may be used. In addition, as a driving method for a display device, in addition to the driving methods described above, ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest host mode, etc. However, it is not limited thereto, and various liquid crystal elements and driving methods thereof may be used.

[0436] In the pixel circuit (501) of the m-th row and n-th column, one of the source electrode and drain electrode of the transistor (550) is electrically connected to the data line (DL_n), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element (570). Additionally, the gate electrode of the transistor (550) is electrically connected to the scan line (GL_m). The transistor (550) has the function of controlling the recording of data of the data signal.

[0437] One of the pair of electrodes of the capacitive element (560) is electrically connected to a wire (hereinafter, potential supply line (VL)) to which potential is supplied, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element (570). In addition, the value of the potential of the potential supply line (VL) is appropriately set according to the specifications of the pixel circuit (501). The capacitive element (560) has the function of a retention capacity that retains recorded data.

[0438] For example, in a display device having a pixel circuit (501) of (B) of FIG. 28, for example, each row of pixel circuits (501) is sequentially selected by a gate driver (504a) shown in (A) of FIG. 28, and the transistor (550) is turned on to record data of a data signal.

[0439] The pixel circuit (501) in which data is recorded is maintained by turning off the transistor (550). By performing this sequentially for each row, an image can be displayed.

[0440] In addition, the plurality of pixel circuits (501) shown in (A) of FIG. 28 can be configured, for example, as shown in (C) of FIG. 28.

[0441] The pixel circuit (501) illustrated in (C) of FIG. 28 has a transistor (552), a transistor (554), a capacitive element (562), and a light-emitting element (572). A transistor shown in the above-described embodiment may be applied to either one or both of the transistor (552) and the transistor (554).

[0442] One of the source electrode and drain electrode of the transistor (552) is electrically connected to a wire (hereinafter referred to as the data line (DL_n)) through which a data signal is supplied. Additionally, the gate electrode of the transistor (552) is electrically connected to a wire (hereinafter referred to as the scan line (GL_m)) through which a gate signal is supplied.

[0443] The transistor (552) has the function of controlling the recording of data of the data signal.

[0444] One of the pair of electrodes of the capacitance element (562) is electrically connected to a wire to which potential is supplied (hereinafter referred to as the potential supply line (VL_a)), and the other is electrically connected to the other of the source electrode and drain electrode of the transistor (552).

[0445] The capacitance element (562) has the function of a retention capacity that holds the recorded data.

[0446] One of the source electrode and drain electrode of the transistor (554) is electrically connected to the potential supply line (VL_a). Additionally, the gate electrode of the transistor (554) is electrically connected to the other of the source electrode and drain electrode of the transistor (552).

[0447] One of the positive and negative electrodes of the light-emitting element (572) is electrically connected to the potential supply line (VL_b), and the other is electrically connected to the other of the source electrode and drain electrode of the transistor (554).

[0448] As for the light-emitting element (572), for example, an organic electroluminescent element (also called an organic EL element) may be used. However, the light-emitting element (572) is not limited to this, and an inorganic EL element made of an inorganic material may be used.

[0449] In addition, a high power potential (VDD) is supplied to one of the potential supply lines (VL_a) and (VL_b), and a low power potential (VSS) is supplied to the other.

[0450] In a display device having a pixel circuit (501) of (C) of FIG. 28, for example, each row of pixel circuits (501) is sequentially selected by a gate driver (504a) shown in (A) of FIG. 28, and the transistor (552) is turned on to record data of a data signal.

[0451] The pixel circuit (501) in which data is recorded is maintained by turning off the transistor (552). Additionally, the amount of current flowing between the source electrode and the drain electrode of the transistor (554) is controlled according to the potential of the recorded data signal, and the light-emitting element (572) emits light with brightness corresponding to the amount of current flowing. By performing this sequentially for each row, an image can be displayed.

[0452] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0453] (Embodiment 5)

[0454] In this embodiment, an example of a circuit configuration applicable to the transistor described in the above embodiment will be explained with reference to FIGS. 29 to 32.

[0455] In addition, in this embodiment, a transistor having an oxide semiconductor as described in the above embodiment is referred to as an OS transistor and is described below.

[0456] <Example of Inverter Circuit Configuration>

[0457] FIG. 29 (A) illustrates a circuit diagram of an inverter that can be applied to a shift register or buffer, etc., of a driving circuit. The inverter (800) outputs a signal to an output terminal (OUT) in which the logic of a signal supplied to an input terminal (IN) is inverted. The inverter (800) has a plurality of OS transistors. Signal (S BG ) is a signal that can switch the electrical characteristics of the OS transistor.

[0458] Figure 29 (B) is an example of an inverter (800). The inverter (800) has an OS transistor (810) and an OS transistor (820). Since the inverter (800) can be manufactured using only n-channel transistors, it can be manufactured at a lower cost compared to the case where an inverter (CMOS inverter) is manufactured using CMOS (Complementary Metal Oxide Semiconductor).

[0459] In addition, the inverter (800) having an OS transistor may be placed on a CMOS composed of a Si transistor. Since the inverter (800) can be placed superimposed on the circuit of the CMOS, the increase in circuit area caused by the addition of the inverter (800) can be suppressed.

[0460] The OS transistor (810, 820) has a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of a source and a drain.

[0461] The first gate of the OS transistor (810) is connected to the second terminal. The second gate of the OS transistor (810) is connected to the signal (S BG It is connected to a wiring that supplies ). The first terminal of the OS transistor (810) is connected to a wiring that supplies voltage (VDD). The second terminal of the OS transistor (810) is connected to an output terminal (OUT).

[0462] The first gate of the OS transistor (820) is connected to the input terminal (IN). The second gate of the OS transistor (820) is connected to the input terminal (IN). The first terminal of the OS transistor (820) is connected to the output terminal (OUT). The second terminal of the OS transistor (820) is connected to a wire that supplies voltage (VSS).

[0463] Figure 29 (C) is a timing chart for explaining the operation of the inverter (800). In the timing chart of Figure 29 (C), the signal waveform of the input terminal (IN), the signal waveform of the output terminal (OUT), and the signal (S BG The signal waveform of ) and the change in the threshold voltage of the OS transistor (810) were illustrated.

[0464] signal(S BG The threshold voltage of the OS transistor (810) can be controlled by supplying ) to the second gate of the OS transistor (810).

[0465] signal(S BG ) is the voltage (V) required to negatively shift the threshold voltage. BG_A ), voltage for positively shifting the threshold voltage (V BG_B It has a voltage (V) on the second gate. BG_A By supplying ), the threshold voltage of the OS transistor (810) is the threshold voltage (V TH_A It can be negatively shifted by ). Also, the voltage (V) on the second gate BG_B By supplying ), the threshold voltage of the OS transistor (810) is the threshold voltage (V TH_B It can be positively shifted to ).

[0466] To visualize the above explanation, Figure 30 (A) shows the Id-Vg curve, which is one of the electrical characteristics of a transistor.

[0467] The electrical characteristics of the OS transistor (810) described above are such that the voltage of the second gate is the voltage (V BG_A By making it larger as shown in ), it can be shifted to the curve illustrated by the dashed line (840) in (A) of FIG. 30. In addition, the electrical characteristics of the above-described OS transistor (810) allow the voltage of the second gate to be the voltage (V BG_B By making it smaller as shown in ), it can be shifted to the curve illustrated by the solid line (841) in (A) of FIG. 30. As illustrated in (A) of FIG. 30, the OS transistor (810) is the signal (S BG ) voltage (V BG_A ) or voltage (V BG_B By switching to ), the threshold voltage can be positively or negatively shifted.

[0468] The threshold voltage is the threshold voltage (V TH_B By shifting the OS transistor (810) to a positive position, it is possible to make it difficult for current to flow. This state is visualized in (B) of FIG. 30.

[0469] As shown in (B) of FIG. 30, the current (I) flowing through the OS transistor (810) B ) can be made very small. Therefore, when the signal supplied to the input terminal (IN) is at a high level and the OS transistor (820) is in the ON state, the voltage at the output terminal (OUT) can be steeply lowered.

[0470] As shown in (B) of FIG. 30, since it is possible to make it difficult for current to flow through the OS transistor (810), the signal waveform (831) of the output terminal in the timing chart shown in (C) of FIG. 29 can be changed steeply. Since the through current flowing between the wiring supplying voltage (VDD) and the wiring supplying voltage (VSS) can be reduced, operation with low power consumption can be performed.

[0471] In addition, the threshold voltage is the threshold voltage (V TH_A By shifting the OS transistor (810) negatively, the OS transistor (810) can be made into a state where current flows easily. This state is visualized in (C) of FIG. 30. As shown in (C) of FIG. 30, the current (I) flowing at this time A ) at least current (I B It can be made larger than ). Therefore, when the signal supplied to the input terminal (IN) is at a low level and the OS transistor (820) is in the off state (OFF), the voltage at the output terminal (OUT) can be steeply increased. As shown in (C) of FIG. 30, since it is possible to make it easy for current to flow through the OS transistor (810), the signal waveform (832) at the output terminal in the timing chart shown in (C) of FIG. 29 can be steeply changed.

[0472] Also, the signal (S BG It is preferable to control the threshold voltage of the OS transistor (810) by means of ) before the state of the OS transistor (820) is switched, that is, before time (T1) or time (T2). For example, as shown in (C) of FIG. 29, the threshold voltage (V) is controlled before time (T1) when the signal supplied to the input terminal (IN) switches to a high level. TH_A At the threshold voltage (V) TH_B It is preferable to switch the threshold voltage of the OS transistor (810) to ). Additionally, as shown in (C) of FIG. 29, the threshold voltage (V) is switched to a low level before the time (T2) when the signal supplied to the input terminal (IN) is switched to a low level. TH_B At the threshold voltage (V) TH_A It is desirable to switch the threshold voltage of the OS transistor (810) to ).

[0473] In addition, in the timing chart of (C) in FIG. 29, depending on the signal supplied to the input terminal (IN), the signal (S BG Although a configuration for switching the voltage is shown, other configurations may be used. For example, the voltage for controlling the threshold voltage may be maintained at the second gate of the OS transistor (810) in a floating state. An example of a circuit configuration capable of implementing the above configuration is shown in (A) of FIG. 31.

[0474] In FIG. 31 (A), an OS transistor (850) is included in addition to the circuit configuration shown in FIG. 29 (B). The first terminal of the OS transistor (850) is connected to the second gate of the OS transistor (810). Additionally, the second terminal of the OS transistor (850) is connected to the voltage (V BG_B )(or voltage(V BG_A It is connected to the wiring that supplies )). The first gate of the OS transistor (850) is connected to the signal (S F It is connected to the wiring supplying ). The second gate of the OS transistor (850) is connected to the voltage (V BG_B )(or voltage(V BG_A It is connected to the wiring that supplies )).

[0475] The operation of (A) in Fig. 31 will be explained with reference to the timing chart of (B) in Fig. 31.

[0476] The voltage for controlling the threshold voltage of the OS transistor (810) is configured to be supplied to the second gate of the OS transistor (810) before the time (T3) at which the signal supplied to the input terminal (IN) switches to a high level. F By setting ) to a high level, the OS transistor (850) is turned on, and the node (N BG Voltage (V) for controlling the threshold voltage at ) BG_B supplies ).

[0477] Node(N BG ) is voltage (V BG_B After it becomes ), the OS transistor (850) is turned off. Since the OS transistor (850) has a very small off current, it is kept in the off state so that once the node (N) is formed BG The threshold voltage (V) maintained at ) BG_B ) can be maintained. Therefore, the voltage (V) at the second gate of the OS transistor (850) can be maintained. BG_B Since the number of operations supplying ) is reduced, the voltage (V BG_B The power consumption can be reduced to the extent required for re-recording.

[0478] In addition, the circuit configurations of FIG. 29 (B) and FIG. 31 (A) illustrate a configuration in which the voltage supplied to the second gate of the OS transistor (810) is supplied by external control, but other configurations may be used. For example, a configuration may be used in which a voltage for controlling the threshold voltage is generated based on a signal supplied to the input terminal (IN) and supplied to the second gate of the OS transistor (810). An example of a circuit configuration capable of implementing the above configuration is illustrated in FIG. 32 (A).

[0479] In FIG. 32 (A), a CMOS inverter (860) is provided between the input terminal (IN) and the second gate of the OS transistor (810) in the circuit configuration shown in FIG. 29 (B). The input terminal of the CMOS inverter (860) is connected to the input terminal (IN). The output terminal of the CMOS inverter (860) is connected to the second gate of the OS transistor (810).

[0480] The operation of (A) in Fig. 32 will be explained with reference to the timing chart of (B) in Fig. 32. The timing chart of (B) in Fig. 32 illustrates the signal waveform of the input terminal (IN), the signal waveform of the output terminal (OUT), the output waveform (IN_B) of the CMOS inverter (860), and the change in the threshold voltage of the OS transistor (810).

[0481] The output waveform (IN_B), which is a signal with the logic of the signal supplied to the input terminal (IN) inverted, can be used as a signal to control the threshold voltage of the OS transistor (810). Thus, the threshold voltage of the OS transistor (810) can be controlled as described in (A) to (C) of FIG. 30. For example, when time (T4) in FIG. 32 (B) arrives, the OS transistor (820) is turned on when the signal supplied to the input terminal (IN) is at a high level. At this time, the output waveform (IN_B) becomes a low level. Therefore, the OS transistor (810) can be made into a state where current does not flow, and the rise of the voltage at the output terminal (OUT) can be steeply lowered.

[0482] Additionally, when the time (T5) at (B) in Fig. 32 is reached, if the signal supplied to the input terminal (IN) is at a low level, the OS transistor (820) is turned off. At this time, the output waveform (IN_B) becomes at a high level. Therefore, the OS transistor (810) can be made to a state where current flows easily, and the voltage of the output terminal (OUT) can be raised steeply.

[0483] As described above, in the configuration of the present embodiment, the voltage of the back gate of an inverter having an OS transistor is switched according to the logic of the signal at the input terminal (IN). By configuring it as above, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor by the signal supplied to the input terminal (IN), the voltage at the output terminal (OUT) can be changed steeply. In addition, the through-current between the wires supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.

[0484] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0485] (Embodiment 6)

[0486] In this embodiment, an example of a semiconductor device using a transistor (OS transistor) having an oxide semiconductor as described in the above embodiment in a plurality of circuits is described with reference to FIGS. 33 to 36.

[0487] <Example of Circuit Configuration for Semiconductor Devices>

[0488] Figure 33 (A) is a block diagram of a semiconductor device (900). The semiconductor device (900) has a power circuit (901), a circuit (902), a voltage generation circuit (903), a circuit (904), a voltage generation circuit (905), and a circuit (906).

[0489] The power circuit (901) has a reference voltage (V ORG It is a circuit that generates ). Voltage (V ORG ) may be multiple voltages, not just a single voltage. Voltage (V ORG ) can be generated based on a voltage (V0) supplied from outside the semiconductor device (900). The semiconductor device (900) generates a voltage (V) based on a single power supply voltage supplied from outside. ORG It can generate ). Therefore, the semiconductor device (900) can operate without receiving multiple power supply voltages from the outside.

[0490] Circuit (902), circuit (904), and circuit (906) are circuits that operate with different power supply voltages. For example, the power supply voltage of circuit (902) is voltage (V ORG ) and voltage (V SS )(V ORG >V SS It is a voltage applied by ). Also, for example, the power supply voltage of the circuit (904) is a voltage (V POG ) and voltage (V SS )(V POG >V ORG It is a voltage applied by ). Also, for example, the power supply voltage of the circuit (906) is a voltage (V ORG ) and voltage (V NEG )(V ORG >V SS >V NEG It is the voltage applied based on ). Also, the voltage (V SS If ) is made equipotential with ground (GND), the type of voltage generated in the power circuit (901) can be reduced.

[0491] The voltage generating circuit (903) is a voltage (V POG It is a circuit that generates ). The voltage generating circuit (903) is a voltage (V) supplied from the power supply circuit (901). ORG Based on ), voltage (V POG It can generate ). Therefore, the semiconductor device (900) having the circuit (904) can operate based on a single power supply voltage supplied from the outside.

[0492] The voltage generating circuit (905) is a voltage (V NEG It is a circuit that generates ). The voltage generating circuit (905) is a voltage (V) supplied from the power supply circuit (901). ORG Based on ), voltage (V NEG It can generate ). Therefore, the semiconductor device (900) having the circuit (906) can operate based on a single power supply voltage supplied from the outside.

[0493] (B) of FIG. 33 is the voltage (V POG (904) is an example of a circuit that operates as shown in FIG. 33, and (C) is an example of a waveform of a signal for operating the circuit (904).

[0494] In FIG. 33 (B), a transistor (911) is shown. The signal supplied to the gate of the transistor (911) is, for example, a voltage (V POG ) and voltage (V SS It is generated based on ). When this signal operates to make the transistor (911) conduct, the voltage (V POG As ), when operating in a non-conduction state, the voltage (V SS Set as ). Voltage (V POG ) is the voltage (V) as shown in (C) of FIG. 33. ORG It is larger than ). Therefore, the transistor (911) can more reliably perform the operation of making the source (S) and drain (D) conduct. As a result, the circuit (904) can be made into a circuit with reduced malfunction.

[0495] (D) of FIG. 33 is the voltage (V NEG (E) of FIG. 33 is an example of a circuit (906) that operates as such, and (E) of FIG. 33 is an example of a waveform of a signal for operating the circuit (906).

[0496] In Fig. 33 (D), a transistor (912) having a back gate is illustrated. The signal supplied to the gate of the transistor (912) is, for example, a voltage (V ORG ) and voltage (V SS It is generated based on ). When this signal operates to make the transistor (911) conduct, the voltage (V ORG As ), when operating in a non-conduction state, the voltage (V SS ) is used. Also, the voltage supplied to the back gate of the transistor (912) is the voltage (V NEG It is generated based on ). Voltage (V NEG ) is the voltage (V) as shown in (E) of FIG. 33. SS It is smaller than (GND). Therefore, the threshold voltage of the transistor (912) can be controlled to be positively shifted. Therefore, the transistor (912) can be more reliably kept in a non-conducting state, and the current flowing between the source (S) and the drain (D) can be reduced. As a result, the circuit (906) can be made into a circuit with reduced malfunction and low power consumption.

[0497] Also, voltage (V NEG ) may be configured to be supplied directly to the back gate of the transistor (912). Alternatively, the voltage (V ORG ) and voltage (V NEG It may be configured to generate a signal supplied to the gate of the transistor (912) based on ), and supply this signal to the back gate of the transistor (912).

[0498] Additionally, variations of (D) and (E) of Fig. 33 are shown in (A) and (B) of Fig. 34.

[0499] In the circuit diagram illustrated in FIG. 34 (A), a transistor (922) is shown located between the voltage generation circuit (905) and the circuit (906) and can control the conduction state by the control circuit (921). The transistor (922) is an n-channel type OS transistor. A control signal (S) output by the control circuit (921) BG ) is a signal that controls the conduction state of the transistor (922). Also, the transistor (912A) and transistor (912B) of the circuit (906) are OS transistors like the transistor (922).

[0500] In the timing chart of (B) in Fig. 34, the control signal (S BG ) and the state of the potential of the back gate of transistor (912A) and transistor (912B) at the node (N BG It was plotted as a change in the potential of ). Control signal (S BG When ) is at a high level, the transistor (922) becomes conductive, and the node (N BG ) is voltage (V NEG It becomes ). Afterwards, the control signal (S BG Node(N) when ) is at the row level BG ) becomes electrically floating. Since the transistor (922) is an OS transistor, the off-current is low. Therefore, the node (N BG Even if ) becomes electrically floating, once supplied voltage (V NEG Can maintain ).

[0501] Additionally, FIG. 35 (A) illustrates an example of a circuit configuration applicable to the voltage generation circuit (903) described above. The voltage generation circuit (903) illustrated in FIG. 35 (A) is a five-stage charge pump having diodes (D1) to (D5), capacitance elements (C1) to (C5), and an inverter (INV). A clock signal (CLK) is supplied directly to the capacitance elements (C1) to (C5) or through the inverter (INV). The power supply voltage of the inverter (INV) is the voltage (V ORG ) and voltage (V SS If the voltage applied based on ) is used, the voltage (V) by the clock signal (CLK) ORG Voltage boosted to 5 times the positive voltage (V POG ) can be obtained. In addition, the forward voltage of diodes (D1) to (D5) was set to 0V. Also, by changing the stage of the charge pump, the desired voltage (V) can be obtained. POG You can obtain ).

[0502] Additionally, FIG. 35 (B) illustrates an example of a circuit configuration applicable to the voltage generation circuit (905) described above. The voltage generation circuit (905) of FIG. 35 (B) is a four-stage charge pump having diodes (D1) to (D5), capacitance elements (C1) to (C5), and an inverter (INV). A clock signal (CLK) is supplied directly to the capacitance elements (C1) to (C5) or through the inverter (INV). The power supply voltage of the inverter (INV) is a voltage (V ORG ) and voltage (V SS If the voltage applied by ) is used, then ground, i.e., voltage (V) by the clock signal (CLK). SS Voltage (V) at ) ORG Voltage stepped down to a negative voltage four times that of (V NEG ) can be obtained. In addition, the forward voltage of diodes (D1) to (D5) was set to 0V. Also, by changing the stage of the charge pump, the desired voltage (V) can be obtained. NEG You can obtain ).

[0503] In addition, the circuit configuration of the voltage generation circuit (903) described above is not limited to the configuration of the circuit diagram shown in (A) of FIG. 35. For example, variations of the voltage generation circuit (903) are shown in FIG. 36 (A) to FIG. 36 (C). In addition, variations of the voltage generation circuit (903) can be realized in the voltage generation circuits (903A) to (903C) shown in FIG. 36 (A) to FIG. 36 (C) by changing the voltage supplied to each wiring or by changing the arrangement of the elements.

[0504] The voltage generation circuit (903A) illustrated in (A) of FIG. 36 has transistors (M1) to (M10), capacitance elements (C11) to (C14), and an inverter (INV1). A clock signal (CLK) is supplied directly to the gates of transistors (M1) to (M10) or through the inverter (INV1). By the clock signal (CLK), a voltage (V ORG Voltage boosted to four times the positive voltage (V POG ) can be obtained. In addition, by changing the number of stages, the desired voltage (V POG ) can be obtained. The voltage generation circuit (903A) illustrated in (A) of FIG. 36 can reduce the off-current by making transistors (M1) to (M10) OS transistors, and can suppress the leakage of charge maintained in capacitive elements (C11) to (C14). Therefore, the voltage (V ORG Voltage (V) at ) POG It can efficiently boost the voltage using ).

[0505] The voltage generation circuit (903B) illustrated in (B) of FIG. 36 has transistors (M11) through (M14), capacitance elements (C15) and (C16), and an inverter (INV2). A clock signal (CLK) is supplied directly to the gates of transistors (M11) through (M14) or through the inverter (INV2). By the clock signal (CLK), a voltage (V ORG ) and voltage (V SS Voltage boosted to twice the difference (V POG ) can be obtained. The voltage generation circuit (903B) illustrated in (B) of FIG. 36 can lower the off-current by making transistors (M11) to (M14) OS transistors, thereby suppressing the leakage of charge maintained in capacitive elements (C15) and (C16). Therefore, the voltage (V ORG Voltage (V) at ) POG It can efficiently boost the voltage using ).

[0506] Additionally, the voltage generation circuit (903C) illustrated in (C) of FIG. 36 has an inductor (Ind1), a transistor (M15), a diode (D6), and a capacitance element (C17). The conduction state of the transistor (M15) is controlled by a control signal (EN). By the control signal (EN), the voltage (V ORG ) boosted voltage (V POG ) can be obtained. Since the voltage generation circuit (903C) shown in (C) of FIG. 36 uses an inductor (Ind1) to boost the voltage, the voltage can be boosted with high conversion efficiency.

[0507] As explained above, in the configuration of the present embodiment, the voltage required for the circuit of the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the number of power supply voltages supplied from the outside.

[0508] The above configurations described in the present embodiment may be used in appropriate combination with configurations described in other embodiments.

[0509] (Embodiment 7)

[0510] In this embodiment, a display module and an electronic device having a semiconductor device of one form of the present invention will be described with reference to FIGS. 37 to 40.

[0511] <Display Module>

[0512] The display module (7000) illustrated in FIG. 37 has a touch panel (7004) connected to an FPC (7003), a display panel (7006) connected to an FPC (7005), a backlight (7007), a frame (7009), a printed circuit board (7010), and a battery (7011) between the upper cover (7001) and the lower cover (7002).

[0513] One form of the semiconductor device of the present invention can be used, for example, in a display panel (7006).

[0514] The upper cover (7001) and lower cover (7002) can have their shape or dimensions appropriately changed to fit the size of the touch panel (7004) and display panel (7006).

[0515] The touch panel (7004) may be used by overlaying a resistive or capacitive touch panel on the display panel (7006). Additionally, a touch panel function may be added to the opposing substrate (sealed substrate) of the display panel (7006). Furthermore, a light sensor may be provided within each pixel of the display panel (7006), and it may be made into an optical touch panel.

[0516] The backlight (7007) has a light source (7008). In addition, although FIG. 37 illustrates a configuration in which the light source (7008) is placed above the backlight (7007), it is not limited thereto. For example, the light source (7008) may be placed at the end of the backlight (7007) and a light diffuser may be used. In addition, in the case of using a self-emissive light-emitting element such as an organic EL element, or a reflective panel, the backlight (7007) may not be provided.

[0517] In addition to the protective function of the display panel (7006), the frame (7009) has the function of an electromagnetic shield to block electromagnetic waves generated by the operation of the printed circuit board (7010). Furthermore, the frame (7009) may also have the function of a heat sink.

[0518] The printed circuit board (7010) has a power circuit, a video signal, and a signal processing circuit for outputting a clock signal. As the power source supplying power to the power circuit, it may be an external commercial power source or a power source provided separately from a battery (7011). The battery (7011) may be omitted if commercial power is used.

[0519] In addition, the display module (7000) may be provided with additional components such as a polarizing plate, a phase difference plate, and a prism sheet.

[0520] <Electronic Device 1>

[0521] Next, an example of an electronic device is illustrated in FIGS. 38 (A) to FIGS. 38 (E).

[0522] Figure 38 (A) is a drawing showing the exterior of a camera (8000) with a finder (8100) mounted.

[0523] The camera (8000) has a housing (8001), a display (8002), an operation button (8003), a shutter button (8004), etc. Additionally, the camera (8000) is equipped with a detachable lens (8006).

[0524] Here, the camera (8000) is configured so that the lens (8006) can be detached from the housing (8001) and replaced, but the lens (8006) and the housing may be integrated.

[0525] The camera (8000) can take a picture by pressing the shutter button (8004). Additionally, the display unit (8002) functions as a touch panel, and can also take a picture by touching the display unit (8002).

[0526] The housing (8001) of the camera (8000) has a mount having electrodes, and can connect a strobe device, etc., in addition to the finder (8100).

[0527] The finder (8100) has a housing (8101), a display (8102), a button (8103), etc.

[0528] The housing (8101) has a mount that combines with the mount of the camera (8000), and can mount the finder (8100) to the camera (8000). Additionally, the mount has an electrode, and can display images received from the camera (8000) on the display unit (8102) through the electrode.

[0529] The button (8103) functions as a power button. The on / off status of the display unit (8102) can be switched by the button (8103).

[0530] A display device that is one form of the present invention can be applied to the display portion (8002) of the camera (8000) and the display portion (8102) of the finder (8100).

[0531] In addition, in (A) of FIG. 38, the camera (8000) and the finder (8100) are separate electronic devices and are configured to be detachable, but the finder equipped with a display device may be built into the housing (8001) of the camera (8000).

[0532] Figure 38 (B) is a drawing showing the exterior of a head-mounted display (8200).

[0533] The head-mounted display (8200) has a mounting part (8201), a lens (8202), a main body (8203), a display part (8204), and a cable (8205), etc. Additionally, a battery (8206) is built into the mounting part (8201).

[0534] The cable (8205) supplies power from the battery (8206) to the main body (8203). The main body (8203) is equipped with a wireless receiver, etc., and can display image information, such as received image data, on the display unit (8204). In addition, the movement of the user's eyeball or eyelid is detected by a camera provided in the main body (8203), and the coordinates of the user's viewpoint are calculated based on that information, thereby allowing the user's viewpoint to be used as an input means.

[0535] Additionally, the mounting portion (8201) may be provided with a plurality of electrodes at a position that contacts the user. The main body (8203) may have a function of recognizing the user's viewpoint by detecting the current flowing through the electrodes according to the movement of the user's eyeballs. Additionally, it may have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. Furthermore, the mounting portion (8201) may have various sensors such as a temperature sensor, a pressure sensor, and an accelerometer, and may have a function of displaying the user's biometric information on the display portion (8204). Additionally, it may detect the movement of the user's head, etc., and change the image displayed on the display portion (8204) in accordance with that movement.

[0536] A display device that is one form of the present invention can be applied to the display unit (8204).

[0537] Figures 38 (C), (D), and (E) are drawings illustrating the appearance of a head-mounted display (8300).

[0538] The head-mounted display (8300) has a housing (8301), a display unit (8302), a band-shaped fixture (8304), and a pair of lenses (8305).

[0539] The user can recognize the display of the display unit (8302) through the lens (8305). Additionally, it is preferable to position the display unit (8302) in a curved shape. By positioning the display unit (8302) in a curved shape, the user can experience a high sense of realism.

[0540] A display device having one form of the present invention can be applied to the display unit (8302). Since the display device having one form of the present invention can have very high clarity, even when magnified using a lens (8305) as in (E) of FIG. 38, pixels are not recognized by the user, and a more realistic image can be displayed.

[0541] <Electronic Devices 2>

[0542] Next, an example of an electronic device different from the electronic device shown in FIGS. 38 (A) to FIGS. 38 (E) is shown in FIGS. 39 (A) to FIGS. 39 (G).

[0543] The electronic device illustrated in FIG. 39 (A) to FIG. 39 (G) has a housing (9000), a display unit (9001), a speaker (9003), an operation key (9005) (including a power switch or an operation switch), a connection terminal (9006), a sensor (9007) (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, longitude, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, smell, or infrared), a microphone (9008), etc.

[0544] The electronic device illustrated in FIGS. 39 (A) to FIGS. 39 (G) has various functions. For example, it may have a function to display various information (still images, video, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to connect to various computer networks using a wireless communication function, a function to perform transmission or reception of various data using a wireless communication function, and a function to read programs or data recorded on a recording medium and display them on a display unit. Furthermore, the functions that the electronic device illustrated in FIGS. 39 (A) to FIGS. 39 (G) may have are not limited to these and may have various functions. Additionally, although not illustrated in FIGS. 39 (A) to FIGS. 39 (G), the electronic device may be configured to have a plurality of display units. In addition, this electronic device may be provided with a camera or the like to have a function for capturing still images, a function for capturing video, a function for saving captured images to a recording medium (external or built into the camera), and a function for displaying captured images on a display unit.

[0545] Detailed information regarding the electronic device illustrated in FIGS. 39 (A) to FIGS. 39 (G) will be explained below.

[0546] FIG. 39 (A) is a perspective view illustrating a television device (9100). The television device (9100) may provide a display unit (9001) as a large screen, for example, 50 inches or more, or 100 inches or more.

[0547] FIG. 39 (B) is a perspective view illustrating a portable information terminal (9101). The portable information terminal (9101) has one or more functions selected from, for example, a telephone, a notebook, or an information viewing device. Specifically, it can be used as a smartphone. Additionally, the portable information terminal (9101) may be provided with a speaker (9003), a connection terminal (9006), a sensor (9007), etc. Additionally, the portable information terminal (9101) may display text or image information on its multiple surfaces. For example, three operation buttons (9050) (also called operation icons or simply icons) may be displayed on one surface of the display unit (9001). Additionally, information (9051) illustrated as a dashed rectangle may be displayed on the other surface of the display unit (9001). Additionally, examples of information (9051) include an indication of incoming email, SNS (Social Networking Service), or phone calls, the subject of the email or SNS, the sender's name, date and time, the remaining battery level, and the antenna reception strength. Alternatively, an operation button (9050), etc., may be displayed instead of the information (9051) at the location where the information (9051) is displayed.

[0548] FIG. 39 (C) is a perspective view illustrating a portable information terminal (9102). The portable information terminal (9102) has the function of displaying information on three or more sides of the display unit (9001). Here, an example is illustrated in which information (9052), information (9053), and information (9054) are displayed on different sides. For example, the user of the portable information terminal (9102) can check the display (here, information (9053)) while the portable information terminal (9102) is stored in the chest pocket of clothing. Specifically, the phone number or name of the caller of an incoming call is displayed in a position that can be observed from the top of the portable information terminal (9102). The user can check the display and determine whether to answer the call without taking the portable information terminal (9102) out of the pocket.

[0549] FIG. 39 (D) is a perspective view illustrating a wristwatch-type portable information terminal (9200). The portable information terminal (9200) can execute various applications such as mobile phone, email, text viewing and composition, music playback, internet communication, and computer games. Additionally, the display unit (9001) is provided with a curved display surface and can perform display along the curved display surface. Furthermore, the portable information terminal (9200) can perform short-range wireless communication according to communication standards. For example, hands-free calling can be made through mutual communication with a headset capable of wireless communication. Additionally, the portable information terminal (9200) has a connection terminal (9006) and can directly exchange data with another information terminal through a connector. Additionally, charging can be performed through the connection terminal (9006). Additionally, the charging operation may be performed by wireless power supply without using the connection terminal (9006).

[0550] Figures 39 (E), (F), and (G) are perspective views illustrating a foldable portable information terminal (9201). Additionally, Figure 39 (E) is a perspective view of the portable information terminal (9201) in an unfolded state, Figure 39 (F) is a perspective view of the portable information terminal (9201) in a state of transition from one side of the unfolded or folded state to the other, and Figure 39 (G) is a perspective view of the portable information terminal (9201) in a folded state. The portable information terminal (9201) has excellent portability when folded and excellent visibility of the display with a wide, seamless display area when unfolded. The display unit (9001) of the portable information terminal (9201) is supported by three housings (9000) connected by a hinge (9055). By bending the two housings (9000) together through a hinge (9055), the portable information terminal (9201) can be reversibly deformed from an unfolded state to a folded state. For example, the portable information terminal (9201) can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0551] Additionally, (A) and (B) of FIG. 40 are perspective views of a display device having a plurality of display panels. Also, FIG. 40 (A) is a perspective view of a plurality of display panels in a rolled state, and FIG. 40 (B) is a perspective view of a plurality of display panels in an unfolded state.

[0552] The display device (9500) illustrated in (A) and (B) of FIG. 40 has a plurality of display panels (9501), a shaft portion (9511), and a shaft bearing portion (9512). Additionally, the plurality of display panels (9501) have a display area (9502) and a light-transmitting area (9503).

[0553] Additionally, multiple display panels (9501) are flexible. Additionally, two adjacent display panels (9501) are provided so that a portion of them overlap each other. For example, the light-transmitting areas (9503) of two adjacent display panels (9501) can be overlapped. By using multiple display panels (9501), a large-screen display device can be created. Furthermore, since the display panels (9501) can be rolled up depending on the usage situation, a display device with excellent versatility can be created.

[0554] Additionally, in (A) and (B) of FIG. 40, a state in which the display area (9502) is separated from the adjacent display panel (9501) is illustrated, but it is not limited thereto. For example, the display area (9502) of the adjacent display panel (9501) may be overlapped without gaps to form a continuous display area (9502).

[0555] The electronic device described in this embodiment is characterized by having a display unit for displaying certain information. However, a semiconductor device of one form of the present invention may also be applied to an electronic device that does not have a display unit.

[0556] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0557] (Example 1)

[0558] In this embodiment, the results of measuring sheet resistance and contact resistance for a material that can be used as the gate electrode of a transistor, which is one form of the present invention, are presented.

[0559] The method for preparing the samples used in this embodiment is described below. As samples A1 and A2, thin films were formed using a material that can be used as a second gate electrode, and the sheet resistance of these films was measured. Additionally, as samples A3 to A5, stacked films were formed using a material that can be used as a first gate electrode (also called a bottom gate electrode, BGE) and a material that can be used as a second gate electrode (also called a top gate electrode, TGE), and the contact chain resistance of these stacked films was measured. Furthermore, in this specification, contact chain resistance refers to the resistance value of a device (contact chain) in which contact structures (contact holes) between conductive films are connected in series in a chain shape of 100. In addition, the structures of samples A1 to A5 are shown below.

[0560]

[0561]

[0562] <Preparation of Samples A1 to A5>

[0563] As sample A1, an oxide semiconductor film corresponding to an oxide semiconductor film (112) was formed on a glass substrate. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. In addition, as this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as a sputtering target using a sputtering device, and an AC power source was used as the power source applied to the sputtering target. Subsequently, a conductive film corresponding to a conductive film (114) was formed on this oxide semiconductor film. As this conductive film, a tungsten film with a thickness of 50 nm and a titanium film with a thickness of 100 nm were sequentially formed using a sputtering device.

[0564] As sample A2, an oxide semiconductor film corresponding to an oxide semiconductor film (112) was formed on a glass substrate. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. In addition, as this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as a sputtering target using a sputtering device, and an AC power source was used as the power source applied to this sputtering target.

[0565] As sample A3, a conductive film corresponding to the conductive film (106) was formed on a glass substrate. As this conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were sequentially formed using a sputtering device. Subsequently, an insulating film was formed on this conductive film, and an oxide semiconductor film corresponding to the oxide semiconductor film (112) was formed on the insulating film. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. In addition, as the oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target using a sputtering device, and an AC power source was used as the power source applied to the sputtering target. Subsequently, an opening (contact hole) corresponding to the opening (143) was formed in the insulating film and the oxide semiconductor film. In addition, 100 holes with a diameter of 2.5 μm were made as these openings (contact holes). Subsequently, a conductive film corresponding to the conductive film (114) was formed on the insulating film and oxide semiconductor film having these openings. As this conductive film, a tungsten film with a thickness of 50 nm and a titanium film with a thickness of 100 nm were sequentially formed using a sputtering device. In sample A3, the conductive film corresponding to the conductive film (106) and the conductive film corresponding to the conductive film (114) have a structure having a region in which they are connected in series through 100 openings (contact holes).

[0566] As sample A4, a conductive film corresponding to the conductive film (106) was formed on a glass substrate. As this conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were sequentially formed using a sputtering device. Subsequently, an insulating film was formed on this conductive film, and an opening (contact hole) corresponding to the opening (143) was formed in this insulating film. In addition, 100 holes with a diameter of 2.5 μm were formed as the opening (contact hole). Subsequently, an oxide semiconductor film corresponding to the oxide semiconductor film (112) was formed on the insulating film having this opening. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. In addition, the oxide semiconductor film was formed using a sputtering device with a metal oxide of In:Ga:Zn = 4:2:4.1 [atomic ratio] as the sputtering target, and an AC power source was used as the power source applied to the sputtering target. Subsequently, a conductive film corresponding to the conductive film (114) was formed on the oxide semiconductor film. As the conductive film, a tungsten film with a thickness of 15 nm and a titanium film with a thickness of 100 nm were sequentially formed using a sputtering device. In sample A4, the conductive film corresponding to the conductive film (106) and the oxide semiconductor film corresponding to the oxide semiconductor film (112) have a structure having a region in which they are connected in series through 100 openings (contact holes).

[0567] As sample A5, a conductive film corresponding to the conductive film (106) was formed on a glass substrate. As this conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were sequentially formed using a sputtering device. Subsequently, an insulating film was formed on the conductive film, and an opening (contact hole) corresponding to the opening (143) was formed in the insulating film. In addition, 100 holes with a diameter of 2.5 μm were formed as the opening (contact hole). Subsequently, an oxide semiconductor film corresponding to the oxide semiconductor film (112) was formed on the insulating film having the opening. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. In addition, as this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as a sputtering target using a sputtering device, and an AC power source was used as the power source applied to this sputtering target to form it. In sample A5, the conductive film corresponding to the conductive film (106) and the conductive film corresponding to the oxide semiconductor film (112) have a structure having a region in which they are connected in series through 100 openings (contact holes).

[0568] <Measurement of Sheet Resistance and Contact Chain Resistance>

[0569] The sheet resistance of the above-prepared samples A1 and A2 was measured. The measurement results are shown in Fig. 41. The sheet resistances of samples A1 and A2 were 2.41 Ω / sq. and 508 Ω / sq., respectively.

[0570] That is, sample A1 has a lower sheet resistance than sample A2. In this way, it is suggested that the sheet resistance of the second gate electrode can be reduced by using a structure in which an oxide semiconductor film corresponding to the oxide semiconductor film (112) and a conductive film corresponding to the conductive film (114) are stacked in the second gate electrode.

[0571] In addition, the contact chain resistance of samples A3 to A5 prepared above was measured. The measurement results are shown in Fig. 42. The contact chain resistance of samples A3, A4, and A5 is 3.0 × 10⁻⁶, respectively. 2 Ω, 5.6×10 7 Ω, and 1.9×10 8 It was Ω.

[0572] That is, sample A3 has a lower contact chain resistance than samples A4 and A5. In this way, it is suggested that the contact chain resistance of the first gate electrode and the second gate electrode can be reduced by having a structure in which a region in which a conductive film corresponding to the conductive film (106) and a conductive film corresponding to the conductive film (114) come into contact, and a region in which the first gate electrode and the second gate electrode come into contact.

[0573] The configuration described in this embodiment may be used in appropriate combination with other embodiments or examples.

[0574] (Example 2)

[0575] In this embodiment, a sample corresponding to a transistor, which is one form of the present invention, was prepared, and the electrical characteristics of the transistor and the cross-sectional shape were measured and observed.

[0576] The method for preparing the sample used in this embodiment is described below. In addition, in this embodiment, a sample B1 corresponding to the transistor (100B) shown in (A) and (B) of FIGS. 3 was prepared. Furthermore, in the following description, configurations having the same function as the configuration of the transistor (100B) shown in (A) and (B) of FIGS. 3 are described using the same reference numerals.

[0577] Additionally, for comparison, a sample B2 corresponding to a transistor (100G) in which the second gate electrode does not have a conductive film (114) was also fabricated, as shown in (A) and (B) of FIG. 43. Furthermore, in FIG. 43 (A) and (B), configurations having the same function as the configuration of the transistor (100B) shown in FIG. 3 (A) and (B) are described using the same reference numerals.

[0578] Method of making a transistor

[0579] ≪Preparation of Sample B1≫

[0580] A glass substrate was used as the substrate (102) for producing sample B1. A conductive film (106) was formed on the substrate (102). As the conductive film (106), a tantalum nitride film with a thickness of 10 nm and a copper film with a thickness of 100 nm were sequentially formed using a sputtering device.

[0581] Next, an insulating film (104) was formed on the substrate (102) and the conductive film (106). In addition, in this embodiment, insulating films (104_1), insulating films (104_2), insulating films (104_3), and insulating films (104_4) were sequentially formed continuously in a vacuum using a PECVD device as insulating films (104). In addition, insulating film (104_1) was made of a silicon nitride film with a thickness of 50 nm. In addition, insulating film (104_2) was made of a silicon nitride film with a thickness of 300 nm. In addition, insulating film (104_3) was made of a silicon nitride film with a thickness of 50 nm. In addition, insulating film (104_4) was made of a silicon oxide nitride film with a thickness of 50 nm.

[0582] Next, an oxide semiconductor film was formed on the insulating film (104), and an oxide semiconductor film (108) was formed by processing the oxide semiconductor film into an island shape. As for the oxide semiconductor film (108), an oxide semiconductor film with a thickness of 40 nm was formed. In addition, as for the oxide semiconductor film (108), a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target using a sputtering device, and an AC power source was used as the power source applied to the sputtering target. In addition, a wet etching method was used for processing the oxide semiconductor film (108).

[0583] Next, an insulating film that later becomes an insulating film (110) was formed on the insulating film (104) and the oxide semiconductor film (108). As this insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 100 nm, and a silicon oxynitride film with a thickness of 20 nm were continuously formed in a vacuum using a PECVD device.

[0584] Next, heat treatment was performed. This heat treatment was performed at 350°C for 1 hour under a mixed gas atmosphere of nitrogen and oxygen.

[0585] Next, an oxide semiconductor film, which later becomes an oxide semiconductor film (112), was formed on this insulating film. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 20 nm was formed. In addition, as this oxide semiconductor film, a metal oxide of In:Ga:Zn=5:1:7 [atomic ratio] was used as the sputtering target using a sputtering device, and an AC power source was used as the power source applied to this sputtering target.

[0586] Next, a mask was formed on the oxide semiconductor film, and using this mask, an opening (143) was formed in the oxide semiconductor film, an insulating film in contact with the underside of the oxide semiconductor film, and the insulating film (104). Additionally, a dry etching device was used to process the opening (143).

[0587] Next, a conductive film (114) was formed on an oxide semiconductor film that would later become an oxide semiconductor film (112). As the conductive film, a tungsten film with a thickness of 15 nm and a titanium film with a thickness of 100 nm were sequentially formed using a sputtering device.

[0588] Next, the conductive film (114) and the oxide semiconductor film (112) were formed by processing the above-formed conductive film and oxide semiconductor film into an island shape. In addition, after forming the conductive film (114) and the oxide semiconductor film (112), an insulating film (110) was formed by processing an insulating film that contacts the underside of the oxide semiconductor film (112).

[0589] In addition, a wet etching method was used for processing the conductive film (114) and the oxide semiconductor film (112), and a dry etching method was used for processing the insulating film (110).

[0590] Next, an impurity element addition treatment was performed on the insulating film (104), oxide semiconductor film (108), insulating film (110), oxide semiconductor film (112), and conductive film (114). A doping device was used for the impurity element addition treatment, and argon was used as the impurity element.

[0591] Next, an insulating film (116) was formed on an insulating film (104), an oxide semiconductor film (108), an insulating film (110), an oxide semiconductor film (112), and a conductive film (114). As the insulating film (116), a silicon nitride film with a thickness of 100 nm was formed using a PECVD device.

[0592] Next, an insulating film (118) was formed on the insulating film (116). As the insulating film (118), a silicon nitride film with a thickness of 300 nm was formed using a PECVD device.

[0593] Next, a mask was formed on the insulating film (118), and openings (141a, 141b) were formed in the insulating film (116, 118) using this mask. Additionally, a dry etching device was used to process the openings (141a, 141b).

[0594] Next, an insulating film (122) was formed on the insulating film (118). As the insulating film (122), an acrylic photosensitive resin with a thickness of 1.5 μm was used. Additionally, as the insulating film (122), an opening was provided in an area overlapping with the openings (141a, 141b).

[0595] Next, a conductive film is formed to fill the openings (141a, 141b) on the insulating film (122), and a conductive film (120s, 120d) is formed by processing the conductive film into an island shape.

[0596] As conductive films (120s, 120d), a copper film containing manganese with a thickness of 50 nm and a copper film with a thickness of 100 nm were continuously formed in a vacuum using a sputtering device.

[0597] Sample B1, corresponding to the transistor (100B) shown in (A) and (B) of Fig. 3, was produced by the above process.

[0598] In addition, in this embodiment, the channel width (W) of the sample B1 corresponding to the transistor (100B) was set to 50 μm, and the channel width (L) was set to 2.0 μm, 3.0 μm, and 6.0 μm. Additionally, 20 transistors of each channel width (L) were formed on the substrate.

[0599] ≪Preparation of Sample B2≫

[0600] As with sample B2, a conductive film (106), an insulating film (104), and an oxide semiconductor film (108) were formed on a substrate (102), just like with sample B1.

[0601] Next, an insulating film that later becomes an insulating film (110) was formed on the insulating film (104) and the oxide semiconductor film (108). As this insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 100 nm, and a silicon oxynitride film with a thickness of 20 nm were continuously formed in a vacuum using a PECVD device.

[0602] Next, heat treatment was performed. This heat treatment was performed at 350°C for 1 hour under a mixed gas atmosphere of nitrogen and oxygen.

[0603] Next, a mask was formed on the insulating film, and an opening (143) was formed in the insulating film and the insulating film (104) using this mask. Additionally, a dry etching device was used to process the opening (143).

[0604] Next, an oxide semiconductor film, which later becomes an oxide semiconductor film (112), was formed on this insulating film. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. In addition, as this oxide semiconductor film, a metal oxide of In:Ga:Zn=5:1:7 [atomic ratio] was used as a sputtering target using a sputtering device, and an AC power source was used as the power source applied to this sputtering target.

[0605] Next, an oxide semiconductor film (112) was formed by processing the formed oxide semiconductor film into an island shape. In addition, after forming the oxide semiconductor film (112), an insulating film (110) was formed by processing an insulating film that contacts the lower side of the oxide semiconductor film (112).

[0606] In addition, a wet etching method was used for processing the oxide semiconductor film (112), and a dry etching method was used for processing the insulating film (110).

[0607] Next, an impurity element addition treatment was performed on the insulating film (104), the oxide semiconductor film (108), the insulating film (110), and the oxide semiconductor film (112). A doping device was used for the impurity element addition treatment, and argon was used as the impurity element.

[0608] Next, an insulating film (116) was formed on the insulating film (104), oxide semiconductor film (108), insulating film (110), and oxide semiconductor film (112). As the insulating film (116), a silicon nitride film with a thickness of 100 nm was formed using a PECVD device.

[0609] Next, an insulating film (118) was formed on the insulating film (116). As the insulating film (118), a silicon nitride film with a thickness of 300 nm was formed using a PECVD device.

[0610] Next, a mask was formed on the insulating film (118), and openings (141a, 141b) were formed in the insulating film (116, 118) using this mask. Additionally, a dry etching device was used to process the openings (141a, 141b).

[0611] Next, an insulating film (122) was formed on the insulating film (118). As the insulating film (122), an acrylic photosensitive resin with a thickness of 1.5 μm was used. Additionally, as the insulating film (122), an opening was provided in an area overlapping with the openings (141a, 141b).

[0612] Next, a conductive film is formed to fill the openings (141a, 141b) on the insulating film (122), and a conductive film (120s, 120d) is formed by processing the conductive film into an island shape.

[0613] As conductive films (120s, 120d), a copper film containing manganese with a thickness of 50 nm and a copper film with a thickness of 100 nm were continuously formed in a vacuum using a sputtering device.

[0614] Sample B2, corresponding to the transistor (100G) shown in (A) and (B) of FIG. 43, was produced by the above process.

[0615] In addition, in this embodiment, the channel width (W) of sample B2 corresponding to the transistor (100G) was set to 50 μm, and the channel width (L) was set to 2.0 μm, 3.0 μm, and 6.0 μm. Additionally, 20 transistors of each channel width (L) were formed on the substrate.

[0616] <Evaluation of Transistor Electrical Characteristics>

[0617] FIGS. 44 and FIGS. 45 respectively illustrate the drain current-gate voltage (Id-Vg) characteristics of samples B1 and B2 prepared in this embodiment. In addition, FIG. 44 shows the measurement result of sample B1, and FIG. 45 shows the measurement result of sample B2.

[0618] Additionally, FIG. 44 (A) and FIG. 45 (A) represent characteristics with a channel width of 50 μm and a channel length of 2.0 μm, FIG. 44 (B) and FIG. 45 (B) represent characteristics with a channel width of 50 μm and a channel length of 3.0 μm, and FIG. 44 (C) and FIG. 45 (C) represent characteristics with a channel width of 50 μm and a channel length of 6.0 μm. Furthermore, in FIG. 44 and FIG. 45, the first vertical axis represents Id (A), and the second vertical axis represents the field-effect mobility (μFE (cm²). 2 / Vs)) and the horizontal axis represents Vg(V), respectively.

[0619] In addition, as a measurement condition for the Id-Vg characteristic of the transistor, the voltage applied to the conductive film (106) functioning as the first gate electrode of the transistor (hereinafter also referred to as gate voltage (Vg)), and the voltage applied to the oxide semiconductor film (112) and conductive film (114) functioning as the second gate electrode (hereinafter also referred to as Vbg) were applied in steps of 0.25V from -15V to +20V. In addition, the voltage applied to the conductive film (120s) functioning as the source electrode (hereinafter also referred to as source voltage (Vs)) was set to 0V (comm), and the voltage applied to the conductive film (120d) functioning as the drain electrode (hereinafter also referred to as drain voltage (Vd)) was set to 1V or 10V.

[0620] As shown in FIGS. 44 and 45, samples B1 and B2 produced in this embodiment are shown to have good electrical characteristics, not due to the length of the channel length (L).

[0621] <Regarding Reliability Evaluation in Gate BT Testing>

[0622] Next, reliability evaluation was performed on samples B1 and B2, which were fabricated with a channel width of 50 μm and a channel length of 6.0 μm. For the reliability evaluation, a gate BT (Bias Temperature) test was conducted by applying a stress voltage to the gate electrode. Furthermore, the gate BT test was performed using the four test methods shown below.

[0623] ≪PBTS: Positive Bias Temperature Stress≫

[0624] The gate voltage (Vg) was set to +30V, the drain voltage (Vd) and source voltage (Vs) to 0V (COMMON), the stress temperature to 60℃, the stress application time to 1 hour, and the measurement was performed in a dark environment. That is, the source and drain electrodes of the transistor were set to the same potential, and a potential different from that of the source and drain electrodes was applied to the gate electrode for a certain period of time. In addition, the potential supplied to the gate electrode was higher than the potentials of the source and drain electrodes (applied to the positive side).

[0625] ≪NBTS: Negative Bias Temperature Stress≫

[0626] The gate voltage (Vg) was set to -30V, the drain voltage (Vd) and source voltage (Vs) to 0V (COMMON), the stress temperature to 60℃, the stress application time to 1 hour, and the measurement was performed in a dark environment. That is, the source and drain electrodes of the transistor were set to the same potential, and a potential different from that of the source and drain electrodes was applied to the gate electrode for a certain period of time. In addition, the potential supplied to the gate electrode is lower than the potential of the source and drain electrodes (applied to the negative side).

[0627] ≪PBITS: Positive Bias Illumination Temperature Stress≫

[0628] The gate voltage (Vg) was set to +30V, the drain voltage (Vd) and source voltage (Vs) to 0V (COMMON), the stress temperature to 60℃, the stress application time to 1 hour, and the measurement was performed in a photovoltaic environment (approximately 10,000 Lx with a white LED). That is, the source and drain electrodes of the transistor were set to the same potential, and a potential different from that of the source and drain electrodes was applied to the gate electrode for a certain period of time. In addition, the potential supplied to the gate electrode was higher than the potential of the source and drain electrodes (applied to the positive side).

[0629] ≪NBITS: Negative Bias Illumination Temperature Stress≫

[0630] The gate voltage (Vg) was set to -30V, the drain voltage (Vd) and source voltage (Vs) to 0V (COMMON), the stress temperature to 60℃, the stress application time to 1 hour, and the measurement environment was a photovoltaic environment (approximately 10,000 Lx with a white LED). That is, the source and drain electrodes of the transistor were set to the same potential, and a potential different from that of the source and drain electrodes was applied to the gate electrode for a certain period of time. In addition, the potential supplied to the gate electrode is lower than the potential of the source and drain electrodes (applied to the negative side).

[0631] Furthermore, the Gate BT test is a type of accelerated test that allows for the rapid evaluation of transistor characteristic changes caused by long-term use. In particular, the change in the transistor's threshold voltage (ΔVth) before and after the Gate BT test serves as an important indicator for assessing reliability. The smaller the change in threshold voltage (ΔVth) before and after the Gate BT test, the higher the reliability.

[0632] In addition, ΔVth represents the change in threshold voltage (Vth) and is the value obtained by differing Vth before stress from Vth after stress.

[0633] The gate BT test results of samples B1 and B2 are shown in Fig. 46.

[0634] From the results of FIG. 46, it was found that sample B1 has a smaller variation in the NBITS test than sample B2. This is because sample B1 has a conductive film (114), which prevents light from being irradiated onto the channel region of the oxide semiconductor film (108). Therefore, a configuration having a conductive film (114) is preferred as the second gate electrode.

[0635] <Evaluation of Electrical Characteristics of Transistors Under Light Irradiation>

[0636] Next, the electrical characteristics of the transistors under light irradiation were measured for samples B1 and B2, which were fabricated with a channel length of 6 μm and a channel width of 50 μm. The electrical characteristics of the transistors were defined as the drain current (Id)-gate voltage (Vg) characteristics. For the measurement environment of the electrical characteristics under light irradiation, the stress temperature was set to 60°C, and the light irradiation was performed using a white LED at approximately 10,000 Lx.

[0637] The electrical characteristics of the transistors of samples B1 and B2 are illustrated in FIGS. 47 and 48. FIGS. 47 and 48 show the results obtained by setting the source electrode (Vs) to 0V (comm), the drain voltage (Vd) to 1V and 10V, and applying gate voltages (Vg and Vbg) from -15V to +15V in 0.25V increments. In FIGS. 47 and 48, the vertical axis represents the drain current (Id) and the horizontal axis represents the gate voltage (Vg). FIGS. 47 shows the measurement results of sample B1, and FIGS. 48 shows the measurement results of sample B2. FIGS. 47 (A) and FIGS. 48 (A) show the electrical characteristics of the transistor during light irradiation, while FIGS. 47 (B) and FIGS. 48 (B) show the electrical characteristics of the transistor when light irradiation is not performed.

[0638] In the results of the electrical characteristics shown in FIGS. 47 and 48, the electrical characteristics of the transistor in sample B2 upon light irradiation resulted in an electrical characteristic where the threshold voltage becomes negative (also called a normally-on characteristic). Meanwhile, in sample B1, the electrical characteristics of the transistor even upon light irradiation resulted in an electrical characteristic where the threshold voltage becomes positive (also called a normally-off characteristic). That is, a configuration having a conductive film (114) as a second gate electrode is preferred.

[0639] As described above, a transistor of one embodiment of the present invention can be described as a transistor that has small fluctuations in electrical characteristics and low power consumption even when irradiated with light.

[0640] <Observation of Transistor Cross-section>

[0641] Next, cross-sectional observation was performed on the transistor fabricated above with a channel width of 50 μm and a channel length of 2.0 μm. The results of the cross-sectional observation of the transistor are shown in Figures 49 (A) and (B). Additionally, a transmission electron microscope (TEM) was used for the cross-sectional observation.

[0642] In addition, (A) of FIG. 49 is a cross-section of sample B1, and (B) of FIG. 49 is a cross-section of sample B2, each corresponding to the cross-section in the direction of the dotted line X1-X2 shown in (A) of FIG. 2. In addition, common symbols are indicated for elements corresponding to (A) of FIG. 3 or (A) of FIG. 43.

[0643] As shown in (A) and (B) of FIG. 49, samples B1 and B2 prepared in this embodiment had good cross-sectional shapes. In addition, the second gate electrode width (TGE width) of sample B1 was 1.70 μm. In addition, the second gate electrode width (TGE width) of sample B2 was 1.75 μm.

[0644] For the above, the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0645] (Example 3)

[0646] In this embodiment, the results of evaluating the amount of hydrogen and oxygen emitted are shown for a conductive film that can be used as the second gate electrode of a transistor, which is one form of the present invention.

[0647] As a method to evaluate the amount of hydrogen and oxygen emitted from a conductive film that can be used as a second gate electrode, the thermal degassed gas analysis (TDS) method was used. In the TDS analysis of the conductive film, the amount of hydrogen molecules emitted by the conductive film and the amount of oxygen molecules emitted by the insulating film underneath the conductive film were measured and evaluated.

[0648] First, in order to evaluate the amount of hydrogen released from the conductive film, the following samples C1 to C4 were prepared.

[0649] <Preparation of Samples C1 to C4>

[0650] As sample C1, a tungsten film with a thickness of 30 nm was formed on a glass substrate using a sputtering device.

[0651] For sample C2, a titanium film with a thickness of 30 nm was formed on a glass substrate using a sputtering device.

[0652] As sample C3, a tantalum nitride film with a thickness of 30 nm was formed on a glass substrate using a sputtering device.

[0653] As sample C4, a titanium nitride film with a thickness of 30 nm was formed on a glass substrate using a sputtering device.

[0654] <TDS 분석에 의한 수소 방출량의 평가 1>

[0655] TDS analysis was performed to evaluate the amount of hydrogen molecules released from samples C1 to C4 prepared above. The results of the TDS analysis are shown in (A) to (D) of Fig. 50.

[0656] The amount of hydrogen molecules emitted by various conductive films can be evaluated based on the results of the TDS analysis shown in (A) to (D) of FIG. 50.

[0657] As shown in (A), (C), and (D) of FIG. 50, almost no hydrogen emission was observed in the tungsten film, tantalum nitride film, and titanium nitride film. On the other hand, as shown in (B) of FIG. 50, the emission of many hydrogen molecules was confirmed in the titanium film. Excessive hydrogen emission may cause the oxide semiconductor film in the channel region to become n-type. Therefore, tungsten, tantalum nitride, and titanium nitride are preferred as materials to be used as the conductive film (114).

[0658] Next, samples C5 to C9 were prepared to evaluate the amount of hydrogen permeated by the conductive film.

[0659] <Preparation of Samples C5 to C9>

[0660] For sample C5, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device.

[0661] For sample C6, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a tungsten film with a thickness of 30 nm was formed on the silicon nitride film using a sputtering device.

[0662] For sample C7, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a titanium film with a thickness of 30 nm was formed on the silicon nitride film using a sputtering device.

[0663] For sample C8, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a tantalum nitride film with a thickness of 30 nm was formed on the silicon nitride film using a sputtering device.

[0664] For sample C9, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a titanium nitride film with a thickness of 30 nm was formed on the silicon nitride film using a sputtering device.

[0665] <TDS 분석에 의한 수소 방출량의 평가 2>

[0666] TDS analysis was performed to evaluate the amount of hydrogen molecules released from samples C5 to C9 prepared above. The results of the TDS analysis are shown in (A) to (D) of Figure 51.

[0667] In the results of the TDS analysis shown in Fig. 51, the amount of hydrogen molecules emitted by the silicon nitride film under various conductive films can be evaluated. That is, if the amount of hydrogen molecules emitted by the silicon nitride film is small, it can be seen that the conductive film can block this hydrogen.

[0668] As shown in FIGS. 51 (A) to (D), the release of hydrogen molecules was confirmed in sample C5 (silicon nitride film) at temperatures above 350°C. Meanwhile, as shown in FIGS. 51 (A), no release of hydrogen molecules was confirmed in sample C6 (tungsten film on silicon nitride film) at temperatures between 350°C and 480°C. In other words, it was suggested that hydrogen molecules released by silicon nitride can be blocked by forming a tungsten film on silicon nitride film. Furthermore, as shown in FIGS. 51 (C) and (D), it was confirmed that in sample C8 (tantalum nitride film on silicon nitride film) and sample C9 (titanium nitride film on silicon nitride film), the release of hydrogen molecules was low even at temperatures above 350°C. In other words, it was suggested that hydrogen molecules released by silicon nitride can be blocked by forming a tantalum nitride film or a titanium nitride film on silicon nitride film. However, as shown in (B) of FIG. 51, in sample C7 (titanium film on silicon nitride film), in addition to hydrogen release from the titanium film, the release of many hydrogen molecules at 250°C or higher was confirmed. That is, it was suggested that by forming a tungsten film, a tantalum nitride film, or a titanium nitride film on the silicon nitride film, the hydrogen molecules released by silicon nitride can be blocked. Therefore, tungsten, tantalum nitride, and titanium nitride are preferred as materials to be used as conductive films (114).

[0669] Next, to evaluate the amount of oxygen absorbed by the conductive film, the following samples C10 and C11-1 to C14-2 were prepared.

[0670] <Preparation of Sample C10, and Samples C11-1 to C14-2>

[0671] As sample C10, a silicon nitride oxide film with a thickness of 100 nm was formed on a glass substrate using a PECVD device.

[0672] For sample C11-1, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a tungsten film was formed on the silicon nitride film using a sputtering device. Then, after heat treatment at 250°C for 1 hour, the tungsten film was removed using a wet etching method to expose the silicon nitride film.

[0673] For sample C11-2, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, an oxide semiconductor film with a thickness of 10 nm was formed on the silicon nitride film using a sputtering apparatus. As for this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target, and an AC power source was used to apply power to the sputtering target. Subsequently, a tungsten film was formed on the oxide semiconductor film using a sputtering apparatus. Then, after performing heat treatment at 250°C for 1 hour, the oxide semiconductor film and the tungsten film were removed using a wet etching method to expose the silicon nitride film.

[0674] For sample C12-1, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a titanium film was formed on the silicon nitride film using a sputtering device. Then, after heat treatment at 250°C for 1 hour, the titanium film was removed using a wet etching method to expose the silicon nitride film.

[0675] For sample C12-2, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, an oxide semiconductor film with a thickness of 10 nm was formed on the silicon nitride film using a sputtering apparatus. As for this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target, and an AC power source was used to apply power to the sputtering target. Subsequently, a titanium film was formed on the oxide semiconductor film using a sputtering apparatus. Then, after performing a heat treatment at 250°C for 1 hour, the oxide semiconductor film and the titanium film were removed using a wet etching method to expose the silicon nitride film.

[0676] For sample C13-1, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a tantalum nitride film was formed on the silicon nitride film using a sputtering device. Then, after heat treatment at 250°C for 1 hour, the tantalum nitride film was removed using a wet etching method to expose the silicon nitride film.

[0677] For sample C13-2, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, an oxide semiconductor film with a thickness of 10 nm was formed on the silicon nitride film using a sputtering apparatus. As for this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target, and an AC power source was used to apply power to the sputtering target. Subsequently, a tantalum nitride film was formed on the oxide semiconductor film using a sputtering apparatus. Then, after performing a heat treatment at 250°C for 1 hour, the oxide semiconductor film and the tantalum nitride film were removed using a wet etching method to expose the silicon nitride film.

[0678] For sample C14-1, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a titanium nitride film was formed on the silicon nitride film using a sputtering device. Then, after heat treatment at 250°C for 1 hour, the titanium nitride film was removed using a wet etching method to expose the silicon nitride film.

[0679] For sample C14-2, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD apparatus. Subsequently, an oxide semiconductor film with a thickness of 10 nm was formed on the silicon nitride film using a sputtering apparatus. As for this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target, and an AC power source was used to apply power to the sputtering target. Subsequently, a titanium nitride film was formed on the oxide semiconductor film using a sputtering apparatus. Then, after performing a heat treatment at 250°C for 1 hour, the oxide semiconductor film and the titanium nitride film were removed using a wet etching method to expose the silicon nitride film.

[0680] <TDS 분석에 의한 산소 방출량의 평가>

[0681] TDS analysis was performed to evaluate the amount of oxygen molecules released from the above-prepared samples C10 and C11-1 to C14-2. The results of the TDS analysis are shown in (A) to (E) of Figure 52.

[0682] In the results of the TDS analysis shown in Fig. 52, the amount of oxygen molecules emitted by the silicon nitride film can be evaluated. That is, if the amount of oxygen molecules emitted by the silicon nitride film is small, it can be seen that the conductive film has absorbed the oxygen from the silicon nitride film.

[0683] As shown in Fig. 52 (A), the release of oxygen molecules was confirmed in sample C10 (silicon nitride film). In addition, as shown in Fig. 52 (B) to (E), the release of oxygen molecules was confirmed in samples C11-2, C12-2, C13-2, and C14-2, in which various conductive films were formed after forming an oxide semiconductor film on the silicon nitride film, just as in sample C10. On the other hand, in samples C11-1, C12-1, C13-1, and C14-1, in which various conductive films were formed directly on the silicon nitride film, almost no oxygen molecules were detected in the silicon nitride film.

[0684] In other words, it was suggested that by forming an oxide semiconductor film on a silicon nitride film and forming a conductive film on the oxide semiconductor film, the absorption of oxygen by the conductive film from the silicon nitride can be suppressed.

[0685] By having sufficient oxygen in the insulating film (110), oxygen can be supplied to the oxide semiconductor film in the channel region, thereby reducing oxygen deficiency in the channel region. That is, it is desirable that the insulating film used in the insulating film (110) has a large amount of oxygen release.

[0686] Therefore, as a second gate electrode formed on the insulating film (110), it can be said that a configuration having an oxide semiconductor film and a conductive film is preferable.

[0687] The configuration described in this embodiment may be used in appropriate combination with other embodiments or examples.

[0688] (Example 4)

[0689] In this embodiment, the film damage of the insulating film during the film formation of a conductive film that can be used for the second gate electrode of a transistor, which is one form of the present invention, was evaluated.

[0690] Electron Spin Resonance (ESR) measurements were used to evaluate film damage during the deposition of the conductive film.

[0691] The method for preparing the samples used in this example is described below. In addition, the structures of samples D1-1 to D6-2 are shown below.

[0692]

[0693] <Preparation of Samples D1-1 to D6-2>

[0694] For samples D1-1 and D1-2, an oxide semiconductor film corresponding to an oxide semiconductor film (108) was formed on a quartz substrate. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 40 nm was formed. In addition, as this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target using a sputtering device, and an AC power source was used as the power source applied to the sputtering target. Subsequently, an insulating film corresponding to an insulating film (110) was formed on this oxide semiconductor film. As this insulating film, a silicon nitride film with a thickness of 100 nm was formed. Subsequently, an oxide semiconductor film corresponding to an oxide semiconductor film (112) was formed on this insulating film. As this oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. In addition, as this oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:4.1 was used as the sputtering target using a sputtering device, and an AC power source was used as the power source applied to this sputtering target to form it. Sample D1-2 was fabricated through the above process. In addition, Sample D1-1 was obtained by removing an oxide semiconductor film corresponding to the oxide semiconductor film (112) formed above using a wet etching method.

[0695] Samples D2-1 and D2-2 were fabricated by forming a conductive film equivalent to the conductive film (114) on samples D1-1 and D1-2. As this conductive film, a tungsten film was formed using a sputtering device.

[0696] Samples D3-1 and D3-2 were fabricated by forming a conductive film equivalent to the conductive film (114) on samples D1-1 and D1-2. As this conductive film, a titanium film was formed using a sputtering device.

[0697] Samples D4-1 and D4-2 were prepared by forming a conductive film equivalent to the conductive film (114) on samples D1-1 and D1-2. As this conductive film, a tantalum nitride film was formed using a sputtering device.

[0698] Samples D5-1 and D5-2 were prepared by forming a conductive film equivalent to the conductive film (114) on samples D1-1 and D1-2. As this conductive film, a titanium nitride film was formed using a sputtering device.

[0699] Samples D6-1 and D6-2 were fabricated by forming a conductive film equivalent to the conductive film (114) on samples D1-1 and D1-2. A copper film was formed using a sputtering device as this conductive film.

[0700] <ESR 측정>

[0701] ESR measurements were performed on the above-described samples D1-1 to D6-2. For the ESR measurements, the measurement temperature was set to 85K, the high-frequency power (microwave power) at 8.92 GHz was set to 10 mW, and the direction of the magnetic field was set parallel to the film surface of the fabricated samples. In addition, NO x The detection lower limit of the spin density of the signal attributed to is 1.0×10 16 spins / cm 3 It was. It can be said that the smaller the spin number, the smaller the defect in the insulating film.

[0702] The measured ESR signal is shown in Fig. 53. In addition, the insulating film is an oxide nitride (NO x In the case of having ), NO x There are cases where a signal having three characteristic peaks originating from is observed. These signals having three peaks are observed as a first signal with a g value of 2.037 to 2.039, a second signal with a g value of 2.001 to 2.003, and a third signal with a g value of 1.964 to 1.966. These three signals are NO x Based on this, it is understood to be a signal having a hyperfine structure due to the nuclear spin of N. Also, NO x The signal resulting from this is an asymmetric waveform because the spin species are anisotropic.

[0703] NO in samples D1-1 to D6-2 x The measurement results of the spin density of a signal having three peaks attributable to [the signal] are shown in Fig. 54. In addition, the spin density calculated by converting the measured number of spins into a unit volume is shown here.

[0704] It can be seen that samples D4-1 and D5-1, which do not have an oxide equivalent to an oxide semiconductor film (112) and have tantalum nitride or titanium nitride as a conductive film, are insulating films with a large spin density of a signal having three peaks and a large amount of defects. This is because when forming a conductive film by reactive sputtering using nitrogen, NO x It is thought that this is because NO is generated. Meanwhile, samples D1-2, D2-2, D3-2, D4-2, D5-2, and D6-2, which have oxide semiconductors corresponding to the oxide semiconductor film (112), are NO x The spin density of the signal attributable to it was small and below the lower limit of measurement.

[0705] Thus, it is suggested that damage to the insulating film that occurs when forming a conductive film can be suppressed by forming an oxide semiconductor film (112) on an insulating film (110) corresponding to an insulating film.

[0706] Therefore, as a second gate electrode, it can be said that a configuration having an oxide semiconductor film (112) and a conductive film (114) is preferable.

[0707] The configuration described in this embodiment may be used in appropriate combination with other embodiments or examples.

[0708] (Example 5)

[0709] In this embodiment, the results of evaluating the emission amounts of hydrogen and oxygen for a conductive film that can be used as a second gate electrode of a transistor, which is one form of the present invention, are shown.

[0710] The thermal desalination gas analysis (TDS) method was used to evaluate the amount of hydrogen and oxygen emitted from the conductive film that can be used for the second gate electrode. In the TDS analysis of the conductive film, the amount of hydrogen molecules emitted by the conductive film and the amount of oxygen molecules emitted by the insulating film underneath the conductive film were measured and evaluated.

[0711] First, sample E1 was prepared to evaluate the amount of hydrogen released from the conductive film.

[0712] <Preparation of Sample E1>

[0713] As sample E1, a copper film with a thickness of 50 nm was formed on a glass substrate using a sputtering device.

[0714] <TDS 분석에 의한 수소 방출량의 평가 3>

[0715] TDS analysis was performed to evaluate the amount of hydrogen molecules released from the above-prepared sample E1. The results of the TDS analysis are shown in Fig. 55.

[0716] From the results of the TDS analysis shown in FIG. 55, almost no hydrogen emission was observed in the copper film. Excessive hydrogen emission may cause the oxide semiconductor film in the channel region to become n-type. Therefore, copper can be considered a preferred material for use as the conductive film (114).

[0717] Next, to evaluate the amount of hydrogen permeated by the conductive film, the following samples E2 to E6 were prepared.

[0718] <Preparation of Samples E2 to E6>

[0719] As sample E2, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device.

[0720] For sample E3, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a copper film with a thickness of 100 nm was formed on the silicon nitride film using a sputtering device.

[0721] For sample E4, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a copper film with a thickness of 100 nm was formed on the silicon nitride film using a sputtering device. Subsequently, a titanium film with a thickness of 50 nm was formed on the copper film using a sputtering device.

[0722] For sample E5, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a copper film with a thickness of 100 nm was formed on the silicon nitride film using a sputtering device. Subsequently, a tungsten film with a thickness of 50 nm was formed on the copper film using a sputtering device.

[0723] For sample E6, a silicon nitride film with a thickness of 100 nm was formed on a glass substrate using a PECVD device. Subsequently, a copper film with a thickness of 100 nm was formed on the silicon nitride film using a sputtering device. Subsequently, a titanium nitride film with a thickness of 50 nm was formed on the copper film using a sputtering device.

[0724] <TDS 분석에 의한 수소 방출량의 평가 4>

[0725] TDS analysis was performed to evaluate the amount of hydrogen molecules released from samples E2 to E6 prepared above. The results of the TDS analysis are shown in Figures 56 and 57.

[0726] From the results of the TDS analysis shown in Figures 56 and 57, the amount of oxygen molecules emitted by the silicon nitride film under various conductive films can be evaluated. That is, when the amount of hydrogen molecules emitted by the silicon nitride film is small, it can be seen that the conductive film can block this hydrogen.

[0727] As shown in Fig. 56, the release of hydrogen molecules was confirmed at temperatures above 250°C in sample E2 (silicon nitride film). Meanwhile, in sample E3 (copper film on silicon nitride film), the release of hydrogen molecules was not confirmed up to approximately 350°C. In other words, it was suggested that by forming a copper film on the silicon nitride film, the hydrogen molecules released by silicon nitride can be blocked.

[0728] In addition, as shown in Fig. 57 (B) and (C), it was confirmed that the release of hydrogen molecules was low up to about 350°C in sample E5 (copper film and tungsten film on silicon nitride film) and sample E6 (copper film and titanium nitride film on silicon nitride film). That is, it was suggested that hydrogen molecules released by silicon nitride can be blocked by forming a copper film on silicon nitride film and then forming a tungsten film or titanium nitride film on this copper film. However, as shown in Fig. 57 (A), in sample E4 (copper film and titanium film on silicon nitride film), the release of a large amount of hydrogen molecules was confirmed at 250°C or higher in addition to hydrogen release from the titanium film. That is, it was suggested that hydrogen molecules released by silicon nitride can be blocked by forming a copper film, a tungsten film, and a titanium nitride film on silicon nitride film. Therefore, copper, tungsten, and titanium nitride are preferred materials to be used as the conductive film (114).

[0729] The configuration shown in the above embodiment may be used in appropriate combination with other embodiments or embodiments.

[0730] (Example 6)

[0731] In this embodiment, a sample corresponding to a transistor, which is one form of the present invention, was prepared, and th...

Claims

Claim 1 A semiconductor film having a channel forming region of a transistor; a first insulating film having a region located below the semiconductor film; a first conductive film having an overlap with the channel forming region interposed with the first insulating film; a second insulating film having a region in contact with the upper surface of the semiconductor film; a second conductive film having a region located above the second insulating film and also having a region overlapping with the channel forming region interposed with the second insulating film; a third insulating film having a region in contact with the upper surface of the second conductive film, a region in contact with the side surface of the second conductive film, and a region in contact with the upper surface of the second insulating film, and also having silicon nitride; a fourth insulating film having a region in contact with the upper surface of the third insulating film and also having silicon oxide; a fifth insulating film having a region in contact with the upper surface of the fourth insulating film and also having an organic material; and a region located above the fifth insulating film and also the source of the transistor A third conductive film having a function as either an electrode or a drain electrode, a region in contact with the upper surface of the third conductive film and a region in contact with the upper surface of the fifth insulating film, and a sixth insulating film having an organic material, a region located above the sixth insulating film and a fourth conductive film electrically connected to the third conductive film, and a liquid crystal layer having a region located above the fourth conductive film, wherein the third insulating film has a first opening, the fourth insulating film has a second opening that overlaps with the first opening, and the fifth insulating film has a third opening that overlaps with the first opening and also overlaps with the second opening, wherein in cross-section, the upper end of the second opening and the lower end of the third opening do not coincide, and in cross-section, the diameter of the third opening at the lower end of the third opening is the same as the third at the upper end of the second opening The third conductive film is larger than the diameter of the two openings, and the third conductive film is,A liquid crystal display device having a region in contact with the upper surface of the fifth insulating film and a region in contact with the upper surface of the semiconductor film in a region overlapping with the first opening to the third opening, wherein the channel forming region is made of silicon, the sixth insulating film has an overlap with the channel forming region in a region in contact with the upper surface of the fifth insulating film, the first conductive film has a metal material having light-blocking properties, the second conductive film has the same material as the first conductive film, the first conductive film does not have an overlap with the first opening, and the fourth conductive film has a function as a pixel electrode. Claim 2 A semiconductor film having a channel forming region of a transistor; a first insulating film having a region located below the semiconductor film; a first conductive film having an overlap with the channel forming region interposed with the first insulating film; a second insulating film having a region in contact with the upper surface of the semiconductor film; a second conductive film having a region located above the second insulating film and also having a region overlapping with the channel forming region interposed with the second insulating film; a third insulating film having a region in contact with the upper surface of the second conductive film, a region in contact with the side surface of the second conductive film, and a region in contact with the upper surface of the second insulating film, and also having silicon nitride; a fourth insulating film having a region in contact with the upper surface of the third insulating film and also having silicon oxide; a fifth insulating film having a region in contact with the upper surface of the fourth insulating film and also having an organic material; a region located above the fifth insulating film, and also among the source electrode and drain electrode of the transistor A liquid crystal layer having a third conductive film having a function as one side, a region in contact with the upper surface of the third conductive film, a region in contact with the upper surface of the fifth insulating film, and also having an organic material, a sixth insulating film, a region located above the sixth insulating film, a fourth conductive film electrically connected to the third conductive film, and a region located above the fourth conductive film, wherein the third insulating film has a first opening, the fourth insulating film has a second opening that overlaps with the first opening, and the fifth insulating film has a third opening that overlaps with the first opening and also overlaps with the second opening, wherein in cross-section, the upper end of the second opening and the lower end of the third opening do not coincide, and in cross-section, the diameter of the third opening at the lower end of the third opening is the diameter of the second opening at the upper end of the second opening Larger than the diameter, and in cross-section,A liquid crystal display device, wherein the diameter of the second opening at the top of the second opening is larger than the diameter of the second opening at the bottom of the second opening, the third conductive film has a region in contact with the upper surface of the fifth insulating film and a region in contact with the upper surface of the semiconductor film in a region overlapping with the first opening to the third opening, the channel forming region has silicon, the sixth insulating film has an overlap with the channel forming region in a region in contact with the upper surface of the fifth insulating film, the first conductive film has a metal material having light-blocking properties, the second conductive film has the same material as the first conductive film, the first conductive film does not have an overlap with the first opening, and the fourth conductive film has a function as a pixel electrode.

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