Magnetic field cancellation in radio frequency power amplifier envelope trackers

Abstract

Aspects of the present disclosure relate to generating a bias signal having magnetic field cancellation. A voltage modulator circuit can generate a bias voltage that tracks the envelope of a radio frequency signal. For example, the bias voltage can track the envelope of a radio frequency signal amplified by a power amplifier on a symbol-by-symbol basis. The voltage modulator circuit comprises one or more pairs of switches having magnetic field cancellation.

Description

Technology Field

[0001] Cross-reference for priority applications

[0002] Any and all applications for which a foreign or national priority claim is identified in the application data sheet submitted together with this application are incorporated by reference under 37 CFR §1.57. This application claims the benefit of priority to U.S. Provisional Application No. 63 / 505,009 filed on May 30, 2023, under the title “MAGNETIC FIELD CANCELLATION IN RADIO FREQUENCY POWER AMPLIFIER ENVELOPE TRACKERS”, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0003] Technology field

[0004] Embodiments of the present disclosure relate to generating a bias voltage for a power amplifier, wherein the bias voltage tracks the envelope of a radio frequency signal. Background Technology

[0005] Radio systems can transmit and receive signals in the form of electromagnetic waves having frequencies within the RF range of about 3 kilohertz (kHz) to 300 gigahertz (GHz). Wireless systems can be used for wireless communications such as cellular communications and / or other wireless network communications.

[0006] Wireless systems that transmit signals often include power amplifiers to amplify radio frequency signals for transmission through one or more antennas. Power amplifiers can consume significant power in these systems. Power-efficient power amplifiers may be desirable for various applications.

[0007] The innovations described in the claims each have several aspects, none of which alone constitute its desirable attributes. Without limiting the scope of the claims, some prominent features of the present disclosure will now be briefly described.

[0008] One aspect of the present disclosure is a power amplifier system having magnetic field cancellation in envelope tracking. The voltage amplifier system comprises a voltage modulator circuit and a power amplifier. The voltage modulator circuit is configured to generate a bias voltage that tracks the envelope of a radio frequency signal. The voltage modulator circuit includes a first pair of switches having magnetic field cancellation. The power amplifier is configured to receive the bias voltage and amplify the radio frequency signal.

[0009] A pair of switches may include a first switch and a second switch. The first switch may be in a first current loop that also includes a first bypass capacitor, and the second switch may be in a second current loop that also includes a second bypass capacitor, and the first current loop and the second current loop may generate magnetic fields having opposite directions. The voltage modulator circuit may include a second pair of switches having magnetic field cancellation, the first pair of switches may receive a first supply voltage, and the second pair of switches may receive a second supply voltage. The bias voltage may track the envelope of the radio frequency signal by symbol. The voltage modulator circuit may adjust the bias voltage in correspondence with the symbol boundaries of the radio frequency signal. The bias voltage may track the envelope of the radio frequency signal for a group of symbols. The voltage modulator circuit may further include a capacitor coupled between a first input node configured to receive the first supply voltage and a second input node configured to receive the second supply voltage. The voltage modulator circuit may include a third pair of switches configured to receive a third supply voltage and a fourth pair of switches configured to receive a fourth supply voltage. The second pair of switches may include field-effect transistors. The switches of the second pair of switches may include back-to-back field-effect transistors in a common-source configuration. The switches of the second pair of switches may include back-to-back field-effect transistors in a common-drain configuration.

[0010] The power amplifier system may include a quarter-wavelength transmission line and an antenna between the output of the power amplifier and the voltage modulator.

[0011] Another aspect of the present disclosure is a voltage multiplexer having magnetic field cancellation. The voltage multiplexer comprises a first pair of switches configured to receive a first supply voltage and a second pair of switches configured to receive a second supply voltage. The first pair of switches comprises a first switch of a first current loop and a second switch of a second current loop, wherein the first current loop and the second current loop are configured to generate magnetic fields having opposite directions. The second pair of switches comprises a third switch of a third current loop and a fourth switch of a fourth current loop, wherein the third current loop and the fourth current loop are configured to generate magnetic fields having opposite directions. The voltage multiplexer is configured to generate a bias voltage that tracks the envelope of a radio frequency signal provided to a power amplifier.

[0012] The bias voltage can track the envelope of a radio frequency signal by symbol.

[0013] A voltage multiplexer can adjust the bias voltage in correspondence with the symbol boundaries of a radio frequency signal.

[0014] A voltage multiplexer may include one or more additional pairs of switches having magnetic field cancellation configured to receive one or more additional supply voltages. For example, the voltage multiplexer may include a third pair of switches having magnetic field cancellation and configured to receive a third supply voltage, and a fourth pair of switches having magnetic field cancellation and configured to receive a fourth supply voltage.

[0015] A voltage multiplexer may be included in a power amplifier system that also includes a power amplifier. The power amplifier can receive a bias voltage.

[0016] Another aspect of the present disclosure is a method for generating a bias voltage having magnetic phase cancellation. The method comprises receiving a plurality of supply voltages and controlling a pair of switches to selectively provide one of the plurality of supply voltages as a bias voltage. The controlling step adjusts the bias voltage at the symbol boundaries of a radio frequency signal amplified by a power amplifier receiving the bias voltage. Each pair of switches comprises a first switch of a first current loop and a second switch of a second current loop, wherein the first current loop and the second current loop generate magnetic fields having opposite directions.

[0017] The bias voltage can track the envelope of a radio frequency signal by symbol.

[0018] The controlling step may include block-pre-switching.

[0019] At least one of the pairs of switches may include a switch comprising two series field-effect transistors in a junction-isolated configuration.

[0020] Another aspect of the present disclosure is a power amplifier system having magnetic field cancellation in envelope tracking. The power amplifier system includes a power amplifier configured to amplify a radio frequency signal and a switch-mode power supply voltage regulator circuit configured to provide a bias voltage to the power amplifier. The bias voltage tracks the envelope of the radio frequency signal. The switch-mode power supply voltage regulator circuit includes a first switch of a first current loop that also includes a first bypass capacitor and a second switch of a second current loop that also includes a second bypass capacitor. The first current loop and the second current loop are configured to generate individual magnetic fields having opposite directions. The first switch and the second switch are configured to receive the same supply voltage.

[0021] The bias voltage can continuously track the envelope of a radio frequency signal.

[0022] For the purposes of summarizing the present disclosure, specific aspects, advantages, and novel features of the present inventions have been described herein. It will be understood that not all such advantages may necessarily be achieved according to any specific embodiment. Accordingly, the inventions may be implemented or practiced in a manner that achieves or optimizes one or a group of advantages taught herein without necessarily achieving other advantages such as those that may be taught or proposed herein. Brief explanation of the drawing

[0023] Embodiments of the present disclosure will be described by non-limiting examples with reference to the accompanying drawings. Figure 1 shows the waveforms of a modulated bias voltage and a radio frequency (RF) signal that vary by symbol. FIG. 2 is a schematic block diagram of a multiple-input, multiple-output (MIMO) wireless system according to one embodiment. Figure 3 is a schematic diagram of a wireless transmitter channel having a dual input bias voltage multiplexer for biasing an RF power amplifier. Figure 4 is a schematic diagram of the switch and bypass capacitor of the current loop. FIG. 5 is a schematic diagram of switches having magnetic field cancellation and associated bypass capacitors. FIG. 6 is a schematic diagram of a dual-input, single-output bias voltage multiplexer having magnetic field cancellation according to one embodiment. FIG. 7 is a schematic diagram of a quad-input, single-output bias voltage multiplexer having magnetic field cancellation according to one embodiment. FIGS. 8a, FIGS. 8b, and FIGS. 8c include exemplary waveforms for a dual-input, single-output bias voltage multiplexer during make-before-break-switching according to one embodiment. FIG. 9 is a schematic diagram of a dual-input, single-output bias voltage multiplexer comprising a pair of bypass capacitors coupled between supply voltages according to one embodiment. FIG. 10a is a schematic diagram of the arrangement of external bypass capacitors and an exemplary package pinout for the dual-input, single-output bias voltage multiplexer of FIG. 9 according to one embodiment. FIG. 10b is a schematic diagram of another exemplary package pinout according to one embodiment. FIG. 11 is a schematic diagram of a radio frequency system comprising a dual-input, single-output bias voltage multiplexer including metal oxide semiconductor field effect transistor (MOSFET) switches according to one embodiment. FIG. 12 is a schematic diagram of a radio frequency system comprising a dual-input, single-output bias voltage multiplexer including common-source junction isolated MOSFET switches according to another embodiment. FIG. 13a is a schematic diagram of a radio frequency system including a quad-input, single-output bias voltage multiplexer including MOSFET switches according to one embodiment. FIG. 13b is a schematic diagram of a radio frequency system including a multiple input, single output bias voltage multiplexer including MOSFET switches according to one embodiment. FIG. 14 is a schematic diagram of a radio frequency system including a switch-mode power supply voltage regulator circuit that continuously tracks an envelope having magnetic field cancellation according to one embodiment. Specific details for implementing the invention

[0024] The following detailed description of specific embodiments provides various descriptions of specific embodiments of the invention. However, the innovations described herein may be implemented in a number of different ways, for example, as defined and covered by the claims. In this description, references are made to drawings in which the same reference numerals may represent identical or functionally similar elements. It will be understood that the elements illustrated in the drawings are not necessarily scaled. It will also be understood that specific embodiments may include more elements than illustrated in the drawings and / or a subset of the illustrated elements. Additionally, some embodiments may incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0025] Power amplifiers are important components of transmitters in wireless toe-in systems, including 5th generation (5G) wireless communication systems. Power amplifiers can make a significant contribution to the overall system power consumption, efficiency, and / or linearity. Power amplifiers can drive individual antenna elements of a phase antenna array in certain applications.

[0026] The use of power supplies to power radio frequency (RF) power amplifiers (PAs), such as multiple-input, multiple-output (MIMO) cellular radios, is rapidly increasing. These PAs can be configured as linear amplifiers instead of Class-D amplifiers or other switching amplifiers due to technical specifications for supporting high frequencies. Two or more power supply voltages can be used to modulate the PA's bias voltage to track its RF envelope. This can reduce and / or minimize power dissipation.

[0027] Voltage modulators arranged to generate envelope signals may have switching times of tens of nanoseconds, and the voltage may be significantly stepped (e.g., from 25 V to 50 V). This can result in a high slew rate. By implementing the magnetic field cancellation disclosed herein, introducing little or no inductance into the hot loop can achieve clean transitions without significant overshooting or ring-out. This can be important for preserving the integrity of the RF signal at the output of the diplexing element.

[0028] Aspects of the present disclosure relate to power amplifier systems having magnetic field cancellation in envelope tracking. A power amplifier system may include a voltage modulator circuit for generating a bias voltage for tracking the envelope of a radio frequency signal and a power amplifier configured to receive the bias voltage and amplify the radio frequency signal. The voltage modulator circuit may include a first pair of switches having magnetic field cancellation. The voltage modulator circuit may also include a second pair of switches having magnetic field cancellation, wherein the first pair of switches is configured to receive a first supply voltage and the second pair of switches is configured to receive a second supply voltage. The first and second pairs of switches may be connected to a common bias voltage output to form a dual-input, single-output voltage multiplexer. The bias voltage generated by the voltage modulator circuit may track the envelope of a radio frequency signal by symbol. In certain applications, the voltage multiplexer may include one or more additional pairs of switches having magnetic field cancellation, wherein each additional pair of switches receives a different supply voltage. Each additional pair of switches can be connected to a common bias voltage output.

[0029] Magnetic field cancellation can be implemented by current loops that generate magnetic fields in opposite directions. A pair of switches may include a first switch and a second switch. The first switch may be in a first current loop that also includes a first bypass capacitor. The second switch may be in a second current loop that also includes a second bypass capacitor. The first current loop and the second current loop may generate magnetic fields having opposite directions for magnetic field cancellation.

[0031] SBET Envelope Tracking

[0032] Figure 1 shows exemplary waveforms of a modulated bias voltage and an RF signal that vary by symbol. The PA bias voltage is modulated as a function of the RF waveform. This bias voltage modulation can reduce power dissipation by the PA. The heat dissipated can correspond to the difference between the RF waveform and the PA bias voltage. The PA bias voltage can toggle between distinct voltage levels by symbol. This technique may be referred to as symbol-based envelope tracking (SBET).

[0034] Wireless systems and transmitter channels

[0035] FIG. 2 is a schematic block diagram of an exemplary MIMO wireless system (20) according to one embodiment. As illustrated, the MIMO system (20) includes a plurality of transmitter channels (22A, 22B, 22M), a plurality of power supplies (24A, 24N), and an RF and SBET control block (26). The transmitter channels (22A, 22B, 22M) may be referred to as RF PA transmitter channels. Each of the plurality of transmitter channels (22A, 22B, 22M) may include a PA (27), bypass capacitors (23A to 23N), a voltage multiplexer (28), and an antenna (29). A load capacitor (25) is also illustrated in the transmitter channel (22A). The voltage modulator may include bypass capacitors (23A, 23N) and a voltage multiplexer (28). M (any appropriate integer of a certain amount) transmitter channels may be implemented. For example, in certain applications, there may be 8 to 128 transmitter channels.

[0036] The voltage multiplexer (28) can implement SBET biasing of the PA (27). The voltage multiplexer (28) may have two or more supply voltage inputs and one output. The supply voltage inputs of the voltage multiplexer (28) are configured to receive voltages generated from individual power supplies (24A, 24N). As illustrated in FIG. 2, the power supplies (24A, 24N) may be included in a power supply array. N (any appropriate positive integer) power supplies may be implemented. For example, in certain applications, there may be two power supplies or four power supplies. The output of the voltage multiplexer (28) may be connected to the PA (27) to provide a bias voltage (Vbias) for the PA (27). Input bypass capacitors (23A and 23N) can be positioned near the voltage multiplexer (28) to eliminate and / or minimize parasitic inductance.

[0037] Power supply voltages (VDD1 to VDDn) from power supplies (24A, 24N) may be provided to two or more transmitter channels (22A, 22B, 22M). Power supplies (24A to 24N) may be implemented as separate voltage sources. Power supplies (24A to 24N) may be implemented as voltage sources in series.

[0038] The RF and SBET control block (26) can generate an RF input signal for the PA (27) (e.g., one of TX RF input 1 to TX RF input M), a second bias input signal for the PA (27) (e.g., one of TX bias input 1 to TX bias input M), and one or more voltage multiplexer control signals for each channel (e.g., one of SBET control input 1 to SBET control input M). The one or more voltage multiplexer control signals can control switches of the voltage multiplexer (28) to select a bias voltage (Vbias) that tracks the envelope of the RF signal. Each voltage multiplexer (28) may include a decoder for decoding one or more voltage multiplexer control signals in specific applications. The voltage level of the bias voltage (Vbias) can be adjusted in correspondence with the symbol boundaries of the RF signal. The bias voltage (Vbias) can track the envelope of the RF signal on a symbol-by-symbol basis. In some cases, the bias voltage (Vbias) can track the envelope of the RF signal for a group of symbols and / or for each individual symbol. The bias voltage (Vbias) can be applied to the output (e.g., drain) of the PA (27). A second bias input signal for the PA (27) can be a bias signal for the input terminal (e.g., gate) of the PA (27).

[0039] The power delivered from the power supplies (24A, 24N) may be limited by circuit breakers and / or fuses. Alternatively, the voltage multiplexer (28) may incorporate an electronic circuit breaker protection function. In these cases, the voltage multiplexer (28) of each transmitter channel (22A to 22M) may provide an electronic circuit breaker protection function.

[0040] The PA (27) can amplify the RF input signal. The PA (27) can be implemented by any suitable transistor. In certain applications, the PA (27) may include a gallium nitride (GaN) field-effect transistor. An antenna (29) can be coupled to the output of the PA (27). The antenna (29) can transmit the output signal. The antenna (29) of the transmitter channels (22A, 22B, 22M) can perform beamforming in certain applications.

[0041] FIG. 3 is a schematic diagram of a transmitter channel (30) having a dual input bias voltage multiplexer (32) for biasing a PA (27). The transmitter channel (30) is configured to receive two different supply voltages (VDD1 and VDD2). The voltage multiplexer (32) is configured to modulate the bias voltage (Vbias) by operating switches (34A and 34B) to selectively electrically connect the input nodes at the supply voltages (VDD1 and VDD2) to output nodes providing the bias voltage (Vbias), respectively. The voltage multiplexer (32) may include a decoder (35) for controlling the switching of the switches (34A and 34B) to generate the bias voltages (Vbias) into distinct voltage levels. The decoder (35) may provide binary output signals for controlling the switches (34A and 34B). The decoder (35) can decode a control signal (control). In some applications, the decoder (35) can receive a ternary level input control signal to operate switches (34A and 34B), and the third level is decoded to open all switches simultaneously. The control signal (control) can be provided by a control block such as the RF and SBET control block (26) of FIG. 2.

[0042] Modulation of the PA bias voltage (Vbias) can significantly reduce power dissipation. However, there are technical challenges in actually implementing multiplexers due to technical specifications where the bias voltage (Vbias) changes rapidly in response to control signals. For example, parasitic inductances of power supplies and switches can limit the rate of current change, and multiplexer load capacitance can limit the rate of bias voltage change. Consequently, the parasitic inductances of tracking power supplies and load capacitances can limit the multiplexer's ability to rapidly change the PA bias voltage (Vbias) in response to control signals.

[0043] An embodiment of a bias voltage multiplexer that reduces and / or minimizes parasitic inductances associated with bypass capacitors and switches of power supplies at the input of the multiplexer in order to reduce and / or minimize load capacitance at the output of the multiplexer would be preferred. The switches (34A and 34B) of the voltage multiplexer (32) may each be implemented by an individual pair of switches having magnetic field cancellation to reduce and / or minimize parasitic inductances. Examples of such pairs of switches will be discussed with reference to FIGS. 5 through 7 and FIGS. 9 through 13.

[0045] Generation of bias voltage with self-phase cancellation in voltage modulator circuits and related systems

[0046] Two switches and associated bypass capacitors can split a single magnetic loop into two magnetic loops with linked opposing magnetic fields to cause a cancellation effect and achieve a lower overall magnetic field. This can result in lower parasitic inductance associated with the switches as well as the associated input bypass capacitors. The magnetic loops can be referred to as current loops. Current passing through these loops can generate a magnetic field.

[0047] FIG. 4 is a schematic diagram of a bypass capacitor (42) and a switch (44) of a voltage multiplexer. A current loop including the bypass capacitor (42), the switch (44), and the load capacitance (46) can generate a magnetic field to induce inductance. In FIG. 4, the magnetic field can be generated in a direction into the plane of the page.

[0048] FIG. 5 is a schematic diagram of a pair of switches (54A, 54B) having magnetic field cancellation and associated bypass capacitors (52A, 52B). A first current loop comprising the first switch (54A) and the first bypass capacitor (52A) can generate a first magnetic field in a first direction (e.g., in the plane of the page). A second current loop comprising the second switch (54B) and the second bypass capacitor (52B) can generate a second magnetic field in a second direction (e.g., out of the plane of the page), where the second direction is opposite to the first direction. The first and second magnetic fields are opposite magnetic fields capable of canceling each other. The first and second magnetic fields may have approximately the same magnitude and opposite directions for this cancellation. The magnetic field cancellation may be substantial, even if such magnetic field cancellation cannot completely cancel out the first and second magnetic fields. The lower magnetic field from the magnetic field due to cancellation can reduce the inductance.

[0049] Magnetic field cancellation techniques may be implemented to generate a bias voltage for a power amplifier in envelope tracking applications and / or to generate a bias voltage from multiple supply voltages. Although the embodiments disclosed herein may relate to two or four power supplies, the principles and benefits disclosed herein may be applicable to generating a bias voltage for tracking an envelope signal from any suitable number of supply voltages. Although the embodiments disclosed herein may include two or four pairs of switches and corresponding pairs of bypass capacitors, any suitable number of pairs of switches and corresponding pairs of bypass capacitors may be implemented according to any suitable principles and benefits disclosed herein.

[0050] FIG. 6 is a schematic diagram of a dual-input, single-output bias voltage multiplexer (60) having magnetic field cancellation according to one embodiment. The dual-input, single-output bias voltage multiplexer (60) can generate a bias voltage (Vbias) for a PA that tracks the envelope of an RF signal amplified by the PA. The bias voltage (Vbias) can be toggled in correspondence with the symbol boundaries of the RF signal. The bias voltage can be toggled between distinct voltage levels per symbol. The bias voltage (Vbias) can be toggled between distinct voltage levels for a selected group of symbols. The dual-input, single-output bias voltage multiplexer (60) includes pairs of opposing and opposing switches and pairs of bypass capacitors. A voltage modulator may include the dual-input, single-output bias voltage multiplexer (60) disclosed herein and / or any other suitable voltage multiplexer. The switches of the dual input, single output bias voltage multiplexer (60) and any other voltage multiplexer disclosed herein may be controlled based on one or more switch control signals that may be provided by any suitable control circuit, such as the control circuit portion of the RF and SBET control block (26) of FIG. 2. In some cases, one or more switch control signals may be decoded by a decoder such as the decoder (35) of FIG. 3 or any other suitable decoder, and the outputs of the decoder may be provided to the control terminals of the switches.

[0051] Referring to FIG. 6, the first pair of switches includes switches (62A and 62B) coupled between an output node providing a bias voltage (Vbias) and first input nodes receiving a first supply voltage (VDD1). The second pair of switches includes switches (64A and 64B) coupled between an output node providing a bias voltage (Vbias) and second input nodes receiving a second supply voltage (VDD2). The first pair of capacitors includes capacitors (66A and 66B) that are electrically parallel. Similarly, the second pair of capacitors includes capacitors (68A and 68B) that are electrically parallel. When the output node is connected to the first input nodes receiving the first supply voltage (VDD1), both switches (62A and 61B) are turned on. Similarly, when the output node is connected to the second input nodes that receive the second supply voltage (VDD2), both switches (64A and 64B) are enabled.

[0052] In a dual-input, single-output bias voltage multiplexer (60), a first switch (62A) and a first capacitor (66A) are included in a first current loop. A second switch (62B) and a second capacitor (66B) are included in a second current loop. The first current loop and the second current loop are configured to generate magnetic fields having opposite directions. This can provide magnetic field cancellation. Magnetic field cancellation can be substantial even if the magnetic fields from the first and second current loops are not completely canceled out.

[0053] The third switch (64A) and the third capacitor (68A) are included in the third current loop. The fourth switch (64B) and the fourth capacitor (68B) are included in the fourth current loop. The third current loop and the third current loop are configured to generate magnetic fields having opposite directions. This can provide magnetic field cancellation.

[0054] The configuration of the dual input, single output bias voltage multiplexer (60) can reduce and / or minimize parasitic inductances associated with switches as well as associated input bypass capacitors. This can reduce and / or minimize the technical specifications for output capacitance (Cload).

[0055] FIG. 7 is a schematic diagram of a quad-input, single-output bias voltage multiplexer (70) having magnetic field cancellation according to one embodiment. FIG. 7 illustrates an approach of opposing and opposite switch pairs and bypass capacitor pairs for a quad-input, single-output PA bias voltage multiplexer. In this embodiment, four pairs of opposing switches and four pairs of input bypass capacitors are included. The quad-input, single-output bias voltage multiplexer (70) is similar to the dual-input, single-output bias voltage multiplexer (60) of FIG. 6, except that two additional pairs of switches (72A, 72B and 74A, 74B) and two additional pairs of bypass capacitors (76A, 76B and 78A, 78B) are included in the quad-input, single-output bias voltage multiplexer (70). The additional switch pairs receive different supply voltages. A quad-input, single-output bias voltage multiplexer (70) can generate a bias voltage (Vbias) from four supply voltages (VDD1, VDD2, VDD3, and VDD4). The bias voltage (Vbias) can be toggled in correspondence with symbol boundaries. The bias voltage (Vbias) can track the envelope of the RF signal on a symbol-by-symbol basis.

[0056] FIGS. 8a, FIGS. 8b, and FIGS. 8c include exemplary waveforms for a dual-input, single-output bias voltage multiplexer during make-before-break-switching according to one embodiment. The exemplary waveforms include two switch control signal waveforms in FIG. 8a, two supply voltage waveforms in FIG. 8b, and a bias voltage waveform in FIG. 8c. As shown in FIG. 8b, the dual input supply voltages include a first supply voltage (VDD1) of 48 volts (V) and a second supply voltage (VDD2) of 24 V. FIGS. 8a, FIG. 8b, and FIG. 8c illustrate exemplary waveforms during the rising edge transition of the bias voltage output utilizing make-before-break-switching. The waveforms of FIGS. 8a to 8c correspond to the switch delivering the first supply voltage (VDD1) being turned on before the other switch delivering the second supply voltage (VDD2) is turned off in order to switch the bias voltage between the second supply voltage (VDD2) and the first supply voltage (VDD1).

[0057] For applications utilizing cut-off-pre-switching in voltage multiplexers, bypass capacitors coupled between input supply voltage terminals may be advantageous. In applications corresponding to the waveforms of FIG. 8, bypass capacitors coupled between nodes receiving supply voltages (VDD1 and VDD2) allow for both positive voltage excursion of the 24 V input and negative voltage excursion of the 48 V input across those terminals during the switching overlap period. These capacitors may have the additional advantage of not being implemented by two (or more) series capacitors, but being exposed only to the voltage difference between the 48 V input and the 24 V input.

[0058] FIG. 9 is a schematic diagram of a dual-input, single-output bias voltage multiplexer (90) comprising a pair of bypass capacitors (92A and 92B) coupled between supply voltages (VDD1 and VDD2) according to one embodiment. The pair of bypass capacitors (92A and 92B) is a pair of opposing and opposite capacitors. The dual-input, single-output bias voltage multiplexer (90) is similar to the dual-input, single-output bias voltage multiplexer (60) except that bypass capacitors (92A and 92B) are additionally included. Having bypass capacitors (92A and 92B) allows additional current loops with magnetic field cancellation to be formed. Bypass capacitors (92A and 92B) connected between input nodes receiving power supply voltages (VDD1 and VDD2) can reduce and / or minimize parasitic inductances within the dual-input, single-output bias voltage multiplexer (90). Thus, the dual-input, single-output bias voltage multiplexer (90) may have lower parasitic inductances compared to the dual-input, single-output bias voltage multiplexer (60) of FIG. 6. The dual-input, single-output bias voltage multiplexer (90) may be implemented, for example, in applications utilizing cut-off-pre-switching.

[0059] FIG. 10a is a schematic diagram of the arrangement of external bypass capacitors and an exemplary package pinout for the dual-input, single-output bias voltage multiplexer (90) of FIG. 9 according to one embodiment. The packaged component (100) may include switches (62A, 62B, 64A, 64B).

[0060] Switches (62A, 62B, 64A, 64B) may be connected between terminals (e.g., pins) of the packaged component (100). As illustrated in FIG. 10a, switch (62A) may be connected between a first input terminal (102) configured to receive a first power supply voltage (VDD1) and an output terminal (103) configured to provide a bias voltage (Vbias). Switch (62B) may be connected between a second input terminal (104) configured to receive the first power supply voltage (VDD1) and an output terminal (103). Switch (64A) may be connected between a third input terminal (105) configured to receive a second power supply voltage (VDD2) and an output terminal (103). The switch (64B) can be connected between the fourth input terminal (106) and the output terminal (103) configured to receive the second power supply voltage (VDD2).

[0061] Bypass capacitors (66A, 66B, 68A, 68B, 92A, and 92B) may be implemented outside the packaged component (100). An exemplary arrangement of these bypass capacitors is shown in FIG. 10a. FIG. 10a shows a schematic layout of switches, terminals of the packaged component (100), and bypass capacitors.

[0062] A packaged component including switches for a voltage multiplexer may be any suitable size for a specific application. FIG. 10b is a schematic diagram of another exemplary package pinout according to one embodiment. The packaged component (108) of FIG. 10b may have a different size from the packaged component (100) of FIG. 10a. As an example, the packaged component (108) may be 3 millimeters (mm) along a first dimension (D1) and 3.5 mm along a second dimension (D2).

[0063] The packaged component (108) may include switches of a voltage multiplexer connected to bypass capacitors located outside the packaged component. The switches of the packaged component (108) may be connected between terminals (e.g., pins) of the packaged component (108), as discussed with reference to FIG. 10a, for example. The packaged component (108) includes an arrangement of input terminals (102, 104, 105, 106) and output terminals (103) that are different from the packaged component (100) of FIG. 10a.

[0064] For voltage modulators, there may be a schematic layout of switches, terminals of the packaged component, and bypass capacitors. The terminals for receiving each supply voltage may be symmetric with respect to the output terminal providing the bias voltage. In both the packaged component (108) of FIG. 10b and the packaged component (100) of FIG. 10a, the input terminals (102 and 104) receiving the first power supply voltage (VDD1) are symmetric with respect to the output terminal (103). In both the packaged component (108) of FIG. 10b and the packaged component (100) of FIG. 10a, the input terminals (105 and 106) receiving the second power supply voltage (VDD2) are symmetric with respect to the output terminal (103). The symmetry of the layout of the bypass capacitors and switches shown in FIG. 10a can be implemented using the packaged component (108) of FIG. 10b.

[0065] The switches of the embodiments disclosed herein may be implemented by any suitable circuit elements. Exemplary switches may include, but are not limited to, transistors, field-effect transistors, n-channel field-effect transistors, p-channel field-effect transistors, and metal oxide semiconductor field-effect transistors (MOSFETs). In certain applications, the switch may include one or more transistors in series with respect to each other, for example, back-to-back common-source MOSFETs, back-to-back common-drain MOSFETs, or similar. Alternatively, or additionally, the switch may be implemented by one or more transistors in parallel with respect to each other. In some cases, the switch may be implemented by transistors in combination of parallel and series transistors.

[0066] Switches can be implemented by back-to-back MOSFETs. In certain applications, such as discontinuous PA transmission (DTX), the bias voltage can be discharged below the lowest input voltage (e.g., ground). Back-to-back common-source MOSFETs or back-to-back common-drain MOSFETs can be implemented to isolate the supply voltage input from the bias voltage input. Back-to-back common-source MOSFETs or back-to-back common-drain MOSFETs can be implemented to isolate all supply voltage inputs from the bias voltage input. Back-to-back MOSFETs can also isolate the load instead of a fuse in the event of a failure. Envelope tracers and PAs can be included in one of the transmission channels (e.g., 8 or 128 inherent transmission channels) connected to a common supply voltage (e.g., VDD2). If one of the channels fails, the transmission channel can be isolated from the other transmission channels by back-to-back MOSFETs. Exemplary embodiments having back-to-back MOSFETs will be discussed with reference to FIGS. 11 through 13.

[0067] FIG. 11 is a schematic diagram of a power amplifier system (110) comprising a dual-input, single-output bias voltage multiplexer (111) comprising MOSFET switches according to one embodiment. The dual-input, single-output bias voltage multiplexer (111) comprises two pairs of opposing and opposite switches and capacitors, wherein the switches are realized as N-channel MOSFETs. The MOSFETs may have body diodes connected between their source and drain terminals, resulting in the body of each device being connected to its source terminal. Body diodes are illustrated in FIG. 11, FIG. 12, FIG. 13a, and FIG. 13b.

[0068] Opposite and opposite switches (112A and 112B) connecting input nodes receiving the first supply voltage (VDD1) to an output node providing a bias voltage (Vbias) each include a MOSFET. The dual-input, single-output bias voltage multiplexer (111) includes common-drain junction isolated MOSFETs. Opposite and opposite switches (114A and 114B) connecting input nodes receiving the second supply voltage (VDD2) to an output node providing a bias voltage (Vbias) each include two series MOSFETs in a back-to-back, common-drain configuration. Thus, the output bias voltage (Vbias) can be pulled to ground when the MOSFET is biased at cutoff without shorting the input nodes receiving the second supply voltage (VDD2) through the body diode. The ability to isolate the output node providing the bias voltage (Vbias) from the input nodes can be used during normal operation or when a fault condition is present, for example, when a circuit breaker trips.

[0069] In the dual-input, single-output bias voltage multiplexer (111), the bypass capacitors (66A, 66B, 68A, 68B, 92A, and 92B) are connected similarly to the dual-input, single-output bias voltage multiplexer (90) of FIG. 9.

[0070] In the power amplifier system (110), the PA (27) is exemplified as a common source amplifier having drain connections to the diplexer (118) and the antenna (29). The diplexer (118) may be implemented by a quarter-wavelength transmission line connected between the output node providing the bias voltage (Vbias) and the drain of the PA (27). The drain of the field-effect transistor of the PA (27) may be an alternating current (AC) coupled to the antenna (29) by a direct current (DC) blocking capacitor (119). The load capacitance (117) may be connected by a shunt to the output node providing the Vbias. The capacitance (117) may be composed of a capacitor having a self-resonant frequency centered on the RF signal transmitted by the antenna (29).

[0071] FIG. 12 is a schematic diagram of a power amplifier system (120) comprising a dual-input, single-output bias voltage multiplexer (122) including MOSFET switches according to one embodiment. The dual-input, single-output bias voltage multiplexer (122) is similar to the dual-input, single-output bias voltage multiplexer (111) of FIG. 11, except that back-to-back MOSFET switches (124A and 124B) connecting input nodes receiving a second supply voltage (VDD2) to output nodes providing a bias voltage (Vbias) are in a common-source configuration.

[0072] FIG. 13a is a schematic diagram of a power amplifier system (130) comprising a quad-input, single-output bias voltage multiplexer (132) according to one embodiment. The quad-input, single-output bias voltage multiplexer (132) comprises opposing and opposite MOSFET switches and bypass capacitors. In the quad-input, single-output bias voltage multiplexer (132), input nodes receiving supply voltages (VDD2, VDD3, and VDD4) are each connected to output nodes providing a bias voltage (Vbias) through back-to-back MOSFET switches (114A and 114B, 134A and 134B, and 136A and 136B). These back-to-back MOSFET switches are common-drain MOSFET switches as illustrated. In addition to the input bypass capacitor pairs returning to ground, a bypass capacitor pair (92A, 92B) is included between the inputs (VDD1 and VDD2). Additional input-to-input bypass capacitor pairs may be appropriately included.

[0073] FIG. 13b is a schematic diagram of a radio frequency system (135) comprising a multiple input, single output bias voltage multiplexer (137) comprising MOSFET switches according to one embodiment. The voltage multiplexer (137) comprises a first pair of MOSFET switches (112A and 112B) and a second pair of MOSFET switches (124A and 124B). The voltage multiplexer (137) also comprises one or more additional pairs of MOSFET switches configured to receive one or more additional bias voltages having magnetic field cancellation. One or more additional pairs of MOSFET switches comprises MOSFET switches (138A and 138B) configured to receive an additional bias voltage (VDDn). MOSFET switches (138A, 138B) are each connected to an individual bypass capacitor (139A, 139B). Any appropriate number of additional pairs of switches and additional bias voltages can be implemented for a specific application.

[0074] While specific embodiments relate to symbol-based envelope tracers, any suitable principles and advantages disclosed herein may be applied to envelope tracers that continuously track the envelope of an RF signal. An exemplary envelope tracer utilizing continuous envelope tracking will be discussed with reference to FIG. 14.

[0075] FIG. 14 is a schematic diagram of a radio frequency system (140) comprising a switch-mode power supply voltage regulator circuit (142) having magnetic field cancellation according to one embodiment. The envelope tracker of FIG. 14 includes opposing and opposite switches (144, 145) and bypass capacitors (146, 147). Opposing and opposite top gate switches (144, 145) and opposing and opposite bottom gate switches (148, 149) are included in the switch-mode supply circuit (152). The switch-mode power supply voltage regulator circuit (142) generates a bias voltage (Vbias) that continuously tracks the envelope of an RF signal (e.g., RF input). The switch-mode power supply voltage regulator circuit (142) is an exemplary voltage modulator for continuous envelope tracking.

[0076] The switch-mode power supply voltage regulator circuit (142) includes a switch-mode supply circuit (152) and an inductor (154). The switch-mode supply circuit (152) can provide a voltage pulse width having a duty factor set by the on time of the switches (144, 145) during a switching cycle. The inductor (154) and the load capacitance (156) can generate a bias voltage signal (Vbias) proportional to the product of the duty factor of the voltage pulse and the input supply voltage. The switches (144, 145) can be controlled so that the bias voltage (Vias) tracks the envelope of the RF signal (RF input).

[0077] In FIG. 14, the output bias voltage (Vbias) of the switch-mode power supply voltage regulator circuit (142) can continuously vary the bias voltage (Vbias) to track the PA RF waveform. In this embodiment, opposing and opposite switches (144, 145) and bypass capacitors (146, 147) reduce parasitic inductance within the inductor switch node loop. This can enable faster switch node switching times. Faster switch node switching times can enable one or more of faster switching frequencies, reduced minimum on times of the upper gate switches (144, 145) and lower gate switches (148, 149), reduced electromagnetic interference (EMI), and increased closed-loop bandwidth when negative feedback is used to control the output.

[0079] conclusion

[0080] In the embodiments described above, devices, systems, and methods for power amplifier envelope trackers have been described in relation to specific embodiments. However, it will be understood that the principles and advantages of these embodiments may be applied to any other systems, devices, or methods having a need for an envelope-tracking programmable power amplifier. Furthermore, any suitable principles and advantages disclosed herein may be implemented in systems and methods comprising a power amplifier that transmits a radio frequency signal through one or more antennas.

[0081] The principles and benefits described herein may be implemented in various devices. Examples of such devices may include, but are not limited to, communication infrastructure such as wireless communication infrastructure, consumer electronics, parts of consumer electronics, electronic test equipment, automotive electronics, industrial electronics, etc. Electronic products may include, but are not limited to, base stations such as cellular base stations, access points, repeaters, relays, wireless communication devices, mobile phones (e.g., smartphones), handheld computers, tablet computers, laptop computers, wearable computing devices, automotive electronic systems, radios, wearable health monitoring devices, Internet of Things (IoT) devices, etc. Additionally, devices may include unfinished products.

[0082] Unless the context clearly requires otherwise, throughout the detailed description and claims, the words “consists of,” “consists of,” “includes,” “includes,” and similar words shall be interpreted in an inclusive sense, i.e., “includes without limitation,” as opposed to an exclusive or complete sense. The words “combined” or “linked,” as commonly used in this specification, indicate two or more elements that may be directly connected or connected through one or more intermediate elements. Additionally, the words “in this application,” “above,” “below,” and similar words, when used in this application, refer to the application in its whole, rather than any specific part of the application. Where the context permits, words in the detailed description using the singular or plural may also include the plural or singular, respectively. With respect to a list of two or more items, the words “or” are intended to cover all of the following interpretations: any of the items in the list, all of the items in the list, and any combination of the items in the list. All numerical values ​​provided herein are intended to include similar values ​​within the measurement error.

[0083] In addition, conditional language used herein, such as “can,” “able to,” “can,” “able to,” “for example,” “for example,” and similar language, is generally intended to convey that certain embodiments include certain features, elements, and / or states, while other embodiments do not, unless specifically otherwise stated or otherwise understood in the context in which they are used.

[0084] The teachings of the invention provided herein may be applied to systems other than those described above. The elements and operations of the various embodiments described above may be combined to provide additional embodiments. The operations of the methods discussed herein may be performed in any order as appropriate. Additionally, the operations of the methods discussed herein may be performed in series or in parallel as appropriate.

[0085] Although specific embodiments of the present inventions have been described, such embodiments are presented merely as examples and are not intended to limit the scope of the present disclosure. In practice, the novel methods and systems described herein may be implemented in various other forms. Additionally, various omissions, substitutions, and modifications may be made in the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, while the disclosed embodiments are presented in given arrangements, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in appropriately varied and different ways. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide additional embodiments. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the spirit and scope of the present disclosure. Accordingly, the scope of the present invention is defined by reference to the claims.

Claims

Claim 1 A voltage multiplexer having magnetic field cancellation, comprising a first pair of switches configured to receive a first supply voltage, wherein the first pair of switches includes a first switch of a first current loop and a second switch of a second current loop, and wherein the first current loop and the second current loop are configured to generate magnetic fields having opposite directions; A voltage multiplexer comprising a second pair of switches configured to receive a second supply voltage, wherein the second pair of switches comprises a third switch of a third current loop and a fourth switch of a fourth current loop, wherein the third current loop and the fourth current loop are configured to generate magnetic fields having opposite directions, and wherein the voltage multiplexer is configured to generate a bias voltage that tracks the envelope of a radio frequency signal provided to a power amplifier by controlling the pair of switches to selectively provide one of a plurality of supply voltages as a bias voltage, wherein the pair of switches comprises a first pair of switches and a second pair of switches, and wherein the plurality of supply voltages include the first supply voltage and the second supply voltage. Claim 2 In claim 1, the bias voltage is a voltage multiplexer that tracks the envelope of the radio frequency signal by symbol. Claim 3 A voltage multiplexer according to claim 1, wherein the voltage multiplexer is configured to adjust the bias voltage in correspondence with the symbol boundaries of the radio frequency signal. Claim 4 A voltage multiplexer according to claim 1, further comprising one or more additional pairs of switches having magnetic field cancellation configured to receive one or more additional supply voltages. Claim 5 A power amplifier system having magnetic field cancellation in envelope tracking, wherein the power amplifier system comprises: a voltage modulator circuit including a voltage multiplexer according to claim 1; and a power amplifier configured to receive the bias voltage and amplify the radio frequency signal. Claim 6 A power amplifier system according to claim 5, wherein the first current loop also includes a first bypass capacitor and the second current loop also includes a second bypass capacitor. Claim 7 In paragraph 6, the second pair of switches comprises field-effect transistors, forming a power amplifier system. Claim 8 In claim 7, the bias voltage is a power amplifier system that tracks at least one of: a) an envelope of the radio frequency signal per symbol; and b) an envelope of the radio frequency signal for a group of symbols. Claim 9 A power amplifier system according to claim 7, wherein the voltage modulator circuit comprises: a) configured to adjust the bias voltage in correspondence with the symbol boundaries of the radio frequency signal; b) further comprising a capacitor coupled between a first input node configured to receive the first supply voltage and a second input node configured to receive the second supply voltage; and c) at least one of a third pair of switches configured to receive the third supply voltage and a fourth pair of switches configured to receive the fourth supply voltage. Claim 10 In claim 7, the second pair of switches comprises back-to-back field-effect transistors in a) a common-source configuration or b) a common-drain configuration, in a power amplifier system. Claim 11 A power amplifier system according to claim 5, further comprising a quarter wavelength transmission line and an antenna between the output of the power amplifier and the voltage modulator circuit. Claim 12 A method for generating a bias voltage having magnetic field cancellation, comprising: receiving a plurality of supply voltages; and controlling a pair of switches to selectively provide one of the plurality of supply voltages as a bias voltage, wherein the controlling step comprises adjusting the bias voltage at the symbol boundaries of a radio frequency signal amplified by a power amplifier receiving the bias voltage, wherein the bias voltage tracks the envelope of the radio frequency signal, and each of the pairs of switches comprises a first switch of a first current loop and a second switch of a second current loop, and the first current loop and the second current loop generate magnetic fields having opposite directions. Claim 13 In paragraph 12, the above bias voltage is a method for tracking the envelope of the radio frequency signal by symbol. Claim 14 In claim 12, the controlling step comprises make-before-break switching. Claim 15 A method according to claim 12, wherein at least one of the pairs of switches comprises a switch comprising two series field-effect transistors in a junction-isolated configuration. Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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