Memory system and operating method thereof

Abstract

A memory system according to the present invention includes a plurality of memory blocks, a memory device that outputs voltage information indicating whether an event occurs in which the level of an input voltage drops below a reference level, and a memory controller that stores a read count indicating the number of times a read operation is performed for each of the plurality of memory blocks, controls the memory device to move data stored in a memory block in which the read count exceeds a threshold count to another memory block, and adjusts the threshold count based on the voltage information.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory system including a memory device and a memory controller, and a method of operating the same. Background Technology

[0002] A memory system is a device that stores data under the control of a host device, such as a computer or a smartphone. A memory system may include a memory device that stores data and a memory controller that controls the memory device. Memory devices can be classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices may be memory devices that store data only while power is supplied and lose the stored data when the power supply is cut off. Volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc.

[0004] A non-volatile memory device is a memory device in which data is not lost even when the power is cut off, and may include ROM (Read Only Memory, ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and flash memory. Prior art literature

[65535] U.S. Patent Publication US 2016 / 0012918 The problem to be solved

[0005] An embodiment of the present invention provides a memory system and a method of operation thereof that can improve data reliability and lifespan in an environment where an unstable input voltage is provided. means of solving the problem

[0006] A memory system according to an embodiment of the present invention may include a memory device that includes a plurality of memory blocks and outputs voltage information indicating whether an event occurs in which the level of an input voltage drops below a reference level, and a memory controller that stores a read count indicating the number of times a read operation is performed for each of the plurality of memory blocks, controls the memory device to move data stored in a memory block in which the read count exceeds a threshold count to another memory block, and adjusts the threshold count based on the voltage information.

[0007] A memory system according to an embodiment of the present invention includes a plurality of memory blocks and a memory device that outputs voltage information indicating whether an event occurs in which the level of an input voltage drops below a reference level; and a memory controller that receives read data obtained by a read operation that reads a page included in a selected memory block among the plurality of memory blocks using a read voltage generated through the input voltage, and performs a plurality of recovery read operations that read a page included in the selected memory block while changing the read voltage until the error correction decoding operation fails when an error correction decoding operation that corrects an error bit included in the read data passes, and controls the memory device to move data stored in the selected memory block to another memory block when the number of times the plurality of recovery read operations are performed exceeds a threshold count, wherein the memory controller can adjust the threshold count based on the voltage information. Effects of the invention

[0008] According to the present invention, a memory system and a method of operation thereof are provided that can improve the reliability and lifespan of data in an environment where an unstable input voltage is provided. Brief explanation of the drawing

[0009] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention. FIG. 2 is a drawing for explaining the structure of a memory device according to an embodiment of the present invention. FIG. 3 is a drawing for explaining the structure of a memory block according to an embodiment of the present invention. FIG. 4 is a diagram illustrating an input voltage according to an embodiment of the present invention. FIG. 5 is a diagram illustrating the structure of a memory controller according to an embodiment of the present invention. Figures 6a and 6b are drawings illustrating the distribution of threshold voltages according to an embodiment of the present invention. FIG. 7 is a drawing for explaining a method of operation according to an embodiment of the present invention. FIG. 8 is a drawing for explaining a threshold count table according to an embodiment of the present invention. FIG. 9 is a drawing for explaining a lead count according to an embodiment of the present invention. FIG. 10 is a drawing for explaining a method of operation according to an embodiment of the present invention. FIG. 11 is a drawing for explaining a recovery read operation according to an embodiment of the present invention. FIG. 12 is a drawing for explaining one of the recovery read operations according to an embodiment of the present invention. FIG. 13 is a drawing for explaining the operation method of a memory system according to an embodiment of the present invention. FIG. 14 is a drawing for explaining the operation method of a memory system according to an embodiment of the present invention. FIG. 15 is a block diagram showing a memory card to which a memory system according to an embodiment of the present invention is applied. FIG. 16 is a block diagram showing a Solid State Drive (SSD) system to which a memory system according to an embodiment of the present invention is applied. FIG. 17 is a block diagram showing a user system to which a memory system according to an embodiment of the present invention is applied. Specific details for implementing the invention

[0010] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0012] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention.

[0013] Referring to FIG. 1, a memory system (10) and a host (20) according to an embodiment of the present invention can communicate with each other.

[0014] The memory system (10) may be a semiconductor-based storage device. The memory system (10) may store data under the control of the host (20). The memory system (10) may provide the stored data to the host (20) under the control of the host (20).

[0015] The memory system (10) can be manufactured in any one of various types of package forms. For example, the memory system (10) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0016] The memory system (10) can be implemented as one of various types of storage devices. For example, the memory system (10) can be implemented as any one of various types of storage devices such as SSD (Solid State Disk), MMC (Multi Media Card), eMMC (embedded MMC), RS-MMC (Reduced-Size MMC), micro-MMC, SD (Secure Digital) card, mini-SD card, micro-SD card, USB (universal serial bus) type storage device, UFS (universal flash storage), PCMCIA (personal computer memory card international association), PCI (peripheral component interconnection), PCI-E (PCI express), CF (compact flash) card, smart media card, memory stick, etc.

[0017] The host (20) can control the memory system (10). For example, the host (20) can provide the memory system (10) with commands and data instructing it to perform program operations. In response to this, the memory system (10) can store data in the memory device (100). As another example, the host (20) can provide the memory system (10) with commands requesting the stored data. In response to this, the memory system (10) can provide the data stored in the memory device (100) to the host (20). As another example, the host (20) can provide the memory system (10) with commands instructing it to delete the stored data. In response to this, the memory system (10) can delete the data stored in the memory device (100).

[0018] The host (20) may be one of various electronic devices such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV (Television), tablet PC, or in-vehicle infotainment system, wearable device, etc. The memory system (10) may be implemented as a separate device from the host (20) or as a built-in form in the host (20).

[0019] The host (20) can communicate with the memory system (10) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0020] The memory system (10) may include at least one memory device (100) and a memory controller (200). The number of memory devices (100) may be one or multiple. For convenience of explanation, the following description will focus on at least one of the memory devices (100).

[0021] A memory device (100) may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of pages. That is, a single memory block may include a plurality of pages. Here, a page may be a unit in which a program operation to store data (DATA) is performed. Additionally, a page may be a unit in which a read operation to read stored data (DATA) is performed. A memory block may be a unit in which an erase operation to erase stored data (DATA) is performed. Each of the plurality of pages may include a plurality of memory cells. Each of the plurality of memory cells may store an electric charge, and each of the plurality of memory cells may have a distribution state of threshold voltage according to the amount of stored electric charge. Here, the distribution state of threshold voltage may represent data (DATA).

[0022] The memory device (100) can use an input voltage (Vcc) provided from an external power source as an operating voltage. That is, the memory device (100) can perform operations using the input voltage (Vcc) provided from an external power source. For example, the external power source may be a host (20) or a separate external device. The memory device (100) can generate an internal voltage corresponding to various operations using the input voltage (Vcc). The memory device (100) can perform corresponding operations using the internal voltage. For example, the operations may include one of a program operation to store data (DATA), a read operation to output stored data (DATA), and an erase operation to delete stored data (DATA). The internal voltage may include one of a program voltage, a read voltage, a pass voltage, and an erase voltage.

[0023] The memory device (100) can output data (DATA) stored in a selected memory block among a plurality of memory blocks using an input voltage (Vcc) provided from an external power source. Here, the selected memory block may be a memory block selected by an address (ADDR).

[0024] The memory device (100) can operate under the control of the memory controller (200). When the memory device (100) receives a command (CMD) from the memory controller (200), it can perform an operation corresponding to the command (CMD). Here, the command (CMD) may include any one of a command instructing to perform a program operation, a command instructing to perform a read operation, and a command instructing to perform an erase operation. Here, each command may have a different identifier depending on the operation instructed.

[0025] In one embodiment, the memory device (100) may be implemented as one of NAND flash memory, Vertical NAND flash memory, NOR flash memory, SRAM (Static Random Access Memory, Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous Dynamic RAM), DDR (Double Data Rate) SDRAM, LPDDR (Low Power DDR) SDRAM, GDRAM (Graphics DRAM), RDRAM (Rambus Dynamic RAM), Ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), Phase Change Memory (PCM), Spin Transfer Torque Magnetoresistive RAM (STT-RAM), Resistive RAM (ReRAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0026] The memory controller (200) can control the overall operation of the memory system (10).

[0027] When power is applied to the memory system (10), the memory controller (200) can execute firmware (FW). The firmware may include a Host Interface Layer (HIL) that controls communication with the host (20), a Flash Translation Layer (FTL) that controls communication between the host (20) and the memory device (100), and a Flash Interface Layer (FIL) that controls communication with the memory device (100). The memory controller (200) may be located outside the memory device (100). The memory controller (200) may be connected to the memory device (100) through a channel.

[0028] The memory controller (200) can control the memory device (100). In one embodiment, the memory controller (200) can control the memory device (100) in response to a request received from the host (20). In another embodiment, the memory controller (200) can control the memory device (100) independently of the request from the host (20).

[0029] The memory controller (200) can control the memory device (100) to perform one of a program operation, a read operation, and an erase operation.

[0030] In the case of a program operation, the memory controller (200) may provide the memory device (100) with a command (CMD) that instructs the program operation to be performed, an address (ADDR), and data (DATA). In response to this, the memory device (100) may store data (DATA) by applying a program voltage to the page selected by the address (ADDR).

[0031] In the case of a read operation, the memory controller (200) may provide the memory device (100) with a command (CMD) and an address (ADDR) that instructs the memory device (100) to perform a read operation. In response to this, the memory device (100) may provide the data (DATA) stored in the selected page to the memory controller (200) or the host (20) by applying a read voltage to the page selected by the address (ADDR).

[0032] In the case of an erase operation, the memory controller (200) may provide the memory device (100) with a command (CMD) and an address (ADDR) that instructs the memory device (100) to perform an erase operation. In response to this, the memory device (100) may erase data (DATA) stored in the selected memory block by applying an erase voltage to the memory block selected by the address (ADDR).

[0033] If the memory device (100) repeatedly performs a program operation or a read operation while the input voltage (Vcc) is unstable, it may be impossible to read valid data (DATA) from the memory device (100). An unstable input voltage (Vcc) can occur in various situations, such as when a sudden change in ambient temperature occurs, when the power of the external power supply is unstable, when high frequency is generated in the surroundings, or when an external device is electrically connected to or disconnected from the memory system (10) through a port of various communication methods such as USB.

[0034] A memory system (10) according to one embodiment of the present invention can control the timing of performing a read reclaim operation to move data (DATA) stored in a memory block to another memory block by distinguishing between a stable state and an unstable state of the input voltage (Vcc) and applying different threshold counts. Accordingly, when the input voltage (Vcc) is in an unstable state, it is possible to prevent in advance a situation in which the data (DATA) stored in the memory device (100) is abnormally degraded and the recovery of valid data (DATA) becomes impossible. That is, the reliability of the data (DATA) can be improved, thereby extending the lifespan of the memory system (10).

[0035] Specific embodiments of the present invention will be described below with reference to the attached drawings.

[0037] FIG. 2 is a drawing for explaining the structure of a memory device according to an embodiment of the present invention.

[0038] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), a voltage generation unit (120), an address decoder (130), an input / output circuit (140), and a control logic (150).

[0039] A memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKi). The plurality of memory blocks (BLK1 to BLKi) may be connected to an address decoder (130) via row lines (RL). The plurality of memory blocks (BLK1 to BLKi) may be connected to an input / output circuit (140) via column lines (CL). In an embodiment, the row lines (RL) may include word lines, source select lines, and drain select lines. In an embodiment, the column lines (CL) may include bit lines.

[0040] Each of the multiple memory blocks (BLK1~BLKi) may include multiple memory cells.

[0041] Data can be stored in each of the multiple memory cells. For example, each of the multiple memory cells can store data with a different number of bits according to a Single Level Cell (SLC) that stores one bit, a Multi Level Cell (MLC) that stores two bits, a Triple Level Cell (TLC) that stores three bits, or a Quad Level Cell (QLC) that stores four bits. Here, among the multiple memory cells, memory cells connected to the same word line can be defined as a single page.

[0042] In an embodiment, each of the plurality of memory cells may be a non-volatile memory cell. For example, each of the plurality of memory cells may include a floating gate in which charge can be accumulated. Each of the plurality of memory cells may represent a specific value of data depending on the amount of charge accumulated in the floating gate.

[0043] In the embodiment, the voltage generation unit (120), the address decoder (130), and the input / output circuit (140) may be collectively referred to as a peripheral circuit. The peripheral circuit can drive the memory cell array (110) under the control of the control logic (150). The peripheral circuit can drive the memory cell array (110) to perform a program operation, a read operation, and an erase operation.

[0044] The voltage generation unit (120) may be configured to generate a plurality of operating voltages using an external power supply voltage supplied to the memory device (100). The voltage generation unit (120) may operate in response to the control of the control logic (150).

[0045] As an example, the voltage generating unit (120) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (120) can be used as the operating voltage of the memory device (100).

[0046] As an example, the voltage generation unit (120) can generate at least one operating voltage using an input voltage (Vcc) provided from an external power source. The voltage generation unit (120) can be configured to generate various voltages required by the memory device (100). For example, the voltage generation unit (120) can generate a plurality of erase voltages, a plurality of program voltages, a plurality of read voltages, and a plurality of pass voltages. To this end, the voltage generation unit (120) may include a plurality of pumping capacitors that receive an internal power supply voltage. The voltage generation unit (120) can generate a plurality of operating voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic (150).

[0047] A plurality of operating voltages generated in the voltage generation unit (120) can be supplied to the memory cell array (110) by the address decoder (130).

[0048] The address decoder (130) can be connected to the memory cell array (110) via row lines (RL). The address decoder (130) can be configured to operate in response to the control of the control logic (150). The address decoder (130) can receive an address (ADDR) from the control logic (150). The address decoder (130) can decode a block address among the received address (ADDR). The address decoder (130) can select at least one memory block among the memory blocks (BLK1 to BLKi) according to the decoded block address. The address decoder (130) can decode a row address among the received address (ADDR). The address decoder (130) can select at least one word line among the word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder (130) can decode the column address among the received addresses (ADDR). The address decoder (130) can connect the input / output circuit (140) and the memory cell array (110) according to the decoded column address.

[0049] For example, the address decoder (130) may include components such as a row decoder, a column decoder, an address buffer, etc.

[0050] The input / output circuit (140) may include a plurality of page buffers. The plurality of page buffers may be connected to a memory cell array (110) via bit lines. During a program operation, data stored in the plurality of page buffers is provided to a selected page via bit lines, and the provided data may be stored in memory cells included in the selected page. During a read operation, data stored in memory cells included in the selected page is sensed via bit lines, and the sensed data may be stored in the page buffers.

[0051] The control logic (150) can control the address decoder (130), the voltage generator (120), and the input / output circuit (140). The control logic (150) can operate in response to a command (CMD) transmitted from an external device. The control logic (150) can control peripheral circuits by generating control signals in response to the command (CMD) and the address (ADDR).

[0052] In one embodiment, the memory device (100) may include a voltage sensing unit (160).

[0053] The voltage detection unit (160) can output voltage information (V_Inf) indicating whether an event has occurred in which the level of the input voltage (Vcc) supplied from an external power source drops below a reference level. More specific details will be explained with reference to FIG. 4.

[0055] FIG. 3 is a drawing for explaining the structure of a memory block according to an embodiment of the present invention.

[0056] Referring to FIG. 3, a memory block (BLKi) may include a plurality of strings connected between bit lines (BL1 to BLn) and a source line (SL). The description of the memory block (BLKi) may be applied to each of the plurality of memory blocks (BLK1 to BLKi).

[0057] Multiple strings can be connected one by one to bit lines (BL1~BLn). Multiple strings can be connected in common to a source line (SL). Since multiple strings can be configured identically, the string (ST) connected to the first bit line (BL1) among the multiple strings will be described specifically as an example. The description of string (ST) can be applied equally to other strings.

[0058] The string (ST) may include a source select transistor (SST), a plurality of memory cells (MC1~MC16), and a drain select transistor (DST) connected in series between the source line (SL) and the first bit line (BL1).

[0059] Multiple memory cells (MC1 to MC16) can be connected in series between a source select transistor (SST) and a drain select transistor (DST). The gates of the multiple memory cells (MC1 to MC16) can be connected one by one to multiple word lines (WL1 to WL16). The number of memory cells (MC1 to MC16) included in a single string (ST) may be greater or less than the number shown in the drawing.

[0060] The drain of the drain select transistor (DST) can be connected to the first bit line (BL1). The gate of the drain select transistor (DST) can be connected to the drain select line (DSL). The source of the source select transistor (SST) can be connected to the source line (SL). The gate of the source select transistor (SST) can be connected to the source select line (SSL). The number of source select transistors (SST) and drain select transistors (DST), respectively, included in a string (ST) can be one or more.

[0061] Multiple word lines (WL1 to WL16), source select lines (SSL), and drain select lines (DSL) can be arranged parallel to each other. Multiple word lines (WL1 to WL16), source select lines (SSL), and drain select lines (DSL) can be arranged in a direction perpendicular to the direction in which strings (ST) are arranged.

[0062] A memory block (BLKi) may include multiple pages. A page may represent a group of memory cells connected to the same word line. In this case, the memory block (BLKi) may include a number of pages equal to the number of multiple word lines (WL1 to WL16). Since multiple pages may be configured identically, a page (PG) connected to the third word line (WL3) among the multiple pages will be described specifically as an example. The description of the page (PG) may be applied identically to other pages.

[0063] A page (PG) may include memory cells connected to a third word line (WL3) among a plurality of memory cells included in a memory block (BLKi). Each of the memory cells included in the page (PG) may be a memory cell included in a different string.

[0064] In the case of a program operation, the memory device (100) can store data in the page (PG) by applying a program voltage to the page (PG). Specifically, the memory device (100) can apply a program voltage to the third word line (WL3). In this case, the program voltage applied to the third word line (WL3) can be delivered to the gate of each of the memory cells included in the page (PG) connected to the third word line (WL3). When the program voltage is applied to the gate of each of the memory cells included in the page (PG), charge can be injected into the floating gate of each of the memory cells included in the page (PG) through a tunneling phenomenon. The threshold voltage of the memory cell may vary depending on the amount of charge accumulated in the floating gate. Here, the threshold voltage may represent the voltage applied to the gate when a channel is formed through which current can flow between the source and drain of the memory cell.

[0065] Here, the program operation may utilize an Incremental Step Pulse Program (ISPP) method. The ISPP method may include a plurality of program loops. Each of the plurality of program loops may include a PGM pulse step that applies a program voltage of a predetermined level to a word line and a verification step that applies a verification voltage of a predetermined level to a word line to identify the pass or failure of the corresponding program loop.

[0066] In the case of a read operation, the memory device (100) can output data stored in the selected page (PG) by applying a read voltage to the selected page (PG) and applying a pass voltage to the remaining non-selected pages excluding the selected page (PG). Here, the read voltage may be a voltage having a preset level according to a method such as a single-level cell, multi-level cell, triple-level cell, quad-level cell, etc. The pass voltage may be a high-level voltage set to form a channel through which current can flow in all memory cells included in the non-selected pages.

[0067] Specifically, the memory device (100) can apply a read voltage to the selected page (PG) through a third word line (WL3) connected to the selected page (PG). The memory device (100) can apply a pass voltage to the non-selected pages through word lines connected to the non-selected pages. The read voltage can be delivered to the gate of each memory cell included in the selected page (PG). Among the plurality of memory cells included in the selected page (PG), a channel through which current can flow may be formed in a memory cell having a threshold voltage smaller than the read voltage applied to the gate. Conversely, among the plurality of memory cells included in the selected page (PG), a channel may not be formed in a memory cell having a threshold voltage larger than the read voltage applied to the gate. The pass voltage is delivered to the gate of each memory cell included in the non-selected pages, so that a channel may be formed in each memory cell included in the non-selected pages. The memory device (100) can sense whether current flows through each of the strings. The memory device (100) can output read data as a sensing result of applying a read voltage having a specific level to a selected page (PG). The read data may include a plurality of column data. Here, each column data may represent a result sensed in each string.

[0068] More specific details regarding the lead operation will be explained with reference to Figs. 6a and 6b.

[0070] FIG. 4 is a diagram illustrating an input voltage according to an embodiment of the present invention.

[0071] Referring to FIGS. 2 and FIGS. 4, the voltage detection unit (160) can periodically detect the level of the input voltage (Vcc) supplied from an external power source. The voltage detection unit (160) can generate voltage information (V_Inf) indicating whether an event has occurred in which the level of the input voltage (Vcc) supplied from the external power source drops below a reference level (Vref). Here, the reference level (Vref) may be a preset value. The voltage detection unit (160) can output the generated voltage information (V_Inf) to the memory controller (200).

[0072] In one embodiment, the voltage detection unit (160) can generate voltage information (V_Inf) indicating that an event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref) after the level of the input voltage (Vcc) has risen above the reference level (Vref), and output the generated voltage information (V_Inf) to the memory controller (200). For example, the value of the generated voltage information (V_Inf) may be 1. The memory controller (200) can identify that an event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref) through the value of the voltage information (V_Inf). In this case, the memory controller (200) can determine that the input voltage (Vcc) provided to the memory device (100) is in an unstable state.

[0073] In one embodiment, the voltage detection unit (160) can generate voltage information (V_Inf) indicating that an event of the input voltage (Vcc) falling below the reference level (Vref) has not occurred, if the input voltage (Vcc) level rises above the reference level (Vref) and then does not fall below the reference level (Vref), and output the generated voltage information (V_Inf) to the memory controller (200). For example, the value of the generated voltage information (V_Inf) may be 0. The memory controller (200) can identify that an event of the input voltage (Vcc) level falling below the reference level (Vref) has not occurred through the value of the voltage information (V_Inf). In this case, the memory controller (200) can determine that the input voltage (Vcc) provided to the memory device (100) is in a stable state.

[0074] The voltage detection unit (160) can output voltage information (V_Inf) when an event occurs in which the level of the input voltage (Vcc) drops below a reference level (Vref). Alternatively, the voltage detection unit (160) can output voltage information (V_Inf) at preset intervals. Alternatively, the voltage detection unit (160) can output voltage information (V_Inf) in response to a command requesting voltage information (V_Inf) received from the memory controller (200).

[0075] In one embodiment, the event may be set as an event where the level of the input voltage (Vcc) drops below a first reference level or rises above a second reference level. Here, the first reference level may be a level lower than the second reference level. In this case, the voltage detection unit (160) may output voltage information (V_Inf) indicating whether an event occurs where the level of the input voltage (Vcc) drops below the first reference level or rises above the second reference level. That is, the voltage information (V_Inf) may indicate whether the level of the input voltage (Vcc) falls within the interval between the first reference level and the second reference level. If the level of the input voltage (Vcc) falls within the interval between the first reference level and the second reference level, it is determined to be in a stable state, and if the level of the input voltage (Vcc) does not fall within that interval, it is determined to be in an unstable state.

[0076] In another embodiment, the event may be set as an event in which the number of times the input voltage (Vcc) drops below a reference level exceeds a preset number. In this case, the voltage detection unit (160) may output voltage information (V_Inf) indicating whether the event in which the number of times the input voltage (Vcc) drops below a reference level exceeds a preset number has occurred.

[0077] Meanwhile, the memory device (100) may include a buffer (not shown). The buffer may temporarily store voltage information (V_Inf). The buffer may output the stored voltage information (V_Inf). To this end, the buffer may include at least one of volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc. or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0079] FIG. 5 is a diagram illustrating the structure of a memory controller according to an embodiment of the present invention.

[0080] Referring to FIG. 5, the memory controller (200) may include a voltage information management unit (210) and a voltage information storage unit (215).

[0081] The voltage information management unit (210) receives voltage information (V_Inf) from the memory device (100) and can store the received voltage information (V_Inf) in the voltage information storage unit (215).

[0082] In one embodiment, the voltage information management unit (210) can update the voltage information (V_Inf) stored in the voltage information storage unit (215) to indicate that no event has occurred if, during a reference time from the time when the event occurred, voltage information (V_Inf) indicating that an event has occurred is not received from the memory device (100).

[0083] In one embodiment, the voltage information management unit (210) may update the voltage information (V_Inf) stored in the voltage information storage unit (215) to indicate that no event has occurred if, during a reference time from a certain point in time, voltage information (V_Inf) indicating that an event has occurred is not received from the memory device (100). The certain point in time may be any point in time unrelated to the point in time when the event occurred.

[0084] The voltage information storage unit (215) can store voltage information (V_Inf). The voltage information storage unit (215) can transfer the stored voltage information (V_Inf) to the voltage information management unit (210) or the read reclaim operation control unit (230).

[0085] To this end, the voltage information storage unit (215) may include at least one of volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc. or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0086] The memory controller (200) may include a read operation control unit (220).

[0087] The read operation control unit (220) can control the memory device (100) to perform a read operation to read a page included in a selected memory block among a plurality of memory blocks. That is, the read operation control unit (220) can provide a read command (CMD_R1) to the memory device (100) instructing it to perform a read operation to read a page included in a selected memory block. In response to this, the memory device (100) can perform a read operation to read data stored in the selected page. The read operation may be an operation to read data stored in the selected page by applying a default read voltage to the selected page among the pages included in the selected memory block and applying a pass voltage to the unselected page included in the selected memory block. The memory device (100) can output read data (Data_R1) read by the read operation.

[0088] The read operation control unit (220) can receive read data (Data_R1) read by the read operation from the memory device (100). The read operation control unit (220) can perform an error correction decoding operation to correct error bits included in the received read data (Data_R1).

[0089] In one embodiment, when an error correction decoding operation that corrects an error bit included in the read data (Data_R1) is passed, the read operation control unit (220) can provide the corrected data (Data_C), in which the error bit included in the read data (Data_R1) is corrected, to the host (20).

[0090] Meanwhile, in another embodiment, the read operation control unit (220) can control the memory device (100) to perform a plurality of recovery read operations, which read pages included in a selected memory block while changing the read voltage until the error correction decoding operation fails when the error correction decoding operation that corrects an error bit included in the read data (Data_R1) fails. The order of the plurality of recovery read operations can be pre-set. The read operation control unit (220) can transmit a recovery read count (RRC), which indicates the number of times the plurality of recovery read operations are performed sequentially until the error correction decoding operation is passed, to the read reclaim operation control unit (230).

[0091] A recovery read operation may involve varying the default read voltage according to a specific algorithm to acquire read data using the varied read voltage. A recovery read operation can be performed when the distribution of threshold voltages of memory cells changes to such an extent that it is difficult to distinguish the distribution of threshold voltages of memory cells through the default read voltage.

[0092] In one embodiment, a plurality of recovery read operations may include read retry, history read, optimal read voltage search, and soft read operations. However, this is merely one embodiment, and a plurality of recovery read operations may include recovery read operations according to various algorithms.

[0093] For example, the read operation control unit (220) may provide a first recovery read command (CMD_R2) to the memory device (100) instructing to perform a first recovery read operation if the error correction decoding operation for correcting error bits included in the read data (Data_R1) fails. The read operation control unit (220) may receive the read data (Data_R2) obtained by the first recovery read operation from the memory device (100).

[0094] Additionally, the read operation control unit (220) can perform an error correction decoding operation to correct an error bit included in the read data (Data_R2) obtained by the first recovery read operation. Here, if the error correction decoding operation to correct an error bit included in the read data (Data_R2) is passed, the read operation control unit (220) can provide the corrected data (Data_C), in which the error bit included in the read data (Data_R2) has been corrected, to the host (20).

[0095] Meanwhile, the read operation control unit (220) may provide a second recovery read command to the memory device (100) instructing it to perform a second recovery read operation if the error correction decoding operation for correcting error bits included in the read data (Data_R2) fails. The read operation control unit (220) may receive the read data obtained by the second recovery read operation from the memory device (100) and perform an error correction decoding operation for correcting error bits included in the read data obtained by the second recovery read operation. The recovery read operation may be performed sequentially until the error correction decoding operation passes.

[0096] The memory controller (200) may include a read count storage unit (225).

[0097] The read count storage unit (225) can store a read count (RC) indicating the number of times a read operation is performed for each of the multiple memory blocks. For example, whenever the read operation control unit (220) controls the memory device (100) to perform a read operation for any one memory block, it can update the read count (RC) for the corresponding memory block and store it in the read count storage unit (225). The read count storage unit (225) can output the stored read count (RC).

[0098] To this end, the read count storage unit (225) may include at least one of volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc. or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0099] The memory controller (200) may include a read reclaim operation control unit (230).

[0100] The read reclaim operation control unit (230) can adjust the threshold count. For example, the read reclaim operation control unit (230) can set the threshold count to a first threshold count or a second threshold count. Here, the threshold count may be at least one of threshold count A and threshold count B described later. More specific details will be explained with reference to FIG. 7.

[0101] In one embodiment, the read reclaim operation control unit (230) can control the memory device (100) to move the data contained in the selected memory block to another memory block when the read count (RC) of the selected memory block among a plurality of memory blocks exceeds a threshold count A. Here, the data contained in the selected memory block may include corrected data (Data_C) in which the error bits contained in the read data are corrected.

[0102] In one embodiment, the read reclaim operation control unit (230) can control the memory device (100) to move valid data among the data contained in the selected memory block to another memory block when the read count (RC) of the selected memory block among the plurality of memory blocks exceeds a threshold count A. That is, invalid data among the data contained in the selected memory block may not be moved to another memory block.

[0103] Valid data may refer to data stored when it is possible to identify which logical address the stored data is stored at. Invalid data may refer to data stored when it is impossible to identify which logical address the stored data is stored at. For example, valid data may represent data stored in a page corresponding to a physical address in the memory device (100) when a physical address is assigned to a logical address. Invalid data may represent data stored in a page corresponding to a previous physical address in the memory device (100) when a new physical address is assigned after a physical address has been assigned to a logical address.

[0104] In one embodiment, the read reclaim operation control unit (230) can control the memory device (100) to move data stored in a selected memory block containing corrected data (Data_C) corrected through a passed error correction decoding operation to another memory block when the recovery read count (RRC), which indicates the number of times a plurality of recovery read operations have been performed, exceeds a threshold count B.

[0105] In one embodiment, the read reclaim operation control unit (230) can control the memory device (100) to move valid data among the data stored in the pages included in the selected memory block to another memory block when the recovery read count (RRC), which indicates the number of times a plurality of recovery read operations have been performed, exceeds the threshold count B. That is, invalid data among the data included in the selected memory block may not be moved to another memory block.

[0107] FIGS. 6a and FIGS. 6b are drawings illustrating the distribution of threshold voltage according to an embodiment of the present invention.

[0108] Referring to FIG. 6a, the case in which a memory device (100) performs a program operation on a selected page among the pages included in a memory block included in the memory device (100) according to a multi-level cell (MLC) method is described. In this case, the memory cells included in the selected page may have a distribution of threshold voltages distinguished by an erase state (E0) and each program state (P1~P3).

[0109] And, the memory device (100) can perform a read operation on a selected page and output read data read from the selected page. For example, the memory device (100) can output read data by applying a first read voltage (Vr1) to a third read voltage (Vr3) generated using an input voltage (Vcc) to the selected page. Here, each of the first read voltage (Vr1) to the third read voltage (Vr3) may be a read voltage set as a default to distinguish each state, such as an erase state (E0) and each program state (P1~P3).

[0110] For a specific example, the memory device (100) may apply a first read voltage (Vr1) to a selected page and a pass voltage to a non-selected page. In this case, the cell that turns on as the first read voltage (Vr1) is applied can be identified as being in an erase state (E0). The memory device (100) may apply a second read voltage (Vr2) to a selected page and a pass voltage to a non-selected page. In this case, among the cells that turn on as the second read voltage (Vr2) is applied, the remaining cells excluding the cell identified as being in an erase state (E0) can be identified as being in a first program state (P1). The memory device (100) may apply a third read voltage (Vr3) to a selected page and a pass voltage to a non-selected page. In this case, among the cells turned on by applying the third lead voltage (Vr3), the remaining cells, excluding the cells identified as the erase state (E0) and the first program state (P1), can be identified as being in the second program state (P2). And, the cells that are not turned on can be identified as being in the third program state (P3). The erase state (E0) and each program state (P1~P3) may represent data having a specific number of bits. For example, the data may be 11, 10, 01, 00, etc.

[0111] Referring to FIGS. 6a and 6b, the distribution of threshold voltages of memory cells as in FIG. 6a can be degraded as in the erase state (E0') and each program state (P1'~P3') as in FIG. 6b. Here, the erase state (E0') and the program states (P1'~P3') may partially overlap each other.

[0112] In particular, the degradation of the threshold voltage may be accelerated when program or read operations are performed using an operating voltage generated by an unstable input voltage (Vcc). Under such conditions, if a selected page is read using the default read voltages (Vr1~Vr3), the number of error bits included in the read data may increase depending on the threshold voltages of the degraded memory cells. Here, an error bit may represent a bit where data loss or alteration has occurred. If the number of error bits exceeds a correctable limit, it may become impossible to correct the error bits.

[0113] To resolve this, the memory controller (200) may perform a read reclaim operation to move data stored in a memory block to another memory block at a time when it is possible to read valid data. Since the read reclaim operation may cause overhead during execution and lead to performance degradation of the memory device (100), optimization of the read reclaim operation may be required.

[0114] According to one embodiment of the present disclosure, the memory controller (200) can control a threshold count that functions as a trigger for performing a read reclaim operation.

[0115] Specifically, the memory controller (200) can adjust the threshold count based on voltage information (V_Inf). The memory controller (200) can identify whether an event occurs in which the level of the input voltage (Vcc) drops below a reference level (Vref) through the value of the voltage information (V_Inf). If an event occurs in which the level of the input voltage (Vcc) drops below the reference level (Vref), the input voltage (Vcc) is in an unstable state, and if no event occurs in which the level of the input voltage (Vcc) drops below the reference level (Vref), the input voltage (Vcc) is in a stable state. Here, the threshold count is a value used to compare with the number of times a read operation is performed or the number of times a recovery read operation is performed. That is, the memory controller (200) can adjust the threshold count depending on whether the input voltage (Vcc) is in a stable state or an unstable state.

[0116] In one embodiment, the memory controller (200) may store a read count indicating the number of times a read operation is performed for each of the plurality of memory blocks.

[0117] The memory controller (200) can obtain a read count in various ways. For example, the memory controller (200) can obtain the number of times a control command is transmitted to perform a read operation for each of the multiple memory blocks included in the memory device (100) as the read count for each of the multiple memory blocks. As another example, the memory controller (200) can obtain a read count by receiving a read count for each of the multiple memory blocks from the memory device (100).

[0118] The memory controller (200) can control the memory device (100) to move data stored in a memory block where the read count exceeds the threshold count to another memory block. Here, moving means copying data stored in a memory block to another memory block and then deleting the data stored in the memory block. That is, the memory controller (200) can control the memory device (100) to perform a program operation to store data stored in a memory block where the read count exceeds the threshold count to another memory block, and to perform an erase operation to delete data stored in a memory block where the read count exceeds the threshold count.

[0119] In one embodiment, the memory controller (200) may provide a read command to the memory device (100) instructing it to perform a read operation to read a page included in a selected memory block using read voltages (Vr1, Vr2, Vr3) generated through an input voltage (Vcc). Data including a parity bit may be stored in the page included in the selected memory block. That is, the data stored in the memory device (100) may include actual data and a parity bit. Here, the parity bit may represent an identifier used to detect an error in the data, i.e., an error bit. For example, the parity bit may be inserted at the beginning or end of the data bits for the actual data. As another example, the parity bit may be inserted at a power of 2 position, such as 1, 2, 4, 8, 16, ..., and the data bits for the actual data may be arranged at the remaining positions. The memory controller (200) may receive the read data read by the read operation from the memory device (100).

[0120] The memory controller (200) can perform an error correction decoding operation to correct error bits included in the read data.

[0121] Specifically, the memory controller (200) can detect error bits included in the read data by using parity bits included in the read data. For example, the memory controller (200) can detect error bits included in the read data by using various methods such as a parity check, a block sum check, and a cycle redundancy check (CRC).

[0122] The memory controller (200) can identify that the error correction decoding operation has passed if the number of error bits is less than or equal to a correctable limit. If the error correction decoding operation has passed, the memory controller (200) can correct the error bits included in the read data. Meanwhile, the memory controller (200) can identify that the error correction decoding operation has failed if the number of error bits exceeds a correctable limit. In this case, if the error correction decoding operation has failed, the memory controller (200) cannot correct the error bits included in the read data.

[0123] And, the memory controller (200) can perform a plurality of recovery read operations to read pages included in a selected memory block while changing the read voltages (Vr1, Vr2, Vr3) until the error correction decoding operation to correct error bits included in the read data fails.

[0124] The memory controller (200) can control the memory device (100) to move data stored in a selected memory block to another memory block when the number of times multiple recovery read operations are performed exceeds a threshold count. Since the detailed configuration of the memory controller (200) has been described in FIG. 5, redundant details will be omitted.

[0126] FIG. 7 is a drawing for explaining a method of operation according to an embodiment of the present invention.

[0127] Referring to FIG. 7, the read reclaim operation control unit (230) can adjust the threshold count based on voltage information (V_Inf) (S710). In one embodiment, the read reclaim operation control unit (230) can set the threshold count to a first threshold count. The read reclaim operation control unit (230) can change the threshold count to a second threshold count lower than the first threshold count in response to voltage information (V_Inf) indicating that an event has occurred.

[0128] In one embodiment, the read claim operation control unit (230) can adjust the threshold count using a threshold count table (235). This will be explained with reference to FIG. 8.

[0130] FIG. 8 is a drawing for explaining a threshold count table according to an embodiment of the present invention.

[0131] Referring to FIGS. 5 and FIGS. 8, the read reclaim operation control unit (230) can store a threshold count table (235).

[0132] In one embodiment, the threshold count table (235) may include a first threshold count (THA_1) for a threshold count A mapped to a value of voltage information (V_Inf) (e.g., 0) indicating that no event occurred, and a second threshold count (THA_2) for a threshold count A mapped to a value of voltage information (V_Inf) (e.g., 1) indicating that an event occurred. Here, threshold count A represents a value compared with a read count (RC) indicating the number of times a read operation is performed for each memory block. The second threshold count (THA_2) may be a lower value than the first threshold count (THA_1). For example, the first threshold count (THA_1) may be 100,000 times and the second threshold count (THA_2) may be 30,000 times.

[0133] In one embodiment, the threshold count table (235) may include a first threshold count (THB_1) for threshold count B mapped to a value of voltage information (V_Inf) (e.g., 0) indicating that no event occurred, and a second threshold count (THB_2) for threshold count B mapped to a value of voltage information (V_Inf) (e.g., 1) indicating that an event occurred. Here, threshold count B represents a value compared with a recovery read count (RRC) which represents the number of times different recovery read operations were performed as the error correction decoding operation failed. The second threshold count (THB_2) may be a lower value than the first threshold count (THB_1). For example, the first threshold count (THB_1) may be 10 times and the second threshold count (THB_2) may be 5 times. Threshold count B may be referred to as a reference count to distinguish it from threshold count A.

[0134] The read reclaim operation control unit (230) can adjust the threshold count based on the threshold count table (235). For example, the read reclaim operation control unit (230) can adjust the threshold count to one of the first threshold count and the second threshold count included in the threshold count table (235) that corresponds to the value of the voltage information (V_Inf) stored in the voltage information storage unit (215).

[0135] For a specific example, the read reclaim operation control unit (230) may apply a normal recovery mode when the voltage information (V_Inf) has a value of 0. The normal recovery mode may be to apply a first threshold count (THA_1) to threshold count A and to apply a first threshold count (THB_1) to threshold count B.

[0136] Meanwhile, the read reclaim operation control unit (230) may apply a quick recovery mode when the voltage information (V_Inf) has a value of 1. The quick recovery mode may apply a second threshold count (THA_2) to threshold count A and apply a second threshold count (THB_2) to threshold count B.

[0137] Referring again to FIG. 7, the read reclaim operation control unit (230) can identify a memory block in which the read count (RC) is greater than the threshold count A (S720).

[0138] Specifically, the read reclaim operation control unit (230) can compare the read count (RC) for each of the plurality of memory blocks stored in the read count storage unit (225) with the threshold count A. The read count (RC) will be explained with reference to FIG. 9.

[0140] FIG. 9 is a drawing for explaining a lead count according to an embodiment of the present invention.

[0141] Referring to FIG. 9, the read count storage unit (225) can store read counts (RC) aggregated in units of memory blocks. For example, the read count storage unit (225) can store a first read count (RC1) for a first memory block (Blk1), a second read count (RC2) for a second memory block (Blk2), a third read count (RC3) for a third memory block (Blk3), a fourth read count (RC4) for a fourth memory block (Blk4), ...

[0142] A read count (RC) may indicate the number of times a read operation is performed to read a page included in a memory block. For example, assuming that a read operation is performed once for a first page included in a first memory block (Blk1) and a read operation is performed once for a second page included in the first memory block (Blk1), the first read count (RC1) for the first memory block (Blk1) may be 2 times.

[0143] Referring again to FIG. 7, the read count storage unit (225) can compare the read count (RC) for each of the plurality of memory blocks stored in the read count storage unit (225) with the adjusted threshold count A. If there is a memory block in which the read count (RC) exceeds the threshold count A (S720, Yes), the read count storage unit (225) can select the memory block in which the read count (RC) exceeds the threshold count A. Meanwhile, if there is no memory block in which the read count (RC) exceeds the threshold count A (S720, No), the read count storage unit (225) can terminate the operation without performing a read reclaim operation.

[0144] The read reclaim operation control unit (230) can control the memory device (100) to move data stored in a selected memory block to another memory block (S730). That is, the read reclaim operation control unit (230) can control the memory device (100) to perform a read reclaim operation on a memory block where the read count (RC) exceeds a threshold count A.

[0146] FIG. 10 is a drawing for explaining a method of operation according to an embodiment of the present invention.

[0147] Referring to FIG. 10, the memory controller (200) can control the memory device (100) to perform a read operation to read a page included in a selected memory block (S1010). The memory controller (200) can receive read data read by the read operation from the memory device (100).

[0148] The memory controller (200) can perform an error correction decoding operation to correct error bits included in the read data (S1020).

[0149] In one embodiment, when the error correction decoding operation for correcting the error bit included in the read data is passed (S1030, Yes), the memory controller (200) can provide the corrected data (Data_C), in which the error bit included in the read data (Data_R1) is corrected, to the host (20) (S1050).

[0150] Meanwhile, the memory controller (200) can periodically check voltage information (V_Inf) and adjust the threshold count based on the voltage information (V_Inf). The memory controller (200) can apply a first threshold count (THA_1) to threshold count A and apply a first threshold count (THB_1) to threshold count B when the voltage information (V_Inf) has a value of 0, indicating that no event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref). Meanwhile, the memory controller (200) can apply a second threshold count (THA_2), which is lower than the first threshold count (THA_1), to threshold count A and apply a second threshold count (THB_2), which is lower than the first threshold count (THB_1), to threshold count B when the voltage information (V_Inf) has a value of 1, indicating that an event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref). That is, the operation of adjusting the threshold count is performed periodically and can be performed regardless of the order in which the operations shown in FIG. 10 are performed.

[0151] If there is a memory block in which the read count (RC) exceeds the threshold count A (S1060, Yes), the memory controller (200) can select the memory block in which the read count (RC) exceeds the threshold count A. Meanwhile, if there is no memory block in which the read count (RC) exceeds the threshold count A (S1060, No), the memory controller (200) can terminate the operation without performing a read reclaim operation.

[0152] The memory controller (200) can control the memory device (100) to move data stored in a selected memory block to another memory block (S1070). In one embodiment, the memory controller (200) can control the memory device (100) to move valid data among the data contained in the selected memory block to another memory block.

[0153] In one embodiment, the memory controller (200) can control the memory device (100) to perform a plurality of recovery read operations, which read pages included in a selected memory block while changing the read voltage until the error correction decoding operation fails (S1030, No) when the error correction decoding operation that corrects error bits included in the read data fails.

[0154] Specifically, the memory controller (200) can control the memory device (100) to perform the Nth recovery read operation. Here, N is a natural number and may represent the order in which the recovery read operation is performed. Specific details regarding this will be explained with reference to FIG. 11.

[0155] The memory controller (200) can control the memory device (100) to perform the Nth recovery read operation (S1031). In response to this, the memory device (100) can output the read data read by the first recovery read operation. The memory controller (200) can perform an error correction decoding operation to correct the error bits included in the read data (S1032).

[0156] Here, if the error correction decoding operation is passed (S1033, Yes), the memory controller (200) can provide the corrected data (Data_C), in which the error bits included in the read data are corrected, to the host (20) (S1035). Meanwhile, if the error correction decoding operation fails (S1033, No), the memory controller (200) can control the memory device (100) to perform the N+1 recovery read operation (S1034, S1031). Afterwards, the above-described operation can be repeated.

[0157] The memory controller (200) can select a memory block on which multiple recovery read operations have been performed if the recovery read count (RRC), which indicates the number of times multiple recovery read operations have been performed, exceeds a threshold count B (S1036, Yes). Meanwhile, the memory controller (200) can terminate the operation without performing a read reclaim operation if the recovery read count (RRC) does not exceed the threshold count B (S1036, No).

[0158] The memory controller (200) can control the memory device (100) to move data stored in a selected memory block to another memory block (S1037). Here, the data stored in the selected memory block may include corrected data (Data_C). In one embodiment, the memory controller (200) can control the memory device (100) to move valid data among the data included in the selected memory block to another memory block.

[0160] FIG. 11 is a drawing for explaining a recovery read operation according to an embodiment of the present invention.

[0161] Referring to FIG. 11, a plurality of recovery read operations may include Read Retry, History Read, Optimal Read Voltage Search, and Soft Read operations. For example, the first recovery read operation may be a Read Retry operation, the second recovery read operation may be a History Read operation, the third recovery read operation may be an Optimal Read Voltage Search operation, and the fourth recovery read operation may be a Soft Read operation.

[0162] In the case of (1) in FIG. 11, the error correction decoding operation according to the first recovery read operation fails and the second recovery read operation is performed, and the error correction decoding operation according to the second recovery read operation fails and the third recovery read operation is performed and the error correction decoding operation according to the third recovery read operation is passed. In this case, the recovery read count (RRC) indicating the number of times multiple recovery read operations are performed may be 3 times.

[0163] In the case of (2) in FIG. 11, the error correction decoding operation according to the first recovery read operation fails and the second recovery read operation is performed, the error correction decoding operation according to the second recovery read operation fails and the third recovery read operation is performed, the error correction decoding operation according to the third recovery read operation fails and the fourth recovery read operation is performed, and the error correction decoding operation according to the fourth recovery read operation is passed. In this case, the recovery read count (RRC) indicating the number of times multiple recovery read operations are performed may be 4 times.

[0164] In one embodiment, the memory controller (200) may apply a first threshold count (THB_1) to the threshold count B when the voltage information (V_Inf) has a value of 0, indicating that no event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref).

[0165] Here, it is assumed that the first threshold count (THB_1) is 3 times. In the case of (1) in FIG. 11, the memory controller (200) may not control the memory device (100) to perform a read reclaim operation because the 3 recovery read counts (RRC) do not exceed the 3 first threshold counts (THB_1). In the case of (2) in FIG. 11, the memory controller (200) may control the memory device (100) to perform a read reclaim operation because the 4 recovery read counts (RRC) exceed the 3 first threshold counts (THB_1).

[0166] In one embodiment, the memory controller (200) may apply a second threshold count (THB_2) lower than the first threshold count (THB_1) to the threshold count B when the voltage information (V_Inf) has a value of 1 indicating that an event has occurred in which the level of the input voltage (Vcc) drops below the reference level (Vref).

[0167] Here, it is assumed that the second threshold count (THB_2) is 2 times. In the case of (1) in FIG. 11, the memory controller (200) can control the memory device (100) to perform a read reclaim operation when the recovery read count (RRC) of 3 times exceeds the second threshold count (THB_2) of 2 times. In the case of (2) in FIG. 11, the memory controller (200) can control the memory device (100) to perform a read reclaim operation when the recovery read count (RRC) of 4 times exceeds the second threshold count (THB_2) of 2 times.

[0168] In this way, the memory controller (200) can ensure data reliability by relaxing the conditions for performing a read reclaim operation when the input voltage (Vcc) provided to the memory device (100) is in an unstable state compared to when the input voltage (Vcc) is in a stable state.

[0170] FIG. 12 is a drawing for explaining one of the recovery read operations according to an embodiment of the present invention.

[0171] Referring to FIG. 12, the memory controller (200) may store a read retry table for performing a read retry operation. For example, the read retry table may be stored in the read operation control unit (220). The read retry table may include an index and a level for each read voltage (Vr1, Vr2, Vr3) mapped to the index. The index may indicate the order of changing the levels of the read voltages.

[0172] The memory controller (200) can control the memory device (100) to perform a read operation by changing the default level of each read voltage (Vr1, Vr2, Vr3) to a level included in the read retry table. For example, the memory controller (200) can control the memory device (100) to perform a read operation by changing the level of each read voltage (Vr1, Vr2, Vr3) in order according to the index included in the read retry table. In response to this, the memory device (100) can perform a read operation with a read voltage having a changed level and output the read data read by the read operation. The memory controller (200) can perform an error correction decoding operation to correct error bits included in the read data. When the error correction decoding operation is passed, the memory controller (200) can output corrected data with the error bits included in the read data to the host (20). Meanwhile, if the error correction decoding operation fails, the memory controller (200) can control the memory device (100) to perform a read operation by changing the level of each read voltage (Vr1, Vr2, Vr3) mapped to the index of the next sequence. The memory controller (200) can perform the above-described operation sequentially.

[0173] Meanwhile, the memory controller (200) can control the memory device (100) to perform the next sequence of recovery read operations when the error correction decoding operation for the received read data fails according to the read retry operation. The next sequence of recovery read operations may be one of a history read operation, an optimal read voltage search operation, or a soft read operation.

[0174] For example, a history read operation may store the level of the read voltage used for the read operation when a previously performed error correction decoding operation is passed, and perform the read operation using the read voltage having the stored level. An optimal read voltage search operation may be performed by the memory device (100) applying a read voltage to a selected page of a selected memory block in a changing manner to detect a read voltage at which the number of memory cells having overlapping program states (e.g., P1, P2) is minimized, and performing the read operation using the detected read voltage. A soft read operation may be performed by the memory device (100) reading the threshold voltage of the memory cells included in a selected page of a selected memory block in multiple bits to correct the error bit. For example, the memory controller (200) can correct error bits using various coded modulations such as LDPC (low density parity check) code, BCH (Bose-Chaudhuri-Hocquenghem) code, TPC (turbo product code), Reed-Solomon code, convolution code, RSC (recursive systematic code), TCM (trellis-coded modulation), and BCM (Block coded modulation), but is not limited thereto.

[0176] FIG. 13 is a drawing for explaining the operation method of a memory system according to an embodiment of the present invention.

[0177] Referring to FIG. 13, the method of operation of a memory system (10) according to one embodiment of the present disclosure can adjust a threshold count based on voltage information (V_Inf) indicating whether an event occurs in which the level of an input voltage (Vcc) drops below a reference level (Vref) (S1310).

[0178] And, data stored in a memory block where the read count (RC), which indicates the number of times a read operation is performed for each of the multiple memory blocks, exceeds the threshold count, can be moved to another memory block included in the memory device (100) (S1320). For memory blocks where the read count (RC) does not exceed the threshold count, a read reclaim operation may not be performed.

[0180] FIG. 14 is a drawing for explaining the operation method of a memory system according to an embodiment of the present invention.

[0181] Referring to FIG. 14, the method of operation of a memory system (10) according to one embodiment of the present disclosure can adjust a threshold count based on voltage information (V_Inf) indicating whether an event occurs in which the level of an input voltage (Vcc) drops below a reference level (Vref) (S1410).

[0182] And, read data can be obtained by a read operation that reads a page included in a selected memory block among a plurality of memory blocks included in the memory device (100) using a read voltage generated through an input voltage (Vcc) (S1420).

[0183] And, if the error correction decoding operation that corrects the error bits included in the read data fails, multiple recovery read operations can be performed to read the pages included in the selected memory block using the voltage that changed the read voltage until the error correction decoding operation passes (S1430).

[0184] And, if the recovery read count (RRC), which indicates the number of times multiple recovery read operations have been performed, exceeds a threshold count, the data stored in the selected memory block can be moved to another memory block included in the memory device (100) (S1440). For memory blocks where the recovery read count (RRC) does not exceed the threshold count, a read reclaim operation may not be performed.

[0186] FIG. 15 is a block diagram showing a memory card to which a memory system according to an embodiment of the present invention is applied.

[0187] Referring to FIG. 15, the memory card (2000) may include a memory device (2100), a memory controller (2200), and a connector (2300).

[0188] The memory device (2100) can perform a program operation to store data. For example, the memory device (2100) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque Magnetic RAM), etc. The description of the memory device (100) described with reference to FIG. 1, etc. may be applied equally to the memory device (2100), and redundant content will be omitted below.

[0189] The memory controller (2200) may be configured to access the memory device (2100). For example, the memory controller (2200) may be configured to control the program operation, read operation, and erase operation of the memory device (2100). The memory controller (2200) is configured to provide an interface between the memory device (2100) and a host. The memory controller (2200) is configured to run firmware for controlling the memory device (2100). The memory controller (2200) may be implemented in the same way as the memory controller (200) described with reference to FIG. 1.

[0190] For example, the memory controller (2200) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0191] The memory controller (2200) can communicate with an external device through a connector (2300). The memory controller (2200) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller (2200) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (2300) may be defined by at least one of the various communication standards described above.

[0192] The memory device (2100) and the memory controller (2200) can be integrated into a single semiconductor device to form a memory card. For example, the memory device (2100) and the memory controller (2200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0194] FIG. 16 is a block diagram showing a Solid State Drive (SSD) system to which a memory system according to an embodiment of the present invention is applied.

[0195] Referring to FIG. 16, the SSD system (3000) may include a plurality of flash memories (3100_1 to 3100_n), an SSD controller (3200), an auxiliary power supply (3030), and a buffer memory (3040).

[0196] The SSD system (3000) can exchange signals with the host (3300) through the signal connector (3010) and receive power through the power connector (3020).

[0197] Each of the plurality of flash memories (3100_1 to 3100_n) can perform a program operation to store data. For example, each of the plurality of flash memories (3100_1 to 3100_n) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque Magnetic RAM), etc. The description of the memory device (100) described with reference to FIG. 1, etc. may be applied equally to each of the plurality of flash memories (3100_1 to 3100_n), and redundant content will be omitted below.

[0198] The SSD controller (3200) can control a plurality of flash memories (3100_1 to 3100_n) in response to a signal received from the host (3300). For example, the signal may be a signal based on an interface between the host (3300) and the SSD system (3000). For example, the signal may be a signal defined by at least one of interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. According to an embodiment of the present invention, the SSD controller (3200) can perform the function of the memory controller (200) described with reference to FIG. 1.

[0199] The auxiliary power unit (3030) can be connected to the host (3300) via the power connector (3020). The auxiliary power unit (3030) can receive power from the host (3300) and charge. The auxiliary power unit (3030) can provide power to the SSD system (3000) when power supply from the host (3300) is not smooth. For example, the auxiliary power unit (3030) may be located inside the SSD system (3000) or outside the SSD system (3000). For example, the auxiliary power unit (3030) may be located on the main board and provide auxiliary power to the SSD system (3000).

[0200] The buffer memory (3040) can operate as a buffer memory of the SSD system (3000). For example, the buffer memory (3040) can temporarily store data received from the host (3300) or data received from a plurality of flash memories (3100_1 to 3100_n), or temporarily store metadata (e.g., mapping tables) of the flash memories (3100_1 to 3100_n). The buffer memory (3040) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0202] FIG. 17 is a block diagram showing a user system to which a memory system according to an embodiment of the present invention is applied.

[0203] Referring to FIG. 17, the user system (4000) may include an application processor (4100), a memory module (4200), a network module (4300), a storage module (4400), and a user interface (4500).

[0204] The application processor (4100) can run components included in the user system (4000), an operating system (OS), or user programs, etc. For example, the application processor (4100) may include controllers, interfaces, graphics engines, etc. that control components included in the user system (4000). The application processor (4100) may be provided as a System-on-Chip (SoC).

[0205] The memory module (4200) can operate as the main memory, operational memory, buffer memory, or cache memory of the user system (4000). The memory module (4200) may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc. or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor (4100) and the memory module (4200) may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0206] The network module (4300) can communicate with external devices. For example, the network module (4300) can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module (4300) can be included in the application processor (4100).

[0207] The storage module (4400) can store data. For example, the storage module (4400) can store data received from the application processor (4100). Alternatively, the storage module (4400) can transfer data stored in the storage module (4400) to the application processor (4100). For example, the storage module (4400) can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or a three-dimensional NAND flash. For example, the storage module (4400) can be provided as a removable storage medium such as a memory card or an external drive of the user system (4000).

[0208] For example, the storage module (4400) may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device (100) described with reference to FIG. 1. The storage module (4400) may operate in the same manner as the memory system (10) described with reference to FIG. 1.

[0209] The user interface (4500) may include interfaces for inputting data or commands to the application processor (4100) or outputting data to an external device. For example, the user interface (4500) may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. The user interface (4500) may include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display, AMOLED (Active Matrix OLED) display, LED, speaker, monitor, etc. Explanation of the symbols

[0210] 10: Memory System 100: Memory device 110: Memory cell array 120: Voltage generation unit 130: Address decoder 140: Input / output circuit 150: Control logic 160: Voltage detection unit 200: Memory controller 210: Voltage Information Management Unit 215: Voltage Information Storage Unit 220: Read operation control unit 225: Read count storage unit 230: Read reclaim operation control unit

Claims

Claim 1 A memory system comprising: a memory device including a plurality of memory blocks and outputting voltage information indicating whether an event has occurred in which the level of an input voltage provided from an external power source drops below a reference level; and a memory controller storing a read count indicating the number of times a read operation is performed for each of the plurality of memory blocks, controlling the memory device to move data stored in a memory block where the read count exceeds a threshold count to another memory block, and adjusting the threshold count based on the voltage information. Claim 2 A memory system according to claim 1, wherein the memory controller includes a read reclaim operation control unit that sets the threshold count to a first threshold count and, in response to voltage information indicating that the event has occurred, changes the threshold count to a second threshold count lower than the first threshold count. Claim 3 In paragraph 2, the memory system further comprises: a memory controller that controls the memory device to perform a read operation for reading a page included in a selected memory block among the plurality of memory blocks, receives read data obtained by the read operation from the memory device, and performs an error correction decoding operation for correcting an error bit included in the read data. Claim 4 In paragraph 3, the selected memory block is a memory block among the plurality of memory blocks in which the read count exceeds the threshold count, and the read reclaim operation control unit controls the memory device to move the data in which the error bit included in the read data has been corrected to another memory block. Claim 5 In paragraph 3, the read operation control unit controls the memory device to perform a plurality of recovery read operations, which read pages included in the selected memory block while changing the read voltage until the error correction decoding operation fails when the error correction decoding operation that corrects error bits included in the read data passes; the read reclaim operation control unit controls the memory device to move data stored in the selected memory block containing data corrected through the passed error correction decoding operation to another memory block when the number of times the plurality of recovery read operations are performed exceeds a reference count; and the memory system adjusts the reference count based on the voltage information. Claim 6 In claim 1, the memory controller is a memory system that controls the memory device to move valid data among the data stored in a memory block where the read count exceeds the threshold count to another memory block. Claim 7 In paragraph 2, the read reclaim operation control unit is a memory system that stores a threshold count table including the first threshold count mapped to the value of voltage information indicating that the event has not occurred and the second threshold count mapped to the value of voltage information indicating that the event has occurred. Claim 8 A memory system according to claim 1, wherein the memory controller comprises: a voltage information storage unit for storing the voltage information; and a voltage information management unit for receiving the voltage information from the memory device and storing the received voltage information in the voltage information storage unit. Claim 9 In claim 8, the voltage information management unit is a memory system that updates the value of the voltage information stored in the voltage information storage unit to indicate that the event has not occurred when, during a reference time from the time the event occurs, voltage information indicating that the event has occurred is not received from the memory device. Claim 10 In claim 1, the memory controller comprises a read count storage unit that stores a read count indicating the number of times a read operation is performed for each of the plurality of memory blocks; a memory system. Claim 11 A memory device comprising a plurality of memory blocks and outputting voltage information indicating whether an event occurs in which the level of an input voltage provided from an external power source drops below a reference level; and a memory controller comprising: receiving read data obtained by a read operation that reads a page included in a selected memory block among the plurality of memory blocks using a read voltage generated through the input voltage from the memory device, and, if an error correction decoding operation that corrects an error bit included in the read data fails, performing a plurality of recovery read operations that read a page included in the selected memory block while changing the read voltage until the error correction decoding operation passes, and, if the number of times the plurality of recovery read operations are performed exceeds a threshold count, controlling the memory device to move data stored in the selected memory block to another memory block; wherein the memory controller adjusts the threshold count based on the voltage information. Claim 12 A memory system according to claim 11, wherein the memory controller includes a read reclaim operation control unit that sets the threshold count to a first threshold count and, in response to voltage information indicating that the event has occurred, changes the threshold count to a second threshold count lower than the first threshold count. Claim 13 In claim 12, the read reclaim operation control unit controls the memory device to move data stored in the selected memory block containing data corrected through the passed error correction decoding operation to another memory block when the number of times the plurality of recovery read operations are performed exceeds the threshold count. Claim 14 In claim 12, the read reclaim operation control unit controls the memory device to move valid data among the data stored in the pages included in the selected memory block to another memory block when the number of times the plurality of recovery read operations are performed exceeds the threshold count. Claim 15 In claim 12, the read reclaim operation control unit is a memory system that stores a threshold count table including the first threshold count mapped to the value of voltage information indicating that the event has not occurred and the second threshold count mapped to the value of voltage information indicating that the event has occurred. Claim 16 A memory system further comprising, in claim 11, a memory controller that controls the memory device to perform a read operation for reading a page included in a selected memory block among the plurality of memory blocks, receives read data obtained by the read operation from the memory device, and performs an error correction decoding operation for correcting an error bit included in the read data. Claim 17 In claim 11, the memory device comprises a voltage detection unit that detects whether the event occurs in which the level of the input voltage drops below the reference level and outputs voltage information indicating whether the event occurs. Claim 18 In claim 11, the memory controller comprises: a voltage information storage unit that stores the voltage information; and a voltage information management unit that receives the voltage information from the memory device and stores the received voltage information in the voltage information storage unit; a memory system. Claim 19 In claim 18, the above voltage information management unit is a memory system that updates the value of the voltage information stored in the voltage information storage unit to indicate that the event has not occurred when, during a reference time from the time the event occurs, voltage information indicating that the event has occurred is not received from the memory device. Claim 20 In claim 11, the plurality of recovery read operations include a read retry, a history read, an optimal read voltage search, and a soft read operation in a memory system.

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