Apparatus and method for controlling relay

Abstract

A relay control device and method according to one embodiment of the present invention provides a relay control device and method capable of maintaining a relay in a closed state even if a processor is reset due to a system error. Accordingly, the relay control device and method according to one embodiment of the present invention has the advantage of preventing accidents caused by the processor reset by maintaining the operating state of a plurality of relays when the processor is reset. In addition, if the operating state of the processor remains in a reset state for a predetermined period of time, the operating state of a plurality of relays is changed to a turn-off state, thereby preventing waste of system resources and energy. Furthermore, when the operating state of the processor is restored, the operating state of a plurality of relays can be controlled by the processor.

Description

Technology Field

[0001] The present invention relates to a relay control device and method, and more specifically, to a relay control device and method capable of maintaining the operating state of a plurality of relays even when a processor is reset due to a system error. Background Technology

[0002] Recently, as the demand for portable electronic products such as laptops, video cameras, and mobile phones has increased rapidly, and the development of energy storage batteries, robots, and satellites has accelerated, research on high-performance secondary batteries capable of repeated charging and discharging is actively underway.

[0003] Accordingly, as technological development and demand for mobile devices, electric vehicles, hybrid vehicles, power storage devices, and uninterruptible power supplies increase, the demand for secondary batteries as an energy source is rapidly rising. In particular, secondary batteries used in electric and hybrid vehicles are high-output, high-capacity batteries, and extensive research is being conducted on them.

[0004] Furthermore, along with the high demand for secondary batteries, research is also being conducted on peripheral components and devices related to them. Specifically, research is underway on various components and devices, such as cell assemblies that connect multiple secondary batteries into a single module, Battery Management Systems (BMS) that control the charging and discharging of cell assemblies and monitor the status of each battery, battery packs that combine cell assemblies and BMSs into a single pack, and relays that connect cell assemblies to loads like motors.

[0005] A relay connecting such a cell assembly and a load may be provided in a power system. Additionally, the power system may be responsible for a stable power supply between the battery and the load by selectively opening and closing at least one relay. When such a power system is provided in a vehicle, regarding the safety of the power system, it is important to ensure that the relay remains closed and does not open due to a systemic error during vehicle operation.

[0006] Therefore, the industry requires technology capable of effectively keeping relays in a closed state despite system errors. This requirement increases circuit complexity. The problem to be solved

[0007] The present invention is devised to solve the above-mentioned problems and aims to provide a relay control device and method capable of maintaining a relay in a closed state even if a system error occurs.

[0008] Other objects and advantages of the present invention may be understood from the following description and will become more clearly apparent from the embodiments of the present invention. Furthermore, it will be readily apparent that the objects and advantages of the present invention can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0009] A relay control device according to one aspect of the present invention may be configured to include: a processor configured to output a first control signal for controlling the operating state of a first relay and a second control signal for controlling the operating state of a second relay; a monitoring unit connected to the processor and configured to monitor the operating state of the processor and output a retain signal for maintaining the operating state of the first relay and the second relay according to the operating state of the processor; and a relay state determination unit configured to receive the first control signal and the second control signal from the processor and receive the retain signal from the monitoring unit, and output a first relay control signal for controlling the operating state of the first relay and a second relay control signal for controlling the operating state of the second relay based on the received first control signal, the second control signal, and the retain signal.

[0010] The above processor may be configured to further output a third control signal or a recovery signal to the relay state determining unit, which determines the relay control signal output from the relay state determining unit according to the operating state of the above processor.

[0011] The relay state determination unit may be configured to output a portion of the first control signal, the second control signal, and the retain signal as the first relay control signal and the second relay control signal, based on the signal level of the third control signal or the recovery signal received from the processor.

[0012] The above processor may be configured to output the third control signal to the relay state determination unit when the operating state of the above processor is in a reset state.

[0013] The above processor may be configured to output the recovery signal to the relay state determination unit when the operating state of the above processor is in a recovery state.

[0014] The above recovery signal may be configured such that the signal level is output as a first signal level, and after a predetermined time has elapsed, the signal level transitions to a second signal level.

[0015] The third control signal above may be configured such that when the recovery signal of the first signal level is output, the signal level transitions from the first signal level to the second signal level.

[0016] The third control signal above may be pre-set so that the signal level maintains the first signal level until the recovery signal of the first signal level is output.

[0017] The above relay state determination unit may be configured to receive the recovery signal from the processor when the operating state of the processor is the recovery state, output the first control signal as the first relay control signal, and output the second control signal as the second relay control signal.

[0018] The above relay state determining unit may be configured to receive the third control signal of the first signal level from the processor when the operating state of the processor is the reset state, and to output the retain signal as the first relay control signal and the second relay control signal.

[0019] The monitoring unit may be configured to output the signal level of the retain signal at a second signal level for a predetermined time when the operating state of the processor is the reset state, and to output the signal level of the retain signal at a first signal level after the predetermined time.

[0020] The relay state determining unit may be configured to maintain the operating state of the first relay and the second relay when the signal level of the retain signal is the second signal level.

[0021] The above relay state determining unit may be configured to change the operating state of the first relay and the second relay when the signal level of the retain signal is the first signal level.

[0022] A battery pack according to another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0023] An automobile according to another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0024] A relay control method according to another aspect of the present invention may include: a first signal output step in which a processor outputs a first control signal for controlling the operating state of a first relay and a second control signal for controlling the operating state of a second relay; a second signal output step in which a monitoring unit is connected to the processor and monitors the operating state of the processor, and outputs a retain signal configured to maintain the operating state of the first relay and the second relay according to the operating state of the processor; and a relay control signal output step in which a relay state determination unit outputs a first relay control signal for controlling the operating state of the first relay and a second relay control signal for controlling the operating state of the second relay based on the first control signal, the second control signal, and the retain signal.

[0025] A relay control method according to another aspect of the present invention may further include, after the second signal output step, a third signal output or recovery signal output step in which a third control signal or recovery signal determining a relay control signal output from the relay state determining unit is further output in the processor.

[0026] The relay control signal output step may be a step of outputting a portion of the first control signal, the second control signal, and the retain signal as the first relay control signal and the second relay control signal based on the signal level of the third control signal or the recovery signal. Effects of the invention

[0027] According to one aspect of the present invention, there is an advantage in that the operating state of a plurality of relays is maintained when the processor is reset, thereby preventing accidents caused by the reset of the processor.

[0028] In addition, according to one aspect of the present invention, if the operating state of the processor is in a reset state after a predetermined time has elapsed, the operating state of a plurality of relays is changed to a turn-off state, thereby preventing waste of system resources and energy.

[0029] In addition, according to one aspect of the present invention, when the operating state of the processor is restored, there is an advantage that the operating state of a plurality of relays can be controlled by the processor.

[0030] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0031] The following drawings attached to this specification serve to further enhance understanding of the technical concept of the invention in conjunction with the detailed description of the invention set forth below; therefore, the invention should not be interpreted as being limited only to the matters described in such drawings. FIG. 1 is a schematic diagram illustrating a relay control device according to one embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an exemplary configuration of a relay control device according to one embodiment of the present invention. FIG. 3 is a schematic diagram illustrating an embodiment in which the signal level of a third control signal according to one embodiment of the present invention is maintained at a first signal level. FIG. 4 is a schematic diagram illustrating a comparative example when the signal level of a third control signal according to one embodiment of the present invention is not maintained at the first signal level. FIG. 5 is a schematic diagram illustrating an embodiment of a processor in a recovery state according to one embodiment of the present invention. FIG. 6 is a drawing illustrating a relay state determination unit according to one embodiment of the present invention in more detail. FIG. 7 is a schematic diagram illustrating an exemplary configuration of a relay state determination unit according to one embodiment of the present invention. FIG. 8 is a schematic diagram illustrating another exemplary configuration of a relay state determination unit according to one embodiment of the present invention. FIG. 9 is a schematic diagram illustrating a relay control method according to an embodiment of the present invention. Specific details for implementing the invention

[0032] Terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of the invention, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention.

[0033] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention; thus, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0034] In addition, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the invention, such detailed description is omitted.

[0035] Terms including ordinal numbers, such as first, second, etc., are used for the purpose of distinguishing one of the various components from the rest, and are not used to limit the components by such terms.

[0036] Throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0037] Additionally, terms such as processor described in the specification refer to a unit that processes at least one function or operation, which may be implemented in hardware, software, or a combination of hardware and software.

[0038] Additionally, throughout the specification, when it is said that a part is "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other components in between.

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0041] FIG. 1 is a schematic diagram illustrating a relay control device (100) according to one embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an exemplary configuration of a relay control device (100) according to one embodiment of the present invention.

[0042] Referring to FIG. 1, a relay control device (100) according to one embodiment of the present invention may include a processor (110), a monitoring unit (120), and a relay status determination unit (130).

[0043] The processor (110) may be configured to output a first control signal (CS1) for controlling the operating state of the first relay (200) and a second control signal (CS2) for controlling the operating state of the second relay (300).

[0044] For example, the first relay (200) and the second relay (300) may be relays that connect the battery and the load. More specifically, the first relay (200) may be a high-voltage side relay as a high-side relay. And, the second relay (300) may be a low-voltage side relay as a low-side relay.

[0045] When the processor (110) is in a normal state, it can output a first control signal (CS1) to control the operating state of the first relay (200) to a turn-on state or a turn-off state. Also, when the processor (110) is in a normal state, it can output a second control signal (CS2) to control the operating state of the second relay (300) to a turn-on state or a turn-off state. Here, the operating state of each of the first relay (200) and the second relay (300) can be controlled according to the signal levels of the first control signal (CS1) and the second control signal (CS2), respectively.

[0046] The monitoring unit (120) may be connected to the processor (110) and configured to monitor the operating status of the processor (110).

[0047] Specifically, the monitoring unit (120) can be connected to communicate with the processor (110). The monitoring unit (120) can monitor whether the operating state of the processor (110) is a normal state or a reset state. Here, a reset state means a state in which the operation of the processor (110) is restarted.

[0048] For example, in the embodiment of FIG. 2, the monitoring unit (120) is connected to the processor (110) and can monitor the operating status of the processor (110).

[0049] Additionally, the monitoring unit (120) may be configured to output a retain signal (RS) to maintain the operating state of the first relay (200) and the second relay (300) according to the operating state of the processor (110).

[0050] Specifically, the retain signal (RS) may be a signal for maintaining the operating state of the first relay (200) and the second relay (300) in the current state. For example, if the operating state of the first relay (200) and the second relay (300) is in the turn-on state and the monitoring unit (120) outputs the retain signal (RS), the operating state of the first relay (200) and the second relay (300) may be maintained in the turn-on state. Conversely, if the operating state of the first relay (200) and the second relay (300) is in the turn-off state and the monitoring unit (120) outputs the retain signal (RS), the operating state of the first relay (200) and the second relay (300) may be maintained in the turn-off state.

[0051] The relay state determination unit (130) may be configured to receive the first control signal (CS1) and the second control signal (CS2) from the processor (110).

[0052] For example, in the embodiment of FIG. 2, the relay state determination unit (130) is electrically connected to the processor (110) and can receive a first control signal (CS1) and a second control signal (CS2) from the processor (110).

[0053] Additionally, the relay status determination unit (130) may be configured to receive the retain signal (RS) from the monitoring unit (120).

[0054] For example, in the embodiment of FIG. 2, the relay state determination unit (130) is electrically connected to the monitoring unit (120) and can receive a retain signal (RS) from the monitoring unit (120).

[0055] The relay state determination unit (130) may be configured to output a first relay control signal (RCS1) that controls the operating state of the first relay (200) and a second relay control signal (RCS2) that controls the operating state of the second relay (300) based on the received first control signal (CS1), the second control signal (CS2), and the retain signal (RS).

[0056] Here, the first relay control signal (RCS1) is a signal that is output to the first relay (200) to determine the operating state of the first relay (200). Likewise, the second relay control signal (RCS2) is a signal that is output to the second relay (300) to determine the operating state of the second relay (300).

[0057] The relay state determination unit (130) can select a first control signal (CS1) as a first relay control signal (RCS1) and select a second control signal (CS2) as a second relay control signal (RCS2). Conversely, the relay state determination unit (130) can also select a retain signal (RS) as a first relay control signal (RCS1) and a second relay control signal (RCS2). The first relay control signal (RCS1) and the second relay control signal (RCS2) selected by the relay state determination unit (130) can be determined by a third control signal (CS3) received from the processor (110).

[0058] Specifically, the processor (110) may be configured to further output a third control signal (CS3) or a recovery signal (R) that determines the relay control signal output from the relay state determination unit (130) according to the operating state of the processor (110).

[0059] Preferably, the processor (110) may be configured to output the third control signal (CS3) to the relay state determining unit (130) when the operating state of the processor (110) is in a reset state. Conversely, the processor (110) may be configured to output the recovery signal (R) to the relay state determining unit (130) when the operating state of the processor (110) is in a recovery state. Here, the reset state refers to a state in which the processor (110) is rebooted, and the recovery state refers to a state in which the processor (110) is booted normally and has recovered to a normal state.

[0060] For example, in the embodiment of FIG. 2, when the operating state of the processor (110) becomes a reset state, the processor (110) can immediately output a third control signal (CS3) to the relay state determination unit (130).

[0061] And, the relay state determination unit (130) may be configured to output some of the first control signal (CS1), the second control signal (CS2), and the retain signal (RS) as the first relay control signal (RCS1) and the second relay control signal (RCS2) based on the signal level of the third control signal (CS3) received from the processor (110).

[0062] Here, signal levels can be classified into low levels and high levels. A high level refers to a signal level above a predetermined reference level, and a low level refers to a signal level above 0 and below the reference level.

[0063] Preferably, when the processor (110) is in a reset state, the signal level of the third control signal (CS3) can be set to maintain a low level.

[0064] When the operating state of the processor (110) is in a reset state, the relay state determination unit (130) can select the first relay control signal (RCS1) and the second relay control signal (RCS2) among the first control signal (CS1), the second control signal (CS2), and the retain signal (RS) depending on whether the signal level of the third control signal (CS3) is high level or low level.

[0065] As another example, in the embodiment of FIG. 2, when the operating state of the processor (110) changes from a reset state to a recovery state, the processor (110) can immediately output a recovery signal (R) to the relay state determining unit (130).

[0066] When a recovery signal (R) is output from the processor (110), the signal level of the third control signal (CS3) can be transitioned from a low level to a high level. And, when the operating state of the processor (110) is in a recovery state, the relay state determining unit (130) can select the first control signal (CS1) as the first relay control signal (RCS1) and select the second control signal (CS2) as the second relay control signal (RCS2). That is, when the operating state of the processor (110) becomes a recovery state, it can recover the control of the operating state of the first relay (200) and the second relay (300) by outputting a recovery signal (R).

[0067] A relay control device (100) according to one embodiment of the present invention can control the operating state of the first relay (200) and the second relay (300) so that it is maintained even when the processor (110) is unexpectedly reset. For example, while the relay control device (100) is installed in a vehicle and the vehicle is in operation, the processor (110) may be unintentionally reset due to a system error. In such a case, since the operating state of the processor (110) is in a reset state, if the operating state of the first relay (200) and the second relay (300), which are in a turn-on state, is changed to a turn-off state, there is a problem that an unexpected accident may occur. Therefore, the relay control device (100) can prevent an unexpected accident in advance by maintaining the operating state of the first relay (200) and the second relay (300) as they are, even if the processor (110) is reset due to a system error.

[0068] Additionally, the relay control device (100) can enable the operating state of the first relay (200) and the second relay (300) to be controlled normally by the processor (110) when the operating state of the processor (110) is switched to a recovery state.

[0070] Meanwhile, the processor (110) provided in the relay control device (100) may optionally include an application-specific integrated circuit (ASIC), other chipsets, logic circuits, registers, communication modems, data processing devices, etc., known in the art, to execute various control logics performed in the present invention. Additionally, when the control logic is implemented in software, the processor (110) may be implemented as a set of program modules. In this case, the program modules may be stored in memory and executed by the processor (110). The memory may be located inside or outside the processor (110) and may be connected to the processor (110) by various well-known means.

[0072] Preferably, the recovery signal (R) may be configured such that the signal level is output at a first signal level, and after a predetermined time has elapsed, the signal level transitions to a second signal level. Additionally, the third control signal (CS3) may be configured such that when the recovery signal (R) of the first signal level is output, the signal level transitions from the first signal level to the second signal level. That is, the third control signal (CS3) may be pre-set so that the signal level maintains the first signal level until the recovery signal (R) of the first signal level is output. Here, the first signal level may refer to a low level. That is, the signal level may be divided into a low level, which is the first signal level, and a high level, which is the second signal level.

[0073] For example, in the embodiment of FIG. 2, when the operating state of the processor (110) is in a reset state, the signal level of the third control signal (CS3) output from the processor (110) may be set to maintain the first signal level (low level).

[0074] FIG. 3 is a schematic diagram illustrating an embodiment in which the signal level of the third control signal (CS3) is maintained at the first signal level. FIG. 4 is a schematic diagram illustrating a comparative example in which the signal level of the third control signal (CS3) is not maintained at the first signal level. Specifically, the embodiment of FIG. 3 and the comparative example of FIG. 4 are embodiments for the case in which the operating state of the processor (110) is in a reset state and is not switched to a recovery state.

[0075] FIGS. 3 and 4 are drawings illustrating a first control signal (CS1), a second control signal (CS2), a third control signal (CS3), a first output value (Q1), a second output value (Q2), a retain signal (RS), a first relay control signal (RCS1), and a second relay control signal (RCS2) that are output over time.

[0076] In FIGS. 3 and 4, the signal level or output value of each of the first control signal (CS1), second control signal (CS2), third control signal (CS3), first output value (Q1), second output value (Q2), retain signal (RS), first relay control signal (RCS1), and second relay control signal (RCS2) can be described as a first signal level meaning a low level and a second signal level meaning a high level.

[0077] Additionally, in FIGS. 3 and 4, it is assumed that the processor (110) is reset once at time t1, reset twice at time t2, and reset three times at time t3.

[0078] In the embodiment of FIG. 3, since the signal level of the third control signal (CS3) is set to be maintained at the first signal level, the first relay control signal (RCS1) and the second relay control signal (RCS2) can be maintained at a constant level even if the processor (110) is reset once, twice, and three times. That is, the operating state of the first relay (200) and the second relay (300) can be maintained.

[0079] On the other hand, in the comparative example of FIG. 4, the signal level of the third control signal (CS3) is initially maintained at the first signal level, but can subsequently transition to the second signal level. For example, the signal level of the third control signal (CS3) output at time t1 is the first signal level, but at time t11, the signal level of the third control signal (CS3) can transition to the second signal level. This may be because, in the comparative example of FIG. 4, the signal level of the third control signal (CS3) is not set to be maintained at the first signal level.

[0080] More specifically, in the comparative example of FIG. 4, when the processor (110) is reset once, that is, at time t1 to time t2, the first relay control signal (RCS1) and the second relay control signal (RCS2) can be maintained at a constant state. That is, at time t1 to time t2, the operating state of the first relay (200) and the second relay (300) can be maintained.

[0081] On the other hand, when the processor (110) is reset two or more times, that is, at time t2, a third control signal (CS3) having a first signal level is output, and even if a retain signal (RS) is output, the signal levels of the first relay control signal (RCS1) and the second relay control signal (RCS2) may change. This is because, at time t2, the signal level of the third control signal (CS3) transitions from the second signal level to the first signal level, and thus the first output value (Q1) and the second output value (Q2) of the flip-flop (131) change. And, at time t21, the signal level of the third control signal (CS3) may transition from the first signal level to the second signal level.

[0082] Subsequently, if the processor (110) is reset for the third time at time t3, the signal level of the third control signal (CS3) at time t3 may transition from the second signal level to the first signal level. In this case, the first output value (Q1) and the second output value (Q2) of the flip-flop (131) may be changed again. That is, although the processor (110) is reset for the third time at time t3, the first output value (Q1) and the second output value (Q2) of the flip-flop (131) have been changed, so the signal levels of the first relay control signal (RCS1) and the second relay control signal (RCS2) may also be changed. And, at time t31, the signal level of the third control signal (CS3) may transition from the first signal level to the second signal level.

[0083] Therefore, in the comparative example of FIG. 4, when the processor (110) is reset once, the operating state of the first relay (200) and the second relay (300) can be maintained to prevent unexpected accidents, but when the processor (110) is reset two or more times, there is a problem in that the operating state of the first relay (200) and the second relay (300) cannot be maintained.

[0084] On the other hand, as in the embodiment of FIG. 3, the relay control device (100) according to one embodiment of the present invention has the advantage of being able to maintain the operating state of the first relay (200) and the second relay (300) even when the processor (110) is reset two or more times.

[0086] The above relay state determination unit (130) may be configured to receive the recovery signal (R) from the processor (110) when the operating state of the processor (110) is the recovery state, output the first control signal (CS1) as the first relay control signal (RCS1), and output the second control signal (CS2) as the second relay control signal (RCS2).

[0087] That is, the relay state determination unit (130) may be configured to output the first control signal (CS1) as the first relay control signal (RCS1) and output the second control signal (CS2) as the second relay control signal (RCS2) when it does not receive the third control signal (CS3) of the first signal level from the processor (110).

[0088] FIG. 5 is a schematic diagram illustrating an embodiment of a processor in a recovery state according to one embodiment of the present invention.

[0089] Specifically, the embodiment of FIG. 5 is an embodiment for the case where the operating state of the processor (110) at time t4 in the embodiment of FIG. 3 is switched to a recovery state.

[0090] In the embodiment of FIG. 5, when the operating state of the processor (110) is switched from a reset state to a recovery state at time t4, the processor (110) can immediately output a recovery signal (R). In this case, the signal level of the output recovery signal (R) may be a first signal level. And, while outputting the recovery signal (R) of the first signal level, the processor (110) can simultaneously transition the signal level of the third control signal (CS3) from the first signal level to the second signal level.

[0091] At time t5, after a predetermined time has elapsed from time t4, the signal level of the recovery signal (R) output from the processor (110) may transition from a first signal level to a second signal level. In this case, the signal levels of the first control signal (CS1) and the second control signal (CS2) may transition from a first signal level to a second signal level. Additionally, the first output value (Q1) and the second output value (Q2) of the flip-flop (131) may be changed.

[0092] Preferably, at the moment when the signal level of the recovery signal (R) output from the processor (110) to the relay state determination unit (130) transitions from the first signal level to the second signal level, the signal levels of the first output value (Q1) and the second output value (Q2) of the flip-flop (131) may be changed.

[0093] That is, the signal levels of the recovery signal (R), the first control signal (CS1), the second control signal (CS2), the third control signal (CS3), the first output value (Q1), and the second output value (Q2) can be the same as before time t1 from time t5.

[0094] Accordingly, from time t5, the operating state of the first relay (200) and the second relay (300) can be controlled by the processor (110) whose operating state has been switched to a recovery state.

[0095] That is, in the case where the processor (110) is reset one or more times, the relay control device (100) according to one embodiment of the present invention can maintain the operating state of the first relay (200) and the second relay (300) based on the third control signal (CS3) output from the processor (110). Subsequently, when the operating state of the processor (110) is switched to a recovery state, the signal levels of the first control signal (CS1), the second control signal (CS2), the third control signal (CS3), the first output value (Q1), and the second output value (Q2) are returned to the original signal levels based on the recovery signal (R) output from the processor (110), thereby allowing the operating state of the first relay (200) and the second relay (300) to be controlled by the processor (110).

[0097] Conversely, the relay state determining unit (130) may be configured to receive the third control signal (CS3) of the first signal level from the processor (110) when the operating state of the processor (110) is the reset state, and to output the retain signal (RS) as the first relay control signal (RCS1) and the second relay control signal (RCS2).

[0098] That is, the relay state determination unit (130) may be configured to output the retain signal (RS) as the first relay control signal (RCS1) and the second relay control signal (RCS2) when it receives the third control signal (CS3) of the first signal level from the processor (110).

[0099] Preferably, when the operating state of the processor (110) is in a reset state, the monitoring unit (120) outputs a retain signal (RS) to the relay state determination unit (130), and the processor (110) can output a third control signal (CS3) to the relay state determination unit (130).

[0100] For example, referring to FIGS. 3 and FIGS. 5, the signal level of the output retain signal (RS) may be the second signal level, and the signal level of the third control signal (CS3) may be the first signal level.

[0101] That is, when the relay state determining unit (130) receives the third control signal (CS3) from the processor (110), the operating state of the processor (110) may be in a reset state. Conversely, when the relay state determining unit (130) does not receive the third control signal (CS3) from the processor (110), the operating state of the processor (110) may be in a normal state or a recovery state.

[0102] Accordingly, when the relay state determination unit (130) receives the third control signal (CS3), it can output a retain signal (RS) as the first relay control signal (RCS1) and the second relay control signal (RCS2) to maintain the operating state of the first relay (200) and the second relay (300). Conversely, when the relay state determination unit (130) does not receive the third control signal (CS3), it can output the first control signal (CS1) as the first relay control signal (RCS1) and output the second control signal (CS2) as the second relay control signal (RCS2). That is, the relay state determination unit (130) can control the operating state of each of the first relay (200) and the second relay (300) according to the first control signal (CS1) and the second control signal (CS2) received from the processor (110).

[0104] The monitoring unit (120) may be configured to output the signal level of the retain signal (RS) at a second signal level for a predetermined time when the operating state of the processor (110) is the reset state. Then, the monitoring unit (120) may be configured to output the signal level of the retain signal (RS) at a first signal level after the predetermined time. That is, if the operating state of the processor (110) does not switch to a recovery state for a predetermined time, the monitoring unit (120) may transition the signal level of the retain signal (RS) from the second signal level to the first signal level.

[0105] For example, when the monitoring unit (120) determines that the operating state of the processor (110) is in a reset state, it may output a retain signal (RS) having a second signal level (high level) for a predetermined time, and after a predetermined time, output a retain signal (RS) having a first signal level (low level).

[0106] As previously explained, the first signal level may include 0. That is, the monitoring unit (120) may output a retain signal (RS) having a second signal level for a predetermined time, and may not output a retain signal (RS) after a predetermined time.

[0107] The relay state determining unit (130) may be configured to maintain the operating state of the first relay (200) and the second relay (300) when the signal level of the retain signal (RS) is the second signal level. Additionally, the relay state determining unit (130) may be configured to change the operating state of the first relay (200) and the second relay (300) when the signal level of the retain signal (RS) is the first signal level.

[0108] For example, in the embodiment of FIG. 3, it is assumed that at time t0, the signal level of the retain signal (RS) changes from a second signal level to a first signal level. And, it is assumed that the operating state of the processor (110) remains in a reset state. In this case, since the operating state of the processor (110) is in a reset state, the monitoring unit (120) outputs the retain signal (RS) to the relay state determination unit (130), and the processor (110) can output a third control signal (CS3) to the relay state determination unit (130). Here, the retain signal (RS) may have a second signal level from time t1 to time t0, and may have a first signal level from time t0 onwards. And, the third control signal (CS3) may have a first signal level from time t1 onwards. Accordingly, the relay state determining unit (130) can maintain the operating state of the first relay (200) and the second relay (300) in a turn-on state by outputting a retain signal (RS) having a second signal level with the first relay control signal (RCS1) and the second relay control signal (RCS2) from time t1 to time t0. Then, the relay state determining unit (130) can change the operating state of the first relay (200) and the second relay (300) to a turn-off state by outputting a retain signal (RS) having a first signal level with the first relay control signal (RCS1) and the second relay control signal (RCS2) from time t0.

[0109] That is, the monitoring unit (120) can output a retain signal (RS) having a second signal level for a predetermined time so that when the operating state of the processor (110) is in a reset state, the operating state of the first relay (200) and the second relay (300) can be maintained in a turn-on state for a predetermined time.

[0110] For example, there is a problem in that the operating state of the first relay (200) and the second relay (300) cannot be continuously maintained in the turned-on state even when the processor (110) is repeatedly reset. In this case, since the processor (110) is in a reset state, the signal levels of the first control signal (CS1), the second control signal (CS2), and the third control signal (CS3) cannot be changed. Therefore, the monitoring unit (120) can change the operating state of the first relay (200) and the second relay (300) to the turned-off state by changing the signal level of the output retain signal (RS). And, since the third control signal (CS3) having the first signal level is continuously output when the processor (110) is in the reset state, the operating state of the first relay (200) and the second relay (300) can be maintained in the turned-off state. Therefore, waste of system resources and energy in a situation where the processor (110) is repeatedly reset can be prevented.

[0112] FIG. 6 is a drawing illustrating a relay state determination unit (130) according to one embodiment of the present invention in more detail. FIG. 7 is a drawing schematically illustrating an exemplary configuration of a relay state determination unit (130) according to one embodiment of the present invention.

[0113] Referring to FIGS. 6 and FIGS. 7, the relay state determining unit (130) may include a flip-flop (131) and a buffer unit (132).

[0114] A flip-flop (131) is a logic circuit capable of storing and maintaining 1 bit of information. For example, in the embodiment of FIG. 7, the flip-flop (131) may be a D flip-flop. In addition, an RS flip-flop, a JK flip-flop, or a T flip-flop may be applied to the flip-flop (131). For convenience of explanation, the flip-flop (131) is described below as being a D flip-flop.

[0115] In the embodiment of FIG. 7, the flip-flop (131) may include a data terminal (D), a clock terminal, a first output terminal (Q), and a second output terminal (Q'). A second control signal (CS2) is input to the data terminal (D), and a third control signal (CS3) is input to the clock terminal (C). Depending on the signal levels of the second control signal (CS2) and the third control signal (CS3), a first output value (Q1) may be output from the first output terminal (Q) and a second output value (Q2) may be output from the second output terminal (Q'). The first output value (Q1) and the second output value (Q2) may be input to the buffer unit (132). Here, the signal levels of the first output value (Q1) and the second output value (Q2) may be opposite to each other. That is, if the signal level of the first output value (Q1) is the first signal level, the signal level of the second output value (Q2) is the second signal level.

[0116] The buffer unit (132) can receive a first control signal (CS1) and a second control signal (CS2) from the processor (110). Additionally, the buffer unit (132) can receive a first output value (Q1) and a second output value (Q2) from the flip-flop (131) and receive a retain signal (RS) from the monitoring unit (120). Furthermore, the buffer unit (132) can output a first relay control signal (RCS1) that controls the operating state of the first relay (200) to the first relay (200). Additionally, the buffer unit (132) can output a second relay control signal (RCS2) that controls the operating state of the second relay (300) to the second relay (300).

[0117] The relay state determination unit (130) includes a flip-flop (131) and a buffer unit (132), so that even if the operating state of the processor (110) is in a reset state, the operating state of the first relay (200) and the second relay (300) can be maintained according to the signal level of the third control signal (CS3) and the signal level of the retain signal (RS).

[0119] More specifically, the buffer section (132) may include a plurality of buffers. For example, the buffer section (132) may include a first buffer, a second buffer, a third buffer, and a fourth buffer.

[0120] The first buffer may be configured to receive a retain signal (RS) and a first output value (Q1), and to determine whether to output the retain signal (RS) based on the signal level of the first output value (Q1). For example, if the signal level of the first output value (Q1) is a second signal level (high level), the retain signal (RS) may be output through the first buffer. Conversely, if the signal level of the first output value (Q1) is a first signal level (low level), the retain signal (RS) may not be output through the first buffer.

[0121] The second buffer may be configured to receive a first control signal (CS1) and a second output value (Q2), and to determine whether to output the first control signal (CS1) based on the signal level of the second output value (Q2). For example, if the signal level of the second output value (Q2) is the second signal level, the first control signal (CS1) may be output through the second buffer. Conversely, if the signal level of the second output value (Q2) is the first signal level, the first control signal (CS1) may not be output through the second buffer.

[0122] Additionally, the output line of the first buffer and the output line of the second buffer can be integrated with each other. That is, the first buffer and the second buffer respectively receive a first output value (Q1) and a second output value (Q2) with opposite signal levels. Therefore, when a retain signal (RS) is output from the first buffer, the first control signal (CS1) may not be output from the second buffer. For example, this is because when the signal level of the first output value (Q1) input to the first buffer is the second signal level (high level), the signal level of the second output value (Q2) input to the second buffer is the first signal level (low level).

[0123] Accordingly, depending on the signal levels of the first output value (Q1) and the second output value (Q2), the first relay control signal (RCS1) can be output as the first control signal (CS1) or the retain signal (RS).

[0124] And, when the processor (110) is in a reset state, the signal level of the third control signal (CS3) input to the clock terminal (C) of the flip-flop (131) can always be set to the first signal level. In this case, the signal level of the first output value (Q1) output from the flip-flop (131) can always be the second signal level, and the signal level of the second output value (Q2) can always be the first signal level. Therefore, when the processor (110) is in a reset state, the operation state of the first relay (200) can be maintained because the retain signal (RS) is output from the first buffer as the first relay control signal (RCS1).

[0125] Conversely, when the processor (110) is in a recovery state, the signal level of the third control signal (CS3) input to the clock terminal (C) of the flip-flop (131) can be set to the second signal level. In this case, the signal level of the first output value (Q1) output from the flip-flop (131) can be the first signal level, and the signal level of the second output value (Q2) can be the second signal level. Therefore, when the processor (110) is in a recovery state, the first control signal (CS1) can be output from the first buffer as the first relay control signal (RCS1). That is, the operating state of the first relay (200) can be controlled by the processor (110).

[0127] The third buffer may be configured to receive the second control signal (CS2) and the second output value (Q2), and to determine whether to output the second control signal (CS2) based on the signal level of the second output value (Q2). For example, if the signal level of the second output value (Q2) is the second signal level, the second control signal (CS2) may be output through the third buffer. Conversely, if the signal level of the second output value (Q2) is the first signal level, the second control signal (CS2) may not be output through the third buffer.

[0128] The fourth buffer may be configured to receive a retain signal (RS) and a first output value (Q1), and to determine whether to output the retain signal (RS) based on the signal level of the first output value (Q1). For example, if the signal level of the first output value (Q1) is a second signal level (high level), the retain signal (RS) may be output through the fourth buffer. Conversely, if the signal level of the first output value (Q1) is a first signal level (low level), the retain signal (RS) may not be output through the fourth buffer.

[0129] Similar to the first and second buffers, the output lines of the third buffer and the fourth buffer can also be integrated. The third buffer and the fourth buffer respectively receive a second output value (Q2) and a first output value (Q1), which have opposite signal levels. Therefore, when the second control signal (CS2) is output from the third buffer, the retain signal (RS) is not output from the fourth buffer. Conversely, when the second control signal (CS2) is not output from the third buffer, the retain signal (RS) is output from the fourth buffer. That is, the second relay control signal (RCS2) is the second control signal (CS2) output from the third buffer or the retain signal (RS) output from the fourth buffer.

[0130] As previously explained, when the processor (110) is in a reset state, the signal level of the first output value (Q1) output from the flip-flop (131) based on the signal level of the third control signal (CS3) can always be the second signal level. Therefore, when the processor (110) is in a reset state, the operation state of the second relay (300) can be maintained because the retain signal (RS) is output from the fourth buffer as the second relay control signal (RCS2).

[0131] Conversely, when the processor (110) is in a recovery state, the signal level of the first output value (Q1) output from the flip-flop (131) may be the first signal level, and the signal level of the second output value (Q2) may be the second signal level. Therefore, when the processor (110) is in a recovery state, the second control signal (CS2) may be output from the fourth buffer as the second relay control signal (RCS2). That is, the operating state of the second relay (300) may be controlled by the processor (110).

[0133] FIG. 8 is a schematic diagram illustrating another exemplary configuration of a relay state determining unit (130) according to one embodiment of the present invention.

[0134] Referring to FIGS. 6 and FIGS. 8, the relay state determining unit (130) may further include a gate unit (133).

[0135] The gate section (133) may be configured to be connected between at least one of the first relay (200) and the second relay (300) and the buffer section (132).

[0136] In the embodiment of FIG. 8, the gate unit (133) may be connected between the buffer unit (132) and the second relay (300). The gate unit (133) may receive a third relay control signal (RCS3) from the buffer unit (132) and a retain signal (RS) from the monitoring unit (120). Then, the gate unit (133) may output a second relay control signal (RCS2) to the second relay (300) based on the signal levels of the third relay control signal (RCS3) and the retain signal (RS).

[0137] As in the previous embodiment, when the operating state of the processor (110) is in a reset state, a retain signal (RS) may be output from the fourth buffer of the buffer unit (132). That is, the third relay control signal (RCS3) may be the retain signal (RS) output from the fourth buffer. In this case, since the retain signal (RS) from the buffer unit (132) and the monitoring unit (120) is input to the gate unit (133), the second relay control signal (RCS2) output from the gate unit (133) may be the retain signal (RS). Accordingly, the retain signal (RS) is input to the second relay (300), so that the operating state of the second relay (300) can be maintained.

[0139] The relay control device (100) according to the present invention can be applied to a Battery Management System (BMS). That is, the BMS according to the present invention may include the relay control device (100) described above. In this configuration, at least some of the components of the relay control device (100) may be implemented by supplementing or adding the functions of the components included in a conventional BMS. For example, the processor (110), monitoring unit (120), and relay status determination unit (130) of the relay control device (100) may be implemented as components of the BMS.

[0140] In addition, the relay control device (100) according to the present invention may be provided in a battery pack. That is, the battery pack according to the present invention may include the relay control device (100) described above and one or more battery cells. In addition, the battery pack may further include electrical components (relays, fuses, etc.) and a case, etc.

[0141] Here, a battery cell refers to a single independent cell that is physically separable and equipped with a negative terminal and a positive terminal. As an example, a single pouch-type lithium polymer cell may be considered as a battery cell. Additionally, a battery pack may include one or more battery modules, each comprising one or more battery cells connected in series and / or parallel.

[0143] Additionally, the relay control device (100) according to the present invention may be provided in a vehicle. Accordingly, the relay control device (100) can control the relay so that the relay connecting the battery and the vehicle remains closed and does not open even when the processor (110) is reset due to a systemic error while the vehicle is driving.

[0144] Additionally, the relay control device (100) can immediately grant the processor (110) control over the operating state of the first relay (200) and the second relay (300) when the processor (110) is recovered.

[0146] FIG. 9 is a schematic diagram illustrating a relay control method according to an embodiment of the present invention. Each step of the relay control method according to an embodiment of the present invention can be performed by a relay control device (100).

[0147] Referring to FIG. 9, the relay control method may include a first signal output step (S100), a second signal output step (S200), a third signal or recovery signal output step (S300), and a relay control signal output step (S400).

[0148] The first signal output step (S100) is a step of outputting a first control signal (CS1) for controlling the operating state of the first relay (200) and a second control signal (CS2) for controlling the operating state of the second relay (300), and can be performed by a processor (110).

[0149] The second signal output step (S200) is a step of outputting a retain signal (RS) configured to be connected to the processor (110) to monitor the operating state of the processor (110) and to maintain the operating state of the first relay (200) and the second relay (300) according to the operating state of the processor (110), and can be performed by a monitoring unit (120).

[0150] The monitoring unit (120) monitors the operating state of the processor (110), and when the operating state of the processor (110) becomes a reset state, it can output a retain signal (RS) to the relay state determination unit (130).

[0151] The third signal or recovery signal output step (S300) may be performed after the second signal output step (S200). Specifically, the third signal or recovery signal output step (S300) may be performed by the processor (110) as a step of further outputting a third control signal (CS3) or a recovery signal (R) that determines the relay control signal output from the relay state determination unit (130) according to the operating state of the processor (110).

[0152] The processor (110) can output a third control signal (CS3) to the relay state determining unit (130) as soon as the operating state becomes a reset state. Preferably, the signal level of the third control signal (CS3) can be set to always maintain a first signal level (low level).

[0153] Additionally, the processor (110) can output a recovery signal (R) to the relay state determination unit (130) as soon as the operating state becomes a recovery state. Here, the signal level of the output recovery signal (R) may be a first signal level. Then, the processor (110) can transition the signal level of the third control signal (CS3) from the first signal level to the second signal level. Subsequently, when the signal level of the recovery signal (R) transitions from the first signal level to the second signal level, the signal levels of the first control signal (CS1), the second control signal (CS2), the first output value (Q1), and the second output value (Q2) can be restored to the state before the processor (110) was reset.

[0154] The relay control signal output step (S400) is a step of outputting a first relay control signal (RCS1) that controls the operating state of the first relay (200) and a second relay control signal (RCS2) that controls the operating state of the second relay (300) based on the first control signal (CS1), the second control signal (CS2), and the retain signal (RS), and can be performed by the relay state determination unit (130).

[0155] More specifically, the relay control signal output step (S400) may be a step of outputting some of the first control signal (CS1), the second control signal (CS2), and the retain signal (RS) as the first relay control signal (RCS1) and the second relay control signal (RCS2), based on the signal level of the third control signal (CS3) or the recovery signal (R) received from the processor (110).

[0156] For example, if the operating state of the processor (110) is in a reset state, the signal level of the third control signal (CS3) may be the first signal level. In this case, a retain signal (RS) may be output as the first relay control signal (RCS1) and the second relay control signal (RCS2). Accordingly, the operating state of the first relay (200) and the second relay (300) may be maintained or changed depending on the signal level of the retain signal (RS).

[0157] Specifically, it is assumed that the processor (110) is reset when the operating state of the first relay (200) and the second relay (300) is in the turn-on state. In this case, the signal level of the retain signal (RS) may be the second signal level. And, since the retain signal (RS) is input to the first relay (200) and the second relay (300), the operating state of the first relay (200) and the second relay (300) may be maintained in the turn-on state.

[0158] Afterward, if the operating state of the processor (110) remains in a reset state even after a predetermined amount of time has passed, the signal level of the retain signal (RS) can be transitioned to a first signal level. In this case, since the retain signal (RS) is input to the first relay (200) and the second relay (300), the operating state of the first relay (200) and the second relay (300) can be changed to a turn-off state.

[0159] Accordingly, the relay control method according to one embodiment of the present invention has the advantage of maintaining the operating state of a plurality of relays when the processor (110) is reset, thereby preventing accidents caused by the reset of the processor (110). In addition, if the operating state of the processor (110) remains in a reset state for a predetermined period of time, the operating state of a plurality of relays is changed to a turn-off state, thereby preventing waste of system resources and energy.

[0160] As another example, when the operating state of the processor (110) is switched from a reset state to a recovery state, a recovery signal (R) of a first signal level is output, and the signal level of the third control signal (CS3) can be transitioned from the first signal level to the second signal level. Subsequently, when the signal level of the recovery signal (R) transitions from the first signal level to the second signal level, the first control signal (CS1) can be output as the first relay control signal (RCS1), and the second control signal (CS2) can be output as the second relay control signal (RCS2). Accordingly, the operating state of the first relay (200) and the second relay (300) can be controlled by the processor (110).

[0161] Accordingly, the relay control method according to one embodiment of the present invention has the advantage of stably controlling the operating state of a plurality of relays by allowing the processor (110) to reclaim control of a plurality of relays when the operating state of the processor (110) is restored.

[0163] The embodiments of the present invention described above are not limited to implementation through devices and methods, but may also be implemented through a program that realizes a function corresponding to the configuration of the embodiments of the present invention or a recording medium on which such a program is recorded. Such implementation can be easily achieved by a person skilled in the art to which the present invention pertains, based on the description of the embodiments described above.

[0164] Although the present invention has been described above by limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims described below by those skilled in the art to which the present invention belongs.

[0165] Furthermore, since the present invention described above allows for various substitutions, modifications, and changes within the scope of the technical concept of the present invention to those skilled in the art without departing from the technical spirit of the present invention, it is not limited by the aforementioned embodiments and attached drawings, but rather all or part of each embodiment may be selectively combined to allow for various modifications. Explanation of the symbols

[0167] 100: Relay control device 110: Processor 120: Monitoring Department 130: Relay status determination unit 131: Flip-flop 132: Buffer section 133: Gate Department 200: 1st Relay 300: 2nd Relay

Claims

Claim 1 A relay control device comprising: a processor configured to output a first control signal for controlling the operating state of a first relay and a second control signal for controlling the operating state of a second relay; a monitoring unit connected to the processor and configured to monitor the operating state of the processor; and a relay state determination unit configured to output a first relay control signal for controlling the operating state of the first relay and a second relay control signal for controlling the operating state of the second relay, wherein the processor is configured to output a third control signal to the relay state determination unit when the operating state of the processor is a reset state, and to output a recovery signal to the relay state determination unit when the operating state of the processor becomes a recovery state from the reset state, wherein the monitoring unit is configured to output a retain signal for maintaining the operating state of the first relay and the second relay when the operating state of the processor is the reset state, and wherein the relay state determination unit is configured to output a portion of the first control signal, the second control signal, and the retain signal as the first relay control signal and the second relay control signal based on the signal level of the third control signal or the recovery signal. Claim 2 delete Claim 3 A relay control device according to claim 1, wherein the recovery signal is configured such that the signal level is output at a first signal level and, after a predetermined time has elapsed, the signal level transitions to a second signal level, and the third control signal is configured such that when the recovery signal of the first signal level is output, the signal level transitions from the first signal level to the second signal level. Claim 4 A relay control device according to paragraph 3, wherein the third control signal is preset such that the signal level maintains the first signal level until the recovery signal of the first signal level is output. Claim 5 A relay control device according to claim 3, wherein the relay state determining unit is configured to receive the recovery signal from the processor when the operating state of the processor is the recovery state, output the first control signal as the first relay control signal, and output the second control signal as the second relay control signal. Claim 6 A relay control device according to claim 3, wherein the relay state determining unit is configured to receive the third control signal of the first signal level from the processor when the operating state of the processor is the reset state, and to output the retain signal as the first relay control signal and the second relay control signal. Claim 7 A relay control device according to claim 6, wherein the monitoring unit is configured to output the signal level of the retain signal as a second signal level for a predetermined time when the operating state of the processor is the reset state, and output the signal level of the retain signal as a first signal level after the predetermined time. Claim 8 A relay control device according to claim 7, wherein the relay state determining unit is configured to maintain the operating state of the first relay and the second relay when the signal level of the retain signal is the second signal level. Claim 9 A relay control device according to claim 7, wherein the relay state determining unit is configured to change the operating state of the first relay and the second relay when the signal level of the retain signal is the first signal level. Claim 10 A battery pack comprising a relay control device according to any one of paragraphs 1 and 3 through 9. Claim 11 An automobile comprising a relay control device according to any one of paragraphs 1 and 3 through 9. Claim 12 A step of outputting a first control signal for controlling the operating state of a first relay and a second control signal for controlling the operating state of a second relay in a processor; a step of monitoring the operating state of the processor connected to a monitoring unit in a monitoring unit; a step of outputting a third control signal to a relay state determining unit in the processor when the operating state of the processor is in a reset state, and outputting a recovery signal to the relay state determining unit when the operating state of the processor is in a recovery state from the reset state; a step of outputting a retain signal to the relay state determining unit in the monitoring unit to maintain the operating state of the first relay and the second relay when the operating state of the processor is in the reset state. A relay control method comprising, in the relay state determining unit, a step of outputting a first relay control signal for controlling the operating state of the first relay and a second relay control signal for controlling the operating state of the second relay, wherein the step of outputting the first relay control signal for controlling the operating state of the first relay and the second relay control signal for controlling the operating state of the second relay is characterized by outputting a portion of the first control signal, the second control signal, and the retain signal as the first relay control signal and the second relay control signal based on the signal level of the third control signal or the recovery signal.

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