Device and method for wireless communication

Abstract

An image processing method is provided, which is performed by an image processing system to detect a target. The image processing method may include: acquiring original lines by receiving an original image line by line; setting a kernel corresponding to each of a plurality of pixels included in the original lines; generating reference lines corresponding to each of the original lines by performing operations on the original lines based on the kernel; calculating residual lines based on the original lines and the reference lines; and generating a target detection result based on a residual image including the residual lines.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to wireless communication, and more specifically, to an apparatus and method for wireless communication. Background Technology

[0002] In wireless communication systems, BCH (Bose-Chaudhuri-Hocquenghem) codes can be designed for error correction capabilities based on finite field properties, and encoded bits can be transmitted by mapping them to symbols on a constellation map through Gray coding-based symbol mapping. At the receiver, decoding can be performed using Hard Decision Detection (HDD) or Soft Decision Detection (SDD) techniques based on the bit-by-bit reliability determined by symbol mapping.

[0003] Meanwhile, Gray coding-based symbol mapping may not account for assigning different error robustness to bit positions, and if the reliability of the received signal decreases and errors exceeding the designed error correction capability occur, the decoding algorithm may fail to perform effectively, which could degrade the system's connection stability and service quality. The problem to be solved

[0004] The present disclosure is proposed to solve the aforementioned problems, and the technical problem is to perform symbol mapping such that the bit value of a specific bit position (e.g., MSB) between adjacent symbols on a constellation diagram is maintained identically, and to perform symbol mapping in which information bits and parity bits are separately assigned to bit positions within the symbol with different error robustness. In addition, a decoding method is proposed that provides error correction capability even for a range exceeding the error correction capability at the decoding stage.

[0005] The technical problems to be solved by the present disclosure are not limited to the technical problems described above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present disclosure belongs from the description below. means of solving the problem

[0006] A method of operation of a first device configured to communicate with a second device according to one embodiment of the present disclosure comprises: generating a codeword including an information bit and a parity bit by encoding input data; rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position by assigning the information bit to a first bit position including at least one bit position and assigning the parity bit to a second bit position different from the first bit position; generating at least one symbol by mapping the at least one bit group to at least one of a plurality of constellation points; and transmitting the at least one symbol to the second device, wherein the length of the at least one bit group is equal to the bit length of the symbol label assigned to each of the plurality of constellation points, and the symbol label may be set such that the bit value of at least one bit of the first bit position is the same for a pair of symbol labels corresponding to an adjacent pair of constellation points on a constellation diagram.

[0007] According to one embodiment, the operation method may include: calculating soft decision confidences corresponding to bits corresponding to each of the at least one received symbol based on at least one received symbol received from the second device; selecting at least one test bit among the bits corresponding to each of the at least one received symbol in which the soft decision confidence is less than a threshold confidence; generating a plurality of test patterns based on the at least one test bit; and performing decoding based on the correlation between the plurality of test patterns and the at least one received symbol.

[0008] According to one embodiment, the second bit position may be characterized by including the LSB (Least Significant Bit) position of the symbol label.

[0009] According to one embodiment, the bits corresponding to each of the at least one received symbol may be characterized as bits corresponding to the first bit position.

[0010] According to one embodiment, the interface setting information may be characterized by including communication protocol information for sending and receiving messages between the component models.

[0011] According to one embodiment, the operation method further includes the step of generating a plurality of candidate test patterns having the same length as the codeword by encoding each of the plurality of test patterns, and the step of performing the decoding may be characterized by including: the step of generating a reference pattern by arranging the soft decision confidences in the order of the codeword based on the inverse process of the rearrangement; and the step of performing the decoding by selecting a candidate test pattern having the largest correlation value with the reference pattern among the plurality of candidate test patterns.

[0012] According to one embodiment, the step of performing the simulation operation may be characterized by including the step of performing a subsequent operation based on the event trigger condition information and the step of updating the shared information based on the subsequent operation.

[0013] According to one embodiment, the step of generating the plurality of test patterns may be characterized by including the step of generating the plurality of test patterns, wherein the plurality of combination patterns obtainable by changing the bit value of the at least one test bit to either 0 or 1 are generated as the plurality of test patterns.

[0014] According to one embodiment, the parity bit may be characterized by having the same bit length as the information bit.

[0015] A first device configured to communicate with a second device according to one embodiment of the present disclosure comprises: a communication circuit configured to transmit and receive a wireless signal to and from the second device; and at least one processor, wherein the at least one processor generates a codeword including an information bit and a parity bit by encoding input data, assigns the information bit to a first bit position including at least one bit position, and assigns the parity bit to a second bit position different from the first bit position, thereby rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position, generates at least one symbol by mapping the at least one bit group to at least one of a plurality of constellation points, and is configured to transmit a wireless signal modulated with the at least one symbol to the second device through the communication circuit, wherein the length of the at least one bit group is equal to the bit length of a symbol label assigned corresponding to each of the plurality of constellation points, and the symbol label may be set such that the bit value of at least one bit of the first bit position is the same for a pair of symbol labels corresponding to an adjacent pair of constellation points on the constellation diagram.

[0016] An apparatus according to one embodiment of the present disclosure comprises: an encoder configured to generate a codeword including information bits and parity bits by encoding input data; a symbol mapper configured to generate at least one symbol by assigning the information bits to a first bit position including at least one bit position and assigning the parity bits to a second bit position different from the first bit position, thereby rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position, and mapping the at least one bit group to at least one of a plurality of constellation points; and a modulator configured to generate a radio signal by modulating the at least one symbol, wherein the length of the at least one bit group is equal to the bit length of a symbol label assigned to each of the plurality of constellation points, and the symbol label may be set such that the bit value of at least one bit of the first bit position is the same for a pair of symbol labels corresponding to an adjacent pair of constellation points on the constellation diagram. Effects of the invention

[0017] According to an apparatus and method for wireless communication according to one embodiment of the present disclosure, a symbol label can be set so that the value of a specific bit position between adjacent constellation points is maintained, and an information bit and a parity bit can be differentially assigned to positions with different error robustness within the symbol, thereby ensuring reception reliability for the information bit even in an environment where an error exceeding the error correction capability designed in the encoding stage occurs due to the deterioration of the channel environment.

[0018] In addition, since decoding can be performed using test patterns generated based on the reliability of information bits, the decoding performance of the wireless communication system can be improved.

[0019] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the description below. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0020] FIG. 1 is a block diagram showing a wireless communication system according to one embodiment of the present disclosure. FIG. 2 is a block diagram showing a first device configured to communicate with a second device according to one embodiment of the present disclosure. FIG. 3 is a block diagram showing the components included in the transmission path of a first device according to one embodiment of the present disclosure. FIG. 4 is a block diagram showing the components included in the receiving path of a first device according to one embodiment of the present disclosure. FIG. 5 is a flowchart illustrating a wireless signal transmission method performed in a first device according to one embodiment of the present disclosure. FIG. 6 is a table showing an example of rearranging bits of a codeword according to one embodiment of the present disclosure. FIG. 7 is a table showing examples of symbol labels for star points according to one embodiment of the present disclosure. FIG. 8 is a flowchart illustrating a wireless signal reception method performed in a first device according to one embodiment of the present disclosure. Figure 9 is a graph showing the bit error rate (BER) of a codeword bit by bit. Figure 10 is a graph showing the BER for the decoder. Specific details for implementing the invention

[0021] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice them. It should be noted that the detailed description disclosed below is intended to describe exemplary embodiments of various types and is not intended to limit the scope to specific embodiments.

[0022] The terms used in the embodiments have been selected to be as widely used and general as possible, taking into account their functions in this disclosure; however, these may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, the applicant has arbitrarily selected terms, and in such cases, their meanings will be described in detail in the relevant description section. Therefore, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the overall content of this disclosure.

[0023] The following embodiments are combinations of the components and features of various embodiments in a predetermined form. Each component or feature may be considered optional unless otherwise explicitly stated. Each component or feature may be implemented in a form not combined with other components or features, or various embodiments may be constructed by combining some components and features. Additionally, the order of operations described in various embodiments may be changed. Some components or features of one embodiment may be included in another embodiment and may be replaced with corresponding components or features of another embodiment.

[0024] In the description of the drawings, procedures or steps that could obscure the essence of the various embodiments were not described, nor were procedures or steps that could be understood by a person of ordinary knowledge in the relevant technical field described.

[0025] Throughout the specification, when a part is described as "comprising" or "including" a component, it means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. In this document, the singular form of a noun corresponding to an item may be used to include both singular and plural forms, unless otherwise indicated in the specification or clearly contradicted by the context. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or any combination thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish a component from other corresponding components and do not limit the components in any other aspect (e.g., importance or order).

[0026] Each component (e.g., module or program) of the components described in this document may include a singular or multiple entities. According to various embodiments, one or more of the components or operations may be omitted, or one or more other components or operations may be added. Additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the components of the multiple components in the same or similar manner as they were performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, or repeatedly; one or more of the operations may be executed in a different order; may be omitted; or one or more other operations may be added.

[0027] As used in this document, the terms "module" or "...part" refer to a unit that processes at least one function or operation, and may include a unit implemented by hardware, software, firmware, or a combination thereof.

[0028] Various embodiments of this document may be implemented as software (e.g., a program or application) comprising one or more instructions stored in a storage medium (e.g., memory) readable by a machine. For example, the processor of the machine may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to at least one called instruction. One or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by a machine may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain a signal, and does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily in the storage medium.

[0029] In addition, specific terms used in various embodiments are provided to aid in understanding the various embodiments, and the use of such specific terms may be modified in other forms within the scope of not departing from the technical concept of the various embodiments.

[0030] FIG. 1 is a block diagram illustrating a wireless communication system according to one embodiment of the present disclosure. Referring to FIG. 1, the wireless communication system (WCS) may include a first cell (11) and a communication device (12).

[0031] The first cell (11) may refer to a fixed station that communicates with at least one of a communication device (12) and another network node (or other cell), and may exchange data and control information by communicating with at least one of the communication device (12) and another network node. For example, the first cell (11) may refer to a base station, Node B, eNB (evolved-Node B), gNB (Next generation Node B), Sector, Site, BTS (Base Transceiver System), AP (Access Point), Relay Node, RRH (Remote Radio Head), RU (Radio Unit), a device configured to communicate with the communication device (12), etc. For example, the first cell (11) may refer to a device or server configured to communicate with a military communication device. The first cell (11) may provide wireless broadband access to the communication device (12) within its coverage area. For example, the first cell (11) can provide wireless broadband access to a communication device (12) within its coverage (10). Although only the first cell (11) is illustrated in this specification, it is not limited thereto. For example, other cells in addition to the first cell (11) may be included.

[0032] The communication device (12) may be fixed or mobile and may refer to any device capable of communicating with the first cell (11) to transmit data and control information. For example, the communication device (12) may be referred to as User Equipment, terminal, terminal equipment, MS (Mobile Station), MT (Mobile Terminal), UT (User Terminal), SS (Subscribe Station), wireless communication device, wireless device, handheld device, etc. For example, the communication device (12) may include various military communication devices such as a drone, unmanned aerial vehicle, and ground mobile robot.

[0033] The first cell (11) and the communication device (12) can transmit and receive wireless signals through a wireless channel. Either of the first cell (11) and the communication device (12) may be referred to as the first device, and the other may be referred to as the second device. In one embodiment, when the first device transmits a wireless signal to the second device, the first device may modulate the data to be transmitted into a wireless signal by performing an encoding and symbol mapping method, and transmit it to the second device. For example, the first device may encode the data to be transmitted to generate a codeword including information bits and parity bits, and rearrange the bits of the codeword by assigning the information bits to a first bit position with relatively high error robustness. The rearranged bits may be divided into at least one bit group, and the first device may generate at least one symbol by mapping at least one bit group to a constellation point on a constellation diagram, and modulate the generated at least one symbol into a wireless signal and transmit it to the second device. The first device can set a symbol label such that for a pair of symbol labels corresponding to an adjacent pair of constellation points on a constellation diagram, at least one bit value of a first bit position is the same. An example of the first device rearranging the bits of a codeword will be described later with reference to FIG. 6, and an example of the first device setting a symbol label for a pair of symbol labels will be described later with reference to FIG. 7.

[0034] In the present disclosure, a codeword may be a sequence of bits generated by encoding input data according to specific encoding rules. For example, the codeword may include information bits (or systematic bits) corresponding to the original data to be transmitted and parity bits added during the encoding process for error correction on the channel. For example, the codeword may be generated by Bose-Chaudhuri-Hocquenghem (BCH) encoding utilizing finite field properties or by extended BCH (eBCH) encoding, which improves error correction and detection performance by adding additional parity bits to BCH encoding.

[0035] In the present disclosure, a bit group may be a mapping unit corresponding to a symbol, as a set of bits formed by rearranging the bits of a codeword. For example, a bit group may include a first bit position with relatively high error robustness and at least one second bit position with relatively low error robustness. For example, if the modulation scheme is 16PSK (Phase Shift Keying), a bit group may include four bit positions, the upper two bits including the MSB (Most Significant Bit) may be set as the first bit positions, and the lower two bits including the LSB (Least Significant Bit) may be set as the second bit positions.

[0036] In the present disclosure, a constellation point may refer to the physical coordinates of a signal having a specific phase and amplitude on a complex plane. For example, a plurality of constellation points may be defined by at least one unique complex number value determined according to the modulation order.

[0037] In the present disclosure, a symbol label may be a bit sequence uniquely assigned to each of a plurality of constellation points. A symbol label may be set for each of a plurality of constellation points by a labeling rule. For example, a symbol label may be set so that a bit value corresponding to a first bit position is maintained identically for a pair of adjacent constellation points on a constellation diagram, and may be configured with different lengths depending on the modulation method.

[0038] In the present disclosure, error robustness may indicate the degree to which the original bit value can be determined or restored without error even if distortion of the received signal occurs due to noise or interference occurring on the wireless channel. In one embodiment, bit positions in which the bit value is maintained identically for a pair of symbol labels corresponding to a pair of adjacent constellation points on a constellation diagram may have relatively higher error robustness. For example, a first bit position, which is a bit position of upper bits including the MSB, may be a bit position set such that the pair of symbol labels corresponding to a pair of adjacent constellation points on the constellation diagram maintains a relatively identical bit value compared to a second bit position, which is a bit position of lower bits including the LSB, and may have the characteristic that no error occurs in the bit value of the first bit position even if the receiving device misidentifies the symbol as an adjacent constellation point due to noise.

[0039] In one embodiment, when the first device receives a wireless signal from the second device, the first device may demodulate the received wireless signal into at least one received symbol, calculate soft decision confidences corresponding to bits corresponding to each of the at least one received symbol, select at least one test bit that is less than a threshold confidence based on the soft decision confidences, and generate a plurality of test patterns based on the at least one test bit to perform decoding. For example, the soft decision confidences compared with the threshold confidence may be the soft decision confidences of the bits corresponding to the first bit position. An example of the first device decoding the wireless signal will be described later with reference to FIG. 8.

[0040] In the present disclosure, soft decision reliability may be a bit-by-bit reliability index calculated from received symbols. For example, soft decision reliability may be a Log-Likelihood Ratio (LLR) value calculated based on received symbols. The higher the soft decision reliability, the relatively higher the probability that the received bit was correctly determined to be 0 or 1.

[0041] In the present disclosure, a test bit may refer to a bit having a reliability value smaller than a preset threshold reliability among bit-by-bit soft decision reliabilitys. For example, the test bit may be p (where p is an integer greater than or equal to 1) bits selected by the first device during the process of executing a specific algorithm (e.g., Chase-II algorithm). For example, the test bit may be p bits selected by the first device from among information bits assigned to a first bit position.

[0042] In the present disclosure, the test pattern may be a plurality of combination patterns that can be obtained by changing the bit values ​​of selected p test bits to 0 or 1. For example, if the test bit is a bit selected from among the information bits assigned to a first bit position, the first device may re-encode each of the plurality of combination patterns to expand them into a plurality of candidate test patterns equal to the original codeword length.

[0043] A first cell (11) or communication device (12) of a wireless communication system (WCS) according to the present disclosure can assign an information bit to a first bit position where the bit value between adjacent constellation points is maintained relatively identically, thereby ensuring reception reliability for the information bit even in an environment where an error exceeding the error correction capability designed in the encoding stage occurs due to the deterioration of the channel environment. Additionally, the first cell (11) or communication device (12) of the wireless communication system (WCS) can perform decoding through a test pattern generated based on the reliability of the information bit, thereby improving the decoding performance of the wireless communication system.

[0044] FIG. 2 is a block diagram showing a first device (200) configured to communicate with a second device according to one embodiment of the present disclosure. The first device (200) of FIG. 2 may be an example of the first cell (11) or communication device (12) of FIG. 1. Descriptions of FIG. 2 that overlap with the content of FIG. 1 are omitted.

[0045] Referring to FIG. 2, the first device (200) may include a processor (210), memory (220), a transceiver (230), and a plurality of antennas (240_1 to 240_n). Only the components of the first device (200) illustrated in FIG. 2 are shown that are relevant to the embodiments. Therefore, it is obvious to a person skilled in the art that the first device (200) may include other general-purpose components in addition to those shown in FIG. 2. For example, the first device (200) may include a communication device including a transceiver (230), an input unit, and an output unit. The communication technologies used by the communication unit may include GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), LTE (Long Term Evolution), 5G, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), ZigBee, NFC (Near Field Communication), etc. The input unit may be, for example, a traditional type keypad or keyboard, a mouse, a microphone that receives voice signals, a camera, and various other types of input means that detect or receive various types of user input. The output unit may be, for example, a display that outputs images, a speaker that outputs sound, a haptic device that generates vibrations, and various other types of output means.

[0046] The processor (210) may include a core for executing instructions and / or at least one dedicated hardware block designed to perform specific functions. For example, the processor (210) may be implemented as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), AP (Application Processor), DSP (Digital Signal Processor), and communication modem, etc., provided within the first device (200), but is not limited thereto. The processor (210) may perform overall control operations of the first device (200) or coordinate operations between multiple modules. The memory (220) may include non-volatile memory such as flash memory, ROM (Read Only Memory), SSD (Solid State Drive), etc., and may include volatile memory such as RAM (Random Access Memory). In this disclosure, the processor (210) may be referred to as a device configured to perform the method described below with reference to the drawings and to communicate with another device, such as a second device. Memory (220) can store instructions (or instructions), and the processor (210) can perform the method described below by referring to the drawings by executing the instructions stored in memory (220). The processor (210) may include hardware logic.

[0047] A transceiver (230) is a wireless communication module or circuit that performs both the transmission and reception functions of wireless signals and can transmit and receive signals through an antenna in a wireless frequency band. The transceiver (230) can receive RF (Radio Frequency) signals transmitted by the second device through a plurality of antennas (240_1 to 240_n). The transceiver (230) can up-convert intermediate frequency or baseband signals output from the processor (210) and transmit them as RF signals through the plurality of antennas (240_1 to 240_n). The transceiver (230) can generate data signals by filtering, decoding, and / or digitizing intermediate frequency or baseband signals, and can encode, multiplex, and / or analogize the data signals.

[0048] A transceiver (230) is a wireless communication module or circuit that performs both the transmission and reception functions of wireless signals and can transmit and receive signals through an antenna in a wireless frequency band. The transceiver (230) can receive RF (Radio Frequency) signals transmitted by the second device through a plurality of antennas (240_1 to 240_n). The transceiver (230) may be referred to as a transceiver and can transmit intermediate frequency or baseband signals output from the processor (210) as RF signals through a plurality of antennas (240_1 to 240_n) by frequency up-converting them. The transceiver (230) can generate data signals by filtering, decoding, and / or digitizing the intermediate frequency or baseband signals, and can encode, multiplex, and / or analogize the data signals.

[0049] In one embodiment, when the first device (200) performs a transmission operation, the processor (210) can encode input data to generate a codeword including information bits and parity bits. The processor (210) can generate at least one bit group by rearranging the bits of the codeword by assigning the information bits to a first bit position with relatively high error robustness and assigning the parity bits to a second bit position with relatively low error robustness. For example, if the modulation scheme is 16PSK, the length of the codeword is 8 bits, and the information bits are 4 bits, the length of one bit group may be 4 bits since the symbol label length of one symbol is 4 bits. The codeword may be rearranged into two bit groups, and the information bits may be assigned 2 bits each to the first bit position of each of the two bit groups. Here, the first bit positions may be the upper two bit positions including the MSB. For example, if the modulation scheme is 16PSK, the codeword length is 4 bits, and the information bit is 2 bits, the codeword can be rearranged into one bit group, and 2 bits of the information bit can be assigned to the first bit position of the bit group. Here, the first bit position may be the upper two bit positions including the MSB. The processor (210) can generate at least one symbol by mapping at least one bit group to a star point on a constellation diagram determined according to the modulation scheme. The processor (210) can set a symbol label with differential error robustness according to the bit position on the star point on the constellation diagram. For example, the processor (210) can set the MSB of the symbol label to maintain the same value for a pair of symbol labels corresponding to an adjacent pair of star points on the constellation diagram, and as it moves toward the LSB, the bit value of the same bit position for the pair of symbol labels can be set to have a different value.

[0050] In one embodiment, when the first device (200) performs a transmission operation, the transceiver (230) modulates at least one symbol output from the processor (210) into a wireless signal according to a modulation method and transmits it to the second device through a plurality of antennas (240_1 to 240_n).

[0051] In one embodiment, when the first device (200) performs a receiving operation, the transceiver (230) can receive a wireless signal from the second device through a plurality of antennas (240_1 to 240_n). The transceiver (230) can demodulate the received wireless signal to generate at least one receiving symbol and provide at least one receiving symbol to the processor (210).

[0052] In one embodiment, when the first device (200) performs a receiving operation, the processor (210) can calculate bit-by-bit soft-decision reliabilitys for at least one received symbol provided from the transceiver (230). For example, the processor (210) can calculate soft-decision reliabilitys corresponding to bits corresponding to each of the at least one received symbol corresponding to the codeword. The processor (210) can compare the soft-decision reliabilitys of the bits corresponding to the first bit position among the soft-decision reliabilitys with a threshold reliability, and select a bit having a reliability smaller than the threshold reliability as a test bit. When performing a transmitting operation, the processor (210) can arrange the bits corresponding to the information bit among the bits corresponding to the at least one received symbol into the information bit position, which is the bit position where the information bit of the codeword is located, by arranging them in the order of the codeword based on the reverse process of rearrangement. The processor (210) can generate a plurality of combination patterns that can be obtained by changing the bit corresponding to the test bit among the bits of the information bit position to either 0 or 1, and can generate a plurality of candidate test patterns equal to the length of the codeword by encoding the plurality of combination patterns. The processor (210) can select a candidate test pattern having the largest correlation value with at least one received symbol among the plurality of candidate test patterns and decode it.

[0053] FIG. 3 is a block diagram showing the components included in the transmission path of a first device according to one embodiment of the present disclosure. The components of FIG. 3 may be examples of components included in the transmission path of the first device (200) of FIG. 2. For example, the encoder (310) and the symbol mapper (320) may be components included in the processor (210) of FIG. 2, and the modulator (330) may be components included in the transceiver (230) of FIG. 2. Descriptions of FIG. 3 that overlap with the content of FIG. 2 are omitted.

[0054] Referring to FIG. 3, the encoder (310) may be configured to add redundancy to the original data to correct channel errors that occur during data transmission. In one embodiment, the encoder (310) may receive input data (ID) and generate a codeword (C) by encoding the input data (ID) according to a preset encoding method. For example, the encoder (310) may receive input data (ID) which is data to be transmitted of k bits (k is an integer greater than or equal to 1) and generate a codeword (C) of a total length of n bits (n is an integer greater than or equal to 1) by adding nk bits of parity bits according to an eBCH encoding method. The codeword (C) may include k bits of information bits and nk bits of parity bits, and the information bits may be set to the same bit length as the parity bits.

[0055] A symbol mapper (320) may be a device configured to convert a bit sequence into a symbol, which is a physical coordinate on a complex plane. In one embodiment, the symbol mapper (320) may rearrange the bits of a codeword (C) and generate at least one symbol (S) that maps to a constellation point where the symbol label of each constellation point is set according to a labeling rule. For example, the symbol label of each constellation point may be set such that the value of at least one bit at a first bit position containing the MSB is kept the same for a pair of symbol labels corresponding to a pair of adjacent constellation points on a constellation diagram. For example, the symbol mapper (320) may rearrange the bits by assigning an information bit within the codeword (C) to a first bit position and assigning a parity bit to a second bit position. The rearranged bits form at least one bit group, and the symbol mapper (320) may select a constellation point corresponding to each bit group to generate at least one symbol (S).

[0056] The modulator (330) may be configured to modulate a complex symbol in the baseband into an analog signal in a high-frequency band that can be radiated through an actual antenna. In one embodiment, the modulator (330) may be configured to receive at least one symbol (S) in the baseband and convert it into a wireless signal according to a modulation method and output it. For example, modulation methods may include QPSK, 16PSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, etc.

[0057] FIG. 4 is a block diagram showing the components included in the receiving path of a first device according to one embodiment of the present disclosure. The components of FIG. 4 may be examples of components included in the receiving path of the first device (200) of FIG. 2. For example, the demodulator (410) may be a component included in the transceiver (230) of FIG. 2, and the decoder (420) may be a component included in the processor (210) of FIG. 2. Descriptions of FIG. 4 that overlap with the content of FIG. 2 are omitted.

[0058] The demodulator (410) may be configured to convert an analog signal in the radio frequency band into a digital signal in the baseband and to estimate a transmitted symbol by analyzing coordinates on a constellation diagram. In one embodiment, the demodulator (410) may demodulate a radio signal to generate at least one received symbol and calculate bit-by-bit soft-decision reliabilitys for at least one received symbol. Hereinafter, it is described that the demodulator (410) calculates bit-by-bit soft-decision reliabilitys, but it is not limited thereto. For example, a decoder (420) may receive at least one received symbol from the demodulator (410) and calculate bit-by-bit soft-decision reliabilitys based thereon, and bit-by-bit soft-decision reliabilitys may be calculated by a separate circuit (or module) other than the demodulator (410) and the decoder (420).

[0059] The decoder (420) may be configured to perform decoding including error correction, and decoding may be a process of correcting channel errors and restoring original data using parity bits added at the transmitting side. The decoder (420) may include a test pattern generator (421) and an encoder (422).

[0060] In one embodiment, the test pattern generator (421) compares the soft decision reliability of the bits corresponding to the first bit position among the soft decision reliabilitys with the threshold reliability, and can select a bit having a reliability smaller than the threshold reliability as a test bit. The test pattern generator (421) can arrange the bits corresponding to the information bit among the bits corresponding to at least one received symbol into the information bit position, which is the bit position where the information bit of the codeword is located, by arranging the bits in the order of the codeword based on the reverse process of rearrangement performed during the transmission operation. The test pattern generator (421) can generate a plurality of combination patterns as a plurality of test patterns by changing the bit corresponding to the test bit among the bits of the information bit position to either 0 or 1. For example, if the number of test bits is p, the number of test patterns may be 2 to the power of p.

[0061] In one embodiment, the process of arranging to information bit positions may precede the selection of test bits. For example, the test pattern generator (421) can generate a reference pattern by arranging bits corresponding to at least one received symbol into information bit positions, which are bit positions where the information bits of the codeword are located, and parity bit positions, which are bit positions where the parity bits of the codeword are located, based on the reverse process of rearrangement performed during the transmission operation. In the reference pattern, the information bits of the first bit position may be arranged to information bit positions, and the parity bits of the second bit position may be arranged to parity bit positions. The test pattern generator (421) may compare the soft judgment reliability of the bits of the information bit position with a threshold reliability and select a bit having a reliability smaller than the threshold reliability as a test bit. The test pattern generator (421) can generate a plurality of combination patterns as a plurality of test patterns by changing the bit corresponding to the test bit among the bits of the information bit position to either 0 or 1.

[0062] In one embodiment, the encoder (422) may be configured to encode a plurality of test patterns. For example, the encoder (422) may generate a plurality of candidate test patterns having a length equal to the length of a codeword by encoding each of the plurality of test patterns, which are composed of information bits, in the same way as the encoding method used during transmission operation (e.g., eBCH encoding method). The decoder (420) may compare the correlation between the plurality of candidate test patterns and the received signal to select the candidate test pattern with the largest correlation value and perform decoding based thereon. For example, the decoder (420) may compare the correlation between the plurality of candidate test patterns and a reference pattern to select the candidate test pattern with the largest correlation value and perform decoding based thereon.

[0063] FIG. 5 is a flowchart illustrating a wireless signal transmission method (500) performed in a first device according to one embodiment of the present disclosure. The wireless signal transmission method (500) may include a plurality of steps (S510 to S530). In the following embodiments, the operations of S510 to S530 may be performed sequentially, but are not necessarily performed sequentially. For example, the order of each operation may be changed, and at least two operations may be performed in parallel.

[0064] Referring to FIG. 5, in step S510, the first device (200) can generate a codeword by encoding input data. In one embodiment, the processor (210) can generate a codeword including information bits and parity bits by encoding input data according to an eBCH encoding method. For example, the processor (210) can generate a codeword of 16 bits by encoding input data of 4 bits in length. The length of the parity bit may be 12 bits. For example, the processor (210) can generate a codeword of 16 bits in length by encoding input data of 8 bits in length. The length of the parity bit may be 8 bits.

[0065] In step S520, the first device (200) can rearrange the bits of a codeword into at least one bit group. In one embodiment, the processor (210) can create at least one bit group by rearranging the bits of the codeword by assigning an information bit to a first bit position with relatively high error robustness and assigning a parity bit to a second bit position with relatively low error robustness. For example, if the modulation scheme is 16PSK, the length of the codeword is 16 bits, and the information bit is 8 bits, the length of one bit group may be 4 bits since the symbol label length of one symbol is 4 bits. The codeword may be rearranged into four bit groups, and the information bit may be assigned 2 bits to the first bit position of each of the four bit groups. Here, the first bit position may be the upper two bit positions including the MSB.

[0066] In step S530, the first device (200) can perform symbol mapping for at least one bit group. In one embodiment, the processor (210) can generate at least one symbol by mapping at least one bit group to a constellation point on a constellation diagram determined according to a modulation method. The symbol label corresponding to the constellation point can be set to have differential error robustness according to the bit position based on a labeling rule. For example, the MSB of the symbol label can be set to maintain the same value for a pair of symbol labels corresponding to an adjacent pair of constellation points on the constellation diagram, and as it moves toward the LSB, the bit value at the same bit position for the pair of symbol labels can be set to have a different value. For example, in the case of 16PSK, there may be 16 constellation points, and the processor (210) can perform symbol mapping to select a constellation point that matches the symbol label by comparing each of the four bit groups with the 16 constellation points. For bit groups having the same bit value among the four bit groups, the processor (210) can select the same constellation point. In one embodiment, the first device (200) can transmit a wireless signal by modulating at least one selected constellation point into an analog signal.

[0067] FIG. 6 is a table showing an example of bit rearrangement of a codeword according to one embodiment of the present disclosure. Referring to FIG. 6, the first table (600) may be an example of rearrangement for a codeword of 16 bits in length when the modulation method is 16PSK (or 16QAM).

[0068] In one embodiment, a 16-bit codeword may include 8-bit information bits (I0 to I7) and 8-bit parity bits (P0 to P7). Depending on the modulation method, the length of the symbol label of each constellation point may be 4 bits, and the processor (210) may rearrange the codeword into 4-bit bit groups (BG1 to BG4). Each of the bit groups (BG1 to BG4) may consist of a first bit position with relatively high error robustness and a second bit position with relatively low error robustness. The first bit position may include a bit position (b0) corresponding to the MSB and a bit position (b1) corresponding to the second-highest bit, and the second bit position may include a bit position (b4) corresponding to the LSB and a bit position (b3) corresponding to the second-lowest bit. The processor (210) can sequentially assign information bits (I0 to I7) to first bit positions of bit groups (BG1 to BG4) and sequentially assign parity bits (P0 to P7) to second bit positions of bit groups (BG1 to BG4).

[0069] For example, the processor (210) may assign a first information bit (I0) and a second information bit (I1) to a first bit position of a first bit group (BG1), assign a third information bit (I2) and a fourth information bit (I3) to a first bit position of a second bit group (BG2), assign a fifth information bit (I4) and a sixth information bit (I5) to a first bit position of a third bit group (BG3), and assign a seventh information bit (I6) and an eighth information bit (I7) to a first bit position of a fourth bit group (BG4).

[0070] For example, the processor (210) may assign a first parity bit (P0) and a second parity bit (P1) to a second bit position of a first bit group (BG1), assign a third parity bit (P2) and a fourth parity bit (P3) to a second bit position of a second bit group (BG2), assign a fifth parity bit (P4) and a sixth parity bit (P5) to a second bit position of a third bit group (BG3), and assign a seventh parity bit (P6) and an eighth parity bit (P7) to a second bit position of a fourth bit group (BG4).

[0071] The processor (210) can arrange information bits that have a relatively large impact on decoding performance at a first bit position, which is a position relatively robust to errors, so that reception reliability for information bits can be secured even in an environment where errors exceeding the error correction capability designed in the encoding stage occur due to the deterioration of the channel environment.

[0072] FIG. 7 is a table showing examples of symbol labels for constellation points according to one embodiment of the present disclosure. Referring to FIG. 7, the second table (700) is a symbol index (S0 to S) when the modulation method is 16PSK. 15 It can represent the correspondence between the phase corresponding to each symbol index and the 4-bit symbol label assigned to that symbol index.

[0073] In one embodiment, the symbol index (S0 to S 15 ) may be an identifier for uniquely identifying each of a plurality of constellation points arranged on a constellation diagram, and a symbol index (S0 to S 15 Each can correspond one-to-one with a single constellation point having a specific phase and amplitude on the complex plane.

[0074] In one embodiment, the symbol label may be set by a labeling rule. The labeling rule may be a rule that is set so that the bit value corresponding to the first bit position is maintained identically for a pair of symbol labels corresponding to an adjacent pair of constellation points on a constellation diagram. For example, the first bit position may include the bit position of the MSB, and the symbol label may be set such that the number of inversions of the bit value is minimized as it approaches the MSB side bit position for the pair of symbol labels.

[0075] For example, the first bit position may include a bit position corresponding to the MSB and a bit position corresponding to the second-highest bit. Among the first bit positions, the bit position corresponding to the MSB is maintained as 0 in the first symbol index (S0) to the eighth symbol index (S7), and in the ninth symbol index (S8) to the sixteenth symbol index (S 15 It can be set to remain at 1 in ). The points where the bit value is inverted between adjacent pairs of symbol indices are at 2 places (the first symbol index (S0) and the 16th symbol index (S 15 The bit position corresponding to the MSB between ) and between the 8th symbol index (S7) and the 9th symbol index (S8) can have the fewest number of inversions. The bit position corresponding to the second bit among the first bit positions is maintained as 0 in the 1st symbol index (S0) to the 4th symbol index (S3), maintained as 1 in the 5th symbol index (S4) to the 8th symbol index (S7), and in the 9th symbol index (S8) to the 12th symbol index (S 11 It is maintained as 1 in ), and the 13th symbol index (S 12 ) to the 16th symbol index (S 15 It can be set to remain at 0. The points where the bit value is inverted between adjacent pairs of symbol indices are at two locations (between the 4th symbol index (S3) and the 5th symbol index (S4) and the 12th symbol index (S 11 ) and the 13th symbol index (S 12The bit position corresponding to the second bit between ) can have the fewest number of inversions. In the same way, the bit position corresponding to the LSB can have the most number of inversions. In other words, the MSB of a symbol label can be set to maintain a relatively identical value for a pair of symbol labels corresponding to an adjacent pair of constellation points on the constellation diagram, and as one moves toward the LSB, the bit value at the same bit position for a pair of symbol labels can be set to have a different value.

[0076] FIG. 8 is a flowchart illustrating a wireless signal reception method (800) performed in a first device according to an embodiment of the present disclosure. The wireless signal reception method (800) may include a plurality of steps (S810 to S840). In the following embodiments, the operations of S810 to S830 may be performed sequentially, but are not necessarily performed sequentially. For example, the order of each operation may be changed, and at least two operations may be performed in parallel.

[0077] Referring to FIG. 8, in step S810, the first device (200) can calculate soft decision reliabilitys. In one embodiment, the transceiver (230) of the first device (200) can generate a received symbol by demodulating a wireless signal, and the transceiver (230) or the processor (210) can generate soft decision reliabilitys of bits corresponding to the received symbol using the distance between the received symbol and candidate constellation points on the constellation diagram. In one embodiment, when the first device (200) calculates the soft decision reliability, it can calculate the soft decision reliability based on constellation points corresponding to adjacent bits that differ from the bit position and value. For example, when the first device (200) calculates the soft decision reliability of a specific bit position, it can search for a constellation point that has a value opposite to the value of the corresponding bit position in the symbol label of the constellation point closest to the received symbol (hereinafter referred to as the closest constellation point). At this time, the candidate constellations to be searched may include all constellations having opposite values ​​at the corresponding bit position, but to reduce computational complexity, the candidate constellations may be set to one constellation among the constellations adjacent to the nearest constellation that has an opposite value at the corresponding bit position.

[0078] In step S820, the first device (200) can select at least one test bit based on soft-decision reliabilitys. In one embodiment, the processor (210) can compare the reliabilitys corresponding to the first bit position among the soft-decision reliabilitys with the threshold reliability, and can select bits having reliabilitys smaller than the threshold reliability as test bits.

[0079] In step S830, the first device (200) can generate a plurality of test patterns based on at least one test bit. In one embodiment, the processor (210) can generate a reference pattern by arranging codewords in order based on the reverse process of rearrangement performed during a transmission operation. A plurality of combination patterns can be generated as a plurality of test patterns by changing the value of the bit corresponding to the test bit among the bats arranged at the information bit position of the reference pattern to either 0 or 1.

[0080] In step S840, the first device (200) can perform decoding based on a plurality of test patterns. In one embodiment, the processor (210) can generate a plurality of candidate test patterns by encoding a plurality of test patterns. Among the plurality of candidate test patterns, the pattern with the greatest correlation with the actual received signal can be selected, and the selected candidate test pattern can be decoded.

[0081] Figure 9 is a graph showing the bit error rate (BER) of a codeword bit by bit. Figure 10 is a graph showing the BER for a decoder.

[0082] Referring to FIG. 9, the first graph (900) may be a graph comparing BER performance according to bit position in an environment with a 16PSK modulation scheme and a codeword length of 16 bits. The horizontal axis of the first graph (900) may represent bit positions (bits), and the vertical axis may represent BER performance values.

[0083] In one embodiment, the first method (coding1) may be a symbol mapping method according to the present disclosure. Referring to the performance of the first method (coding1) of the first graph (900), it can be observed that the BER tends to remain low as it approaches the MSB (1 bit) side of the codeword, and the BER tends to gradually increase as it approaches the LSB (16 bit) side. The MSB (1 bit) side of the codeword may have information bits located therein, and the LSB side may have parity bits located therein. Since the first method (coding1) rearranges the codeword by allocating information bits to a first bit position with relatively high error robustness and parity bits to a second bit position with relatively low error robustness, the BER in the section of the codeword where the information bits are located may remain relatively lower than the BER in the section where the parity bits are located, thereby improving the protection performance for the information bits.

[0084] In a comparative example, the second method (coding2) may be a method in which the entire symbol label between adjacent constellation points on the constellation diagram is designed to be different by only 1 bit (e.g., gray coding). By referring to the performance of the second method (coding2) of the first graph (900), a pattern can be observed in which the BER periodically rises and falls depending on the bit position. The first method (coding1) according to the present disclosure can improve the reception quality of the position where the information bit is allocated (e.g., 1 bit to 7 bits) compared to the second method (coding2). Accordingly, the first device (200) can calculate a relatively high soft decision reliability based on the low BER at the information bit position and improve the decoding success rate to improve the quality of service.

[0085] Referring further to FIG. 10, the second graph (1000) may be a graph showing BER performance according to the change in signal-to-noise ratio for each decoder. The horizontal axis of the second graph (100) may represent signal strength (dB), and the vertical axis may represent BER performance values.

[0086] In comparative embodiments, the first to fourth decoders (decoder1 to decoder4) may correspond to decoders to which only some of the components of the present disclosure are applied, or to decoders that generate a test pattern based on all bits. The first to fourth decoders (decoder1 to decoder4) may exhibit a relatively high BER in a specific dB range.

[0087] In one embodiment, the fifth decoder (decoder5) may be a decoder to which the decoding method according to the present disclosure is applied. For example, the fifth decoder (decoder5) may be a decoder (420). Referring to the second graph (1000), the fifth decoder (decoder5) may exhibit the lowest BER across the entire dB range compared to the comparative embodiments. Unlike the first to fourth decoders (decoder1 to decoder4), the fifth decoder (decoder5) may stack test bits based on information bits and generate test patterns. Accordingly, the fifth decoder (decoder5) can secure a relatively low error rate relative to the same power, thereby improving the quality of service.

[0088] In the foregoing, although all components constituting the embodiments disclosed in this document have been described as being combined or operating in combination, the embodiments disclosed in this document are not necessarily limited to such embodiments. That is, within the scope of the purposes of the embodiments disclosed in this document, all components may be selectively combined in one or more ways to operate.

[0089] Furthermore, terms such as "include," "compose," or "have" as described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the embodiments disclosed in this document pertain, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and, unless explicitly defined in this document, should not be interpreted in an ideal or overly formal sense.

[0090] The foregoing description is merely an illustrative explanation of the technical concept disclosed in this document, and a person skilled in the art to which the embodiments disclosed in this document pertain can make various modifications and variations within the scope of the essential characteristics of the embodiments disclosed in this document. Accordingly, the embodiments disclosed in this document are intended to explain, not limit, the technical concept of the embodiments disclosed in this document, and the scope of the technical concept disclosed in this document is not limited by these embodiments. The scope of protection of the technical concept disclosed in this document shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of this document.

Claims

Claim 1 A method of operation of a first device configured to communicate with a second device, comprising: generating a codeword including an information bit and a parity bit by encoding input data; rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position by assigning the information bit to a first bit position including at least one bit position and assigning the parity bit to a second bit position different from the first bit position; and generating at least one symbol by mapping the at least one bit group to at least one of a plurality of constellation points. A method of operation comprising the step of transmitting the at least one symbol to the second device, wherein the length of the at least one bit group is equal to the bit length of the symbol label assigned to each of the plurality of constellation points, the symbol label is set such that the bit value of at least one bit position is the same for the pair of symbol labels corresponding to adjacent pairs of constellation points on the constellation diagram, and the number of points where the bit value of the first bit position is inverted between adjacent pairs of constellation points on the constellation diagram is less than the number of points where the bit value of the second bit position is inverted. Claim 2 A method of operation according to claim 1, wherein the first bit position includes the MSB (Most Significant Bit) position of the symbol label. Claim 3 A method of operation according to claim 1, wherein the second bit position includes the LSB (Least Significant Bit) position of the symbol label. Claim 4 A method of operation according to claim 1, comprising: calculating soft decision confidences corresponding to bits corresponding to each of the at least one received symbol based on at least one received symbol received from the second device; selecting at least one test bit among the bits corresponding to each of the at least one received symbol in which the soft decision confidence is less than a threshold confidence; generating a plurality of test patterns based on the at least one test bit; and performing decoding based on the correlation between the plurality of test patterns and the at least one received symbol. Claim 5 A method of operation according to claim 4, wherein the bits corresponding to each of the at least one received symbol are bits corresponding to the first bit position. Claim 6 A method of operation according to claim 5, further comprising the step of generating a plurality of candidate test patterns having the same length as the codeword by encoding each of the plurality of test patterns, wherein the step of performing the decoding comprises: generating a reference pattern by arranging the soft decision confidences in the order of the codeword based on the inverse process of the rearrangement; and performing the decoding by selecting a candidate test pattern having the largest correlation value with the reference pattern among the plurality of candidate test patterns. Claim 7 In claim 4, the step of generating the plurality of test patterns comprises the step of generating the plurality of combination patterns, which can be obtained by changing the bit value of at least one test bit to either 0 or 1, as the plurality of test patterns. Claim 8 A method of operation according to claim 1, wherein the parity bit is configured to have the same bit length as the information bit. Claim 9 A first device configured to communicate with a second device, comprising a communication circuit configured to transmit and receive wireless signals with said second device; and includes at least one processor, wherein the at least one processor generates a codeword including information bits and parity bits by encoding input data, assigns the information bits to a first bit position including at least one bit position, and assigns the parity bits to a second bit position different from the first bit position, thereby rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position, generates at least one symbol by mapping the at least one bit group to at least one of a plurality of constellation points, and is configured to transmit a wireless signal modulated with the at least one symbol to the second device through the communication circuit, wherein the length of the at least one bit group is equal to the bit length of the symbol label assigned corresponding to each of the plurality of constellation points, and the symbol label is set such that the bit value of at least one bit at the first bit position is the same for the symbol label pair corresponding to the pair of adjacent constellation points on the constellation diagram, and the number of points where the bit value of the first bit position is inverted between adjacent pairs of constellation points on the constellation diagram is the number of points where the bit value of the second bit position is inverted A first device characterized by having fewer than the number. Claim 10 An encoder configured to generate a codeword including information bits and a parity bit by encoding input data; and a symbol mapper configured to generate at least one symbol by assigning the information bits to a first bit position including at least one bit position and assigning the parity bits to a second bit position different from the first bit position, thereby rearranging the bits of the codeword into at least one bit group including the first bit position and the second bit position, and mapping the at least one bit group to at least one of a plurality of constellation points. The device comprises a modulator configured to generate a wireless signal by modulating at least one symbol, wherein the length of the at least one bit group is equal to the bit length of a symbol label assigned to each of the plurality of constellation points, the symbol label is set such that at least one bit value of the first bit position is the same for a pair of symbol labels corresponding to a pair of adjacent constellation points on the constellation diagram, and the number of points where the bit value of the first bit position is inverted between adjacent pairs of constellation points on the constellation diagram is less than the number of points where the bit value of the second bit position is inverted.

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