Package substrate and semiconductor package comprising the same

Abstract

A package substrate according to embodiments of the present invention comprises: a glass substrate having a first surface and a second surface facing each other; and a through hole penetrating the glass substrate from the first surface to the second surface, wherein the through hole comprises an internal space and an inner wall surrounding the internal space, and the centerline average roughness (Ra) of the inner wall of the through hole is greater than 0.2 μm and less than or equal to 2.0 μm.

Description

Technology Field

[0001] The present invention relates to a package substrate and a semiconductor package including the same. Background Technology

[0003] The semiconductor packaging process generally involves a series of assembly steps in which a wafer on which a semiconductor chip is formed is cut, mounted onto various interposers or substrates, and electrically connected to external circuits. In this back-end technology, the package substrate can function as a transmission path for electrical signals and as a supporting structure for the semiconductor package.

[0004] Previously, ceramic substrates or organic substrates such as resins were primarily used. However, ceramics generally have a high dielectric constant, making them unsuitable for high-frequency package structures where high-speed signals are transmitted. Furthermore, their high mechanical rigidity can lead to defects such as cracks during microfabrication or thinning processes. Additionally, resin substrates have a high coefficient of thermal expansion and low thermal conductivity, which degrades dimensional stability in high-temperature environments and can make it difficult to achieve fine pitches.

[0005] As an alternative, glass-based substrates are attracting attention. Glass is evaluated as a next-generation packaging material suitable for high-speed and high-density systems because it has a coefficient of thermal expansion similar to silicon, as well as excellent insulation properties and dimensional stability.

[0006] In addition, Through-Glass Via (TGV) technology, which forms through holes within a glass substrate, can be advantageous in terms of high-speed signal transmission, package miniaturization, and improved thermal characteristics. The TGV structure can provide effects such as short wiring distance, low signal delay, and excellent electromagnetic shielding compared to conventional materials by precisely machining micro-holes that penetrate the glass layer vertically and filling them with a conductive material to form an electrical path. Prior art literature

[0008] Republic of Korea Registered Patent Publication No. 10-1067109 The problem to be solved

[0009] The problem to be solved by the present invention is to provide a package substrate comprising a glass substrate and a through hole having a predetermined surface roughness, wherein the adhesion and electrical characteristics between the material filled in the through hole and the glass substrate are improved.

[0010] In addition, we intend to provide a semiconductor package including the above-mentioned package substrate. means of solving the problem

[0012] A package substrate according to an embodiment of the present invention comprises: a glass substrate having a first surface and a second surface facing each other; and a through hole penetrating the glass substrate from the first surface to the second surface, wherein the through hole comprises an internal space and an inner wall surrounding the internal space, and the centerline average roughness (Ra) of the inner wall of the through hole is greater than 0.2 μm and less than or equal to 2.0 μm.

[0013] A semiconductor package according to another embodiment of the present invention includes a package substrate according to the above-described embodiment; and a semiconductor device mounted on the package substrate. Effects of the invention

[0015] According to an embodiment of the present invention, the inner wall of a through hole penetrating a glass substrate may be roughened to have a centerline average roughness of a specific range. Accordingly, the adhesion between the glass substrate and the conductive material filled in the internal space of the through hole may be improved, and delamination or voids between the glass substrate and the conductive material may be reduced, thereby improving electrical characteristics.

[0016] In addition, the roughness of the inner wall of the through hole can be controlled by adjusting the laser irradiation interval during the process of forming a through hole in a glass substrate. Therefore, the surface roughness of the inner wall of the through hole can be controlled to a desired range while simultaneously forming the through hole. Accordingly, additional processes such as surface roughening for the through hole are not required, and the degradation of the physical properties of the glass substrate caused by this can be prevented. Brief explanation of the drawing

[0018] FIG. 1 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 2 is a schematic plan view of a package substrate according to some embodiments. Figure 3 is an enlarged view of area A of Figure 1. FIG. 4 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 5 is a schematic cross-sectional view illustrating the process of forming via electrodes during the manufacturing process of a package substrate according to some embodiments. FIG. 6 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 7 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 8 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 9 is a schematic cross-sectional view illustrating the process of forming a through hole during the manufacturing process of a package substrate according to some embodiments. FIG. 10 is a schematic plan view illustrating the process of forming a through hole during the manufacturing process of a package substrate according to some embodiments. FIGS. 11a to 11e are images of through holes in package substrates manufactured in Manufacturing Examples 2, 4, 6, 8, and 10, respectively. FIGS. 12a to 12e are 3D images of through holes in package substrates prepared in Manufacturing Examples 2, 4, 6, 8, and 10, respectively. Specific details for implementing the invention

[0019] The present invention will be described in detail below through various embodiments. The embodiments are not limited to those disclosed below and may be modified in various forms as long as the essence of the invention is not altered.

[0020] In this specification, terms referring to each component are used to distinguish it from other components and are not intended to limit the embodiments. Additionally, singular expressions in this specification include singular or plural expressions unless the context clearly indicates otherwise.

[0021] In this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0022] All numerical ranges representing physical property values, dimensions, etc. of the components described in this specification should be understood to be modified by the term "approximately" in all cases unless otherwise specified.

[0023] In this specification, terms such as "first," "second," etc. are used to describe various components, and said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another.

[0024] In this specification, the description that one component is formed or positioned above or below another component includes both direct formation or indirect placement between these components through the interposition of another component. Furthermore, it should be understood that the reference for the top and bottom of each component may vary depending on the direction in which the object is observed.

[0025] The description in this specification that one component is connected to another component includes both direct and indirect connections between these components through another component.

[0026] In numerical ranges defining the size, physical properties, etc., of components described in this specification, if a numerical range in which only the upper limit is defined and a numerical range in which only the lower limit is defined are separately exemplified, it should be understood that a numerical range combining these upper and lower limits is also included in the exemplary range.

[0027] Additionally, the dimensions of each component in the drawings may be exaggerated for illustrative purposes and do not imply their actual dimensions. Furthermore, throughout the specification, the same reference numerals refer to the same components.

[0029] Package Substrate

[0030] A package substrate according to an embodiment of the present invention comprises: a glass substrate having a first surface and a second surface facing each other; and a through hole penetrating the glass substrate from the first surface to the second surface, wherein the through hole comprises an internal space and an inner wall surrounding the internal space, and the centerline average roughness (Ra) of the inner wall of the through hole is greater than 0.2 μm and less than or equal to 2.0 μm.

[0031] Hereinafter, embodiments of the present invention will be described in detail through the drawings.

[0032] FIG. 1 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 2 is a schematic top view of a package substrate according to some embodiments. For example, FIG. 1 is a cross-sectional view observed by cutting the package substrate along the C-C' line of FIG. 2.

[0033] Referring to FIG. 1, the package substrate includes a glass substrate (110).

[0034] By including a glass substrate in the package, the generation of parasitic elements within the core and power loss resulting from the application of high-frequency power can be suppressed. Additionally, glass materials possess a low coefficient of thermal expansion and high hardness, which prevents thermal deformation of the package substrate during the packaging process. Consequently, the breakage and defect rates of the glass substrate can be reduced, and integration density can be improved by enabling the formation of finer and more precise patterns.

[0035] In one embodiment, the glass substrate (110) may include alkali borosilicate, alkali-free borosilicate, alkali aluminosilicate, alkali-free aluminosilicate, alkali-free aluminoborosilicate, etc., but any plate glass material applied as an electronic component may be used without limitation. For example, the glass substrate (110) may be manufactured by Schott, AGC, Corning, etc., but is not limited thereto.

[0036] The glass substrate (110) includes a first surface (112) and a second surface (114) facing each other. The first surface (112) and the second surface (114) may face each other in the thickness direction of the glass substrate (110).

[0037] The glass substrate (110) may include a side formed in the thickness direction, which is connected to the first surface (112) and the second surface (114), respectively. The side may be a plane perpendicular to the first surface (112) and the second surface (114), or an inclined surface inclined at a predetermined angle with respect to the first surface (112) and the second surface (114). Additionally, the side may be a curved surface.

[0038] The first surface (112) and the second surface (114) of the glass substrate (110) may be parallel to each other. Accordingly, the glass substrate (110) may have a substantially constant thickness overall.

[0039] The thickness of the glass substrate (110) may be 50 μm or more. For example, the thickness of the glass substrate (110) may be 100 μm or more, 150 μm or more, 200 μm or more, 250 μm or more, 300 μm or more, 400 μm or more, or 500 μm or more. Additionally, the thickness of the glass substrate (110) may be 3,000 μm or less. For example, the thickness of the glass substrate (110) may be 2,500 μm or less, 2,000 μm or less, 1,500 μm or less, or 1,000 μm or less.

[0040] The above package substrate includes a through hole (120) that penetrates the glass substrate (110).

[0041] The through hole (120) is a via formed for electrical connection between the upper and lower parts of the package substrate, and can be referred to as, for example, a TGV (through glass via).

[0042] The through hole (120) penetrates the glass substrate (110) in the thickness direction, that is, from the first surface (112) to the second surface (114).

[0043] The through hole (120) includes an internal space (124) and an inner wall (122) surrounding the internal space (124). The internal space (124) of the through hole (120) refers to an empty space. The inner wall (122) of the through hole (120) refers to the side wall of the glass substrate (110) where the through hole (120) is defined, that is, the surface of the glass substrate (110) at the interface between the glass substrate (110) and the through hole (120).

[0044] Figure 3 is an enlarged view of area A of Figure 1.

[0045] Referring to FIG. 3, the inner wall (122) of the through hole (120) has an irregular uneven structure. For example, the cross-sectional profile of the inner wall (122) of the through hole (120) may have an irregular shape.

[0046] Generally, through-holes are filled with conductive materials, such as metal, to implement electrical signal transmission paths within a glass substrate. However, as conductive materials have low adhesion to glass, problems such as interfacial delamination between the glass substrate and the conductive material and degradation of plating quality may occur within the through-holes.

[0047] According to embodiments of the present invention, the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) is greater than 0.2 μm and less than or equal to 2.0 μm.

[0048] Within the above range, a stable interlocking structure can be formed between the inner wall (122) of the through hole (120) and the conductive material through a mechanical anchoring effect. Accordingly, the conductive material can be adhered more uniformly to the glass substrate (110), and the peel resistance and electrical reliability of the via can be improved.

[0049] For example, when the Ra of the inner wall of the through hole is 0.2 μm or less, the mechanical anchoring effect between the glass substrate and the conductive material within the through hole may not be substantially provided. Consequently, delamination or voids may increase at the interface between the glass substrate and the conductive material, and electrical reliability and stability may be reduced. In addition, as the bonding surface between the glass substrate and the conductive material becomes relatively flat and the bonding area decreases, it is difficult to disperse the stress accumulated on the bonding surface, and consequently, localized delamination or cracks may occur during subsequent processes.

[0050] For example, if the Ra of the inner wall of the through hole exceeds 2.0 μm, the height variation of the inner wall of the through hole increases excessively, which may actually reduce the adhesion of the conductive material to the glass substrate. In addition, if the roughness of the inner wall of the through hole becomes excessively high, the cross-sectional profile of the conductive material formed on the inner wall may become rough. In this case, voids may be formed inside the conductive material or the flow of current may be distorted, which may increase resistance.

[0051] In some embodiments, the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) may be 0.25 μm or more, 0.3 μm or more, 0.35 μm or more, 0.4 μm or more, or 0.45 μm or more. Additionally, the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) may be 1.8 μm or less, 1.6 μm or less, or 1.4 μm or less. Preferably, the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) may be 1.3 μm or less, and more preferably, 1.2 μm or less, 1.0 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.55 μm or less.

[0052] For example, Ra of the inner wall (122) of the through hole (120) may be greater than 0.2 μm and less than or equal to 1.8 μm, 0.25 μm to 1.6 μm, 0.25 μm to 1.4 μm, 0.25 μm to 1.3 μm, 0.25 μm to 1.2 μm, 0.3 μm to 1.0 μm, 0.3 μm to 0.8 μm, 0.3 μm to 0.6 μm, 0.3 μm to 0.55 μm, 0.4 μm to 0.55 μm, or 0.45 μm to 0.55 μm. Within the above range, a more stable bonding structure can be formed between the conductive material formed inside the through hole (120) and the glass substrate (110), and the area of ​​contact between the conductive material and the glass substrate (110) can be further increased, thereby further improving structural stability, electrical reliability, and low resistance characteristics.

[0053] The above centerline average roughness (Ra) was obtained using a laser microscope ISO 21920 Measurements can be taken according to the specifications. The above laser microscope may include the KEYENCE VK-X3000, but is not limited thereto.

[0054] The centerline average roughness (Ra) of the inner wall (122) of the through hole (120) may be measured for a glass substrate having a thickness of 50 μm to 3,000 μm and a through hole having a width of 40 μm to 250 μm. Specifically, the centerline average roughness (Ra) may be measured for a glass substrate with a thickness of 0.53t and a through hole with a width of 140 μm.

[0055] In one embodiment, the ratio of the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) to the width of the through hole (120) may be 0.15% to 1.43% in percentage, and specifically, 0.15% to 1.29%, 0.18% to 1.14%, 0.18% to 1.00%, 0.18% to 0.93%, 0.18% to 0.86%, 0.21% to 0.71%, 0.21% to 0.57%, 0.21% to 0.43%, 0.21% to 0.39%, 0.29% to 0.39%, or 0.32% to 0.39%.

[0056] Within the above range, as the micro-irregular structure of the inner wall (122) has an appropriate size relative to the internal volume of the through hole (120), the mechanical bonding force between the conductive material filled inside the through hole (120) and the micro-curves can be more effectively enhanced. Accordingly, the plating adhesion and stress distribution effects are enhanced, thereby improving the peelability and connectivity of the via and reducing resistance.

[0057] Meanwhile, considering the local deviation of the inner wall (122) of the through hole (120), the Ra value may be measured multiple times in different areas of the inner wall (122) of the through hole (120), and the average of the measured values ​​may be used as the Ra of the inner wall (122) of the through hole (120). For example, the inner wall (122) of the through hole (120) may include a plurality of arbitrarily selected measurement areas, and the Ra of the inner wall (122) may be obtained by averaging the Ra values ​​of each measurement area. Each of the above measurement areas may have a line shape extending in the thickness direction of the glass substrate (110).

[0058] In some embodiments, the inner wall (122) of the through hole (120) includes a total of three arbitrarily selected measurement areas, and when the Ra values ​​of each measurement area are measured, the standard deviation of the Ra values ​​may be 0.3 μm or less. The standard deviation may be the sample standard deviation.

[0059] The standard deviation of the above Ra values ​​may indicate the uniformity of roughness over the entire area of ​​the inner wall (122). For example, the smaller the standard deviation of the above Ra values, the more uniform the roughness value of the inner wall (122) of the through hole (120) may be, and the larger the standard deviation of the above Ra values, the greater the difference in roughness value in the local area of ​​the inner wall (122).

[0060] As the standard deviation of the Ra values ​​measured at the inner wall (122) of the through hole (120) is 0.3 μm or less, the thickness distribution and bonding characteristics of the plating layer can be uniform throughout the inner wall during the plating and filling process of the conductive material. In addition, the mechanical anchoring effect of the conductive material on the glass substrate (110) is formed similarly throughout the inside of the through hole (120), so that the stress acting on the interface can be more evenly distributed. Accordingly, stress concentration in localized areas can be relieved, thereby further suppressing peeling and cracking.

[0061] The standard deviation of the above Ra values ​​may be 0.15 μm or less. Accordingly, the uniformity of bonding of the conductive material to the inner wall (122) of the through hole (120) is further improved, and stress concentration is further relieved, thereby suppressing localized delamination and voids.

[0062] For example, the standard deviation of the above Ra values ​​may be 0.13 μm or less, 0.1 μm or less, 0.08 μm or less, 0.06 μm or less, or 0.05 μm or less. Additionally, the standard deviation of the above Ra values ​​may be 0.01 μm or more, or 0.02 μm or more.

[0063] In one embodiment, the 10-point average roughness (Rz) of the inner wall (122) of the through hole (120) may be 10 μm or less. Accordingly, a conductive material can be plated uniformly and stably along the inner wall (122) of the through hole (120), and a uniform bond between the glass substrate (110) and the conductive material can be ensured.

[0064] For example, the above 10-point average roughness (Rz) represents the average distance between the five highest peaks and the five deepest valleys in the cross-sectional roughness profile. If the Rz of the inner wall (122) of the through hole (120) is excessively large, plating non-uniformity and bonding defects may occur due to local deep or high irregularities, and long-term reliability may be reduced.

[0065] In some embodiments, the Rz of the inner wall (122) of the through hole (120) may be 9 μm or less, 8 μm or less, and preferably 7.5 μm or less, 7 μm or less, 6.5 μm or less, 5 μm or less, 4 μm or less, or 3.5 μm or less. Additionally, the Rz of the inner wall (122) of the through hole (120) may be 0.5 μm or more, 1.0 μm or more, 1.5 μm or more, or 2 μm or more.

[0066] For example, the Rz of the inner wall (122) of the through hole (120) may be 0.5 μm to 10 μm, 0.5 μm to 9 μm, 0.5 μm to 8 μm, 0.5 μm to 7.5 μm, 0.5 μm to 6.5 μm, 0.5 μm to 5 μm, 0.5 μm to 4 μm, 0.5 μm to 3.5 μm, 0.5 μm to 3.5 μm, 1 μm to 3.5 μm, 1.5 μm to 3.5 μm, or 2 μm to 3.5 μm.

[0067] As irregularities of appropriate height and depth are formed on the inner wall (122) of the through hole (120) within the above range, mechanical anchoring of the conductive material to the glass substrate (110) is more stably secured, and the bonding strength can be further improved. In addition, due to structural stress distribution by peaks and valleys at the bonding interface, mechanical stability at the bonding interface is further enhanced, and cracks caused by thermal and electrical expansion can be further suppressed.

[0068] The 10-point average roughness (Rz) of the inner wall (122) of the through hole (120) may be measured for a glass substrate having a thickness of 50 μm to 3,000 μm and a through hole having a width of 40 μm to 250 μm. Specifically, the 10-point average roughness (Rz) may be measured for a glass substrate (110) with a thickness of 0.53t and a through hole with a width of 140 μm.

[0069] In one embodiment, the ratio of the 10-point average roughness (Rz) of the inner wall (122) of the through hole (120) to the width of the through hole (120) may be 0.36% to 7.14% in percentage, and specifically, 0.36% to 6.43%, 0.36% to 5.71%, 0.36% to 5.36%, 0.36% to 4.64%, 0.36% to 3.57%, 0.36% to 2.86%, 0.36% to 2.50%, 0.71% to 2.50%, 1.07% to 2.50%, or 1.43% to 2.50%. Within the above range, the adhesion between the conductive material filled in the internal space (124) of the through hole (120) and the inner wall (122) of the through hole (120) can be further improved and the electrical properties can be further improved.

[0070] The above 10-point average roughness (Rz) was obtained using a laser microscope ISO 21920 Measurements can be taken according to the specifications, and the above laser microscope can be the KEYENCE VK-X3000, etc.

[0071] Specifically, the Rz value can be measured multiple times at the inner wall (122) of the through hole (120), and the average of the measured Rz values ​​can be used as the Rz of the inner wall (122). For example, the inner wall (122) of the through hole (120) may include a plurality of arbitrarily selected measurement areas, and the Rz of the inner wall (122) may be obtained by averaging the Rz values ​​of each measurement area. Each of the measurement areas may have a line shape extending in the thickness direction of the glass substrate (110).

[0072] In some embodiments, the inner wall (122) of the through hole (120) includes a total of three arbitrarily selected measurement areas, and when the Rz values ​​of each measurement area are measured, the standard deviation of the Rz values ​​may be 3 μm or less. Accordingly, a conductive material may be uniformly deposited or formed over the entire inner wall (122) of the through hole (120), and bonding strength and resistance characteristics may be evenly displayed. The standard deviation may be a sample standard deviation.

[0073] For example, the standard deviation of the above Rz values ​​may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, 0.5 μm or less, 0.4 μm or less, or 0.3 μm or less. Additionally, the standard deviation of the above Rz values ​​may be 0.1 μm or more, or 0.2 μm or more. Within the above range, the height may be uniform overall on the inner wall (122) of the through hole (120) while providing irregularities of an appropriate size, thereby further improving the adhesion of the conductive material to the glass substrate (110).

[0074] In some embodiments, the ratio of Rz to Ra (Rz / Ra) of the inner wall (122) of the through hole (120) may be 5.0 or higher. The Rz / Ra can quantitatively indicate the uniformity of the roughness distribution of the through hole (120) and the size distribution of local irregularities. For example, the lower the Rz / Ra value, the more uniform and smooth the irregularity distribution of the inner wall (122) of the through hole (120) may be, and the higher the Rz / Ra value, the greater the variation in the size of the irregularities in local areas may be.

[0075] Preferably, the Rz / Ra of the inner wall (122) of the through hole (120) may be 5.5 or higher, 5.7 or higher, 5.9 or higher, 6 or higher, or 6.2 or higher, and may be 10 or lower, 8 or lower, 7.5 or lower, 7 or lower, or 6.6 or lower. Within the above range, as the uneven structure has an appropriate height variation, the bonding strength to the plating layer, etc. is further improved, and the uneven size can be uniform throughout the inner wall (122), thereby suppressing localized peeling, defects, and cracks, and further enhancing the uniformity of the plating layer.

[0076] The through hole (120) may include a first opening (126) in contact with a first surface (112) of the glass substrate (110), and a second opening (128) in contact with a second surface (114) of the glass substrate (110).

[0077] For example, the first opening (126) is a surface exposed through the first surface (112) of the glass substrate (110) and may be located on the same plane as the first surface (112). Additionally, the second opening (128) is a surface exposed through the second surface (114) of the glass substrate (110) and may be located on the same plane as the second surface (114).

[0078] The first opening (126) and the second opening (128) may have various shapes such as a circle, ellipse, rectangle, square, rhombus, parallelogram, triangle, etc. In one embodiment, the shape of the first opening (126) and the second opening (128) may be circular or elliptical, and specifically, may be circular.

[0079] In one embodiment, the first opening (126) and the second opening (128) may have the same shape as each other.

[0080] The width (W1) of the first opening (126) and the width (W2) of the second opening (128) may be substantially the same.

[0081] The width (W1) of the first opening (126) and the width (W2) of the second opening (128) may each be 40 μm or more, 60 μm or more, 80 μm or more, or 100 μm or more, and may be 250 μm or less, 230 μm or less, 210 μm or less, 200 μm or less, 180 μm or less, 160 μm or less, or 140 μm or less.

[0082] For example, the width (W1) of the first opening (126) and the width (W2) of the second opening (128) may each be 40 μm to 250 μm, 40 μm to 230 μm, 40 μm to 210 μm, 40 μm to 200 μm, 60 μm to 180 μm, 80 μm to 160 μm, or 100 μm to 140 μm. Within the above range, the package substrate may be more highly integrated, and electrical characteristics and reliability may be further improved.

[0083] In one embodiment, the width or diameter of the through hole (120) in the thickness direction of the glass substrate (110) may be substantially constant. Specifically, the entire area of ​​the through hole (120) may have the same diameter as the diameter (W1) of the first opening (126) and the diameter (W2) of the second opening (128).

[0084] The through hole (120) may have a column shape, specifically a cylinder shape. For example, the cross-section of the through hole (120) may have a square or rectangular shape.

[0085] In one embodiment, the width or diameter of the through hole (120) may vary in the thickness direction of the glass substrate (110). For example, the width or diameter of the through hole (120) may gradually decrease and then increase again in the direction from the first opening (126) toward the second opening (128). In this case, the cross-section of the through hole (120) may have an hourglass shape.

[0086] In one embodiment, the first opening (126) and the second opening (128) may overlap each other in the thickness direction of the glass substrate (110). For example, the through hole (120) may extend parallel to the thickness direction of the glass substrate (110).

[0087] In one embodiment, the through hole (120) may be extended at a predetermined angle of inclination with respect to the thickness direction of the glass substrate (110), in which case the first opening (126) and the second opening (128) may partially overlap or not overlap in the thickness direction of the glass substrate (110).

[0088] FIG. 4 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0089] Referring to FIG. 4, the package substrate may include a via electrode (130) that fills at least a portion of the internal space (124) of the through hole (120).

[0090] The via electrode (130) can cover the inner wall (122) of the through hole (120). For example, the via electrode (130) can come into direct contact with the inner wall (122) of the through hole (120). As the inner wall (122) of the through hole (120) satisfies the roughness described above, a mechanical anchoring effect between the inner wall (122) and the via electrode (130) can be provided, so that the via electrode (130) can be stably adhered or attached to the glass substrate (110).

[0091] The upper and lower portions of the glass substrate (110) can be electrically connected through via electrodes (130). For example, the via electrodes (130) may be connection terminals for vertical electrical connection within the package substrate.

[0092] FIG. 5 is a schematic cross-sectional view illustrating the process of forming via electrodes during the manufacturing process of a package substrate according to some embodiments.

[0093] Referring to FIG. 5, the via electrode (130) may include a seed layer (132) and an electrically conductive layer (134) formed on the seed layer (132).

[0094] Referring to FIG. 5(a), the seed layer (132) is formed along the inner wall (122) of the through hole (120) and can uniformly cover the inner wall (122) of the through hole (120). As the inner wall (122) of the through hole (120) has the roughness described above, the seed layer (132) can be stably adhered to the glass substrate (110) by an anchoring effect in which the surface irregularities of the inner wall (122) and the metal particles of the seed layer (132) interact with each other.

[0095] The seed layer (132) can be formed in a dry manner. For example, the seed layer (132) can be formed through a deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). For example, it can be formed by sputtering a metal element along the inner wall (122) of the through hole (120).

[0096] The seed layer (132) may include metals such as copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), cobalt (Co), tin (Sn), magnesium (Mg), silver (Ag), and gold (Au), or alloys thereof, but is not limited thereto.

[0097] Referring to FIG. 5(c), an electrically conductive layer (134) may be formed on the seed layer (132). The electrically conductive layer (134) may be formed by a plating method using the seed layer (132). Although the seed layer (132) and the electrically conductive layer (134) are distinguished by solid lines in FIG. 5, they may have a one-body form in which they are integrated and there is no distinction between the layers.

[0098] The electrically conductive layer (134) comprises a conductive material. For example, the electrically conductive layer (134) may comprise metals such as copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), cobalt (Co), tin (Sn), magnesium (Mg), silver (Ag), gold (Au), or alloys thereof, but is not limited thereto.

[0099] The thickness of the electrically conductive layer (134) can be controlled by adjusting various process conditions, such as the concentration of the plating solution, the plating time, and the type of additive included in the plating solution, during the plating process.

[0100] In some embodiments, the seed layer (132) may include a metal element included in the electrically conductive layer (134). In some embodiments, the seed layer (132) may include an element different from the metal element included in the electrically conductive layer (134).

[0101] Meanwhile, referring to FIGS. 5(b) and (d), a mask pattern (135) may be formed in a portion where the formation of the electrically conductive layer (134) is unnecessary before the plating process. The mask pattern (135) may include an insulating material. In this case, the mask pattern (135) can be removed after the electrically conductive layer (134) is formed.

[0102] In some embodiments, the via electrode (130) may fill the entire internal space (124) of the through hole (120). For example, only the via electrode (130) may exist within the internal space (124) of the through hole (120).

[0103] FIG. 6 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0104] Referring to FIG. 6, the via electrode (130) may fill only a portion of the internal space (124) of the through hole (120). For example, the via electrode (130) in the internal space (124) of the through hole (120) may have a hollow column shape formed along the inner wall (122) of the through hole (120). For example, when observed in a direction perpendicular to the thickness direction of the glass substrate (120), the cross-section of the via electrode (130) may have a circular, elliptical, or square ring shape.

[0105] When the via electrode (130) is formed only in a part of the internal space (124) of the through hole (120), an insulating layer may be disposed in the remaining space. For example, the via electrode (130) may be disposed adjacent to the inner wall (122) of the through hole (120), and an insulating layer may be disposed in the space surrounded by the via electrode (130).

[0106] FIG. 7 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0107] Referring to FIG. 7, the through hole (130) may have a shape in which the width gradually decreases from the first opening to the second opening and then increases again. Additionally, the cross-section of the via electrode (130) filled in the through hole (130) may have an hourglass shape.

[0108] FIG. 8 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0109] Referring to FIG. 8, the package substrate includes a core layer (100). The core layer (100) includes a glass substrate (110) and a through hole (120). The core layer (100) may include a via electrode (130) filled inside the through hole (120). The through hole (120) and the via electrode (130) may be referred to as a TGV (through glass via).

[0110] The core layer (100) can serve as an intermediate or intermediary connecting the upper and lower parts of the package substrate within the package substrate. For example, the via electrode (130) of the core layer (100) can function as a passage for transmitting electrical signals between the upper and lower parts within the package substrate.

[0111] The core layer (100) may further include via pads (140) connected to via electrodes (130) and disposed on one or both sides of the glass substrate (110). The via pads (140) may be formed to have a width longer or a wider area than the opening of the through hole (120). Thus, electrical connectivity and reliability may be further improved by the via pads (140).

[0112] The via pad (140) can be formed together with the via electrode (130). For example, the via electrode (130) and the via pad (140) can be formed together through electroplating using the same seed layer.

[0113] The above package substrate may include an upper layer (200) disposed on one side of the core layer (100).

[0114] The upper layer (200) may include an upper insulating layer (210) covering one side of the core layer (100).

[0115] The upper insulating layer (210) may include a build-up layer material such as an epoxy resin or an imide resin, but is not limited thereto, and any material that functions as an insulator for a semiconductor device or a package substrate may be applied as the upper insulating layer (210).

[0116] The upper layer (200) may further include an upper redistribution layer (220) that is at least partially embedded in the upper insulating layer (210). The upper redistribution layer (220) may be electrically connected to a via electrode (130).

[0117] The upper redistribution layer (220) may be composed of a plurality of layers along the thickness direction of the package substrate. For example, the upper redistribution layer (220) may have a 2-layer structure, a 3-layer structure, a 4-layer structure, a 5-layer structure, or a multilayer structure of 6 layers or more.

[0118] For example, in the case of a four-layer structure, the upper redistribution layer (220) may include a first upper redistribution layer (220a), a second upper redistribution layer (220b), a third upper redistribution layer (220c), and a fourth upper redistribution layer (220d) that are sequentially stacked and connected from one side of the core layer (100).

[0119] In FIG. 8, the upper insulating layer (210) is depicted as a single layer, but the upper insulating layer (210) may be composed of multiple layers. When the upper insulating layer (210) is composed of multiple layers, multiple upper redistribution layers (220) may be disposed on at least one of the upper and lower surfaces of each layer of the upper insulating layer (210).

[0120] The outermost upper redistribution layer (220) in the thickness direction of the package substrate may be exposed from the upper surface of the upper layer (200). The outermost upper redistribution layer (220) may function as a connection electrode connected to a connection terminal of a semiconductor device, etc.

[0121] In one embodiment, the upper layer (200) may further include an upper cover layer (230). The upper cover layer (230) may protect the surface circuit of the package substrate from the external environment. The upper cover layer (230) may include an opening that exposes the outermost upper redistribution layer (220). Through the opening, the outermost upper redistribution layer (220) and a connection terminal of an external component may be connected.

[0122] The upper cover layer (230) may include an insulating film such as solder resist or polyimide film (PI).

[0123] The above package substrate may further include a lower layer (300) disposed on the other side of the core layer (100).

[0124] The lower layer (300) may include a lower insulating layer (310) covering the other side of the core layer (100).

[0125] The lower insulating layer (310) may include a build-up layer material such as an epoxy resin or an imide resin, but is not limited thereto, and any material that functions as an insulator for a semiconductor device or a package substrate may be applied as the lower insulating layer (310).

[0126] The lower layer (300) may further include a lower redistribution layer (320) that is at least partially embedded in the lower insulating layer (310). The lower redistribution layer (320) may be electrically connected to the via electrode (130).

[0127] The lower redistribution layer (320) may be composed of a plurality of layers along the thickness direction of the package substrate. For example, the lower redistribution layer (320) may have a 2-layer structure, a 3-layer structure, a 4-layer structure, a 5-layer structure, or a multilayer structure of 6 layers or more.

[0128] For example, in the case of a two-layer structure, the lower redistribution layer (320) may include a first lower redistribution layer (320a) and a second lower redistribution layer (320b) that are sequentially stacked and connected from the other side of the core layer (100).

[0129] In FIG. 8, the lower insulating layer (310) is depicted as a single layer, but the lower insulating layer (310) may be composed of multiple layers. When the lower insulating layer (310) is composed of multiple layers, multiple lower redistribution layers (320) may be disposed on at least one of the upper and lower surfaces of each layer of the lower insulating layer (310).

[0130] The outermost lower redistribution layer (320) in the thickness direction of the package substrate may be exposed to the outside from the lower surface of the lower layer (300). The outermost lower redistribution layer (320) may function as a connection electrode connected to a connection terminal of a semiconductor device, etc.

[0131] In one embodiment, the lower layer (200) may further include a lower cover layer (330). The lower cover layer (330) may protect the surface circuit of the package substrate from the external environment. The lower cover layer (330) may include an opening that exposes the outermost lower redistribution layer (320). Through the opening, the outermost lower redistribution layer (320) and a connection terminal of an external component may be connected.

[0132] The lower cover layer (330) may include an insulating film such as solder resist or polyimide film (PI).

[0133] A semiconductor package according to embodiments of the present invention comprises a package substrate according to the embodiments described above; and a device mounted on the package substrate.

[0134] In one embodiment, a device may be mounted on the upper layer (200) and / or lower layer (300) of the package substrate. The device may be electrically connected to the package substrate. Examples of the device include a capacitor, a transistor, an impedance, a semiconductor, etc., but are not limited to any device mounted on a semiconductor device.

[0135] In some embodiments, the glass substrate (110) may further include a cavity formed by being indented internally. For example, the cavity may be formed by being indented in part on the first surface (112) side in the thickness direction of the glass substrate (110), or by being formed by being indented in part on the second surface (114) side. Additionally, the cavity may have a shape that penetrates the glass substrate (110) in the thickness direction.

[0136] A device may be mounted in the above cavity. The device may be electrically connected to a package substrate. Examples of the device include capacitors, transistors, impedance devices, semiconductor devices, etc., but are not limited to any device mounted on a semiconductor device.

[0137] The above semiconductor device may be a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, an application processor (AP) chip, or a memory chip.

[0139] Method for manufacturing a package substrate

[0140] A method for manufacturing a package substrate according to embodiments of the present invention includes a step of forming a through hole in a glass substrate that penetrates in the thickness direction of the glass substrate.

[0141] FIG. 9 is a schematic cross-sectional view illustrating the process of forming through holes during the manufacturing process of a package substrate.

[0142] Referring to FIG. 9 (a) and (b), a defect can be formed at a predetermined location on one side of a glass substrate (110). Methods such as mechanical etching or laser irradiation can be used to form the defect (50), and specifically, the defect (50) can be formed through laser irradiation.

[0143] In some embodiments, a laser can be irradiated at regular intervals along the perimeter of a region (VH) on one side of a glass substrate (110) where a through hole is to be formed. Accordingly, a plurality of defects (50) can be formed at regular intervals along the perimeter of the VH region.

[0144] FIG. 10 is a schematic plan view illustrating the process of forming a through hole during the manufacturing process of a package substrate. Specifically, FIG. 9 (b) is a cross-sectional view of a glass substrate (110) cut along the BB' line of FIG. 10.

[0145] In a subsequent process of etching the glass substrate, the portion where the defect is formed can be removed, for example, by reacting with the etching solution. Accordingly, by forming a plurality of defects (50) along the perimeter of the region (VH) where the through hole is to be formed, the defect (50) may enlarge or expand during the etching process and meet with an adjacent defect (50), and accordingly, the VH region may be removed from the glass substrate (110). For example, the process of forming the through hole may be performed by a laser-assisted etching or laser-induced etching method.

[0146] The laser can be irradiated perpendicularly to one surface of the glass substrate (110).

[0147] In one embodiment, the laser may have a wavelength of 290 nm to 330 nm, and for example, a 308 nm XeCl excimer laser may be used, but is not limited thereto. In addition, the laser irradiation may be performed for 5 seconds to 20 seconds under conditions of an energy density of 1 J / cm² to 10 J / cm², a pulse of 5 ns to 20 ns, and a spot size of 5 µm to 30 µm.

[0148] The defects (50) may have a shape that is recessed inward from the surface of the glass substrate (110). For example, each of the defects (50) may have a groove shape that extends in a direction perpendicular to the surface of the glass substrate (110).

[0149] In some embodiments, the method may further include the step of irradiating a laser at regular intervals along the perimeter of the region (VH) where the through hole is to be formed on the other side of the glass substrate (110). Accordingly, a plurality of defects may be formed on the other side of the glass substrate (110).

[0150] For example, a plurality of defects (50) formed on one side of the glass substrate (110) and a plurality of defects formed on the other side of the glass substrate (110) may overlap each other in the thickness direction of the glass substrate (110). Accordingly, the etching time required to form a through hole may be further reduced. In addition, in this case, a through hole with a cross-section in the shape of an hourglass may be formed.

[0151] Referring to FIG. 9 (c) and (d), a glass substrate (110) with a defect (50) formed therein can be etched to form a through hole (120) that penetrates the glass substrate (110).

[0152] The above etching can be performed by wet etching using an etchant. The etchant is not limited to any that can be conventionally applied to etch a glass substrate. For example, the etchant may include a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, etc.

[0153] In one embodiment, the wet etching may be performed by immersing a glass substrate in an etching solution containing hydrofluoric acid and / or nitric acid and applying ultrasonic treatment, etc. For example, the concentration of hydrofluoric acid in the etching solution may be 0.5 M or more, or 1.1 M or more, and 3 M or less, or 2 M or less. For example, the concentration of nitric acid in the etching solution may be 0.5 M or more, or 1 M or more, and 2 M or less. The ultrasonic treatment may be performed at a frequency of 40 Hz to 120 Hz, or 60 Hz to 100 Hz.

[0154] In the above etching process, a mask pattern can be applied to the remaining surface of the glass substrate (110), excluding the area (VH) where a through hole is to be formed, to prevent etching of the remaining surface. Additionally, etching can be performed without a mask pattern.

[0155] Generally, when through holes are formed in a thin glass substrate, localized stress concentration occurs during the processing of the glass substrate, which may weaken the mechanical properties of the glass substrate or cause microcracks. Consequently, processability and workability may be degraded during the manufacturing and packaging processes of the package substrate.

[0156] According to embodiments of the present invention, by irradiating a laser at regular intervals in an area where a through hole is to be formed to form defects, and then proceeding with etching on a glass substrate, workability and processability can be improved while preventing degradation of the mechanical properties of the glass substrate.

[0157] In one embodiment, when observed on one side of the glass substrate (110), the spacing (D) between adjacent defects (50) along the perimeter of the VH region may be 2 μm to 6 μm. Within this range, the roughness of the inner wall of the through hole (120) formed after the etching process can be controlled to a desired range.

[0158] For example, if the spacing (D) between defects (50) is less than 2 μm, the roughness of the inner wall of the through hole may increase excessively. If the spacing (D) between defects (50) is greater than 6 μm, as the number of defects per unit area decreases, harsher etching conditions may be required to form the through hole, or the etching time may increase. In this case, surface characteristics may change or physical properties may change due to etching in other areas of the glass substrate besides the area where the through hole is formed, and electrical and thermal properties may deteriorate.

[0159] The spacing (D) between adjacent defects (50) along the perimeter of the VH region may be greater than 2 μm and less than 6 μm, greater than 2 μm and less than 6 μm, 2.5 μm to 5.5 μm, 2.5 μm to 5 μm, 3 μm to 5 μm, 3 μm to 4.5 μm, or 3.5 μm to 4.5 μm.

[0160] In one embodiment, the diameter of the VH region may be 40 μm to 250 μm, 40 μm to 230 μm, 40 μm to 210 μm, 40 μm to 200 μm, 60 μm to 180 μm, 80 μm to 160 μm, or 100 μm to 140 μm. For example, as defects (50) are formed along the perimeter of the VH region having the diameter of the above range at intervals (D) of the above range, the surface roughness characteristics of the inner wall of the through hole can be more easily adjusted to a desired range.

[0161] In one embodiment, the thickness of the glass substrate (110) may be 50 μm or more, 100 μm or more, 150 μm or more, 200 μm or more, 250 μm or more, 300 μm or more, 400 μm or more, or 500 μm or more, and may also be 3,000 μm or less, 2,500 μm or less, 2,000 μm or less, 1,500 μm or less, or 1,000 μm or less.

[0162] The centerline average roughness (Ra) of the inner wall of the through hole (120) formed after the etching process may be greater than 0.2 μm and less than or equal to 2.0 μm, and the 10-point average roughness (Rz) may be less than or equal to 10 μm.

[0163] For example, Ra of the inner wall of the through hole (120) may be greater than 0.2 μm and less than or equal to 1.8 μm, 0.25 μm to 1.6 μm, 0.25 μm to 1.4 μm, 0.25 μm to 1.3 μm, 0.25 μm to 1.2 μm, 0.3 μm to 1.0 μm, 0.3 μm to 0.8 μm, 0.3 μm to 0.6 μm, 0.3 μm to 0.55 μm, 0.4 μm to 0.55 μm, or 0.45 μm to 0.55 μm.

[0164] For example, the Rz of the inner wall of the through hole (120) may be 0.5 μm to 10 μm, 0.5 μm to 9 μm, 0.5 μm to 8 μm, 0.5 μm to 7.5 μm, 0.5 μm to 6.5 μm, 0.5 μm to 5 μm, 0.5 μm to 4 μm, 0.5 μm to 3.5 μm, 0.5 μm to 3.5 μm, 1 μm to 3.5 μm, 1.5 μm to 3.5 μm, or 2 μm to 3.5 μm.

[0165] According to some embodiments, an additional roughening process for the through hole may not be included after forming the through hole.

[0166] If additional processes, such as additional surface roughening on the sidewalls of the through-holes, are performed after forming through-holes in a glass substrate, the mechanical properties of the glass substrate may be weakened or the thermal properties may change. Furthermore, roughness may be imparted not only to the sidewalls of the through-holes but also to other surfaces of the glass substrate requiring flatness due to the surface roughening process; as the process becomes more complex for partial surface roughening, processability may be reduced.

[0167] According to embodiments of the present invention, the roughness of the inner wall of a through hole can be controlled by adjusting the laser irradiation interval during the process of forming a through hole in a glass substrate. Accordingly, the surface roughness of the inner wall of the through hole can be controlled to a desired range while simultaneously forming the through hole, thereby eliminating the need for additional processes such as a roughening process for the through hole, and preventing the degradation of the physical properties of the glass substrate caused by this.

[0168] According to some embodiments, the step of forming a via electrode inside the through hole (120) may be further included.

[0169] The step of forming the via electrode may be the same as described through FIG. 5. For example, the step of forming the via electrode may include the step of forming a seed layer along the inner wall of the through hole (120), and the step of forming an electrically conductive layer inside the through hole (120) using the seed layer.

[0171] The above contents are explained in more detail by the following examples. However, the following examples are merely for illustrating the present invention, and the scope of the present invention is not limited to these examples.

[0173] [Example]

[0174] (1) Manufacturing of package substrate

[0175] A glass substrate with a thickness of 0.53t (Corning SG7.8) was prepared. An etching area having a circular shape with a diameter of 140 μm was set on one side of the glass substrate. A plurality of defects were formed by irradiating a laser at regular intervals along the perimeter of the etching area. The laser irradiation interval (i.e., the interval between defects) was set as shown in Table 1 below.

[0176] Specifically, the laser was irradiated for 10 seconds under conditions of a wavelength of about 308 nm, a pulse of about 10 ns, an energy density of about 5 J / cm², and a spot size of about 5 µm.

[0177] The glass substrate was etched to form a through hole penetrating the glass substrate in the thickness direction. The through hole was formed to have a cylindrical shape with a diameter of 140 μm.

[0178] The above etching was performed for 30 minutes, and was carried out by placing the glass substrate in a deionized water-based acidic etchant containing 2 M hydrofluoric acid (HF) and 1.1 M nitric acid (HNO3) and applying ultrasound at 80 Hz.

[0180] (2) Measurement of the roughness of the inner wall of the through hole

[0181] The roughness of the inner wall of the through hole manufactured above was measured. Specifically, a total of three measurement areas were arbitrarily selected on the inner wall of the through hole. Each measurement area was specified so as not to overlap with one another, and was set to have a line shape extending along the inner wall of the through hole in the thickness direction of the glass substrate. For example, each measurement area was set as the area indicated by the dotted line in FIG. 11a.

[0182] The above roughness was measured using a laser microscope (KEYENCE VK-X3000) according to ISO 21920 standards, with centerline average roughness (Ra) and 10-point average roughness (Rz).

[0183] The average value of the Ra values ​​in each measurement area was set as the Ra of the inner wall of the penetration hole, and the average value of the Rz values ​​in each measurement area was set as the Rz of the inner wall of the penetration hole. The ratio of Ra to Rz (Rz / Ra) was calculated. Meanwhile, among the measured values ​​in each measurement area, the maximum value was indicated as "max" in Table 1 below, and the minimum value was indicated as "min".

[0185] Package substrates were manufactured by changing the spacing between defects in the above laser processing process as shown in Table 1 below. At this time, package substrates were manufactured twice with the same defect spacing. For example, Manufacturing Examples 1 and 2 are for package substrates manufactured by setting the laser irradiation spacing to 2 μm, and Manufacturing Examples 3 and 4 are for package substrates manufactured by setting the laser irradiation spacing to 3 μm.

[0186] The roughness of the inner wall of the through hole of the above-manufactured package substrate was measured. The measurement results are shown in Table 1 below.

[0188] Preparation Example Defect spacing (㎛) Ra (㎛) Rz (㎛) Rz / Ra average Standard deviation max min average Standard deviation max min 1 2 1.513 0.149 1.619 1.302 8.082 0.769 8.949 7.079 5.342 2 2 1.652 0.211 1.915 1.398 8.674 1.098 9.614 7.134 5.251 3 3 1.267 0.267 1.529 0.9 7.495 2.101 9.855 4.752 5.916 4 3 1.153 0.128 1.268 0.974 6.624 0.471 7.141 6.001 5.745 5 4 0.519 0.055 0.586 0.451 3.278 0.348 3.676 2.829 6.316 6 4 0.481 0.03 0.521 0.449 3.157 0.272 3.441 2.79 6.563 7 5 0.598 0.11 0.751 0.498 3.979 1.036 5.421 3.035 6.654 8 5 0.570 0.11 0.726 0.487 3.675 0.638 4.448 2.925 6.447 9 6 0.596 0.128 0.776 0.484 3.612 0.5 4.206 2.984 6.060 10 6 0.599 0.049 0.647 0.531 3.737 0.438 4.168 3.135 6.239

[0190] Referring to Table 1 above, it was confirmed that the roughness of the inner wall of the through hole varies depending on the spacing between defects formed by laser irradiation. Specifically, referring to Manufacturing Examples 1 and 2, when the spacing between defects was 2 μm, the inner wall of the through hole had an Ra value of about 1.5 μm to about 1.7 μm and an Rz value of about 8 μm to about 9 μm.

[0191] In addition, referring to Manufacturing Examples 3 to 10, when the spacing between defects is 3 μm to 6 μm, the Ra value of the inner wall of the through hole is controlled to 1.3 μm or less, and the Rz value is controlled to 8 μm or less.

[0192] Meanwhile, as the number of defects per unit area decreases as the defect spacing increases, harsher etching conditions may be required to form through holes, or the etching time may increase. In this case, surface characteristics may change or physical properties may be altered by etching in other areas of the glass substrate besides the area where through holes are formed, and electrical and thermal properties may deteriorate.

[0194] FIGS. 11a to 11e are images of through holes in Preparation Examples 2, 4, 6, 8, and 10, respectively, taken using a laser microscope (KEYENCE VK-X3000). Specifically, FIG. 11a is an image of the through hole in Preparation Example 2, FIG. 11b is an image of the through hole in Preparation Example 4, FIG. 11c is an image of the through hole in Preparation Example 6, FIG. 11d is an image of the through hole in Preparation Example 8, and FIG. 11e is an image of the through hole in Preparation Example 10.

[0195] FIGS. 12a to 12e are 3D images of through holes in Preparation Examples 2, 4, 6, 8, and 10, respectively, obtained using a laser microscope (KEYENCE VK-X3000). Specifically, 3D images of the through holes were obtained using an image program (VK-X3000 Viewer Application) linked with the laser microscope. FIG. 12a is a 3D image of the through hole in Preparation Example 2, FIG. 12b is a 3D image of the through hole in Preparation Example 4, FIG. 12c is a 3D image of the through hole in Preparation Example 6, FIG. 12d is a 3D image of the through hole in Preparation Example 8, and FIG. 12e is a 3D image of the through hole in Preparation Example 10.

[0196] Referring to FIGS. 11a to 11e and FIGS. 12a to 12e, it was confirmed that the surface characteristics of the inner wall of the through hole were changed by adjusting the laser irradiation interval before wet etching during the process of forming the through hole.

[0197] Referring to FIGS. 11c and FIGS. 12c, it can be seen that in the case of the through hole in Manufacturing Example 6, irregularities of an appropriate size are provided on the inner wall, thereby providing a mechanical anchoring effect with the metal layer structurally formed on the inner wall. In addition, it can be seen that as the irregularities are distributed in a uniform size throughout the inner wall of the through hole, stress concentration, peeling, and defects in localized areas are suppressed, and uniform plating can be provided. Explanation of the symbols

[0199] 100: Core layer 110: Glass substrate 112: Page 1 114: Page 2 120: Through hole 122: Inner wall 124: Interior space 130: via electrode 132: Seed Layer 134: Electrically conductive layer 140: Core wiring layer 200: Upper layer 210: Upper insulation layer 220: Upper redistribution layer 230: Cover layer 300: Lower floor 310: Lower insulation layer 320: Lower redistribution layer 50: Defect

Claims

Claim 1 A glass substrate having a first surface and a second surface facing each other; and a through hole penetrating the glass substrate from the first surface to the second surface, wherein the through hole includes an internal space and an inner wall surrounding the internal space, and the centerline average roughness (Ra) of the inner wall of the through hole is greater than 0.2 μm and less than or equal to 2.0 μm, and the ratio of the centerline average roughness of the inner wall of the through hole to the width of the through hole is, in percentage, 0.15% to 1.43%. Claim 2 A package substrate according to claim 1, wherein the centerline average roughness (Ra) of the inner wall of the through hole is 0.3 μm to 0.55 μm. Claim 3 A package substrate according to claim 1, wherein the inner wall of the through hole comprises a total of three arbitrarily selected measurement areas, and the standard deviation of the Ra values ​​of each measurement area is 0.3 μm or less. Claim 4 A package substrate according to claim 1, wherein the 10-point average roughness (Rz) of the inner wall of the through hole is 10 μm or less. Claim 5 A package substrate according to claim 4, wherein the inner wall of the through hole comprises a total of three arbitrarily selected measurement areas, and the standard deviation of the Rz values ​​of each measurement area is 3 μm or less. Claim 6 In claim 1, the through hole comprises a first opening in contact with the first surface and a second opening in contact with the second surface, wherein the diameter of the first opening and the diameter of the second opening are substantially the same, a package substrate. Claim 7 In claim 6, the through hole has a cylindrical shape, the package substrate. Claim 8 A package substrate according to claim 1, further comprising a via electrode that fills at least a portion of the internal space of the through hole. Claim 9 In claim 8, the via electrode covers the inner wall of the through hole, the package substrate. Claim 10 In claim 8, the via electrode comprises a seed layer and an electrically conductive layer disposed on the seed layer, wherein the seed layer contacts the inner wall of the through hole, a package substrate. Claim 11 A package substrate according to claim 1, comprising: a core layer including the glass substrate and the through hole; and an upper layer disposed on one surface of the core layer, wherein the upper layer comprises an upper insulating layer covering the one surface of the core layer. Claim 12 A package substrate according to claim 11, wherein the core layer further comprises via electrodes filling at least a portion of the internal space of the through hole, and the upper layer further comprises an upper redistribution layer embedded in the upper insulating layer and electrically connected to the via electrodes. Claim 13 A package substrate according to claim 11, further comprising a lower layer disposed on the other side of the core layer, wherein the lower layer comprises a lower insulating layer covering the other side of the core layer. Claim 14 A package substrate according to claim 13, wherein the core layer further comprises via electrodes filling at least a portion of the internal space of the through hole, and the lower layer further comprises a lower redistribution layer embedded in the lower insulating layer and electrically connected to the via electrodes. Claim 15 A semiconductor package comprising: a package substrate according to claim 1; and a semiconductor device mounted on the package substrate.

Images